ALU

8 BIT ALU

module ALU (sel, carryin, A, B, Y, Arith_Unit, Logic_Unit, Alu_Shift);

input [7:0] A,B;

input [4:0] sel;

input carryin;

output [7:0] Y;

output [7:0] Arith_Unit, Logic_Unit, Alu_Shift;

reg [7:0] Y;

reg [7:0] Arith_Unit, Logic_Unit, Alu_Shift;

always @ (sel or A or B or carryin)

begin: ALU_Processing

// Logical Unit

case (sel(1:0))

2’d0: Logic_Unit=A&B;

2’d1: Logic_Unit=A | B;

2’d2: Logic_Unit=A ^ B;

2’d3: Logic_Unit=!A;

endcase

case ( {sel[1:0], carryin} )

2’d0: Arith_Unit=A;

2’d1: Arith_Unit=A+1;

2’d2: Arith_Unit=A+B;

2’d3: Arith_Unit=A+B+1;

2’d4: Arith_Unit=A+!B;

2’d5: Arith_Unit=A-B;

2’d6: Arith_Unit=A-1;

2’d7: Arith_Unit=A;

Endcase

// Multiplexing

if (sel[2])

Alu_Shift=Logic_Unit;

else

Alu_Shift=Arith_Unit;

// Shift Operations

case (sel[4:3])

2’d0: Y=ALU_Shift;

2’d1: Y=ALU_Shift << 1;

2’d2: Y=ALU_Shift >> 1;

2’d3: Y = 8’bx;

endcase

end

endmodule

8 Bit ALU using case

4 BIT ALU

module ALU4BIT(A, B, Y, S, F);

input [3:0] A;

input [3:0] B;

output [3:0] Y;

input [2:0] S;

output F;

reg[3:0] Y;
 reg F;

always @(A,B,S)

begin

case(S)

3'b000:

{F,Y} = A+B;

3'b001:

{F,Y} = A-B;

3'b010:

Y = A*B;

3'b011:

Y = A>>2;

3'b100:

Y = A & B;

3'b101:

Y = A | B;

3'b110:

Y = A^B;

3'b111:

Y = ~(A^B);

default:

Y = 4'b0000;

endcase

end

endmodule