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G85 SESH
(OCT «a
Sixth Semester B.E. Degree Examination, Dee.2018/Jan. 2019
VLSI Design
‘Time: ¥ hes Max, Matks: 80
Note: Answer any FIVE full questions, choosing @
Z ‘ONE full question from each module.
a
: ‘Modate-1
Bota
*
(08 Marks
Mention any two differences between CMOS and Bipolar tcl (02 Maris)
Write all he mask steps of p-well process. (We Mars)
With neat dingrams, expla the cutoff Finear and satura fs in MOSFET
‘with different valoes oF; and Vg
oR
2. a. Explain body effet as non ideal IV effects of MAREET (estar)
1 Pxplain Noise margin, wih respect 9 CMOS in (es ark)
Explain the steps of m-MOS fabrication wit (os Mars)
3a With a neat dlagram, explain 24
sectional view of same, (wite
Estimate theese time and fal ci
fi batting contact and show thE cross
e urtes contact). estan)
inverter and summarise she result. (08 Mark)
cones
t
4n
a
fol | and relative capacitance value is 0.075 C,
polysilicon snd eitive capacitance value i 0.1-Cy oe)
schematic and sick diagram for Boolean expression 9 = (@+ Bs} implement
10S los), (08 Mars)
Meno 444 ta! shir Wet the oMOS inplementton as
Erplin cares ae with neat ack om.
ay for the
Marks)
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on
6 a Define regulary
1h Derive the scaling factor forthe device parameter
3) Parasite capacitance
ii) Channel resistance
ii) Gate delay.
z
:
z
2
3
g
g
2
:
2
Mo
7a. Explain the fllowing logics
5) Clocked CMOS logic
ii) mp CMOS logic (08 Mars)
1b. Explain party generator, wit the MOS im ty generator with stick
diagram, (as Maris)
o
Explain Pscudo-oMOS gic, Find 7, a1 0.5Vb0, Vir 02Vo.
Von = SV and te" Sup. (os tars)
Explain the d-eay data selector feclean equation and nMOS based stick
diagram, (os stars)
S
98. Write the system tii {0 Mork
Explain logic veritg (8 Marks)
on
10s. Explain three ysioMgamic RAM sith neat circuit and tick diagram, (06 Mar)
bh What are design Miyact bili contents)
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