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    Bipolar and Mos Analog Integrated Circuit Design 2003 Grebene

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    ey alten WAL __(jrebene Bipolar and MOS Analog Integrated Circuit Design BIPOLAR AND MOS ANALOG INTEGRATED CIRCUIT DESIGN ALAN B. GREBENE MICRO-LINEAR CORPORATION SUNNYVALE, CAUFORNIA ‘A Wiley-Interscience Publication John Wiley & Sons New York Chichester Brisbane Toronto Singapore PREFACE ‘The contents and organization ofthis book are primarily aimed at the practicing engineerin the field of solid-state electronic. Its intended asa valuable reference forthe IC designer and user alike. For the analog IC designer, it provides rigorous esign guidelines and examples, while for the user, it offers a deiled analysis of various classes of analog circuits, points out their design philosophy, capabilities, and limitations, and presents application examples and guidelines 1s intended to be an easy and smooth reading book on a rapidly evolving high-technology subject. To this end, the lengthy and detailed mathematical teat. ‘ment of the subject matter is minimized. Long derivations of device or circuit ‘equations are avoided whenever possible; instead, the emphasis is placed onthe end result, and the basic design philosophy leacng up to it, with clear understanding ‘ofthe underlying assumptions and trade-offs. Whenever possible, each new design ‘dea or concept is also demonstrated with a practical example ‘The advent of integrated circuit technology has altered many ofthe established circuit design techniques and principles. This is particularly evident in the field of analog integrated circuits where the designer is faced with a new set of design ‘constraints and ground rules. In writing this book, it is my intention to educate the practicing electronics engineerin the fundimental design principles, capabiliies, ‘nd applications of monolithic analog circuits. However, the subject matters treated ‘rigorously and from a fundamental viewpoint, to make this book suitable as a text for graduate study in semiconductor circuit This book i an updated sequel to an ear book by the author. Analog Integrated Circuit Design (published by Van Nostrard Reinhold, 1972) which covered the analog IC design technology of the 1960's. Since then, many significant changes ‘have occurred inthe world of microelectronics. Perhaps the most important ofthese ‘has been the “microprocessor revolution,” waich has resulted in arly evolutionary ‘growth of digital signal-processing techniques. In tur, this has led to a rapid {evolution and advancement of analog circu! methods, particularly in the areas that interface with digital echniques and technologies. As a result complete LSI systems hhave evolved which combine complex analog and digital functions on the sume chip. “ PREECE ‘A great deal of this development has been possible by extending the capabilities of MOS devices and process technology to cover anslog functions. Consequently, analog IC design using MOS technology has rapidly evolved into x major area of growth. These developments of recent years are profoundly refected inthe contents snd the organization ofthis book. Inthe preparation of the text, itis assumed thatthe reader is familiar with the basic theory and principles of solid-state devices. Therefore, the solid-state device theory, which is already well covered elsewhere in the literature, i reviewed only briefly, and almost all of the space is devoted to circuit approaches unique to ‘monolithic imegrated circuits. Hybrid integrated circuits, which represent an area of ‘overlap between discrete and monolithic circuits, are not covered explicitly ‘The text of the book is comprised of fifeen chapters which follow a logical ‘sequence in the form of thre “sections.” The frst section of the book, comprised ‘of Chapters 1-3, reviews the basic “tools” of analog IC design and fabrication, ‘namely, process technology, IC components, and techniques for placing these ‘components on the chip, tht is, the chip layout. These chapters ae intended to {amiliarize the designer with the physical structures, advantages, and imitations of ‘monolithic components. This knowledge is imperative to an analog IC design engineer since a succesful design is one that efliciently utilizes the advantages of ‘monolithic devices while avoiding their shortcomings. ‘The second section of the text, made up of Chapters 4-6, covers the basic “building blocks,” orsubcrcuits, of analog IC design. One important chapter inthis section, Chapter 6, deals withthe use of MOS technology in analog or combined nalop/digital LSI design. All the subcrcuits covered inthis section serve as exsen- tial building blocks ofthe complex IC designs that are covered in the remainder of the book ‘The third and main section of the book, comprised of Chapters 7-15, covers the entire field of analog integrated circuits by dividing them into functional categories and then examining each category separately. Thus, for example, circuit classes such a8 operational amplifiers, multipliers, oscillators, phase-locked loops, filters, and data conversion citeuits are examined separately. In this section, particular ‘emphasis i given tothe recent developments inthe field of analog circuits, partc- ularly in the areas of switched-capacitor filters, switching regulators, voltage- controled oscillators, high-resolution data conversion circuits, and the precision reference circuitry astociated with them, Pat of the material inthis hook is patered after a sequence of graduate level ‘courses in integrated electronics which I taught at Santa Clara University. Therefore, ‘when preceded by courses on solid-state circuits and semiconductor electronics, this book will be well suited for senior or graduate level course. Tam grateful to many people who have contributed directly or indirectly to the ‘preparation of this book. In particular, I would like to thank miy wife, Karen, who has been a constant source of encouragement for me during the long years of effort that have gone into this book. I would also like 10 extend my appreciation to many ‘colleagues and associates in the IC industry for their assistance and guidance in the PREEACE wi ‘organization and technical accuracy of the ext. am particularly grail wo the management of Exar Integrated Systems, Inc.. for providing me the line 0 work ‘on this book, and to Ms. Sue Wooldridge who has patiently typed and eyed the draft ofthe manuscript several times over. ALAN B. GREBINE Saatogs, Calorie ‘ang 1585, CONTENTS CHAPTER 1. INTEGRATED-CIRCUIT FABRICATION 19. 110 un ne LB ha ‘The Planar Process 1 Electrical Resistivity of Silicon 4 Solid-State Diffusion 5 Epitaxial Deposition 12 Oxidation of Silicon 13 Photomasking 17 Ton Implantation 20 ‘Thin-Film Processes 22 Bipolar Integrated-Circuit Fabrication Steps 26 Moaifications of Basic Process 31 ‘Assembly and Packaging 38 Integrted-Circuit Packages 41 Testing of Integrated Circuits 46 Reliability Considerations 47 (CHAPTER 2. ACTIVE DEVICES IN INTEGRATED CIRCUNTS npn Transistors $4 npn Transistors for Special Applications 75 ‘pro Transistors #3 Junction Field-Effet Transistors 95 (MOS Field-Effect Transistors 106 CHAPTER 3. PASSIVE COMPONENTS: DIODES, RESISTORS, AND CAPACITORS Part | Integrated Diodes 3.1 Junetion Diodes 122 53 mm irr Part 34 33 36 37 38 39 Part 1 contents Schouky Diodes 126 Zener Diodes 120 Integrated Resistors Bs Diffused Resistors 136 Pinched Resistors 144 Epitaxial Resistors 147 Ton-Implanied Resistors 150 ‘Thin-Film Resistors 154 ‘Trimming of Resistors 155 Integrated Capacitors 160 3.10. Junction Capacitors 160 3.11 MOS Capacitors 164 CHAPTER 4. BIAS CIRCUTTS 169 4.1 Constant-Current Stages 170 ‘pnp Current Sources 183 Voltage-Contolled Current Sources 187 Supply-Independent Biasing 189 Voltage Sources 193 DC Level Shift Sages 197 ‘Temperature-Independent Biasing 204 ‘Stabilization of Chip Temperature 210 (CHAPTER 5. BASIC GAIN STAGES 28 sa 52 33 Differential Guin Stages 215 Gain Stages with Active Loads 233, ‘Ourput Stages 246 CHAPTER 6. ANALOG DESIGN WITH MOS TECHNOLOGY 263 Basic Characteristics of MOS Transistors 264 Building Blocks of NMOS Analog Design 271 ‘Analog Design with Depletion-Mode Load Devices 284 ‘Analog Design with CMOS Technology 290 MOS Voltage References 299 MOS Transisir as an Analog Switch 303 CONTENTS. CHAPTER mM 7. OPERATIONAL AMPLIFIERS. 309 Fundamentals of Operational Amplifiers 310 7.2 Cieuit Conhigurstions tor Monolithic Operational Amplilirs 320 7.3. Frequency Compensation 325 7.4 Large-Signal Operation 333 7.5 Input Stage Design 339 7.6 Practical Op Amp Circuits 350 7.7 MOS Operational Amplifiers 368 7.8 Special-Purpose Op Amp 375 1.9 Other Operational Amplifer-Based Circuits; Buffers and Comparators 383 CHAPTER 8. WIDEBAND AMPLIFIERS 397 8.1 General Design Considerations 398 82 High-Frequency Transistors 399 8.3 High-Frequency Device Models 401 8.4 Frequency Response of Single-Transistor Guin Stages 403 8.5 Compound Devices 410 8.6 Neutralization of Collector-Base Capacitance 415 8.7 Amplifier Citeuits Using Local Feedback 417 8.8 Amplifier Circuits Using Overall Feedback 423, 8.9 Dual-Loop Feedback Amplifiers 429 8.10 Root-Locus Techniques 433 8.11 Current Amplifiers: The Gilbert Gain Cell 437 8.12 Electonic Gain Control 443 CHAPTER 9. ANALOG MULTIPLIERS AND MODULATORS 451 9.1 A Classification of Modulators and Mulipiers 451 9.2. Properties of an Analog Multiplier 452 9.3. Applications of an Analog Mukiplier 454 9.4 Variable-Transconductance Multiplier 456 9.5 Four-Quadrant Multipliers with Wide Dynamic Range 450 9.6 Practical Analog Muliplier Circuits 462 9.7 Balanced Modulators 469 9.8 Applications of Balanced Modulators 472 CHAPTER 10. VOLTAGE REGULATORS, 481 Part | Series Regulators 482 10.1 Fundamentals of Series Regulators 482 a CONTENTS. 10.2 Protection Circuits 489 10.3 Practical Series Regulator Citeuits 497 10.4 Layout Considerations for Power Circuits 509 10.5 Tailue Mechanisms in Power Devices 312 Part It Switching Regulators sis 10.6 Fundamentals of Switching Regulators $4 10.7 Modes of Operation with Inductive Output Circuits 521 10.8 Efficiency Considerations 527 10.9 Practical Switching Regulator Circuits 528 (CHAPTER 11, INTEGRATED-CIRCUIT OSCILLATORS AND TIMERS SSI Part | Integrated-Circuit Oscillators sat 11.1 An Overview of Oscillator Types S41 11.2 Tuned Oscillator Circuits $43 11.3 Relaxation Oscillators 556 11.4 Emiter-Coupled Mulivibrators $71 11.5 CMOS Relaxation Oscillators. $81 11.6 Limitations of Relaxation Oscillators $86 11.7 Monolithic Wave-Shaping Techniques 591 Part I Integrated-Circuit Timers 599 11.8 Fundamentals of Integrated-Circuit Timers 599 11,9 One-Shot Timers 600 M110 TimesiCounter Circuits 609 Part Ill Frequency-to-Voltage and Voltage-to-Frequency Converters 615 T1.11 Voltage-to-Frequency Converters 615 M112 Frequency-to-Voltage Converters 622 (CHAPTER 12. PHASE-LOCKED-LOOP CIRCUITS er Part | Fundamentals of Phase-Locked Loops os 12.1 Principle of Operation of a PLL System 628 122 PLL in Locked Condition 635 123 Effects of Loop Filter and Loop Gain on PLL Performance 637 12.4 Applications of Phase-Locked Loops 647 Part lt Building Blocks of Monolithic Phase-Locked-Loop Circuits 657 12.5 Phase Detectors 657 CONTENTS, si 12.6 Voltage-Controlled Oscillators 668 12.7 Monolithic PLL Design Example 673 CHAPTER 13. INTEGRATED-CIRCUIT FILTERS, 9 Part 1A Review of Filter Characteristics ost 13.1 Basic Filter Specifications 681 13.2 A Review of Basic Filter Types 684 13.3 Biquadratic Filter Function | 687 13.4 Sensitivity Considerations 690 13.5. Analog Sampled:Data Filters 69% Part Il Switched-Capacitor Filters 703 13.6 Fundamentals of Switched-Capactor Circuits 703 13.7 Characteristics of MOS Circuit Elements 712 13.8 Effects of Parasitic Capacitanees 719 13.9 Practical Design Constraints 725 13.10. Second-Order Filter Configurations 727 IBAL Higher Onder Filters 739 13.12 Applications and Limitations of Switched-Capacitor Filters 750 CHAPTER 14. DATA CONVERSION CIRCUITS: DIGITAL-TO-ANALOG CONVERTERS 753 14.1 Principles of DA Conversion 754 14.2. Basic D/A Converter Circuits 757 14.3 Definitions of DYA Converter Terms 76 144 DIA Converter Architecture 770 14.5 Current Switches 780 14.6 Resistor and Capacitor Networks 785 14.7 Voltage References 750 14.8 Biasing of Current Sources 791 14.9. Bffects of Device Mismatches 795 14.10 Accuracy Considerations 799 4.11 Monolithic Design Examples 802 14.12. Ultraprecision DVA Converter Circuits 817 CHAPTER 15. DATA CONVERSION CIRCUITS: ‘ANALOG-TO-DIGITAL CONVERTERS 25 15.1 Fundamentals of A/D Conversion $27 15.2 Integrating-Type A/D Converters 835 133 134 re 157 58 59 INDEX ‘CONTENTS. Digital-Ramp-Type A/D Converters 846 ‘Successive-Approximation A/D Converters 847 Priel A Conners 63 ne MOS Testi, 80 BIPOLAR AND MOS Notined iD Comerer fr Teeconmuestons 873 ‘ANALOG INTEGRATED ‘An Overview of A/D Converter Techniques 876 CIRCUIT DESIGN CHAPTER ONE INTEGRATED-CIRCUIT FABRICATION ‘The sim of this chapter isto familiarize the reader with the fabrication processes for analog integrated circuits. As a designer, one does not need to know the specific details of each and every process step, since these fabrication processes ‘often become, by themselves, areas of specialization and rapid technological ‘development, However, these manufacturing processes determine the capabili- and limitations of monolithic integrated-circuit (IC) products. Therefore, it is imperative at all times that a successful design engineer be familie withthe fundamental properties and the constraints of each of the major process steps in the fabrication of integrated circ ‘THE PLANAR PROCESS. ‘The fabrication of a monolithic integrated circuit involves a complex sequence ‘of processing steps. Even though the specific nature ofthese processes is well ‘diversified, the bulk of the manufacturing steps associated with the present-day IC technology can be grouped under the term planar process." Prior 10 the invention of the planar process in 1959, the solid-state electronics eld was ‘dominated by germanium devices, Introduction of the planar process has revo. Iutionized the field of microelectronics almost overnight; and silicon, ther than ‘germanium, emerged as the predominant semiconductor material ‘When exposed to air, silicon forms an insulating oxide layer, called silicon (1.10) where t,t, fy, . - . are the different diffusion times, and Dy, D3, Ds, .. . are the comesponding diffusion coefficients as determined by the respective tem- Peratures of the diffusion cycles. Thus, for example, in the planar device fabri- cation, the emitter region ofa bipolar transistor is formed by a diffusion process which succeeds the base diffusion step. Therefore, the effective Dr product of the base region contains a finite contribution from the emitter diffusion step. 1.3 SOUD-STATE DIFFUSION " FIGURE 1.6. Vales of te complementary enor fncton (ere) sad the Gain eben at fests 2,_‘The diffusion profiles of Eqs. (1.8) and (1.9) are both functions of (VD). ‘Therefore, tor a given surtace and background concentration, the junction depths x, and x associated with the two separate diffusions having “different times and temperatures, can be related as x | Bin S- Vae aay 3. The diffusions proceed sideways from a diffusion window es well as downward. In considering the lateral dimensions of the planar device, particu- larly in the case of lateral pnp transistors and MOS transistors, these lateral 2 INTEGRATED-CIECUIT FABRICATION. ‘diffusion effects need 1 be considered. Typically, the lateral diffusion distance is about 75-80% ofthe vertical penetration, 144. EPITAXIAL DEPOSITION Epitany is a deposition technique where the single-crystal structure of a silicon substrate can be extended by vapor phase deposition of additional atomic layers of silicon. Epitaxial growth, or deposition, is carried out in a special furnace called a reactor, where silicon wafers having clean and chemically polished surfaces are heated up to temperatures comparable to those encountered in the Aiffusion step (.e., 1000"-1200°C). During the epitaxial growth, vapors con- ‘wining silicon are passed over the heated substrate, Normally hydrogen is used {asthe carer gas, with ether silicon tetrachloride (SiCl,) or silane (SiHL,) as the Source of silicon. Normally the SiCl, process requires somewhat higher tem peratures than SiH, decomposition, and also has a slower growth rate. During the expitaxial growth process, the source compound is chemically reduced, resulting in fee silicon atoms, some of which are deposited on the single-crystal substrate. Under proper deposition conditions, the interatomic forces of the single-erysal silicon lattice constrain the deposited silicon atoms to follow the original crystal structure, Thus, structurally, the deposited epitaxial layer forms «continuation of the original crystal structure ‘During the process of epitaxial growth, controlled amounts of p- oF n-type ‘impurities are also introduced into the carrier gas to contol the type and te sistvity of the deposited layer. Unlike the diffusion process, epitaxial growth proceeds by uniform addition of atomic layers onto the substrate. Thus, the ‘dopant impurities are uniformly distributed through the epitaxial layer, and do ‘not show a concentration gradient. Furthermore, epitaxial layers can be grown, ‘over diffused regions or over other epitaxial layers. Redistribution of impurities during Epitaxy Since epitaxial growth is a high-temperature process, the impurities at the inerface of the epitaxial layer (epi) and the substrate tend to redistribute them. selves via the diffusion process. For example, in the case of an n-type epitaxial layer grown on a p-type substrate the epi-substate interface no longer repre- Sens a step junction, but becomes graded due tothe diffusion of impurities from ‘the epitaxial layer into the substrate, and vice versa. Consequently, the impurity distribution atthe epi-substrate interface may look as illustrated in Figure 1.7. ‘The dashed line shows the ideal p-type impurity distribution atthe interface, and the solid line corresponds to the actual distribution, For relatively rapid rates of epitaxial growth (ie., > 0.2 jm/min), the im- Purity distribution N(x, ¢) across the interface can be written as 1A EPITAXIAL DEPOSITION 3 | we a * le eases FIGURE 17. Inpuriy tein ae seat ineriaedaring whet asl th and Mw ete: a) 1.12 Ns 2° \3Vp; oe ‘where Ns isthe impurity concentration within the bulk ofthe substrate. The total amount of intediffusion across the epi-substate interface during the entire Oridation proceeds by an inward mation of the oxidizing species toward the silicon-SiO, interface. Therefore, a the oxidation proces proceeds is neces- Sary forthe oxygen molecules to diffuse dough a thicker layer ofS}, to get to te silicon surface where the chemical reaction (1-13) or (0-14) can take place. Consequently, the time rte of oxide growth decreses rapidly with ‘thickness. It can be shown" that for very thin layers of SiO;, time, However 8 the oxide thickness, increases, the growth rate becomes proportional to Vr. “The practical thicknesses of thermally grown SiO, layers used in monolithic IC fabrication ae inthe range of $00-20,000 A (10,000 A = 1 um). The lower limit of thickness is often dictated by electrical breakdown of random defect, densities (i... pin holes) in the oxide layer. The upper limit i set by required % INTEGRATED CIRCUIT FABRICATION. oxidation sme and teil of hing he onde ayer ding the phat masking step. * Masking Properties of SiO, ‘The diffusion coefficients of most dopants in SiO, are about two to four orders ‘of magnitude smaller than those in silicon. Therefore, for these impurities, ‘which include all those listed in Table 1.1 with the exception of gallium. an SiO, layer of proper thickness can serve as a diffusion barrier. The minimum oxide thickness necessary to mask against a given diffusion step depends to a large ‘extent on the specifics of the diffusion process, such as type of dopant used, surface concentration, predeposition temperature, and time. Figure 1.8 gives some typical curves showing the minimum oxide thickness needed to mask ‘gainst the two most commonly used dopants, boron and phosphorous.” Several positively charged ionic species, such as sodium (Na " )or hydrogen (HJ ions, can diffuse through the SiO; layer with relative ease at temperatures 8s low as 150°C. Therefore, oxide passivation is prone to ionic contamination. ‘These ions tend to generate a positive space charge within the silicon-SiO, interface, which in tum leads to an increased free-electron concentration of the silicon side of the interface. As a consequence, the surface layer of silicon directly against the SiO, layer tends to appear less p type or more n type than ‘would be expected from the dopant impurity concentration. This effect, when ‘coupled withthe depletion ofthe p- type boron concentration during the oxide ‘growth cycle, may result inthe formation of a parasitic n-type inversion layer at the Si-SiO, interface. This parasitic inversion layer, known as channeling, is ' dominant failure mechanism for integrated devices containing lightly doped D-type regions. It can be eliminated by maintaining a relatively high surface ‘concentration of boron within the p-type regions (typically = 10" atoms/em’) and by avoiding ionic contamination ofthe SiO; layer i i i P| coe ANGURE 18, Minima onde thoes eid 19 mu ssn fii fo) Howe ad |. PHOTOMASKING "7 ‘Chemically Deposited Oxide Layers ‘Sometimes it is advantageous to form an inert dielectric coating over the surface ff the integrated circuit by pyrolytically depositing an oxide layer Such & deposition process is often referred to as chemical vapor deposition (CVD) step. During the CVD step, the silicon wafer is maintained at a relatively ow tem perature (typically 400°C). Thus, such a step is particularly useful us a final passivation layer over the IC surface, subsequent o the completion of the metal interconnection or the thin-film deposition step, and protects the deviee surface fiom mechanical damage or scratches. Silicon Nitride Passivation Silicon nitride (SisN.) is far more resistant to {onic contamination than SiOs ‘Therefore, itis frequently utilized as a passvating layer for IC structures whose performance can be easily degraded by surface contamination. This is particu- larly true for analog integrated circuits involving MOS devices or operating a low current levels. An additional advantage of SiN, over the thermal'y grown, ‘oxide is its superior masking properties against the dopant impurities. Even such dopants as gallium, which readily diffuse through SiO,, can be effectively masked by SiN The SisNi, passivating layer is most conveniently formed by a pyrolytic deposition process at a temperature range of 800-1000°C. “The deposition is obtained by the decomposition of SiH, and ammonia (NHs) in the presence of hydrogen gas, in accordance with the reaction 3 SiH, + 4 NHy— SiN, + 12H, is) Silicon nitride is often used 10 complement the SiO; passivation process. In such an application, a layer of SisN, (typically 1000 A thick) is sandwiched between two SiO, layers on the wafer surface to provide an added degree of surface passivation. The second layer of SiO; over the nitride layer is normally formed by pyrolytic deposition, This second oxide layer also serves as a mask ‘during the photomasking and etching ofthe contact windows through the nitride layer. 1.6. PHOTOMASKING ‘The initial layout of an integrated circuit is normally done at 4 scale several ‘hundred times larger than the final dimensions ofthe finished monolithic chp. ‘This initial layout is then decomposed into individual mask layers, each corre sponding to a masking step during the fabrication process. The individual mask layers are then reduced photographically othe final dimensions ofthe imegrated unit. The reduced form of each of these patterns is then contactprined on a transparent glass slide to form a photographic mask ofthe pattems tobe etched INTEGRATED-CIRCUIT FABRICATION. ‘on to the SiO; surface. To facilitate batch processing, a large number of such ‘masks are contact-printed on the same glass slide, forming a masking plate. The plate is sufficiently large to cover the entire surface of the silicon wafer o be ‘masked. Ths, in single masking operation, an array of a large nutnber of ‘identical masks can be applied simultaneously over the wafer surface, During the masking operation, the mask patter is transfered from the mask- ing plate tothe wafer surface by photolithographic techniques. The wafer surface ‘to be masked is intially coated with a photosensitive coating known as photo resist of resist. The resist-couted wafer surface is then brought into intimate ‘contact with the masking plate and exposed under an ultraviolet light. The Portions ofthe photosensitive resist not covered by opaque portions of the mask polymerize and harden asa result ofthis exposure. Then the unexposed parts of the resist can be washed away, leaving a photoresist mask on the wafer surface ‘As consequence of the masking step, the pattem tobe etched through the oxide is transferred to the wafer surface in the form of a hardened etch-resistant photoresist pattern ‘The photomasking step is followed by an etching step during which the pars of the SiO; layer not protected by the exposed resist mask are etched away, forming the diffusion or the contact windows on the oxide. In this process. & buffered hydrofiouric acid (HF) solution is used as the etchant. Following the etching step, the photoresist is washed away by a special cleaning solution, and the silicon wafer is ready forthe next diffusion step. A similar photomasking step is also used in forming the metal interconnection patterns. The typical Sequence of steps in the photomasking process is illustrated in Figure 1 Dimensional Tolerances In most monolithic circuit structures, the lateral dimensions of the integrated ‘components are determined by the limitations of the photolithographic reduc- tion, masking, and etching processes. The two fundamental limitations on the photolithography process are the alignment and the resolution of the mask pattems. ‘Since the monolithic IC fabrication steps require the successive application of ‘a number of masks, itis necessary that each new mask applied to the silicon surface align withthe previous set of masks over the entre surface ofthe wafer, ‘This requires a good degres of dimensional accuracy associated with the initial layout of the circuit. To ensure this dimensional accuracy, the initial layout is carried out at the largest possible magnification within the capabilites of the Photoreduction system. Typically, a 500% size is preferred forthe initial layout for circuits having final reduced dimensions of up to approximately 70 sq mils. For larger overall chip dimensions, a smaller initial layout sale, such as 400x , ‘may be preferred to avoid optical distortion during the reduction process, Note that the drafting inaccuracies associated with the intial layout are also reduced at the same scale asthe original layout. Thus, for example, a 0.01-in. dimen- US PHOTOMASKIN o feted ” FAGURE9._ Typ one fis nh hocrasing oe which ena ion window pate the SO, ayer at pica te pater on etapa (Gringo ae aie, ing no pcr od ar nr ng pa Nk fis) devlopiog sd ectng phoresis ()cehng theese SO, oye and Sp Focus to depths tion was ihe S10, er sional inaccuracy inthe initial layout leads to a + 0.5-1 jem error inthe final dimension at a $00% reduction. ‘A possible source of error inthe masking step isthe tolerance associated with the “step-and-repeat” process in contact-prnting the mask array on the masking plate. The source of error in this case is the mechanical advance mechanism involved. An additional factor limiting the alignment tolerances of a mask set is » 1 HEGRATED-CIRL._. FABRICATION the accuracy of positioning the mask on the wafer surface. This is done with the id of a mechanical alignment jg under a high-powered microscope. However, itis ill subject to some operator eror. To minimize the alignment erors a the stage of the masking operation, itis customary to use concentric alignment palters on successive mask layers. The alignment accuracy fora typical mask set, under production conditions, is approximately 1 jum for concent “The ability of the mask to define or reproduce fine details on the wafer surface is determined by the resolution of the photomasking step. A good measure ofthe resolution is the minimum line width needed to resoive, reproducibly, two parallel ines spaced on line with apart. The main limitation tothe resolving power of the photomaskng techniques are the statistical uctuations in the ‘molecular structure of photographic emulsions andthe diffraction ofthe light at the mask edges. At present, the minimum line width that can be resolved under production conditions is approximately 2 um ‘The etching step also introduces random iregulaites, or errors, which tend to reduce the overall mask resolution. The grainy structure of the exposed and polymerized photoresist does not define a te edge during the etching step, but an cause random irregularities of the order of 0.5 jm along straight edges This effect, along with the nonuniform etching properties of the oxide layers, ‘so tends io round te sharp comers on the masks to atypical radivs of 2-3 gm ‘At present, the minimum dimensions of a diffusion window that canbe formed routinely under production environment is approximately 4 ym % 4 yn. How- cover, thse dimensional tolerances can be improved significantly by using more advanced and complex pattem-forming techniques, such as electron-beam photolithography”. 1.7. ION IMPLANTATION In the ion-implantation process, the impurities are introduced into silicon by the wafer surface with high-energy ions of the desired impurity ‘ype. The implantation operation takes place in a vacuum, Impurity ions are accelerated from an ion source, and a mass spectrometer is used to separate the undesired impurities from the beam. The ion beam is then focused toa small area Aypically smaller than | in”) and is scanned across the semiconductor wafer ‘which serves asthe target. During the implantation process, the depth of ene- ‘tation of the impurity ions into the silicon latice is controlled by their energy, ‘which is set by the accelerating field; and the density of the implanted ions is controlled by the beam current. Typical energy levels used in the ion- implantation process ae in the range of 30-200 kilo-electron-vols (keV). When ions penetrate the silicon wafer, they produce latice defects or dislocations. ‘These are removed by annealing the wafer at temperatures as the order of| 500-600°C, subsequent tothe implanation step. ‘The impurity profile resulting from ion implantation has a Gaussian distribu- 17 JON IMPLANTATION. a Impurty concentration tee fl = beat to scan FHICURE 1.10. Typ dstibton of implanted inp eons in in. tn whe ea fe baton pening ew te fe te ion vals as shown in Fp 110, The pal fhe ion sa ay AG ced he mean rng, whhinceases insane eer themida on Te rine yea of he danas ese ot is standard deviation, iy the ealve spe ee me Gepedso rao Stet tence ot has a aa a Henvierom pode namower protien Te Pa aie a Xpand A sold wih aos pu tee a TABLE 1.2. Mean Range Xan Spread AX of planted ty Various Dopans at Oierent pant Energy Levene : Implant Energy Level eV) Dope inn ery Level ev) Iprty x % ea 7 Boon ium 008 1s2 20 ae eum oars das ar te ism 003 002 ome on os sxtim Gores oss re ous = bons Zum == — 0010002087 on som = oon tos gan, a 2 n INTEGRATED CIRCUIT FABRICATION. “The semiconductor surface can be easily masked against the implanted ions by using a surface oxide (Si0,) layer as a mask. Thus, the ion-implanted regions can be readily patterned con the silicon surface, in the same manner as the masting technique can be used, In this process atin layer of metal fm (ypically copper is deposited aad etched into an inverse, or negative, of the deste inal metal pattern, Then the desired thin-film layer is deposited on this inverse meal patter. Inthe fina etching ep, the inverse meal patter ofthe inital metal film is eched away, taking wi the layer of desired metal deposited ont, and only the portions of the desied metal layer tat adhere directly tothe sibtate are let behind, Interconnections and Ohmic Contacts ‘The basic prerequisite for the conductive films used for interconnections is that they should make good ohmic contact with the diffused components or other metalic films deposited on the device surface. A good ohmic contact is defined as one that exhibits a linear current-voltage (I-V) relationship which passes though the origin ofthe I-V characteristic. Ina great majority of IC applica- tions, aluminum is used asthe interconnection layer. This is because ofits ease “Ls THIN-FUM PROCESSES B of deposion and paterning, as well a its high degree of conductivity and ts BBY to form ohmic conti with silicon The expos of contact set 0 he ambit amosphee fen wu in te formation of parasite oxide lajers over the chip aeas to be imramncted. Therefor, to provide good ohmic contact, the Interconsctng els must be hemialy active sothattcan be alloyed tough these ants onde lane ‘The most commonly used interconnection etal aluminum, Hesn be ay alloyed into the silicon substrate to form ohmic contacts Since slums ype dopant (ee Table 1), to avo the formation of noob eying Cont the cotact reas onthe ighly doped nye emicondaror sets oe 2° doped prio to mealization (se, for example, the collector contr of he pn bipolar transistors of Figs. 1.13 and 1-14). The heay n” doping cubes a high degree of damage to the silicon iste atte surface ‘Tertore, he parasite pm junction formed by the alloying of p-type alumnim ney onncton into n-type silicon is very lak an eal ohms non Properties, In conventions! monolithic IC fabrication, the alloying ofthe aluminum imereomeston ino silicon is the last step of the planar paces Ie isrormaly accomplisied bya short heat teainent in an incet atmosphere, piel aoe TO min at sore ‘A oublesome meal interconnection problem can oevut in devices which employ two active dissimilar metals in their intreonneston whores Are interface of two disimilr metals, parasite intermetallic compounds nel ies can form, typical example of iss the inermcalic wold soning Bounds fomning beeen the aluminum bonding pads ao the old ces maybe used to connect the chip (othe package terminals Thee conseunne ‘hich ae brite and noncondusve, are commonly refed toa he as Bogue” because of ter dark color. Under certain cumsunes (os Soa 1.14) this may be a detriment othe rlubliy IC neon en f0ld-wire bonds and aluminum bonding pas. Although aluminum sa good conductor it silinroduces aie anount of sete resistance int the device interconnections, Typical eva of ns ‘pum is of the order of 2.8 x 10° ohm-cm. In the case of a ‘typical aluminum interconnection tace of Im thickness ths conespondh tog cer ae of approximately 0.03 112 ner very high cument denies, conductive thin fms suchas ahininum exhibitafailre mode due tothe so-alledelecromigrationelees ons an metal atoms to gradually mignte away ffom the highouree dena ine within the conductor. This isa progressive fale tole, nies sees operation, and comes about rom the momentum exchange Seneca ees ing elecwons and the stationary metal som. Eletomigraion i cleo cy hich speds up athe curemtdeasity othe tempers is motenee ace 2 3 fomation of localized vous, or gaps nthe conducting Rena aie evenly leads toa complet ope ct he pointe high within the conductor strip. ® * » INTEGRATED-CIRCUIT FABRICATION ‘To avoid electromigration effects, current densities in the IC interconnection ‘paths are normally kept at less than the 10'-A/em* level. Inthe case of atypical {luminum interconnection path of 1-am thickness, this corresponds to @ max: {mum allowable continuous current of approximately 50 mA per mil width of the interconnection path. 1.9, BIPOLAR INTEGRATED-CIRCUIT FABRICATION STEPS “The fabrication ofa bipolar integrated circuit involves a sequence of five to eight masking and diffusion steps. ‘The sequence of some of these basic steps is illustrated in Figure 1.11 for the case of an npn bipolar transistor and a p-type diffused resistor. 1.9 BIPOLAR Ns. .RATED-CIRCUL, . ABRICATION SERS y pte base atusions so arid er zat! Fone ty se. FIGURE 1.11. Basic sequence of sep a te fbicon of iol monolithic cre ati Cridaion sal baie lper iffuin: (2) expsial yer pow and econ oration: (lta ‘tee: tae foe, () nei fs; contact windows and neon suofirate o 2 simi al of pp mop he acme i tele es only ime oF ec ati ine Dmenn conn TS tas A ee he ire anya a Sct yicene gaara, is called a buried layer, andthe corresponding diffusion is called the buried layer Si tame ae tena tet ise mpasetersza amen a ‘in Wis coos, the + sign is sed w imply hey impurity concenetio, nt lec charg, » INTEGRATED-CIRCUN FABRICATION ‘are chosen because they diffuse slowly and, thus, do not redistribute signif ‘cantly during the subsequent diffusion steps. “After the buried layer diffusion step, the oxide covering on the wafer is stripped and an n-type epitaxial layer is grown over the entire wafer surface. as ‘Shown in Figure 1.11b. The thickness and the impurity concentration of this epitaxial layer determine the breakdown voltage ofthe resulting transistor struc- ture. Assuming @ minimum transistor breakdown voltage LVceo of 30 V is ‘required, the epitaxial layer will be chosen to be approximately 15 jum thick, with an impurity concentration of 2 X 10! atoms/em, which corresponds to a resistivity of approximately 2.5 {em (see Fig. 1.2). Note that, as shown in Figure 1.116, the n-type buried layer also out-diffuses somewhat into the epitaxial layer during this process. Following te epitaxial growth, an oxide layer is formed on the wafer surface. ‘Then, after a masking step, a p-type (boron) diffusion is made, as shown in Figure I. 1c. The function ofthis diffusion isto form the deep p-type isolation walls, which reach through the n-type epitaxial layer into the p-type substrate Because of the depth to which this diffusion must penetrate, it requires several hours of diffusion time at temperatures in excess of 1200°C. The sheet resistance ofthe p-type isolation diffusion is in the range of 20-40 £10, Note that the 1n-type buried layer diffusion is omited in the regions directly under the iso- lation diffusion, and that the n”-type buried layer does nor touch the p-type isolation wall. This is done to avoid forming a low-breakdown p-n junction between the n-type tub and the p-type isolation; and to ensure that the p-type isolation wall can reach down to the p-type substrate, thus forming a continuous wall surrounding the n-type tub. ‘The next masking and diffusion step (Fig. 1.11d) forms the p-type base region of the npn transistor, It results in a sheet resistance in the range of 100-200 2/0 and a junction depth of 1-3 um. Since ths diffusion also forms many of the resistors in the circuit, its sheet resistance is closely controlled to be within +20% of the target value. Following the base diffusion, the n-type emitter regions of the npn transistor sare formed by the emitter mask and the subsequent emitter diffusion step, a8 shown in Figure 1.1 le. Normally, phosphorus is used as a dopant forthe emitter diffusion, The resistance of the emitter diffusion is ofthe order of 2-10 910, and the resulting junction depth is in the range of 0.5-2.5 um. Since the difference in the junction depth of the base and the emitter diffusions determines the base ‘width of the npn cransisior, the depth of the emitter diffusion is controlled to be approximately 0.51 ym, less than that ofthe base diffusion. The heavily doped (a*-type) emit diffusion also serves asa low-resistance contact to the n-type epitaxial layer to form the ohmic collector contact for the transistor. This is ‘necessary because a direct ohmic contact between the aluminum interconnection ‘andthe lightly doped n-type epitaxial region is dificult to form (see Section 18). “Alter the emitter diffusion, the wafer undergoes # masking step called the ‘contact mask, wiich opens ail the contact windows over all the passive and "9 POLAR INTEGRATO-CRCUIT FABRICATION ES » sctve devices onthe chip. Them the ene wafer is outed with a hin wafer is costed with a thin ayer of alumina (0.51, wich wil form 2 conductive interconnection pan Between he devices. Then, nthe nest asking sep calle te mlm te aumioum is thet aay, leaving behind the dened meron pit tween the components onthe chip. The resting device sete shown Figure 1.11f. ° * “ns " Figur 1.12 shows a plane view of he compl 3 completed device src of Figure 11 Forisratve purposes, the oletor of he npn arson ou fo be connected tothe resistor form asm common emiter apie stage Figur 13 shows they impaniy concentration thine eel sts ston ofthe esuling tans sirctre. Assuming a bse depth ou sod anemiter depth of 28 um, a ace wid of “0.3 pimis shred Aon, tha the w'-ype buried layer has omditasedappronimatly 6 yn ‘nominal epi-substrate interface, » 6 Ain fom the cones SS ts Resistor, Sail cietion he out @ CURE 112, ane view fir ness combiatn how iii hseaig nection STMT Gin tage: a) Plane vw fcc lajot o) equvlem ce INTEGRATED-CIRCUTT FABRICATION oe Emitter Pintertoce ~— pe et te rot fe Ne eee | st “ Sr, Distance = (4m) pana yer cencervaton Wo) FIGURE 113. Device css seton an pi iaparty pale for x monolibic yp amis: dese ces etn () inpnty pose slog 4-4 sk ep, te normal fvicatin proces, sbsetet ote metal mask Sep, sin wafer undergoes analy ce uiner sepa ow temperatures (PAY $ dma SFC) xe oper ohm cont ees sin Fruronnon an the cote windows on he wafer ure. Fal. Stee ae le depron wae orc wing ower Steal Sete 3) fom sation ayer ner ct hip Sef wh abo cover tc dminun fersmeston Fly pesatn SITE plete te siton wale toch ge windows on topo he beding son be IC cio whch enc onsestions il be mae. The prose rn puso layer sw prec the hp sure from i, mechan dhnage ad sera "Alt compcion af the sequence of fibration eps decid above, he salt son wafers ey fr vation ae uncon etl esting ind eat Chie “ oF aay thewafes peed though ie aricion proces eps in oops 140 MODIFICAT. 45 OF BASIC Ph ESS ” called Lots, with typically 15-25 wafers to a lot. Thus, many wafers, each containing hundreds of complex circuit chips, are manufactured simukancously, This batch processing capability of the planar process, which enables one t0 fabricate thousands of circuits in one process sequence, isthe key t the eco. nomic advantages of integrated circuits 1.10 MODIFICATIONS OF BASIC PROCESS The vast majority of the monolithic bipolar analog circuits presendy in pro- duction are fabricated using the basic Sequence of steps illustrated in Figute LIL, However, when certain performance characteristics are required, addi- tional steps can be incorporated into the basic manufacturing sequence 10 en- hhance such characteristics. Some of these modifications will be briefly discussed inthis section. Although these modifications improve specific device character istics, they often require addtional process steps or tighter process controls and, thus, add to the manufacturing cost of the monolithic circuit. Dielectric isolation In certain circuit applications, the parasitic capacitances, leakage curents, and ‘breakdown characteristics associated with the conventional junction isolated ‘device structures may not be acceptable. Typical examples of such applications are circuits that must operate at high frequencies or very high voltages (ie, in excess of 100 V) or circuits that must withstand high amounts of ionizing radiation (such as gamma rays) without suffering permanent damage. In such ‘cases, superior electrical isolation can be obtained by surrounding each n-type Pocket or tub not with a reverse-bias p-n junction, but with a dielectric layer. ‘Normally, thermally grown SiO, is used as the dielectric material In forming the dielectrcally isolated pockets on the wafer surface, « number of alternate fabrication techniques can be utilized. ©" Figure I. 14 shows atypical sequence of fabrication steps in forming the dielecrically isolated single-crystal silicon pockets or islands. Starting with an n-type substrate, @ nonselective n-type layer is diffused into the wafer surface, For reasons which will be explained shortly, a < 100 > oriented crystal is utilized asthe starting material, 88 opposed to the < 111 > oriented crystal normally used for junction iso. lation.* Following the inital n* diffusion, the wafer surface is oxidized, and a mirror image mask ofthe desired isolation grid pattern is applied tothe wafer to remove the Oxide along the isolation grid. The exposed silicon surface is then ciched by Dering he inti slicon crystal growth, the oriented crystal esc o grow delete then the <100> orientation and, hereore, some less expensive. te adivon Be III ‘ysis les afeted by surface contamination than the <100> crysal These it he conn ‘extons forthe hoie ofthe <111> orem bse for mon tiple deve orcas £1007 antes Sequence of sep in leetsectton proces (2) A” aye fon and peng of ‘aca window, () ching of Hilalon mows; ()foming SiO, dete her and growing jeri slicon ner, Yoming icles ype pocket by ging aay shart uni ek of V goove appear 110 MODIFICATIONS OF BASIC PRE £5 » 4 potassium hydroxide (KOH) based etch. The etchant used in this sep etches Away the exposed silicon anisotropically, that i, the etch rate is mach faster along the {111} planes than along the (100] crystal planes. This preferential fetching results in formation of a V-shaped isolation groove or mout onthe watet surface, as shown in Figure 1.146, Referring to Figure 1.146, i should be noted that the vertical dimensions of the drawings are not to scale, and the depth dof the isolation moat is « small fraction of the total wafer thickness. After the preferential etching step, the ‘exposed silicon is reoxidized, and a thick layer of polycrystalline silicon is

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