Design Logic Circuits

Boolean expression can be implemented using logic gates

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 Design Logic Circuits
Implement the expression as given using the
available gates, otherwise:
 From the specifications of the circuit, determine the
required number of inputs and outputs and assign a
symbol to each.
 Derive the truth table that defines the required
relationship between inputs and outputs.
 Obtain the simplified Boolean functions for each
output as a function of the input variables.
 Draw the logic diagram and verify the correctness
of the design (manually or by simulation).
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 Design Logic Circuits
Example: Design a code convertor to convert BCD to Excess 3
Input BCD Output Excess-3 Code
A B C D w x y z
0 0 0 0 0 0 1 1 The remaining
0 0 0 1 0 1 0 0 Input
0 0 1 0 0 1 0 1 Combinations
0 0 1 1 0 1 1 0 generate don’t
0 1 0 0 0 1 1 1 care cases as
0 1 0 1 1 0 0 0 they don’t
0 1 1 0 1 0 0 1 exist!
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
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 Design Logic Circuits
X: Z:
CD
00 01 11 10
CD
AB AB 00 01 11 10
00 1 1 1 00 1 1
01 1
01 1 1
11 d d d d 11 d d d d
10 1 d d 10 1 d d

Similarly:

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 Logic Gates
 Gates AND/OR/NOT are enough to
build any Boolean function
 Other gates are used because:
 Very useful (no choice), Ex: XOR for
parity bit
 Save transistors number
 Self sufficient (can build any gate
from it) NAND/NOR: save, self
sufficient
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 Exclusive OR Gate
A A B F
F
B 0 0 0
0 1 1
 XOR gate is defined by the relation: 1 0 1
F = (A⊕B) and/or by the shown truth table. 1 1 0
 F can be rewritten as:
F = A'B + AB'
 ⊕ is commutative, i.e. a ⊕ b = b ⊕ a
 a ⊕ 0 = a,  a ⊕1 = a'
 a ⊕ a = 0,  a ⊕ a' = 1
 ⊕ is associative, i.e. a⊕(b⊕c) = (a⊕b)⊕c
= a⊕b⊕c
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 Exclusive OR Gate
a
a⊕b
b
F = (a ⊕ b) ⊕ c
c

a
G = a ⊕(b ⊕ c)
b b⊕c
c
Similarly:
F = (a ⊕ b) ⊕ c
G = a ⊕(b ⊕ c)
= (a'b + ab') ⊕ c
= a'b'c + a'bc' +
= (a'b + ab')'c + (a'b + ab')c'
ab'c' + abc
= (a'b)'(ab')'c + (a'b + ab')c'
= (a + b')(a' + b)c + (a'b + ab')c'
= abc + a'b'c + a'bc' + ab'c' Note: Odd Number of
inputs are one!!! 10
 Exclusive NOR Gate
 Inverse of Exclusive OR (Equivalence)
a F = (a ⊕ b⊕ c)'
b
c

F = (a ⊕ b⊕ c)'
= (a'b'c +a'bc' + ab'c' +abc)'
= (a'b'c)'(a'bc')'(ab'c')'(abc)'
= (a +b + c')(a + b' + c)(a' +b + c)(a' +b' + c')
= abc' + ab'c + a'bc + a'b'c'
Note: Even Number of
inputs are one!!!
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 NAND Gate
A A B F
B
F 0 0 1
0 1 1
1 0 1
 NAND gate is defined by the relation: 1 1 0
F = (AB)' and/or by the shown truth
table.
 F can be rewritten as:
F = A' + B' which leads to the
equivalent symbol shown.
A
F
B
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 Extending from 2 to 3 inputs
 It is easy to extend the 2 input gates to 3 inputs if
they are commutative and associative
 AND, OR, XOR, and XNOR are commutative and
associative
 NAND is not associative!!!
x F
y (yz)'
F = (x(yz)')' = x'+yz
z
x
(xy)' G = ((xy)'z)' = xy +z'
y
G
z
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 NAND Gate
 NAND gate is self sufficient
(i.e. can build any circuit from it)
 Can be used for building
AND/OR/NOT gates
 Build NOT gate using NAND gate:

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 NAND Gate
 Build AND gate using NAND gates:

 Build OR gate using NAND gates:

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 Build using NAND gates
 One can build Boolean circuits for any
Boolean expression using NAND
gates.
 Steps:
 Obtain sum-of-product Boolean expression
• E.g: F = xy + yz
 Use DeMorgan theorem to get expression
using two level NAND gate

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Construction of SOP Expression
Thus, any SOP can be
implemented by a 2 level
NAND combinational
Circuit
Note that the circuit is
equivalent to:

And the bubbles cancel out

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 Construction of SOP Expression
 Any Sum-of-product expression can be
built using:
 Two level AND-OR gates.
 Two level NAND-NAND gates.
 Two level AND-OR gate for:
F = AB + CD + E

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 Construction of SOP Expression
 NAND-NAND circuit:
 Replace Each gate with its equivalent
NAND gate(s)
A
B
C F
D
E

 Now Remove any two successive invertors.

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 Analysis of NAND Circuits

X=ABCDEF

= A B C D + EF

= A B C D + EF

= (AB + C)D + EF

= (AB + C)D + EF
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 Analysis of NAND Circuits

Which can be redrawn as:

Cancel Bubbles
Cancel Bubbles

Bubble C'

Cancel Bubbles

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 Analysis of NAND Circuits
 Starting from the output divide the circuit
into levels, output gate(s) being at level 1.
 Gates whose outputs lead into level i will
be labeled as level i + 1
 If a gate’s output is connected to the inputs
of gates at multiple levels, duplicate it and
label each by its appropriate level.
 Replace gates at odd levels by ORs and
those at even levels by ANDs
 Direct inputs to odd levels MUST be
complemented.
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 Analysis of NAND Circuits
b a
3 2 F
a
1
c 3,4
d 2

b' a
a 3 2
c 4 F
1
a'
c' 3 2
d

F = a(b'+ac) + d(a' + c') = ab' + ac +a'd + c'd 23

 NOR Gate
 NOR gate is also self sufficient
 Can be used for building
AND/OR/NOT gate
 Build NOT gate using NOR gate

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 NOR Gate
 Build AND gate using NOR gates

 Build OR gate using NOR gates

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 Build using NOR gate
 One can build Boolean circuits for any
Boolean expression using NOR gates.
 Steps:
 Obtain product-of-sum Boolean expression
• E.g: F = (x+y).(y+z)
 Use De Morgan theorem to get expression
using two level NOR gates

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 Pulsed Waveforms

Determine the final output waveform X for the circuit in the following
Figure, with input waveforms A, B, and C as shown.

Y=B+C

X = A(B + C)
= A + (B + C)

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Determine the output waveform X for the logic circuit in the
following Figure by first finding the intermediate waveform at
each of points Y1, Y2, Y3, and Y4. The input waveforms are
shown in the next slide.
Y1 = A' + B'
Y2 = C'

Y3 = CY1 Y4 = DY2 X = Y3 + Y4

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Y1 = A' + B'

Y2 = C'

Y3 = CY1

Y4 = DY2

X = Y3 + Y4

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Determine the output waveform X for the circuit directly from
the output expression.

X = C(A' + B') + C'D = A'C + B'C + C'D

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X = C(A' + B') + C'D = A'C + B'C + C'D

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