Digital Assessment I - B2

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1. Timer 0 and Timer 1 does not share TCON register and TMOD register *
(1 Point)

False

True

2. If an 8051 system is operated with 11.0925 MHz crystal frequency, then the timer
clock period is *
(1 Point)

1.085 ms

2 ms

1.085 µs

3. The Data Set Ready (DSR) is asserted by DCE to DTE *

(1 Point)

False

True

5/11/2021
 4. The address of the Accumulator is *
(1 Point)

D0H

E0H

F0H

5. The 8051 timer has ............ modes of operation *

(1 Point)

6. The I/O Ports of 8051 are *

(1 Point)

8-bit wide

32-bit wide

16-bit wide

7. In half duplex data is transmitted in only one direction at a time *

(1 Point)

False

True

5/11/2021
 8. ......................... Special function Registers are related to timer operations *
(1 Point)

TMOD

PCON

SCON

9. In mode 1 timer register is configured as ............ bit register *

(1 Point)

16

13

10. If the value Loaded in TMOD register is, TMOD=0x10, then *

(1 Point)

Timer 0 operate in Mode 0

Timer 0 operate in Mode 1

Timer 1 operate in Mode 1

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5/11/2021