EL568 – Memory Interfacing

Assignment for the Examples Class

1. (a) Design an 4-word x 8-bit mask-programmed CMOS ROM to store F9, 3D, 57, 4C
in rows 1, 2, 3, and 4 respectively.
[Note: Memory contents are shown in hexadecimal notation].
[ 4 marks ]
(b) Design a tree-type column decoder for the above CMOS ROM.
[ 3 marks ]

2. (a) In a 16 Mbit symmetric DRAM, each memory cell has a gate capacitance of
0.95fF and parasitic capacitance of 0.05fF. If the polysilicon resistance of each cell is
100Ω, calculate the delay through the row line. Neglect any delay associated with the
row decoder circuit.
[ 4 marks ]
(b) What will be the delay if each row is partitioned into four sections?
[ 4 marks ]

3. (a) Determine the logic expressions to implement an address decoding circuit to

realize the address map shown below (in hexadecimal notation). Any unused
address should generate an active low signal to be connected to the BERR* input of
the M68000 microprocessor. Use partial address decoding in your design.
ROM1 00 0000 – 03 FFFF
ROM2 04 0000 – 07 FFFF
unused 08 0000 – 3F FFFF
RAM 40 0000 – 7F FFFF.
[ 6 marks ]
(b) Figure 1 shows the internal memory cells of a 16x4 PROM chip. What data do
you need to store in these cells to realise a PROM based implementation of the
decoder you designed in Question 3(a)? You must also show the input sources and
output destinations of the PROM chip.

[ 4 marks ]

The solutions MUST be handed to the EDA Reception

before midday on 1st February 2017 (Wednesday)
[In addition to showing the bits to be stored in the PROM cells, you
must label the input sources and output destinations.]

(MSB)

(LSB)

Figure 1. A Programmable ROM