You are on page 1of 25
‘The module in (i) uses a successive approximation ADC with clock of 1 microsecond. Determine: i, The maximum and minimum time for conversion and the analog value corresponding to these times. k. The time required for converting an input of 250°C. |. Draw the block diagram of the successive approximation ADC and explain the procedure of its operation m. In which applications can the successive approximation ADC be used? Remember fia? fie motile in (¢) was Vt bis “chon 2 LMS or = WV Doo ® = I ALeds = [{1MS ) na: i bis The anchg Vee Csrespanclig to it is 5 Y goo Tain Tag 208 AMS [ELAS / Kewtrber Sar successyve ADC Aas Onsfant’ Cuv€.3lon Yone.= NV becee The ang Velie Coresponclige ro if Is k) Infup 22500 D analog = 250 ~ e%c| TV Eley LHS m Gompateror ° sum process a eben S07 Vin Crbred in raped succession o when Van ts Vagpin§ of Mh speed DAC ITF clk \ succes ve Bree 1s fer ‘The module in (i) uses a single ramp ADC with clock of 1 microsecond. Determine: ‘fn. The maximum and minimum time for conversion and the analog value corresponding to these times. ©. The time required for converting an input of 250°C. p. Draw the block diagram of the single ramp ADC and explain the procedure of its operation YT, 7 @- "4) Cog? (2- “1x 10s (Zo4zods | Gnaby Vihe Corresponding ob rh 15 [EY )xa Tan 1X Bigg = [LAE Omslef Value Crrerpenoling hitis Ee LHS var] OAK ME YO °) /apor 2 = 25 ¥ = oc => 4nsho x ps a Vv Mh aa —, 047 ee ° of _— aa = /023§ = |/024 l } as er aE AP Single Ramp : Cmpictho- Vin ——| Battin Gunde 15 Gurdag op tnt Vi, = Ramp vilue « The module in (i) uses a dual ramp ADC with fixed charging time of 200 microseconds. Determine: 4. The maximum and minimum time for conversion and the analog value corresponding to these times. F.The time required for converting an input of 250°C. 5. Draw the block diagram of the dual ramp ADC and explain the procedure of its operation ve = 2 2005 = GlOoUSs Y Inag 7 2 Degas dime Carespenoing amp = cae Y S000 Fon ° Cheong Ame Cores penoling Greg sOY Y OC = 200 os 1) npitls LEC ay RIV ay Toe 2? Ziggy Ym UMA ols XAB TKS = Sotto [500 0ks | * Cawrersion® Legg dele y Vet @ Ad SiS th 4 oufpuA ¥ my iy es 3- With NEAT block diagrams explain IN DETAIL what is meant by: pao Sample and Hold circuit Input multiplexing of ADC Nyquist theorem Aliasing and Anti-aliasing filter Smart sensors @) Sample & polo Crout y,—~ Vous ; ; bese C%uit ) Yordye plover ¥, contch — Vee ler arf Vou ee ms (Typ Gl oreurt) WP es mp Hd te 1 Gmversin process * = Samjlin a Ths is ADC. h, Quartifr Cofith Aue -Dyrl Ouveriie, L Golag Vin t PN Let We use 3 bLF AE ie Pee Blond, = 27% 23 Samln BO a Goling old ui tro! oi 7 antag spn! 13 Cuvore! b otyitel yore the move bis» The pure Posie is =A Cawiy moreases TL vids C Samplag Ame) decreases L Wheh. wmetns haf Fan plling eafe In Cbses GC Ww. of Singles |sene/ yo Kesolufum. LO Vo. of bts] morvsses. Accuracy elt), C % Higher Sampling rate Higher Resolution (0), —— x(t) of b) Input Jaltiolaing of ARC muldiglexerr eas) _ Oe, —_— Elecham Sane Inpufs _|/ ton, Chirnel selbed- shod of ving sepiiie pvc par every ae em mult plexer- ls Used ob selec? ont mpet rb fo » We Cm we Single ADC m4 paul: mpurs ea ome Sample palol Crtut- Oar be wird Prall apis OR infu bas. 15 own sample 4 fold Cyr with ids own CfwictorsAcs [Be Nu, SG lin WU 2 Paper? The O Lwite A => 400 Hz 10 fe 4 La, Oo f7Z a Lon nypud 3if leas Von es if y ha Lb £2 FB S26, Max a a of ali (a6 will Le hagored s0-- wht 1s aligsng 22 Ae eae , Be 2 lbooHz fe: ea ? Pe = ooHz2 alasing Lfthe. Guersion dé) crlvasing phenomena: when A LS Lheeg » False Represenkifim of s9nq_ will goootuced. AS Shown in last fgures- Ant abasng, pir the hygh (Propentits for Input Spr, hee Boylan orl Ye avojl dd A Sify, (ales) 2) Smaty se71s— ie 1s @ SE2507- Cmbreol Wh Sane indore nf Jasolatares SEp Sar + Jn ferae Dartlare = Sr6d Ota Ths ie Cin tot (Kangnf — Gli bofon— Decision akue PO Grrrmm Capon s 5 Uplizaton of olde mp pe brdew Module loci omy | 7 | |e | ane co nnn | Gael pong 6 mw aaljus/ Teen perehore Gonflen safion

You might also like