Q.1.

Consider a machine with a byte addressable main memory

of 216 bytes and block size of 16 bytes. Assume that a direct
mapped cache consisting of 16 lines used with this machine.
(a) Show the format of the main memory address.
(b) Suppose the byte with address 0001 1010 0110 0001 is
stored in the cache.
(c) What are the addresses of other bytes stored along with it?
(d) How many total bytes of memory can be stored in the cache?
(e) Into what line would bytes with each of the following
addresses be stored?

i) 1101 0000 0001 1101

ii) 0001 0010 0011 1101
iii) 1010 1010 1010 1010
iv) 1001 0001 1111 0101

Solution :

2^16 of main memory means 16 bit address of main memory

0000 0000 0000 0000 to 1111 1111 1111 1111

Block size of 16 Byte : which can be represented in 4 bits 0000 to 1111

Cache has 16 lines means 16 blocks of main memory can at most reside
in cache.
So, cache can address total 8 bits.

Show the format of the main memory address.

Tag – 8bits Line – 4 bits WORD – 4 bits

Suppose the byte with address 0001 1010 0110 0001 is stored
in the cache.
What are the addresses of other bytes stored along with it?

Make the high 12 bit constant and lower 4 bit from 0000 to 1111

0001 1010 0110 0000

0001 1010 0110 0001
0001 1010 0110 0010
…
…
.
0001 1010 0110 1110
0001 1010 0110 1111
How many total bytes of memory can be stored in the cache?
2^8 = 256 Bytes

Into what line would bytes with each of the following addresses
be stored?

i) 1101 0000 0001 1101 - 1st Li ne (0001)

ii) 0001 0010 0011 1101 - 3rd Line(0011)
iii) 1010 1010 1010 1010 – 9th Line(1010)
iv) 1001 0001 1111 0101 - 15th Line (1111)

Considering line starts from 0 to 15.

Q.1 Consider a machine with a byte addressable main memory of

216 bytes and block size of 16 bytes. Assume that a direct
mapped cache consisting of 64 lines is used with this machine.

(a) How is a 16-bit memory address divided into tag, line

number and byte
number?
(b) How is a 16-bit memory address divided if the mapping used
is fully set
associative?
(c) How is a 16-bit memory address divided if the mapping used
is 4-way set associative?
(d) Why is a tag also stored in the cache?

Solution :

2^16 bytes of main memory means 16 bit address

Block size of 16 byte means – 4 bits are used to represent the memory
location witin the block.

64 lines of cache means, 64 blocks of main memory can atmost reside in

cache.

(a) How is a 16-bit memory address divided into tag, line

number and byte
number?

Tag = (16-6-4) = 6 Line – 6 bits Word – 4 bit

(b) How is a 16-bit memory address divided if the mapping used
is fully set
associative?

TAG = 12 bits Word = 4 bit

(c) How is a 16-bit memory address divided if the mapping used
is 4-way set associative?

Total lines in cache is 64.

So in vase of 4 way set associative mapping we have 64/4 ( 2^6/2^2)
== 16 ( 2^4 )

4 bits are used as SET bits

TAG (16-4-4) = 8 SET BIT = 4 WORD= 4

(d) Why is a tag also stored in the cache?

There are various address of main memory that maps to cache, The tag
bits are used to uniquely identify a particular address.

Q.1 Consider a machine with a byte addressable main memory of

216 bytes and block size of 8 bytes. Assume that a direct mapped
cache consisting of 32 lines is used with this machine.
(a) How is a 16-bit memory address divided into tag, line
number and byte
number?
(b) Into what line would a byte with following address be
stored?
0001 0001 0001 1011
(c) Suppose the byte with address 0001 1010 0001 1010 is
stored in the cache.
What are the addresses of other bytes stored along with it?
(d) How many total bytes of memory can be stored in the cache?
(e) Why is a tag also stored in the cache?
Solution

Bits to represent address of main memory = 16 bits

Block size = 8 byte ( 2^3) , so 3 bits are used to identify memory

location within the block.

Cache of 32 lines ( 2^5) , 5 bits are used to represent the line.

(a) How is a 16-bit memory address divided into tag, line

number and byte
number?
TAG ( 16-5-3) = 8 LINE = 5 bits WORD - 3 bits

(b) Into what line would a byte with following address be

stored?
0001 0001 0001 1011 - Line 3 (00011)

(c) Suppose the byte with address 0001 1010 0001 1010 is
stored in the cache.
What are the addresses of other bytes stored along with it?

0001 1010 0001 1000

0001 1010 0001 1001
0001 1010 0001 1010
0001 1010 0001 1011
0001 1010 0001 1100
0001 1010 0001 1101
0001 1010 0001 1110
0001 1010 0001 1111

How many total bytes of memory can be stored in the cache?

2^8 = 256 bytes

(e) Why is a tag also stored in the cache?

There are various address of main memory that maps to cache, The tag
bits are used to uniquely identify a particular address.
Consider a memory system that uses a 32- bit address to address at
the byte level, plus a cache memory that uses a 64-byte line size.
a) Assume an associative cache and determine the following:
(i) Address format
(ii) Number of blocks in main memory
(iii) Number of addressable units
b) Assume a 4-way Associative cache with a tag field in the address of
9 bits and
determine the following:
(i) Address format
(ii) Number of lines in a set
(iii) Number of lines in cache memory
c) If cache design is changed to 8-way Associative then what will be
the address
format?
d) Draw the block diagram to show how processor’s requests are
interpreted in 4-way
Associative cache design i.e. in (b).

Solution

Number of Bits to represent main memory address : 32

Block/Line Size : 64 byte ( 2^6)

Assume an associative cache and determine the following:

(i) Address format
TAG = 26 bits WORD = 6 bits

(ii) Number of blocks in main memory

(2^32)/2^6 = ( 2^26 blocks)

(iii) Number of addressable units

2^32 addressable units.
b) Assume a 4-way Associative cache with a tag field in the address of
9 bits and
determine the following:

(i) Address format

TAG = 9 bits SET = 17bits WORD =6 bits