EXPERIMENT: -4

Objective:
Design a chain of 6 inverters using CMOS based NOT gate. Simulate this with VDD_L (3V)
and VDD_H (5V) and compare the propagation delay and power consumed in each case.

(i). At VDD_H= 5V

Delay Calculation:
Power Calculation

Total Power= 146.04uW

Dynamic Power= 124.99uW
Static Power= 21.05uW

(i). At VDD_L= 3V
Delay Calculation:

Power Calculation:
Total Power= 48.722uW
Dynamic Power= 44.998uW
Static Power= 3.724uW

Results:

Supply TPHL TPLH Total Power Dynamic Static Power

Voltage Power
5V 9.73us 11.9us 146.04uW 124.99uW 21.05uW
3V 20.4us 7.64us 48.722uW 44.998uW 3.724uW