Department of Electrical Engineering

EGEE-465 Fall 2020

Introduction to VLSI Design (Fall 2020)

Logic Gate Design

Student Name: __Jeffry Salazar

Student CWID: __891884140__

Instructor: Yitsen Ku Ph.D.

October 23, 2020

1
I. Introduction
NOR Gate is done using two PMOS and NMOS transistors as seen below which also creates the truth
table shown.

OR Gate is created using an Inverter and a NOR Gate as seen below. This achieves the opposite results
in the truth table compared to the NOR Gate.

NAND Gate is created with 2 PMOS and NMOS transistors, to create a truth table shown below.

2
AND Gate is created with an Inverter and a NAND Gate. Which gives the opposite result truth table.

XOR Gate which is an exclusive OR Gate, only one can be on at a time as shown on the truth table.

3
II. Circuit Description
A. NOR Gate
Describe the schematic, symbol, spice code, and layout of NOR gate.

(b) symbol

4
 (c) spice code

(d) layout (with measurement)

5
B. OR Gate
Describe the schematic, symbol, spice code, and layout of OR gate.
Fig. 2 OR (a) schematic

(b) symbol
Is another symbol that looks just like the Nor symbol, but includes the two symbols above.

6
(c) spice code

7
(d) layout (with measurement)

8
C. NAND Gate
Describe the schematic, symbol, spice code, and layout of NAND gate.
Fig. 3 NAND (a) schematic

(b) symbol

9
(c) spice code

10
(d) layout (with measurement)

11
D. AND Gate
Describe the schematic, symbol, spice code, and layout of AND gate.
Fig. 4 AND (a) schematic

(b) symbol

12
(c) spice code

13
(d) layout (with measurement)

14
E. XOR Gate
Describe the schematic, symbol, spice code, and layout of XOR gate.
Fig. 5 XOR (a) schematic

(b) symbol

15
(c) spice code

16
 (d) layout (with measurement)
Shown with and without measurements to clearly see the paths.

17
18
III. Simulation Results
Fig. 6 NOR gate simulation result

The wave form shows that when only both A and B are low that the output is high. Which matches
the truth table.

Fig. 7 OR gate simulation result

The wave form shows that when either A or B or both are high, the output is high. Which matches the
truth table.

19
 Fig. 8 NAND gate simulation result

The wave form shows that when both A and B are high is the only time the output is low. Which
matches the truth table.

Fig. 9 AND gate simulation result

The wave form shows that when both A and B are high is the only time the output is high. Which
matches the truth table.

20
 Fig. 10 XOR gate simulation result

The wave form shows that when only A is high or only when B is high is when the output is high.
Which matches the truth table.

IV. Conclusion
These gates are considered the basic logic gates that are used to build more complex logic gates. Being
able to use the NAND and Inverter gate I am able to build a AND Gate. Also, being able to build a NOR
Gate then using an Inverter Gate, I can build an OR Gate. From there I was able to build a XOR Gate
from four NAND Gates.

21