IMPLEMENTATION OF FSK DEMODULATION USING PLL 565 Digital Communication Lab Based Project B.Tech 5° Semester Autonomous (A2) Regulation Submitted by 19331A0498 19331A0499 19331A04A0 Under the Guidance of Mr.Rajaramesh Assistant Professor MTech Department of Electronics and CommunicationABSTRACT: FSK mode was introduced in the year 1900 to use in mechanical tele printers. When personal computers became general and networks came into being, this is the signaling speed was tedious. Transmi ion of the large text documents and programs taken hours; image transfer was unknown. During the 1970s, engineers began to develop modems that run at faster speeds, and the search for ever-greater bandwidth has been unremitting ever since. Today, a standard telephone modem operates at thousands of bits per second, Cable and wireless modems work at more than 1,000,000 bps (one megabit per second or | Mbps), and the optical fiber modems function at lots of Mbps. But the fundamental principle of FSK modulation has not changed in more than halfa century. The phase-locked loop is one of the bi ic blocks in modern electronic systems. It is used in multimedia, communication and in many other applications. An especially usefull application of the 565 PLL is as a FSK demodulator. In the 565 PLL the frequency shift is usually accomplished by driving a VCO with the binary data signal so that the two resulting frequencies correspond to the logic 0 and logic 1 states of the binary data signal. The frequencies corresponding to logic 1 and logic 0 states are commonly called the mark and space frequencies. Several standards are used to set the mark and space frequencies.INTRODUCTION: FSK DEMODULATOR FSK demodulator is a very beneficial application of the 565 PLL. In this, the frequency shift is generally proficient by motivating a VCO with the binary data signal. So that the two subsequent frequencies resemble the logic 0 & | states of the binary data signal. These frequencies corresponding to two states are generally called the mark and space frequencies, Numerous values are used to set the mark & space frequencies. An FSK signal demodulator can be made as shown in the figure. The demodulator gets a signal at one of, the two separate carrier frequencies, representing the RS-232 C logic levels of mark or space, respectively. The capacitive connection is used as the i/p to eliminate a DC level PHASE LOOP LOCK (PPL): The LMS65 is a general-purpose phase locked loop (PLL) containing a stable, highly linear voltage-controlled oscillator (VCO) and a double balanced phase detector with good carrier suppression. 565 PLL TC Ne ne Ne Vee Timing ‘capacitor Taming restetorCOMPONENTS: R1,R2=600Q R3= 5KQ R4—-R6=10KQ Capacitors C1=0.1 pF (Ceramic Disc) C2= 0.001 uF (Ceramic Dise) C3= 0.05 nF (Ceramic Disc) C4—C7 = 0.2 uF (Ceramic Disc) Semiconductors ICI = 565 (general purpose phase locked loops IC) 1C2=710 (Bi CMOS operational amplifiers with a CMOS input stage.)CIRCUIT DIAGRAM: e000: 565 As An FSK DemodulatorImplementation of Demodulator: The demodulator operates in closed-loop mode with the PC and an external LPF, as shown. Modulated signal Center Frequency (R1, C1) | Demodulator Demodulated Signal <¢ Figure §. Basic Block Diagram of PLL as Demodulator To design a demodulator with maximum and minimum frequency of {MAX and fMIN, respectively (which is sameas that of modulator), the following steps are required: 1, Usethe same value of RI and C1 as that of modulator. 2. While using PC1, the capture range depends on the LPF (R3-C2) characteristics and can bemadeas large as the lock range. For PC2, capturerangeis equal to lock range an independent ofthe LPF. 3. Since leakage current can affect the VDEMOUT, a load resistor (RS) from this pin to GND in the range of 50 kQ to 300 kQ is recommended.Examp! A test circuit (VCC = 5 V) was implemented to demodulate a digital signal using PC2 with following component values: RI = 3 kQ, C1 = 47 pF, R2= open, R3 = 36 kQ, C2= 120 pF Table 2. Demodulator Test Circuit Results | VCO, (at | Frequency of SG, (Hz) at | $16, peak to peak (V) at] DEM, (V) at modulator Wodultor Demodulator demodulator i! 10 ey] 46 18 jay 3 72M at 15 [3 45 750M 2 a8 FESK DEMODULATOR WORKING: © The capacitor coupling at the input is needed for removing the de level in the input FSK signal. © As we apply FSK signal at the input, the loop gets locked to the input frequency and the VCO tracks the input frequency between the two frequencies Fh and Fl. A corresponding de shift will be produced at the output. © The three stage RC low pass filter is used for removing the carrier component from the output. « RlandCl decide the free running frequency of VCO. * VOC control voltage is produced which is given by VeL = Fh —- FO/K © Where, FO = free running VCO frequency and K=V tof transfer coefficient of VCO © When the input frequency is FL the control voltage is given by: Ve2 = FO — FL/K © Where, Vc? is inputside capacitor. © These voltages are compared with the reference voltage by the eternal comparator to produce a digital signalScheme 1: In this scheme, VCO at the modulator transmits a particular frequency during occurrences of bit 1 in the digital data and remains idle during occurrence of bit 0. At the demodulator end, the presence or absence of the frequency is tracked by the PLL. PC output followed by LPF, represents the demodulated signal, which is the equivalent of the original digital information. For this scheme, VCOIN < 0.6 V for logic 0 and VCOIN close to 0.9 x VCC for lo; recommended. Use of PC2 at the demodulator gives good results over a wide range of frequency. Nodultr = Denar Dig Modding Nedualed Sin Denolted Sonal Soul Figure 7. Scheme 4 Advantages: + Power consumptionis less at the modulator. + A burst of frequency is transmitted only during transmission of a specific data bit (cither 1 or 0), hence, there is less noise created in the transmission media. + Single frequency is used; therefore, the bandwidth requirements smaller. * Gives better performance even at higher frequencies (200 kbps or higher) of modulating signal (as compared to scheme 2), because of wide separation possible between logic 0 and logic 1 voltages.Limitations: + It is difficultto determi if the remote modulator is defunct (versus continuously sending 0’s). + When VCOIN < 0.6 V (logic 0), modulator output may either be 0 V or VCC; however, this does not affect demodulation. Scheme 2: In this scheme, VCO at the modulator transmits one particular frequency during occurrences of bit 1 in the digital data and other frequency during occurrence of bit 0. At the demodulator end, the changein the frequency is tracked by the PLL. PC output followed by LPF represents the demodulated signal, which is the equivalent of the original digital information. For this scheme, 1.0 V < VCOIN < 0.9 VCCis required. Use of PC2 at the demodulator gives good results over a wide range of frequency. -O1t0- pote LOtto- Danodiatr | | VATE Dg Motdatng Mota Sa Denodled Sod Sind Figure 8, Scheme 2Level shifting of the input digital signalis required to meet the VCOIN input range which can be achieved using a level-shifter circuit. soma ¥COn 7 fees | vfar af a $m 2m 3m ttm Figure 10. Simulated Waveforms of Level-Shifter Circuit using LP211 As can be seen from the test waveform in Figure 10, a digital signal Vin (0 V-3.3 V)is converted to VCOIN (1.07 V-4.5V).Advantages: + It is easy to determine if the remote modul: Limitations: + Power consumptionis more at the modula Requires more bandwidth. lator is defunct. tor due to continuous oscillations. + + As VCOIN logic 0 and logicl voltage level separation decreases, noise on the demodulated output appears to increase. MODEL WAVEFORM: T \ TATE T \ i UEAANVVTL | i Digi Sia us) kidd St TT Demo Sa TaalADVANTAGES: eee DISADVANTAGE: . It has a lower probability Easy to implement High data rate It has better noise immunity than ASK method, so the probability oferror-free reception of data is high Easy to decode Operate in virtually any wires available FSK transmitter, as well as FSK receiver implementations, are simple for low data rate application ‘The BER performance in the AWGN channel is worse compared to PSK modulation Extensively used in low-speed modems having bit rates below around 1200 bits/sec This increases the channel bandwidth required to transmit the FSK signal type It uses larger bandwidth compared to other modulation techniques like ASK and PSK. Hence it is not bandwidth efficient. FSK is not preferred for the high-speed modems because with increases in speed and also have the bit rate increases. Applications: 1.Audio 2. Automotive and Transportation 3.Amplifiers 4,.Communications and Telecom 5.Data Converters 6.Computers and Peripherals.Conclusion : This application report described logic-level implementation of BESK modulator and demodulator using HC/HCT4046A devices. However, while implementing this circuit for a real-time application, the following imp ortant factors must be considered for a reliable communication link: * Output impedance of the modulator. * Characteristic impedance of the transmission media. + Frequency response of transmission media. + Input impedance of the demodulator. Hence, impedance matching and signal conditioning becomes an imp ortant aspect in a practical system.