Professional Documents
Culture Documents
Course Scope
Basic Electronics,
ENLITE VLSI DESIGN has equipped with FPGA EDA tools and
Educational CPLD/FPGA development boards from Altera. Also uses
Mentor Graphics Model Sim for simulation.
Design Example – Shaft position detector using MUX, ROM and PLA.
Exercises
HDL introduction
Verilog basics
Gate-Level Modeling
Dataflow Modeling
Behavioral Modeling
Exercises
Introduction to VHDL
Sequential Processing
Data Types
Predefined Attributes
Configurations
Exercises
Design methodology
FPGA Architecture
Simulation of VHDL/Verilog
Synthesis of VHDL/Verilog
34-3, Ist Floor, Saraswathi Towers, 10th Street, Gandhipuram, Coimbatore-641012.
Ph: 9500833044, 0422 - 4218585
Email: info@enlite.co.in - Web: www.enlite.co.in
COURSE MODULE
RTL and Technology View (Schematic circuit diagram view of VHDL / Verilog
codes)
Back annotation
Floor plan
Realization of RAM
Introduction to DSP
Design of 2D – DCT
Design of 2D – DWT
Mini Project