Strategic Reduction of Area and Power in FIR
Filter Architecture for ECG Signal Acquisition
Sudhanshu Janwadkar
2020 IEEE 17th India Council International Conference (INDICON) | 978-1-7281-6916-3/20/$31.00 ©2020 IEEE | DOI: 10.1109/INDICON49873.2020.9342386
Department of Electronics Engineering
Sardar Vallabhbhai National Institute of Technology
Surat, India
mr.sudhanshu.janwadkar@gmail.com
Abstract—Literature on VLSI implementation of Finite Im-
pulse Response (FIR) filters has scarce mention of dedicated
filters for portable Electrocardiogram (ECG) acquisition system.
Primary requirements of portable systems are compact design
and low power consumption. This paper, therefore, presents
design and implementation of low-area and low-power FIR
filter architecture for removing high-frequency noise from ECG.
We propose a systematic LSBs quantization approach to lower
the area-power complexity of Urdhva-Tiryagbhyam sutra based
Vedic Multiplier. Vedic FIR filter of order L = 16, 32 and 64, are
constructed using this optimized 16X16 Vedic Multiplier. The
filter architecture is described in VHDL language and imple-
mented on Artix-7 FPGA xc7a200tfbg676-2 using Xilinx Vivado
2019.2 Design Suite. Comparison of proposed architecture with
state of the art FIR filters in literature reveals 52.07% reduction
in slices and 69.63% reduction in power consumption. The
quantization costs meager 0.135 mV 2 Mean Square Error(MSE)
against uncontaminated ECG.
Index Terms—Biomedical Signal Processing, Carry Save
Adder, Electrocardiogram, FIR Filter, Vedic Multiplier, Vedic
FIR filter, VLSI
I. I NTRODUCTION
ECG is the most widely performed cardiovascular diag-
nostic procedure by medical practitioners [1]. ECG analysis
is preferred because of ease, accuracy, non-invasive nature
of diagnosis and good temporal resolution [2], [3]. However,
during signal acquisition using electrodes, ECG signals are
contaminated by numerous noise sources and need to be
filtered in order to render it suitable for diagnosis. The Amer-
ican Heart Association (AHA), in its recommendations for
standardization of electrocardiography, has mandated usage of
digital Low Pass Filter (LPF) as a critical block [1]. The LPF
is responsible to eliminate Electromyographic (EMG) noise
[4], Interference from medical implants [5], Electromagnetic
(EM) interference from other electronic equipments [2], [6]
etc. FIR filters are desired as digital filters because of their
linear phase response [7].
The authors express their gratitude to Special Manpower Development Pro-
gram for Chips to System Design (SMDP-C2SD) project under Ministry of
Electronics and Information Technology, Government of India for providing
access to tools required to conduct this research work.
978-1-7281-6916-3/20/$31.00 ©2020 IEEE
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Rasika Dhavse
Department of Electronics Engineering
Sardar Vallabhbhai National Institute of Technology
Surat, India
rsk@eced.svnit.ac.in
Numerous FIR filter architectures are proposed in literature
based on different topologies such as multi-rate FIR filter
[8], FFA FIR filter [9], DA based FIR filter [10], Parallel
FIR filter [11] etc. However, FIR filter architectures designed
exclusively for ECG are scantily reported [12].
Current quest of research is towards developing portable
acquisition systems for biomedical signals, implying area
and power consumption constraints (as such systems are
battery operated) on the filtering circuitry as well [13]. The
VLSI implementation of Vedic sutra Urdhva-Tiryagbhyam,
called Vedic Multiplier (VM), is known to result in low
power design [7], [12], [14]–[18]. In this paper, we describe
an approach to optimize the architecture of VM for DSP
applications by quantization of product bits. We, thereafter,
design compact low-power FIR filter using optimized VM and
implement on Artix-7 FPGA platform for rapid prototyping.
The implementation results of the proposed Vedic FIR filter
architecture are compared with state of the art architectures.
The paper is organized as follows: Section 2 deals with a
brief literature review of contemporary research developments
in this regard. This is followed by mathematical analysis and
optimization of the Urdhva-Tiryagbhyam sutra based VM in
Section 3. The implementation details and results obtained
are discussed in Section 4.
II. L ITERATURE R EVIEW
Usage of Canonical Sign Digit (CSD) representation and
Common Sub-expression Elimination (CSE) has been advo-
cated as techniques to reduce the number of adders required
to realize multiplier and thereby reduce the complexity of
FIR filters [7], [19], [20]. These techniques involve encoding
filter coefficients with minimum non-zero bits and searching
for common sub-expressions to minimize the number of
operations. However, these techniques add to the combina-
tional logic and throughput per unit area is not high for low
complexity filter coefficients [21], [22]. Biomedical signals
including ECG are filtered by low order filters and coefficients
have low complexity. Filters based on Distributed Arithmetic
(DA) approach involving carry-save accumulators have high
throughput and lower reconfiguration time [10], [23], [24].
The limitation of DA approach is that filter coefficients are
required to be stored in lookup tables or registers. Complex
memory based LUTs are not favored in ASIC implementation and
[23]. Also, they result in higher slice count & more area [12]. X
N −1
B= bj 2j (2)
In recent years, Multiplier based on Urdhva-Tiryagbhyam
j=0
sutra of Vedic mathematics [7], [25]–[27] has gained mo-
mentum as a high-speed low power multiplier alternative to Then the product P can be expressed as [16]:
conventional multipliers. VM is a highly modular multiplier X
N X
−1 N −1
architecture which divides every N X N multiplication into P = ai bj 2i+j (3)
a set of N2 X N2 multiplications, each of which are performed i=0 j=0
in parallel. The parallel generation of partial products and
Or,
their addition in one step results in higher speed while X
2N X
−1 N −1
modular approach results in lower power consumption than P = ai bk−i 2k (4)
conventional multipliers [25]–[28]. k=0 i=0
Several works [7], [12], [13], [17], [18], [28], [29] propose where k = i + j
FIR filter using VM. Mittal and Nandi [28] proposed VM X
2N −1
architecture in which the conventional Ripple Carry Adder P = p k 2k (5)
(RCA) is replaced with Carry Save Adder (CSA) for high k=0
speed. Further, FIR filter is designed using VM-CSA architec- where pk = ai bk−i
ture. Mittal, Nandi and Yadav [7] have compared 16th order This essentially means the product term P is a sum of terms pk
FIR filter architectures using VM, Wallace Tree Multiplier obtained by multiplying the k th parts of a and b in a crosswise
and various parallel prefix adders such as Brent-Kung Adder manner [16]. The Urdhva Tiryagbhyam sutra divides both N-
(BKA) etc. They conclude that although performance using bit multiplicand and N-bit multiplier into a set of two M = N2
Wallace Tree is better, but VM based FIR filter results in lower operands which are then multiplied ’vertical’ (MSBs among
power consumption and Energy Delay Product (EDP). Sekar themselves and LSBs among themselves) and ’crosswise’
and Sasipriya [29] proposed reversible logic Vedic FIR filter (MSBs of multiplier with LSBs of multiplicand and vice-
architecture. This involves design of square-root CSA and VM versa). Resulting partial products are then added using N-bit
using reversible gates. Reversible logic implementation results adders. The N X N VM architecture is shown in Fig. 1
in low power consumption due to unique mapping between
inputs and outputs of a particular gate. However, the condition AXX BXX AXX BYY AYY BXX AYY BYY
that number of inputs and outputs for a gate must be same,
results in large number of garbage outputs and fan-out limi- MXM MXM MXM MXM
tations [30]. Rai et al. [18] proposed a novel carry increment VM VM VM VM
adder (CIA) architecture based Vedic FIR architecture. CIA is M M

built from full-adders realised through multiplexers. CIA has N-bit Adder M
lower combinational path delay than other adders but results M
c N
in higher hardware resource utilization.
c
Sumalatha et al. [12] propose LPF for ECG de-noising HA N-bit Adder
using Vedic Design-Carry Look Ahead adder (VD-CLA FIR) M
approach. The processing element (PE) is a single VM c M M
N-bit Adder
designed using CLA followed by accumulator also designed
using CLA approach. The filter coefficients are stored in N
ROM while input samples are stored in RAM. The samples PXX PXY PYY
and coefficients are loaded to the Vedic design PE by a p0
control unit. Vedic design PE has very low power and area. Fig. 1. Architecture of Conventional Urdhva Tiryagbhyam Sutra N X N VM
Padmavathy et al. [17] have followed a similar approach of
designing Vedic PE, however, the partial products are in the In Fig. 1, each M X M multiplication is performed by a VM
PE are added using RCAs. The obvious limitation of these of lower hierarchy (M = N2 ) . AXX and BXX represent the
designs [12], [17] is usage of RAM and ROM memories. MSBs (A[(M-1): M M
2 ] and B[(M-1) : 2 ]) while AYY and BYY
represent the LSBs (A[( M M
2 − 1) : 0] and B[( 2 − 1) : 0]).The
III. P ROPOSED VM ARCHITECTURE FOR A REA -P OWER partial products are added using N-bit adders. PXX represents
O PTIMIZATION IN DSP A PPLICATIONS MSB of product (P[(2N-1):N) while PXY (P(N-1): N2 ) and
PYY (P( N2 -1):0) represent LSBs.
If A and B be the N-bit multiplicand and multiplier A N X N multiplication results in 2N product bits. In DSP
respectively represented as: applications, quiet often, these 2N bits are quantized to N-
bits through some quantization scheme such as truncation
X
N −1
or rounding off. This is because complex operations in DSP
A= a i 2i (1)
systems are distributed over multiple sub-system blocks and
i=0

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it is desirable to have uniform wordlength across system. architecture of the N-bit CSA realised using full-adders and
It is estimated that almost 50% of chip area is involved to can add three N-bit addends, is shown in Fig. 3.
compute the LSBs which are ultimately truncated [31]. We
therefore propose to modify the existing Urdhva Tiryagbhyam a(3) b(3) a(3) b(2) a(2) b(3) a(2) b(2) a(3) b(1) a(3) b(0) a(2) b(1) a(1) b(3) a(1) b(2) a(0) b(3)

based VM architecture such that calculation of LSBs at each

stage is avoided carefully, thereby resulting in lower area and
lower power consumption (as leakages and switching activity
in significant portions of design is eliminated), yet resulting
in lower bit-error rates.
Equation 1 and 2 can be reorganized as:
N
X
−1
2 X
N −1
‘0’ ’0’ ‘0’ ‘0’
a i 2i + a i 2i
VM oVM oVM
A= (6) 2X2 2X2 2X2

i=0 i= N
2

and N
q[3:0] r[3:0] s[3:0]
2X
−1
X
N −1 q r s
B= bj 2j + b j 2j (7) 4 4 4
j=0 j= N Carry-Save Adder
2

Therefore, the product P is 4

4
P
N N N
2X X
−1 2 −1 2 X X
−1 N −1
Fig. 2. Architecture of Proposed 4 X 4 oVM for DSP Applications
i+j
P = a i bj 2 + ai bj 2i+j
i=0 j=0 i=0 j= N
2
(8)
N q(n-1) r(n-1) s(n-1) q(2) r(2) s(2) q(1) r(1) s(1) q(0) r(0) s(0)
X
N −1 X
−1
2 X
N X
−1 N −1
i+j i+j
+ a i bj 2 + a i bj 2
i= N j=0 i= N j= N
FA ...............
FA FA FA
2 2 2
‘0’

In accordance to our proposed optimization strategy, we C

propose to eliminate the ’vertical’ term which multiplies the FA .........

......
FA FA FA ‘0’

N
2 LSBs of both operands. Equation 8 is reorganized as: s(n-1) s(3) s(2) s(1) s(0)
s(0)
N
X
N X
−1 N −1 2 X X
−1 N −1 Fig. 3. Architecture of N-bit CSA
P = ai bj 2i+j + ai bj 2i+j
i= N N i=0 j= N
2 j= 2 2
(9) A[7:4] B[7:4] A[7:4] B[3:0] A[3:0] B[7:4]
N
X
N −1 2 X
−1

+ ai bj 2i+j 4X4 4X4 4X4

i= N j=0 VM oVM oVM
2

Further going by our optimization strategy, the ’crosswise’ “0000”4

8 “0000” 4
terms are further split and terms containing product of only
LSBs are eliminated. The product P is therefore, c 8-bit Carry Save Adder

N 8
X
N X
−1 N −1 X X
−1 N −1
4 P
P = ai bj 2i+j + ai bj 2i+j
i= N N i=0 j= 3N
2 j= 2 4
A[15:8] B[15:8] A[15:8] B[7:0] A[7:0] B[15:8]
N N
X
2 X
−1 N −1
X
N −1 X
−1
2

+ ai bj 2i+j + ai bj 2i+j (10) 8X8 8X8 8X8

i= N
4 j= N
2 i= N
2 j= N
4 VM oVM oVM
N
X
N −1 4X
−1
16 ‘0’
88
‘0’
88
+ ai bj 2i+j 8 8
i= 3N j=0 C 16-bit Carry Save Adder
4

Based on Equation 10, the architecture of 4 X 4 Optimized 16

P
VM (4 X 4 oVM) has been realised using basic gates and
shown in Fig. 2. In the architecture, the partial products Fig. 4. Architecture of (a) Proposed 8 X 8 oVM and (b) Proposed 16 X 16
are computed in parallel and added using 4-bit CSA. The oVM for DSP Applications

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 In Fig. 4 (a) & (b), the MSBs of multiplicand and multiplier
are multiplied by conventional VM, while multiplication of
MSBs of multiplicand with LSBs of multiplier and vice-
versa are carried out by proposed optimized VM. In order
to verify the functionality of the proposed oVM, the design
was considered as Unit Under Test (UUT) in conventional
testbench. UUT was provided with exhaustive set of test-
vectors and test-responses were verified. A sample testbench
verification of proposed 16X16 oVM is shown in Fig. 5. In
Fig. 5, ’a’ and ’b’ represent 16-bit multiplier and multiplicand
respectively. The product P (conventionally should be 32-bit)
is a 16-bit vector which reflects only MSBs of actual product.
This is sufficient as per the proposed optimization strategy.
Fig. 5. Testbench Verification for Proposed 16 X 16 oVM
x(n-62)
x(n-63) Z-1 Z-1 x(n-61)
Z-1
x(n)
Z-1 Z-1 Z-1
+ + + +
w(0) w(1) w(2) w(32)
+ +
Fig. 6. Proposed 64th order FIR Filter Architecture for Portable ECG
Acquisition System
The architecture of symmetric linear phase Vedic FIR filter
designed using 16 X 16 oVM is shown in Fig. 6. In Fig.
6, each crossed circle represents a 16 X 16 oVM (shown in
Fig.4(b)), while square containing + is a 16-bit RCA. Square
containing Z −1 represents 16-bit shift register. By virtue of
its transfer function, FIR filter structure always has a linear
phase response, implying that the impulse response h(n) of
the filter must satisfy:
h(n) = ± h(L − n − 1)
where L is the filter order and n= 0,1,2....(L -1) In comparison
with Direct-I form implementation, the number of multipliers
required to realize FIR filter are reduced by half. Thus, the
linear phase symmetric form realization further optimizes
area, speed and power.
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IV. E XPERIMENTATION AND R ESULTS
A. Tools and Techniques
Software tools used for this study include MATLAB (and
its FDA tool) and Xilinx Vivado 2019.2 Design Suite. Also,
the MIT-BIH Arrhythmia Database [32] is considered for this
study. The filter design was accomplished using FDA tool
of MATLAB. The filter coefficients were computed using
Blackman window for filter orders L = 16, 32 and 64. The
cut-off frequency and sampling rate were chosen as 50 Hz and
400 Hz respectively. The filter coefficients thus obtained were
quantized to 16-bit binary representation. The proposed Vedic
FIR filter (as shown in Fig. 6) was described using hardware
description language VHDL. The design is targeted for Artix-
7 FPGA xc7a200tfbg676-2, which is based on 28 nm high-
K metal gate (HKMG) process technology [33]. Functional
Verification, Synthesis and Implementation were performed
using Xilinx Vivado 2019.2. To establish the significance of
proposed work, its FPGA implementation results have been
compared with other state of the art designs implemented on
common platform.
B. RTL View
During elaboration, bits of code are recognized and con-
verted to generic technology cells. The resulting RTL view of
proposed 16 X 16 oVM and the 64th order FIR Filter using
Z-1 proposed oVM are shown in Fig. 7 and Fig. 8 respectively.
x(n-33) The RTL of proposed FIR filter consists of three major blocks,
shifters, multipliers and adders.
y(n)
+
Fig. 7. RTL View of Proposed 16 X 16 oVM
C. Functional Verification
The ECG samples from MIT-BIH database were imported
into MATLAB. The raw ECG signal was corrupted using
synthetic noise of high frequencies (f >40 Hz). The noise
corrupted signal was then read using VHDL file IO. The filter
response containing 16-bit binary values of the filtered signal
was imported again in MATLAB and filtered signals were
(11) plotted. Fig. 9 (a) shows the ECG signal of record 100. A
single QRS complex has been shown. The signal is corrupted
with noise signal shown in Fig. 9 (b). The resulting Noisy
ECG signal has been represented in Fig. 9 (c). The noise
corrupted signal was then filtered using the Vedic FIR filter,
shown in Fig. 6. The filtered ECG signal by proposed Vedic
FIR filter (for L= 16, 32 and 64) is shown in Fig. 10.
 Fig. 8. RTL View of Proposed 64th order FIR Filter

Record-100

P
T

Q S

Fig. 9. (a)Raw ECG Signal, MIT-BIH database (Record 100) (b)Random Noise Signal ( f >40Hz) (c) Noise Corrupted ECG signal

D. Results and Discussion

We compared proposed FIR filter architecture against other

state of the art architectures for FPGA device utilization,
timing and power consumption. The results are reported in
Table I. Analysis was carried out at post-implementation
stage after completion of routing. During implementation,
bit-stream is generated and the design is placed and routed
onto the FPGA resources. The tool at post-implementation
stage can report exact number of logic resources, routing
resources, routing delays and exact activity of the internal
nodes. Power analysis at this level provides the most accurate
power estimation [34].

TABLE I
P OST- IMPLEMENTATION S UMMARY OF FIR F ILTER A RCHITECTURES
Fig. 10. ECG Signal filtered by Proposed Vedic FIR Filter
Filter Number of Number Total Power
Total Delay
Work Order Logic of Consumption
(in ns)
L LUTs (#) Slices (#) (in mW)
16 969 294 30.952 116.526
Proposed Vedic FIR filter rejects noise and retains all the [28]
32 2137 631 34.424 227.700
2015
crucial features of the ECG signal. It is also evident from Fig. 64 4355 1279 49.227 483.323
16 1254 375 28.274 139.294
10 that the amplitude of the filtered ECG signal is attenuated [7]
32 2686 787 33.838 294.316
2017
in comparison to the raw ECG signal. Also, the samples in the 64 5524 1603 44.728 651.700
16 1481 444 24.133 165.373
filtered response are linearly shifted. The number of samples [18]
32 3359 962 31.235 359.394
2018
shifted equals half the filter order (8, 16 and 32 samples 64 6795 1946 39.294 749.358
16 965 289 22.562 116.161
for L=16, 32 and 64 respectively). The corresponding MSE [12]
32 2147 637 25.535 226.993
2019
values between uncontaminated ECG signal and filtered signal 64 4368 1257 36.111 473.203
16 568 192 21.337 48.001
was 0.135 mV 2 , 0.133 mV 2 and 0.134 mV 2 for L= 16, 32 Proposed
32 1170 374 24.563 76.990
2020
and 64 respectively. 64 1788 613 31.798 143.673

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 1788 58.94% reduction in 31.798
4368 # LUTs 36.111 11.94% reduction
64 6795 64 39.294 in TD
5524 44.728
4355 49.227

Filter Order, L
Filter Order, L

1170 Proposed 24.563 Proposed

2147 25.535 3.8% reduction
32 45.25% reduction in 32 31.235
3359 [12]
2686 # LUTs
[12] 33.838 in TD
2137 34.424
[18] [18]
568 21.337 [7]
965 [7] 22.562
16 1481 41.13% reduction in 16 24.133 5.42% reduction
[28] 28.274 [28]
1254 # LUTs 30.952 in TD
969

0 10 20 30 40 50 60
0 2000 4000 6000 8000
Total Delay (in ns)
Number of LUTs (Logic)

Fig. 11. Comparison of # LUTs occupied by Existing and Proposed FIR Fig. 13. Comparison of Total Delay of Existing and Proposed FIR Filter
Filter

143.673 69.63% reduction in TPC

473.203
64 749.358
52.07% reduction in 651.7
613 483.323
# Slices

Filter Order, L
1257
64 1946 76.99 Proposed
1603 226.993
1279 32 359.394 66.08% reduction
[12]
294.316
Filter Order, L

in TPC
374 Proposed 227.7
[18]
637 40.73% reduction in
32 962 [12] 48.001
787 # Slices 116.161 58.68% reduction [7]
631 16 165.373
[18] 139.294 in TPC [28]
192 116.526
289 [7]
33.56% reduction in
16 444
375 # Slices [28] 0 200 400 600 800
294
Total Power Consumption @ 10 MHz Clock Frequency (in mW)
0 500 1000 1500 2000 2500
Fig. 14. Comparison of Total Power Consumption of Existing and Proposed
Number of Slices FIR Filter
Fig. 12. Comparison of #Slices occupied by Existing and Proposed FIR
Filter FPGAs have inbuilt internal Phase Locked Loops capable
of generating various clock frequencies. Power Analysis has
been carried out at 10 MHz clock frequency. The static
The device utilization has been captured in terms of number switching probability of 0.5 and toggle rate 12.5% is chosen.
of logic LUTs and number of slices required to implement However, it is understood that biomedical systems need not
the design. Comparison of number of logic LUTs and slices be operated at such high frequencies when implemented on
occupied by existing architectures and proposed FIR filter chip.
architecture is represented graphically in Fig. 11 and Fig. 12 Vivado reports total power consumption (TPC) as an esti-
respectively. FIR filters proposed in [18], [28] deploy fast mate of static power consumption (due to leakages), dynamic
adder architecture such as BKA and CIA, which results in power consumption and IO power [34]. The values reported
consumption of more hardware resources. Our proposed FIR in Table I are TPC values. It is observed that dynamic power
filter has least device utilization, for any given filter order. consumption accounts for more than 80% of the total power
Results indicate that for 64th order FIR filters, proposed consumption. The dynamic power consumption is captured in
architecture occupies 58.94% lower logic LUTs and 52.07% terms of signal power (depends on switching activity across
lesser slices than other design. signals in design) and logic power (depends on switching
To compare speed of the architectures, the comparison has activity in the logic). The comparison in Fig. 14 indicates
been made on Total Delay (TD) of the critical path. Tool a massive 69.63% improvement in TPC of the proposed
reports the paths with maximum delay after implementation Vedic FIR filter against existing designs. Removing of stages
stage [34]. The delay comparison is presented in Fig. 13. involved in multiplication of LSBs results in lowering of
Using BKA and CIA adders instead of conventional adders switching activity, ultimately lowering the design power con-
has worked well for designs described in [7], [18] in terms of sumption. The results clearly testify that the proposed Vedic
delay. However, design described in [12] further reduces de- FIR filter architecture based on the quantization approach
lay, while maintaining low resource utilization. The proposed discussed in Section III has significantly lowered device uti-
Vedic FIR filter has too has improvement (3 - 11 %) in delay lization and power than state of the art architectures, without
for various filter orders. compromising much on signal quality.

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 V. C ONCLUSION
Multiplier is the most resource consuming and power
hungry block in any filter architecture. The area-power com-
plexity of a multiplier can be lowered by quantizing the
product bits. In DSP systems, the LSBs are usually trun-
cated to attain uniform wordlength across the system. We
proposed a systematic product-bit quantization approach to
eliminate combinational logic blocks that compute LSBs, at
each hierarchy level of the modular VM architecture. The
FIR filter designed using optimized VM was employed for
de-noising ECG signals. For verification of functionality, raw
ECG signal from MIT-BIH database was corrupted with high
frequency synthetic noise and filtered using the proposed
Vedic FIR filter. The filtered ECG signal retained all the
features of the uncorrupted ECG signal; however a uniform
phase-shift is introduced in the system. Comparing the FPGA
implementation results revealed that the proposed Vedic FIR
filter consumes 52.07% lower slices and 69.63% lower power
than other contemporary designs, making our proposed Vedic
FIR Filter architecture ideal choice for portable battery op-
erated ECG acquisition systems. The FPGA platform has
been used for rapid prototyping and we further plan for
ASIC implementation, so that it can be tailored as a block
in portable ECG acquisition system.
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