Jonathan W. Valvano 157 Chapter 14 Solutions 6811 Solution 14.4 Part 8) Show hardware. The $k pullups supply enough Ix for the CMOS inputs. The 2500 resistor value was chosen o create the 2 SV, 8mA LED operating point 45 + en it RxD 2500 from -1 Head tontl : no} grounds isolated : fom = ‘rounds isolated fiom other uC from other wc ESEXE 2595. 9800 Part b) Show the stuff in RAM. Two fifo's needed char RFifo[16]; // zeceive fifo for incoming messages char *Rputpt, *agetpts char Sfifo(16]; // send fifo for outgoing messages char *Sputpt, *Sgetpt? att c) Show the software. The FIFO prototypes are as follows void C1ERFifo(void); // initializes the REifo void C1rSEifo(void); // initializes the stito int Rput (unsigned char); // enters a byte into REifo Ant Spt (unsigned char); // enters a byte into sfiro // returns a true if the fifo is full, and the data was not saved. int Rget (unsigned char *); // renoves a byte fron RFifo int Sget (unsigned char *)) // renoves a byte from Sfifo i/ returns data by reference byte and return value is false if successfull 7/ returns true if the fifo was empty at the tine of the call void Ritual (vosd) { asm(* soi"); CLERFifo(); CLrSFifo(); // initialize data structures BAUD=0x307. // max bandvieth depends on software=9600 bits/sec 1/8 bit character 17 Rev armed, Xnt disazned because Sfifo is empty asm(" cli");) int Send(messagetype *pt) (unsigned char data: // compressed message int full ‘datan (0xC06 (PORTEC<6} )+ (0x30 (pt->destinationinfozmation})+ follesput (data); // start to send SCCR2=0xAC7 77 axn teanonit return(foll); } // error if Sfifo is full int Accept (messagetype *pt) {unsigned char data? // compressed message Ant empty expty-Rget (date); // try to receive if (enpty==0) ( e->sourcondata>>6; pe ddestinstion=0x036 (data>na) + pe->ingormation=0x0zédatar rethen(enpty); )// no message Sf REifo is empty fpragns interrupt _handler SCthandier() void Scthandler(véid) { unsigned char datar Jonathan W. Valvano158 Solutions Manual for Real Time Embedded Systems, 2" Edition LE(SCSRERORE)(// incoming message atenSCDR: // read message, ack LE ((PORTEGOXO3) =m (02034 (data>>4) ) Rput (data); // match accept into this computer else sput (data): ) // no mateh retransmit to other computers Sf (scopetpRE) { 7/ time to send outgoing message ie (sget(saata)s) ‘SCOR2=0x207 (1 wot ddsarned because S£ifo enpty else scoRedata; }) _// Initiate output, acknowledge interrupt Part d) Let baud be the baud rat in bits/sec (9600bits/es) Dandwidth-baude(4 bits of information! frame)/(10 bitseame) = 3840 bites (6812 Solution 14.1 Part a) Show hardware The 5k pallups supply enough Ini forthe CMOS inputs. The 2500 resistor value was chosen fo create the 2 SV, 8mA LED operating point $ 5k T4HC14 6812 5 RxD 2500 froma po vas tontl Ww so ‘Ls: sk Ts} sroundsisoat $ $ ey : a ‘grounds istated fom other wC Pay eas n ISO mA Part b) Show the stuff in RAM Two fifo’s needed char REifo(16]; // receive fifo for incoming messages char *eputpt, *Rgetpt: char Sfifo(ié); // send fito for outgoing messages char *sputpt, *Sgetpt Pat c) Show the software. The FIFO prototypes are as follows void CLrRFifo(void); // initializes the REifo void Clrszifo(void); // initializes the Sfifo int Rpat (unsigned char); // enters a byte into Rfifo Ant Sput (unsigned char); // enters 2 byte into S£ito // returns a true if the fifo ie full, and the data was not saved int Rget (unsigned char *); // renoves’a byte from REifo int Sget unsigned char *); // renoves a byte from fifo // returns data by reference byte and retzn value 19 false if successfull, 7/ returns true if the fifo was empty at the time of the call void Ritual (void) ( 480 bytessee Re 2500 asm sei PLE_Init (0; A) 24 wma CLeRFifo(); CLrs#ifo(); // initialize data structures DDRF G= 0x03; // Port T has ewitch inputs SCIED = 39; 17 max bandwidth depends on software+38400 bits/sec ScYcR1 = 0x00; // 8 bit character, SCICR2 = Ox2c; // Rev armed, Xat disarmed because Sfifo is enoty aom cli} int Send(messagetype *pt) (unsigned char data: // conpressed message int 011, data = {0xC0« (PORTI<<é6)}+ (04306 (pt~>destination<<4) ) + (0x08 (pt->information)) 7 Full = sput (data); // start to send SCICRZ = OxRC; 17 arm transmitJonathan W. Valvano 159 return(full); } // error if Sfifo is full Ant Accept (nessagetype *pt) {unsigned char data: // compressed message int engtys empty = Rget(edata); // try to receive if (empty==0) ( ‘pt->source = data>>6; ptrodestination = 02036 (data>>4) Bt-Dinformation = Ox0Fddata? ) return(empty); )_// no message if Rfito is empty void interrupt 20 scthandler(void) ( unsigned char data: AE(SCISRIERORF)(—// incoming message data = ScIORL; // xead message, ack Lf (PTT 40203) m= (02036 (gata>>4)) Rput (data); // match accept into this computer else Spot (data); } // no match retransmit to other computers As(scTsaierpRe) ( // tine to send outgoing message 48 (Suet (saata) 7) SCECR2 = 0x2; // MT disarmed because Sfifo empty else SCIDRL = data: }) // Initiate output, acknowledge interrupt Part d) Let baud be the band rate in bits/sec (38400bits/se<) bandwidth=baud+(t bits of information/frame)(10 bits/frame) = 15360 bits/sec = 1920 bytes/see 6811 Solution 14.2. arta) When the fifo is fll, the 6811 should not acknowledge data, so the TEEE488 will stop sending it Patt b) Show all the software 1 Globalsat 0x0000, stack at Ox00ff, program at OxE000 Binclode “pointerfifo.h" // implenentation in Chapter 4 7+ Fifo Data and pointers go in 0000 to OOFF RAM */ define DAV ox02 define DAC 0208 \ J+ Programs go in E000 to FEF ROM */ W starts here after reset, stack at Ox00RF void main(void) ( unsigned char full, recult, aem(" sei"); TMSK2 = 07 J* two Lsbs axe timer prescale, 500 ns */ initFison)? SCCRI = 07 7+ MeO for @ bit data */ BAUD = 0x357 7+ 300 bits/sec */ SCOR? = 0x08? 7s TIE=0, Teel */ ORC = 0x002 /* Port € are inputs */ PORTA = 07 7 paceo */ PIOC = 0x007 /* STATO no interrupts */ aom("cli") 7 while) ¢ ‘hile ((PORTR & DAV) t= 0)7 J+ Wait for DAV=O */ resultsPoRrC; J* Read fron TEEESOS device */ FullePutF ifo (result)? asn(” sei"); 7+ nem output process */ SCCR2 = 04887 Ye Trpei, Teed */ asm("cli"); white (full) fulleputrito(result); /* wait for room in fifo */ PORTR*DRC: J Acknowledge to TEEESS® */ while ((PORTA & DAV) == 0); J+ wait for ORVEL */ PORTA*0? }) J paceo */ #pragna interrupt_nandler scThandler () yoid scihandler (void) { unsigned char data, Empty; LE(SCSR & 0360) { Bapty = GevFifo(edata) ; Agtampty) SCCR2= 0x08; /* Disarm Sf empty */ else SCDR = datay }) /* send next if not empty */ J+ Hifo programs also go in E000 to FEFE ROM */ Jonathan W. Valvano160 Solutions Manual for Real Time Embedded Systems, 2™ Edition (6812 Solution 14.2, DAV=PM3, DAC=PMO, Data=PIT arta) When the fifo is full, the 6812 should not acknowledge data, so the IEEE488 will stop sending it Part b) Show all the software 1] Giobals at 0x3800, stack at Ox3£tt, progran at 0x10 Wanclude "posnterfifo.h" // imphenentation in Chapter 4 J+ igo Date and pointers go in 3800 to SEFF RAM */ fdetine DAY 0x02 fdetine DAC 0x08 void main (void) { unsigned char full, results TSCRL = 0x807 // enable TENT TSCR2 = 0x01; // S00ns clock Figo tait() SCIBB = 832: // 300 bits/sec («ume CLK) SCICRI = 0x00; // 8 bit character SCICR2 = 0x08? // TIER, Teel DDRI = 0x00; // Port T are inputs from deta DDRE = 0x08; // BES output, PAO input PIM = 0: 71 Dace asm cli while(2) ( while (PTH & DAV) != 0): J+ Wait for DAV=0 */ result = PIT; /* Read from TEEEGB device */ fell = Fito Put (zesult); scrce2 = 0x88; ds Trped, 162 */ while (full) full-Putsifo(result); /* wait for room in fifo */ PPM = DAC: /+ Reknowledge to TEBEGSS */ while ((PTM © DRY) == 0); 7+ fast for BAVeL +/ Pre = 0; )) 7 paes0 */ void interrupt 20 ecihandler(void) | unsigned char date, Empty; AE(SCTSRI & 0x80) { Empty = Fifo Get (sdata) ; if (empty) SCICRZ= 0x08) (* Disarm if empty */ “SCIDRL = data; }} /* send next if not empty */ (6811 Solution 143 1/ ghobals at 0x0000, stack at Ox00€2, program at 0xE000 Hinclude "pointertizo.n" // implenentation in Chapter 4 1 Fifo Data and pointers go in 0000 to OOFF RAM 71 vort B connections to SCSI control signals define co 0x04 define TO 0x02 define REQ 0x02 /* yrograms go in E000 to FEF ROM */ W/ BC7=PCO Anputs = SCSI DAZA 1/ STRAWROR interrupt on fall, then on rise void Init (void) { unsigned char dummy: asm(* sei") TMSK2 /1 two Lsbs axe timer prescale, 500 ns Scerl = 0; // MoO for 8 bit data BADD = 0x32; // 2400 bits/sec SCCR2 = Gx08; // 11E-0, 7E-1 PI0C=0x40;// EGA=O, STAI, wait for falling ACK first DORC=0%00;// STRATACK PORTB=0x00; _ // CD=IO=REQ=O dumy=P10c; dunmy=PORICL? // clear SIAF instFito)7 asm(¥ eli"}:) Fpragna interrupt_handler SIRARaN() void SIRAHan (void) { unsigned char dummy: AE(PIOC & 0x02)( // this is rising ACKJonathan W. Vaivano 161 Proce0x407 1] BoR=0, SEAT, falling next DunmysPORTCL; // ack, Clear STAP PORIE=0x007, 11 CD=t0=RED=0 1 else( I] this is failing ack Ploceax427 77 Boa=i, STAI, rising next PutFifo(PORICL); // ack, Clear STAE SCOR? = 0x88; | // TIES, TE=1 PORTB*REQ? V1 cD=1020, REQ=1 ) , pragma interrupt_handler scthandier() void scihandler (void) ( unsigned char data, Bapty: SE(SCSR @ 0x80) ( Empty = Get¥ifo(edata)s Ar (empty) ‘SCCR2= 0x08; /* Digarm Sf empty */ else SCOR = data; }) /* send next 1f not empty */ W/ starts at main after reset, stack at Ox00FE void main(void) { Tait // initialize STRR, Serial port waite th) 17 ) 7* $ifo prograns also go in B000 to FFFF ROM */ 6812 Solution 143. 712=C/D, PMI=1/0, PMO“REQ, PIT=RCK, PeTminput J/ ghobals at 0x3800, stack at Ox3E##, program at 0x4000 include "pointerfifo.n* // implenentation in Chapter 4 // ¥ifo Data and pointers go in 3600 to 37ff RAM 7/ Port M connections to SCSI contxol eignale féetine co 0x03 fdefine 10 0x02 Adefine REQ 0x02 71 Pr7-PTO inputs = SCST DATA V1 eSTWAGK interrupt on fall, then on rise void Init (vosa) { unsigned char dunay; asm sei TScR1 = 0x80) 7scR2_ = ox01 Fifo_tnit ( SCIBS= 104; // 2400 bits/sec SCIGAL = 0x00; // 8 Bit character SCICR2 = 0x08; // 17860, TEL DORT = 0x00; // Port T are inputs, data bus DORM = 0x38; 7/ PM2=C/D, PAI=z/0, 'PMD=REQ output DORI &» 0x80; 7/ PUT = ACK, Antercupt input PST & 0x80; // fall on 207 BIBS |= 0x80; 7/ arm POT=RCK PIFT = 0x00; // clear flag for PST=ACK PIM = 0x00; 11 CD=TO=REQ=0 asm cli} void interrupt 24 Key#akedHan (void) { LE(PPST & 0x80)( // this is rising ack PPSs = 0x00; // falling edge interrupt next JJ enable 1x 77 S00ns clock erm = 0x0 WU CD=10=REQ=0 : else( I) this is falling ack PST =0x807 17 rising edge interrupt next Fifo_put (PIT); // read data ScicRz= 0x08; // T1Be1, Te1 PIM = REQ? 17 CD=T0%0, REQ=1 ) Jonathan W. Valvano162 Solutions Manual for Real Time Embedded Systems, 2™ Edition PIES © 0x80 U1 clear flag for PI7MACK : void interrupt 20 scinandler (void) ( unsigned char data, Empty: A£(SCESR1 & 0x80) { Enpty = Figo_Get (sdatals sf npty) SCICR? = 0x087 J Disarm if empty */ else SCIDRL © datas }) /* send next if not empty */ // starts at main after reset, stack at Ox0OFE void main(void) { nit ()? // snicialize Po7, serial port interrupts whale (Q) (7 ) Solution 14.4 Open collector NOT gates could be used in place of the NPN transistors Part a) ai PLS13 HO 4l ans Transmit bg = Input Oupat put Partb) Transmit Oxia Receive pat Crossing Input GroundJonathan W. Valvano 163 {6811 Solution 14.5. The objective of tis problem isto develop a message passing facility oo PAS; 6811 pao PCT-0 aa PAO Pag 6811 PC7-0 -—>| <—— -—| sPAS(II') acct eeeeereeeLceee Ae ey cee eee C70 XXXXK OOK Past al Computer T Ant Mode; // Ovstop, inwait sise, 2ewase fall oid Ratual (void) | Senco ees")? 11 wake atomic 77 20°43 sapur capture 1 233.48 sixple output INSK2 = 0x00; /7 500n8 clock PORTA 6= 0x08; 77 PRIMO ode =07 eon? // clears €£0 , void Stare(onsigned cher data) ( Banc" sei") WT nake atente PoRte=datas TerL2 =(2e1L260x"C) 10x01; // ising of FAO INGE Je 0x0) // acm 209/280 EeuGl = Ox01; // anstaally cles 2onra f= 02087 /) Babel Mode “1; (means waicing tor vise asec elt) 2) wold Putssg unsigned char data) { itweae) Fife Pot (data) // previous in progress Stare (datal;) // was idle, 20 start st up pragna interrupt handler Te3Ran() void Te3han (ves) unsigned mar dates ‘Pruglecx0l;// acknowledge BE (lode ==) ( TOM? =(TCT2«O«EC) |0x027 // fadLing of FAO PORTA Go 0408; // PR2=0 Nowe 27) aise { AEifo_ee(sdatay) // returns 0 Lf empty seazesata)? //‘ continue eee ode =0:)) // no nore Fart by Computer 7 Sat Moder // Onvast for sive, lease £012 void Aieual (vesa) aem(" cei") 1 wake atonic 71'm0 is input capture 11 2x31 simple outpat fuse2, = 0x00? // 500ns clock PORTA Ge -0208; _// PAS=O TOM? =(TeTE2GDxEC) |Ox01; // rising of PAO fuGKA [= 0x02; // Arm 33/PA0 qeigl = Gx01; /7 snstsaily clear Node 07 Wy weane waiving for rise Fifo init: // clears fifo ase( cit"): ‘unsigned char Gettsg void) ( unsigned char dats while (1Fszo. See (edata) ) (07, Fetura(aetali | jpragna interrupt handler iCdtian() eid Tekan vos) TELGIMOx02;,—/) acknowledge Sf (ode ==0){ “//'mode=0 means rising edge Hao. Pue(2OR2C);// read and save tend w(TerL2e0xFC) 10x02) //" falling of FAO PORTA To 0300) // PAD Node =71 else t ‘ToTl2 =(Fer12¢0xte) {0x01 // xieing of PO Porta ge -03087" // 2a3—0 Mode Dy U/ Le0k for moze ) , {6812 Solution 14.5. The objective of this problem is to develop a message passing facility. 9512C32 uses PTAD instead of Port H. On the MC68HC812A4, you could use Port H forthe data, 7 eri —>| PIT 6812 pig Pre 6812 PAD7-0 |}-———>|PAD7-0 Pr7ei") ——I- Prec") ——__f 1 PADI YOK OK Part a) Conpueer T Ant Mode; // Osstop, lewait rise, 2eaie fal void Ritual (roid) t tem sed 1/ make atonse 1103 &= ~0x40; // PFE input capture ‘arDoraN = OnE BORAD = O¥FE; // output date Dorr te -0x40: // PEs ka inpse DORE f= 0880/7 P17 Se oueput Tsck2 |= 0x80; 77 enable Tent eck > ont) // Soon clock Pra Ge 0x80 // 38700 Mode = 03 Fito Tait); // clears £i¢0 asm ol Part b) Computer 7 Ene Mode; // Onwait for rése, Iewait fall void Rizua? (void) ( sm sed 11 make atomic TIS &+ -0x80; // PI? input capture ARDDEEN = OxEe? DORAD'= 0800 // Smpur agea DOR? b= -0x60; 7 FI? 4s input Soar I= Owe0: 77 #36 Se output sscan |= 0280; /7 enable reat rsck2 7 ox01; 7/ S00ns clock PRE Ge “oxs0 77 P00 HCILS =(HC12340x96) 10407 _// séaing of 107 MIE I~ 0x80) // Aen 0? MHL] = O330;// snitially clear Nose = 11 meane waiting for zie0 Jonathan W. Valyano164 Solutions Manual for Real Time Embedded Systems, 2 Edition ‘Vora stave tuneignea char dita? Wie inten? 77 clears Sie don set 77 make avaaic asm cit PIAD = datay F IC2L3 = (2CTLSEONCE) 10=202 // eiaing of C6 ‘nasged char Getaeg (void) { unsigned char data: THE |# Oxa0;//'hum 08 wade rEifo eet (edata)) (0s {itet = 0x40: // initially clear vevura (data) Penis odds 77 P27=1 1 Mode = 17 moans waiting for rise void intersupt 15 1e7Han (void) { nen eis ‘TeuGl = OW00;// Acknowledge Affiiede == 0){ // mode0 nesne rising edge d Youd PoeMag (unsigned enar ata) ( Fito Pue(Ptho); // Zesa and save 32 Gfode) rerbie(r011340x38) 10x80s,// folding of 207 Fife Put (data); // previous in progress BEE I= Oxads// PPG as Node Start (data): // was idle, so start ie up else ( : COLD =(ICHLIEOHSE) |Det0r // ising of 107 Youd intexragt 14 Te6zan(voia)( PEL be -0ui0;// Pr6H0 misigned char data; Node = OF (1 ook for nore TLG1 = 0240)" // acknowledge , Sf (eds =1) ( d CTI) =(FEMLIEOxCE) 10x20: // Ealing of 16 PIE ge -02807 7/7 P17=0 ode = erset TE(wite oe (caseal) // returns 0 Af empty stare(aata);// continve Node = 0; // no nore , D 146. Creates the transmission shown in Figure 14.13. 1/ Receive S-bit data from slavel, and send @-bit data? to slave 2 uneigned char 12c_sendlé_13(char Slavel, char elave2, unsigned char dataz) ( unsigned char data: TBCR |= 0x302 11 send START IBDR = slave) 0x01; 17 send addzess with 00=1 eignitying read while ( (18SR40x02)="0) (J // wait for the address to be sent Ber = 0x02) 1 clese IBIE BCR g= =0x18 17. Tx/Rxe0, and THAK=O datat = TBO 1] dusmy xead to initiate receiving while ((IBSR&0%02)==0){}; // wait for the data to be received BSR = 0x02; W cheat IBIE BCR |= 0x08: 1 PRK datal = TADR; W/ capture first byte, initiate second IBCR |= 0x30; 17 send START BOR = olave2c0xF#; _—_// send address with D0-0 signifying write while ((18SR40x02) ==0) (); // wait for the address to be sent qesR = 0x02; 1) clear TBIE BOR = data2; 1) send data? to slave2 1 // wait for the data to be sent W/ clear IBIE 47 send 8702 whe ( (TBSRE0%02) zeturn datal; , Solution 14:7. Frame size is 29+32436= 97 bits. Bandwidth is 4bytes/frame times 100,000bitssec divided by 97 bitsframe = 4123 BYTESISEC. Solution 14.8. Frame size is 11+64+36= 111 bits. Bandwidth is Sbytes/fiame times 100,000 bitsfiame = 7207 BYTESISEC ‘Solution 14.9. In the worst cases messages can arrive every tq. There are five receive buffers on the 9$12C32. ‘CAN interface. After one buffer is full, the RXF flag is first set. 4*tyu later i is possible that all five buffers will be fill. Latency requirement is 4*tyiq. This value assumes the CAN interrupt will receive all pending messages, ‘emptying the FIFO. Extra Question 14.10. In a CAN network, what isthe purpose of the DLC field? 1e., What is it used for? Extra Solution 14.10. The DLC is a 4-bit field specifying the number of data bytes (0-8) in the message. sec divided by 111Jonathan W. Valvano 165 Extra Question 14.11. In a CAN network, what i the purpose of the CRC field? Le, What is it used for? Extra Solution 14.11, The CRC is 2 15-bit field used to detect transmission errors Extra Question 14.12. Assuming transfer rate of 100,000 bits/see on a CAN network and each message contains 4 bytes, what i the maximam bandwidth of the network (in units of bytes of data per sec)? Assume there is no bit- stuffing and the ID is 11 bits. Extra Solution 14.12. The Intermission Frame Space (IFS) separates one frame ffom the next. There are two factors that affect the number of bits in a CAN message frame. The ID (1 or 29 bits) and the Data fields (0,8, 16, 24, 32, 40, 48, 56, of 64 bits) are variable length. The remaining components (36 bits) of the frame are fixed length including SOF (1), RIR (1), IDE/rl (1), 10 (1), DLC (4), CRC (15), and ACK/EOFFintermission (13). A Standard CAN 2.04 frame with 4 data bytes has 11*32436 = 79 bits. Some CAN systems add Stuff Bits; the number of ‘hich depends on the data transmitted, Let n be the numberof data bytes (0 8). For example, CAN 2 0A may add ‘34m stuf bits and a CAN 2.0B may add 54m stuff bits 100,000 bits/sec * 1 fiame/79bits* 4 bytes/frame = 5063 bytes/see Extra Question 14.13. Consider a producer/eonsumer problem linked by a FIFO queue. Both the producer thread and the consumer thread operate in the background using interrupt synchronization, The input device is a CAN reetiver, and the output device is SCI transmitter. When the CAN input is ready an interrupt-38 is generated, and the producer thread (CAN input ISR) reads the data and puts them into 2 FIFO. When the SCI output is idie, an interrupt-20is generated, and the consumer thread (SCI output ISR) gets data from the FIFO and writes them to the output device. Fifo_Get |= Output| Part) The initialization software will clear the FIFO. Which threads should be armed at this time? ‘A) The consumer (SCI output) 'B) The producer (CAN input) ©pBoth D) Neither art b) After the producer thread puts data into the FIFO, it checks the FIFO status, It will disarm itself if it finds the FIFO is fill. When should the producer thread be rearmed? ‘A) Only by the ritual 'B) On the next output interrupt (when the SCI output device is idle) ©) On the next input interrup (when new CAN input i received) ) The producer will call £ifo_Put over and over until it snot fall Part ©) The consumer thread diserms itself if it finds the FIFO is empty. When should the consumer thread be reamed? ‘A) Only bythe ritual 'B) On the next output interrupt (when the SCI output device is idle) © On the next inpat interrupt (when new CAN inputs received) D) The consumer will call Fi£0_Get over and over until itis not empty Extra Solution 14.13, Consider a producer/consumer problem linked by a FIFO queve arta) The best choice isto arm the producer (CAN input), because the Ffo is empty and the fist operation to occur will be to receive input data and Put it into the Fifo. If you were to arm just the consumer. that interrupt would occur resulting inthe input being armed and the output disarmed. Similarly, ifyou were to arm both, the output channel ‘would trigger and disarm itself beceuse the fifo is empty. If you armed neither, then no input/output could ever Part b) The producer thread isthe input channel, which should be earmed when there is more space in the ffo.on the next output interrupt (when the SCI output device is idle) Part c) The consumer thread isthe output channel, which should be rearmed when more data is put into the fifo, ‘Which occurs on the next input interrupt (when new CAN input is received) Input Jonathan W. Valvano