Qts Qii53001 4

2.
Mentor Graphics ModelSim Support
QII53001-9.0.0
Introduction
An Altera ® Quartus® II software subscription includes a no-cost entry-level software
version of the ModelSim® -Altera software on a PC or UNIX platform. Altera also
offers the ModelSim-Altera Subscription Edition software that has full support for
Altera devices. You can use the ModelSim-Altera Starter Edition software to perform
register transfer level (RTL) functional, post-synthesis, and gate-level timing
simulations for either Verilog HDL or VHDL designs that target an Altera FPGA. This
chapter provides detailed instructions about how to simulate your design in the
ModelSim-Altera version or the Mentor Graphics ® ModelSim software version. This
chapter provides details about the specific libraries that are needed for an RTL
functional, post-synthesis, and gate-level timing simulation.
The following topics are discussed in this chapter:
■ “Background”
■ “Software Compatibility” on page 2–3
■ “Altera Design Flow with ModelSim-Altera or ModelSim Software” on page 2–3
■ “Simulation Libraries” on page 2–4
■ “Simulation Netlist Files” on page 2–12
■ “Perform Simulation Using the ModelSim-Altera Software” on page 2–18
■ “Perform Simulation Using the ModelSim Software” on page 2–38
■ “Simulating Designs that Include Transceivers” on page 2–64
■ “Using the NativeLink Feature with ModelSim-Altera or ModelSim Software” on
page 2–70
■ “Generating a Timing VCD File for PowerPlay” on page 2–78
■ “Viewing a Waveform from a .wlf File” on page 2–78
■ “Scripting Support” on page 2–79
■ “Software Licensing and Licensing Setup in ModelSim-Altera Subscription
Edition” on page 2–80
f For more information about the current Quartus II software version, refer to the
Altera website at www.altera.com.
Background
ModelSim-Altera software is included with your Altera software subscription and can
be licensed for PC, Solaris, or Linux platforms to support either Verilog HDL or
VHDL simulation. ModelSim-Altera software supports RTL functional,
post-synthesis, and gate-level timing simulations for all Altera devices.
© March 2009 Altera Corporation Quartus II Handbook Version 9.0 Volume 3: Verification
2–2 Chapter 2: Mentor Graphics ModelSim Support
Background
Table 2–1 describes the differences between the Mentor Graphics ModelSim SE/PE
and ModelSim-Altera software versions.
Table 2–1. Comparison of ModelSim Software Versions

ModelSim-Altera
Product Feature ModelSim SE ModelSim PE ModelSim-Altera Starter Edition
100% VHDL, Verilog HDL, mixed-HDL Optional Optional Supports only Supports only
support single-HDL single-HDL
simulation simulation
Complete HDL debugging environment v v v v
Optimized direct compile architecture v v v v
Industry-standard scripting v v v v
Flexible licensing v Optional v —
Verilog PLI support. Interfaces Verilog HDL v v v v
designs to customer C code and third-party
software
VHDL FLI support. Interfaces VHDL designs v — — —
to customer C code and third-party software
Standard Delay Format File annotation v v v(1) v (1)
Advanced debugging features and v — — —
language-neutral licensing
Customizable, user-expandable GUI and v — — —
integrated simulation performance analyzer
Integrated code coverage analysis and v — — —
SWIFT support
Accelerated VITAL and Verilog HDL v — — —
primitives (3 times faster), and register
transfer level (RTL) acceleration (5 times
faster)
Platform support PC, UNIX, Linux PC only PC, UNIX, Linux PC, UNIX, Linux
Precompiled libraries No No Yes Yes
Note to Table 2–1:
(1) ModelSim-Altera software only allows SDF annotation to modules in the Altera library.
Quartus II Handbook Version 9.0 Volume 3: Verification © March 2009 Altera Corporation
Chapter 2: Mentor Graphics ModelSim Support 2–3
Software Compatibility
Software Compatibility
Table 2–2 shows which ModelSim-Altera and ModelSim software version is
compatible with the Quartus II software versions. ModelSim versions provided
directly from Mentor Graphics do not correspond to specific Quartus II software
versions.
For help with the ModelSim-Altera licensing setup, refer to “Software Licensing and
Licensing Setup in ModelSim-Altera Subscription Edition” on page 2–80.
Table 2–2. Compatibility Between Software Versions

ModelSim-Altera Software Quartus II Software (1)
ModelSim-Altera and ModelSim software version 6.4a Quartus II software version 9.0
ModelSim-Altera and ModelSim software version 6.3g_p1 Quartus II software version 8.1
ModelSim-Altera and ModelSim software version 6.1g Quartus II software version 6.1, 7.0, 7.1, 7.2, and 8.0
ModelSim-Altera and ModelSim software version 6.1d Quartus II software version 6.0
ModelSim-Altera and ModelSim software version 6.0e Quartus II software version 5.1
ModelSim-Altera and ModelSim software version 6.0c Quartus II software version 5.0
ModelSim-Altera and ModelSim software version 5.8.e Quartus II software version 4.2
ModelSim-Altera and ModelSim software version 5.8
(1) Updated ModelSim-Altera pre-compiled libraries are available for download on Altera’s website for each release of the Quartus II service pack.
Altera Design Flow with ModelSim-Altera or ModelSim Software

Figure 2–1 illustrates an Altera design flow using the Mentor Graphics
ModelSim-Altera software or the ModelSim software.
Simulation Libraries
Figure 2–1. Altera Design Flow with ModelSim-Altera Software, ModelSim Software, and Quartus II Software
ALTERA IP
Design Entry
Testbench .v/.vhd RTL Functional Simulation (1)

.v/.vhd
(4)
Functional
Synthesis Simulation
Library Files
Verilog Output
File and VHDL .vo/.vho
Output File
Post-Synthesis Simulation (2)

.v/.vhd
(4)
Post-Synthesis
Place-and-Route Simulation
Library Files
Verilog Output Standard Delay

File and VHDL .vo/.vho .sdo Format Output
Output File File
Gate-Level Timing Simulation (3)

.v/.vhd
(4)
Gate-Level
Simulation
Library Files
Notes to Figure 2–1:

(1) An RTL functional simulation is performed before a gate-level timing simulation or post-synthesis simulation. RTL functional simulation verifies
the functionality of the design before synthesis and place-and-route. If you are performing an RTL functional simulation through NativeLink, you
must complete Analysis and Elaboration first.
(2) A post-synthesis simulation verifies the functionality of a design after synthesis has been performed.
(3) Gate-level timing simulation is a post place-and-route simulation to verify the operation of the design after timing delays have been calculated.
(4) In the ModelSim-Altera software, you do not have to compile the simulation library files, as they are already precompiled for you.
Simulation model libraries are required to run a simulation whether you are running
an RTL functional simulation, post-synthesis simulation, or gate-level timing
simulation. In general, running an RTL functional simulation requires the RTL
functional simulation model libraries, while running a post-synthesis or gate-level
timing simulation requires the gate-level timing simulation model libraries. You must
compile the necessary library files before you can run the simulation.
However, there are a few exceptions where you are also required to compile gate-level
timing simulation library files to perform RTL functional simulation. For example, the
following list shows some of the Altera megafunctions’ gate-level libraries required to
perform an RTL functional simulation using third-party simulators:
■ ALTCLKBUF
■ ALTCLKCTRL
■ ALTDQS
■ ALTDQ
■ ALTDDIO_IN
■ ALTDDIO_OUT
■ ALTDDIO_BIDIR
■ ALTUFM_NONE
■ ALTUFM_PARALLEL
■ ALTUFM_SPI
■ ALTMEMMULT
■ ALTREMOTE_UPDATE
1 To identify which type of simulation libraries are required to run the simulation for a
certain Altera megafunction, refer to the last page in the Altera megafunction
MegaWizard™ Plug-In Manager. This explains which simulation library files are
required to perform an RTL functional simulation for that particular megafunction.
Simulating the Transceiver Megafunction (for example, ALT2GXB) is also another

exception that requires the gate-level libraries to perform RTL functional simulation
and vice-versa.
For detailed, step-by-step instructions about how to simulate the Transceiver
Megafunction, refer to “Simulating Designs that Include Transceivers” on page 2–64.
Pre-Compiled Simulation Libraries in the ModelSim-Altera Software

In the ModelSim-Altera software, the pre-compiled libraries for both functional and
gate-level simulations are available. You do not have to explicitly compile these
library files before running the simulation directly.
It is important that the pre-compiled libraries provided in <ModelSim Altera
path>/altera> must be compatible with the version of the Quartus II software that is
used to create the simulation netlist. To check whether the pre-compiled libraries are
compatible with your version of the Quartus II software, refer to the <ModelSim Altera
path>/altera/version.txt file. This file shows which version and build of the Quartus II
software was used to create the pre-compiled libraries.
RTL Functional Simulation Libraries

RTL functional simulation libraries include the LPM simulation model, Altera
megafunction simulation model, and the low-level primitive simulation model.
Table 2–3 shows the pre-compiled library name and the location in the
ModelSim-Altera software for all RTL functional simulation models in VHDL.
Table 2–3. Pre-Compiled RTL Functional Simulation Libraries in the ModelSim-Altera Software (VHDL)
Pre-Compiled
RTL Simulation Model Library Name Location in ModelSim-Altera
LPM lpm <ModelSim-Altera installation directory>\altera\vhdl\220model\
Altera Megafunction altera_mf <ModelSim-Altera installation directory>\altera\vhdl\altera_mf\
Low-level Primitives altera <ModelSim-Altera installation directory>\altera\vhdl\altera\
ALTGXB Megafunction (Stratix GX) altgxb <ModelSim-Altera installation directory>\altera\vhdl\altgxb\
High-Level Primitives sgate <ModelSim-Altera installation directory>\altera\vhdl\sgate\
Low-Level Primitives alt_vtl <ModelSim-Altera installation directory>\altera\vhdl\alt_vtl\
ModelSim-Altera software for all RTL functional simulation models in Verilog HDL.
Table 2–4. Pre-Compiled RTL Functional Simulation Libraries in the ModelSim-Altera Software (Verilog HDL)
Pre-Compiled
RTL Simulation Model Library Name Location in ModelSim-Altera
LPM lpm_ver <ModelSim-Altera installation directory>\altera\verilog\220model\
Altera Megafunction altera_mf_ver <ModelSim-Altera installation directory>\altera\verilog\altera_mf\
Low-level Primitives altera_ver <ModelSim-Altera installation directory>\altera\verilog\altera\
ALTGXB Megafunction (Stratix GX) altgxb_ver <ModelSim-Altera installation directory>\altera\verilog\altgxb\
High-Level Primitives sgate_ver <ModelSim-Altera installation directory>\altera\verilog\sgate\
Low-Level Primitives alt_ver <ModelSim-Altera installation directory>\altera\verilog\alt_vtl\
Gate-Level Simulation Libraries

Gate-level simulation libraries include the supported Altera device atom simulation
models. Table 2–5 shows the pre-compiled library name and location in the
ModelSim-Altera software for all gate-level simulation models in VHDL.
Table 2–5. Pre-Compiled Gate-Level Simulation Libraries in the ModelSim-Altera Software (VHDL) (Part 1 of 2)
Device Pre-Compiled
Simulation Model Library Name Location in ModelSim-Altera
Arria ® II arriaii <ModelSim-Altera installation directory>\altera\vhdl\arriaii\
(without transceiver block)
Arria II arriaii_hssi <ModelSim-Altera installation directory>\altera\vhdl\arriaii_hssi\
(with transceiver block)
Arria II arriaii_pcie_hip <ModelSim-Altera installation directory>\altera\vhdl\arriaii_pcie_hip\
(with PCI Express)
Arria GX arriagx <ModelSim-Altera installation directory>\altera\vhdl\arriagx\
Table 2–5. Pre-Compiled Gate-Level Simulation Libraries in the ModelSim-Altera Software (VHDL) (Part 2 of 2)
Device Pre-Compiled
Arria GX arriagx_hssi <ModelSim-Altera installation directory>\altera\vhdl\arriagx_hssi\
Stratix® IV stratixiv <ModelSim-Altera installation directory>\altera\vhdl\stratixiv\
Stratix IV stratixiv_hssi <ModelSim-Altera installation directory>\altera\vhdl\stratixiv_hssi\
Stratix IV stratixiv_pcie_hip <ModelSim-Altera installation directory>\altera\vhdl\stratixiv_pcie_hip
(with PCI Express)
Stratix III stratixiii <ModelSim-Altera installation directory>\altera\vhdl\stratixiii\
Stratix II stratixii <ModelSim-Altera installation directory>\altera\vhdl\stratixii
Stratix II GX stratixiigx <ModelSim-Altera installation directory>\altera\vhdl\stratixiigx
Stratix II GX stratixiigx_hssi <ModelSim-Altera installation directory>\altera\vhdl\stratixiigx_hssi
Stratix stratix <ModelSim-Altera installation directory>\altera\vhdl\stratix
Stratix GX stratixgx <ModelSim-Altera installation directory>\altera\vhdl\stratixgx
Stratix GX stratixgx_gxb <ModelSim-Altera installation directory>\altera\vhdl\stratixgx_gxb
HardCopy® II hardcopyii <ModelSim-Altera installation directory>\altera\vhdl\hardcopyii\
Cyclone ® III cycloneiii <ModelSim-Altera installation directory>\altera\vhdl\cycloneiii\
Cyclone II cycloneii <ModelSim-Altera installation directory>\altera\vhdl\cycloneii
Cyclone cyclone <ModelSim-Altera installation directory>\altera\vhdl\cyclone
MAX II
® maxii <ModelSim-Altera installation directory>\altera\vhdl\maxii
MAX 7000 max <ModelSim-Altera installation directory>\altera\vhdl\max
MAX 3000
APEX™ II apexii <ModelSim-Altera installation directory>\altera\vhdl\apexii
APEX 20K apex20k <ModelSim-Altera installation directory>\altera\vhdl\apex20k
APEX 20KC apex20ke <ModelSim-Altera installation directory>\altera\vhdl\apex20ke
APEX 20KE
Excalibur™
FLEX® 10KE flex10ke <ModelSim-Altera installation directory>\altera\vhdl\flex10ke
ACEX 1K
®
FLEX 6000 flex6000 <ModelSim-Altera installation directory>\altera\vhdl\flex6000\
ModelSim-Altera software for all the gate-level simulation models in Verilog HDL.
Table 2–6. Pre-Compiled Gate-Level Simulation Libraries in the ModelSim-Altera Software (Verilog HDL)
Device Pre-Compiled
Arria II arriaii_ver <ModelSim-Altera installation directory>\altera\verilog\arriaii\
Arria II arriaii_hssi_ver <ModelSim-Altera installation directory>\altera\verilog\arriaii_hssi\
Arria II arriaii_pcie_hip_ver <ModelSim-Altera installation directory>
(with PCI Express) \altera\verilog\arriaii_pcie_hip\
Arria GX arriagx_ver <ModelSim-Altera installation directory>\altera\verilog\arriagx\
Arria GX arriagx_hssi_ver <ModelSim-Altera installation directory>\altera\verilog\arriagx_hssi\
Stratix IV stratixiv_ver <ModelSim-Altera installation directory>\altera\verilog\stratixiv\
Stratix IV stratixiv_hssi_ver <ModelSim-Altera installation directory>altera\verilog\stratixiv_hssi\
Stratix IV stratixiv_pcie_hip_ver <ModelSim-Altera installation directory>
(with PCI Express) \altera\verilog\stratixiv_pcie_hip\
Stratix III stratixiii_ver <ModelSim-Altera installation directory>\altera\verilog\stratixiii\
Stratix II stratixii_ver <ModelSim-Altera installation directory>\altera\verilog\stratixii
Stratix II GX stratixiigx_ver <ModelSim-Altera installation directory>\altera\verilog\stratixiigx
Stratix II GX stratixiigx_hssi_ver <ModelSim-Altera installation directory>
(with transceiver block) \altera\verilog\stratixiigx_hssi
Stratix stratix_ver <ModelSim-Altera installation directory>\altera\verilog\stratix
Stratix GX stratixgx_ver <ModelSim-Altera installation directory>\altera\verilog\stratixgx
Stratix GX stratixgx_gxb_ver <ModelSim-Altera installation directory>\altera\verilog\stratixgx_gxb
HardCopy II hardcopyii_ver <ModelSim-Altera installation directory>\altera\verilog\hardcopyii\
Cyclone III cycloneiii_ver <ModelSim-Altera installation directory>\altera\verilog\cycloneiii\
Cyclone II cycloneii_ver <ModelSim-Altera installation directory>\altera\verilog\cycloneii
Cyclone cyclone_ver <ModelSim-Altera installation directory>\altera\verilog\cyclone
MAX II maxii_ver <ModelSim-Altera installation directory>\altera\verilog\maxii
MAX 7000 max_ver <ModelSim-Altera installation directory>\altera\verilog\max
MAX 3000
APEX II apexii_ver <ModelSim-Altera installation directory>\altera\verilog\apexii
APEX 20K apex20k_ver <ModelSim-Altera installation directory>\altera\verilog\apex20k
APEX 20KC apex20ke_ver <ModelSim-Altera installation directory>\altera\verilog\apex20ke
APEX 20KE
Excalibur™
FLEX 10KE flex10ke_ver <ModelSim-Altera installation directory>\altera\verilog\flex10ke
ACEX 1K
FLEX 6000 flex6000_ver <ModelSim-Altera installation directory>\altera\verilog\flex6000\
Simulation Library Files in the Quartus II Software

In ModelSim SE/PE, no pre-compiled libraries are available. You must compile the
necessary libraries to perform RTL functional or gate-level simulation. The following
sections show the location of these library files in the Quartus II directory structure.
You can refer to these library files for a particular simulation model.
RTL Functional Simulation Library Files

Table 2–7 shows the VHDL RTL simulation model location in the Quartus II directory.
Table 2–7. RTL Functional Simulation Library Files in the Quartus II Directory (VHDL)
RTL Simulation Model VHDL Libraries
ALTGX Megafunction <path to Quartus II installation directory>\eda\sim_lib\stratixiv_hssi_components.vhd
(Stratix IV GX) <path to Quartus II installation directory>\eda\sim_lib\stratixiv_hssi_atoms.vhd
LPM <path to Quartus II installation directory>\eda\sim_lib\220pack.vhd
<path to Quartus II installation directory>\eda\sim_lib\220model.vhd
<path to Quartus II installation directory>\eda\sim_lib\220model_87.vhd (1)
Altera Megafunction <path to Quartus II installation directory>\eda\sim_lib\altera_mf_components.vhd
<path to Quartus II installation directory>\eda\sim_lib\altera_mf.vhd
<path to Quartus II installation directory>\eda\sim_lib\altera_mf_87.vhd (1)
ALT2GXB Megafunction <path to Quartus II installation directory>\eda\sim_lib\stratixiigx_hssi_components.vhd
(Stratix II GX) <path to Quartus II installation directory>\eda\sim_lib\stratixiigx_hssi_atoms.vhd
<path to Quartus II installation directory>\eda\sim_lib\arriagx_hssi_components.vhd
<path to Quartus II installation directory>\eda\sim_lib\arriagx_hssi_atoms.vhd
ALTGXB Megafunction <path to Quartus II installation directory>\eda\sim_lib\stratixgx_mf_components.vhd
(Stratix GX) <path to Quartus II installation directory>\eda\sim_lib\stratixgx_mf.vhd
High-Level Primitives <path to Quartus II installation directory>\eda\sim_lib\sgate_pack.vhd
<path to Quartus II installation directory>\eda\sim_lib\sgate.vhd
Low-Level Primitives <path to Quartus II installation directory>\eda\sim_lib\altera_primitives_components.vhd
<path to Quartus II installation directory>\eda\sim_lib\altera_primitives.vhd
(1) Simulating a design that uses VHDL-1987.
Table 2–8 shows the Verilog RTL simulation model location in the Quartus II
directory.
Table 2–8. RTL Functional Simulation Library Files in the Quartus II Directory (Verilog HDL) (Part 1 of 2)
RTL Simulation Model Verilog HDL Libraries
ALTGX Megafunction (Stratix IV GX) <path to Quartus II installation directory>\eda\sim_lib\stratixiv_hssi_atoms.v
LPM <path to Quartus II installation directory>\eda\sim_lib\220model.v
Altera Megafunction <path to Quartus II installation directory>\eda\sim_lib\altera_mf.v
ALT2GXB Megafunction (Stratix II GX) <path to Quartus II installation directory>\eda\sim_lib\stratixiigx_hssi_atoms.v
<path to Quartus II installation directory>\eda\sim_lib\arriagx_hssi_atoms.v
ALTGXB Megafunction (Stratix GX) <path to Quartus II installation directory>\eda\sim_lib\stratixgx_mf.v
Table 2–8. RTL Functional Simulation Library Files in the Quartus II Directory (Verilog HDL) (Part 2 of 2)
RTL Simulation Model Verilog HDL Libraries
High-Level Primitives <path to Quartus II installation directory>\eda\sim_lib\sgate.v
Low-Level Primitives <path to Quartus II installation directory>\eda\sim_lib\altera_primitives.v
Gate-Level Simulation Library Files

Table 2–9 shows the VHDL gate-level simulation model location in the Quartus II
directory.
Table 2–9. Gate-Level Timing Simulation Library Files in Quartus II Software (VHDL) (Part 1 of 2)
Device Simulation Model Location in Quartus II Directory Structure
Arria II <Quartus II installation directory>\eda\sim_lib\arriaii_components.vhd
(without transceiver block) <Quartus II installation directory>\eda\sim_lib\arriaii_atoms.vhd
Arria II <Quartus II installation directory>\eda\sim_lib\arriaii_hssi_components.vhd
(with transceiver block) <Quartus II installation directory>\eda\sim_lib\arriaii_hssi_atoms.vhd
Arria II <Quartus II installation directory>\eda\sim_lib\arriaii_pcie_components.vhd
(with PCI Express) <Quartus II installation directory>\eda\sim_lib\arriaii_pcie_atoms.vhd
Arria GX <Quartus II installation directory>\eda\sim_lib\arriagx_components.vhd
(without transceiver block) <Quartus II installation directory>\eda\sim_lib\arriagx_atoms.vhd
Arria GX <Quartus II installation directory>\eda\sim_lib\arriagx_hssi_components.vhd
(with transceiver block) <Quartus II installation directory>\eda\sim_lib\arriagx_hssi_atoms.vhd
Stratix IV <Quartus II installation directory>\eda\sim_lib\stratixiv_components.vhd
<Quartus II installation directory>\eda\sim_lib\stratixiv_atoms.vhd
Stratix IV <Quartus II installation directory>\eda\sim_lib\stratixiv_hssi_components.vhd
(with transceiver block) <Quartus II installation directory>\eda\sim_lib\stratixiv_hssi_atoms.vhd
Stratix IV (with PCI Express) <Quartus II installation directory>\eda\sim_lib\stratixiv_pcie_hip_components.vhd
<Quartus II installation directory>\eda\sim_lib\stratixiv_pcie_hip_atoms.vhd
Stratix III <Quartus II installation directory>\eda\sim_lib\stratixiii_components.vhd
<Quartus II installation directory>\eda\sim_lib\stratixiii_atoms.vhd
Stratix II <Quartus II installation directory>\eda\sim_lib\stratixii_components.vhd
<Quartus II installation directory>\eda\sim_lib\stratixii_atoms.vhd
Stratix II GX <Quartus II installation directory>\eda\sim_lib\stratixiigx_components.vhd
(without transceiver block) <Quartus II installation directory>\eda\sim_lib\stratixiigx_atoms.vhd
Stratix II GX <Quartus II installation directory>\eda\sim_lib\stratixiigx_hssi_components.vhd
(with transceiver block) <Quartus II installation directory>\eda\sim_lib\stratixiigx_hssi_atoms.vhd
Stratix <Quartus II installation directory>\eda\sim_lib\stratix_components.vhd
<Quartus II installation directory>\eda\sim_lib\stratix_atoms.vhd
Stratix GX <Quartus II installation directory>\eda\sim_lib\stratixgx_components.vhd
<Quartus II installation directory>\eda\sim_lib\stratixgx_atoms.vhd
Stratix GX <Quartus II installation directory>\eda\sim_lib\stratixgx_hssi_components.vhd
(with transceiver block) <Quartus II installation directory>\eda\sim_lib\stratixgx_hssi_atoms.vhd
Table 2–9. Gate-Level Timing Simulation Library Files in Quartus II Software (VHDL) (Part 2 of 2)
HardCopy II <Quartus II installation directory>\eda\sim_lib\hardcopyii_components.vhd
<Quartus II installation directory>\eda\sim_lib\hardcopyii_atoms.vhd
Cyclone III <Quartus II installation directory>\eda\sim_lib\cycloneiii_components.vhd
<Quartus II installation directory>\eda\sim_lib\cycloneiii_atoms.vhd
Cyclone II <Quartus II installation directory>\eda\sim_lib\cycloneii_components.vhd
<Quartus II installation directory>\eda\sim_lib\cycloneii_atoms.vhd
Cyclone <Quartus II installation directory>\eda\sim_lib\cyclone.vhd
<Quartus II installation directory>\eda\sim_lib\cyclone_atoms.vhd
MAX II <Quartus II installation directory>\eda\sim_lib\maxii_components.vhd
<Quartus II installation directory>\eda\sim_lib\maxii_atoms.vhd
MAX 7000 <Quartus II installation directory>\eda\sim_lib\max_components.vhd
MAX 3000 <Quartus II installation directory>\eda\sim_lib\max_atoms.vhd
APEX II <Quartus II installation directory>\eda\sim_lib\apexii_components.vhd
<Quartus II installation directory>\eda\sim_lib\apexii_atoms.vhd
APEX 20K <Quartus II installation directory>\eda\sim_lib\apex20k_components.vhd
<Quartus II installation directory>\eda\sim_lib\apex20k_atoms.vhd
APEX 20KC <Quartus II installation directory>\eda\sim_lib\apex20ke_components.vhd
APEX 20KE <Quartus II installation directory>\eda\sim_lib\apex20ke_atoms.vhd
Excalibur
FLEX 6000 <Quartus II installation directory>\eda\sim_lib\flex6000_components.vhd
<Quartus II installation directory>\eda\sim_lib\flex6000_atoms.vhd
FLEX 10KE <Quartus II installation directory>\eda\sim_lib\flex10ke_components.vhd
ACEX 1K <Quartus II installation directory>\eda\sim_lib\flex10ke_atoms.vhd
Table 2–10 shows the Verilog HDL gate-level simulation model location in the
Quartus II directory.
Table 2–10. Gate-Level Timing Simulation Library Files in the Quartus II Software (Verilog HDL) (Part 1 of 2)
Arria II <Quartus II installation directory>\eda\sim_lib\arriaii_atoms.v
Arria II <Quartus II installation directory>\eda\sim_lib\arriaii_hssi_atoms.v
Arria II <Quartus II installation directory>\eda\sim_lib\arriaii_pcie_atoms.v
(with PCI Express)
Arria GX <Quartus II installation directory>\eda\sim_lib\arriagx_atoms.v
Arria GX <Quartus II installation directory>\eda\sim_lib\arriagx_hssi_atoms.v
Stratix IV <Quartus II installation directory>\eda\sim_lib\stratixiv_atoms.v
Stratix IV <Quartus II installation directory>\eda\sim_lib\stratixiv_hssi_atoms.v
Simulation Netlist Files
Table 2–10. Gate-Level Timing Simulation Library Files in the Quartus II Software (Verilog HDL) (Part 2 of 2)
Stratix IV <Quartus II installation directory>\eda\sim_lib\stratixiv_pcie_hip_atoms.v
(with PCI Express)
Stratix III <Quartus II installation directory>\eda\sim_lib\stratixiii_atoms.v
Stratix II <Quartus II installation directory>\eda\sim_lib\stratixii_atoms.v
Stratix II GX <Quartus II installation directory>\eda\sim_lib\stratixiigx_atoms.v
Stratix II GX <Quartus II installation directory>\eda\sim_lib\stratixiigx_hssi_atoms.v
Stratix <Quartus II installation directory>\eda\sim_lib\stratix_atoms.v
Stratix GX <Quartus II installation directory>\eda\sim_lib\stratixgx_atoms.v
Stratix GX <Quartus II installation directory>\eda\sim_lib\stratixgx_hssi_atoms.v
HardCopy II <Quartus II installation directory>\eda\sim_lib\hardcopyii_atoms.v
Cyclone III <Quartus II installation directory>\eda\sim_lib\cycloneiii_atoms.v
Cyclone II <Quartus II installation directory>\eda\sim_lib\cycloneii_atoms.v
Cyclone <Quartus II installation directory>\eda\sim_lib\cyclone_atoms.v
MAX II <Quartus II installation directory>\eda\sim_lib\maxii_atoms.v
MAX 7000 <Quartus II installation directory>\eda\sim_lib\max_atoms.v
MAX 3000
APEX II <Quartus II installation directory>\eda\sim_lib\apexii_atoms.v
APEX 20K <Quartus II installation directory>\eda\sim_lib\apex20k_atoms.v
APEX 20KC <Quartus II installation directory>\eda\sim_lib\apex20ke_atoms.v
APEX 20KE
Excalibur
FLEX 6000 <Quartus II installation directory>\eda\sim_lib\flex6000_atoms.v
FLEX 10KE <Quartus II installation directory>\eda\sim_lib\flex10ke_atoms.v
ACEX 1K

Simulation netlist files are required to perform post-synthesis simulation or gate-level
timing simulation. These simulation netlist files are generated from the EDA Netlist
Writer.
If you are performing post-synthesis simulation, the Verilog HDL Output File (*.vo) or
VHDL Output File (*.vho) is required. For the steps to generate post-synthesis
simulation netlist files for *.vo or *.vho files, refer to “Generate Post-Synthesis
Simulation Netlist Files” on page 2–13.
If you are performing gate-level timing simulation, the *.vo file or *.vho file and the
Standard Delay Format Output File (*.sdo) are also required. The *.sdo file is used to
annotate the delay for the elements found in the *.vo or *.vho file. The section
“Generate Gate-Level Timing Simulation Netlist Files” on page 2–14 shows you the
steps to generate simulation netlist files for *.vo or *.vho, and *.sdo files.
Generate Post-Synthesis Simulation Netlist Files

The following steps describe the process of generating post-synthesis simulation
netlist files in the Quartus II software:
1. Perform Analysis and Synthesis. On the Processing menu, point to Start and click
Start Analysis & Synthesis (you can also perform this after step 2).
2. Turn on the Generate Netlist for Functional Simulation Only option by
performing the following steps:
a. On the Assignments menu, click EDA Tool Settings. The Settings dialog box
appears.
b. In the Category list, expand EDA Tool Settings and click Simulation. The
Simulation page appears.
c. In the Tool name list:
■ If you are using the ModelSim-Altera software, select ModelSim-Altera.
■ If you are using the Mentor Graphics ModelSim software, select ModelSim.
d. Under EDA Netlist Writer options, in the Format for output netlist list, select
VHDL or Verilog. You can also modify where you want the post-synthesis
netlist to be generated by editing or browsing to a directory in the Output
directory box.
e. Click More EDA Netlist Writer Settings. The More EDA Netlist Writer
Settings dialog box appears.
f. In the Existing options settings list, click Generate netlist for functional
simulation only.
g. In the Setting list under Options, select On.
h. Click OK.
i. In the Settings dialog box, click OK.
3. Run the EDA Netlist Writer. On the Processing menu, point to Start and click Start
EDA Netlist Writer.
During the EDA Netlist Writer stage, the Quartus II software produces a *.vo file or
*.vho file that can be used for post-synthesis simulations in the ModelSim software.
This netlist file is mapped to architecture-specific primitives. No timing information is
included at this stage. The resulting netlist is located in the output directory you
specified in the Settings dialog box, which defaults to the <project
directory>/simulation/modelsim directory.
If you want to generate a post-synthesis simulation netlist with just the cell delays,
you can generate an *.sdo file without running the Fitter. In this case, the *.sdo file
includes all timing values for only the device cells. Interconnect delays are not
included because fitting (placement and routing) has not been performed. To generate
the post-synthesis netlist and the *.sdo file, type the following commands at a
command prompt:
■ quartus_map <project name> -c <revision name> r
■ quartus_sta <project name> -c <revision name> --post_map r

or
quartus_tan <project name> -c <revision name> --post_map \
--zero_ic_delays r
■ quartus_eda <project name> -c <revision name> --simulation \
--tool= <3rd party EDA tool> --format=<HDL language> r
For more information about the –format and –tool options, type the following
command at a command prompt:
quartus_eda --help=<options> r
Generate Gate-Level Timing Simulation Netlist Files

To perform gate-level timing simulation, the ModelSim or ModelSim-Altera software
requires information about how the design was placed into device-specific
architectural blocks. The Quartus II software provides this information in the form of
a *.vo file for Verilog HDL designs and a *.vho file for VHDL designs. The
accompanying timing information is stored in the *.sdo file, which annotates the
delay for the elements found in the *.vo file or *.vho file.
To generate a gate-level timing simulation netlist in the Quartus II software, perform
the following steps:
1. On the Assignments menu, click EDA Tool Settings. The Settings dialog box
appears.
2. In the Category list, click the “+” icon to expand EDA Tool Settings and select
Simulation. The Simulation page appears.
3. In the Tool name list:
■ If you are using the ModelSim-Altera software, select ModelSim-Altera.
■ If you are using the Mentor Graphics ModelSim software, select ModelSim.
4. Under EDA Netlist Writer options, in the Format for output netlist list, select
VHDL or Verilog. You can also modify where you want the post-synthesis netlist
to be generated by editing or browsing to a directory in the Output directory box.
5. Click OK.
6. In the Settings dialog box, click OK.
7. If you have not run a full compilation, perform a full compilation. On the
Processing menu, click Start Compilation.
8. If you have already run a full compilation, run the EDA Netlist Writer. On the
Processing menu, point to Start and click Start EDA Netlist Writer.
During the full compilation or EDA Netlist Writer stage, the Quartus II software
produces a *.vo file, *.vho file, and a *.sdo file used for gate-level timing
simulations in the ModelSim software. This netlist file is mapped to
architecture-specific primitives. The timing information for the netlist is included
in the *.sdo file. The resulting netlist is located in the output directory you
specified in the Settings dialog box, which defaults to the
<project directory>/simulation/modelsim directory.
Generating Timing Simulation Netlist Files with Different Timing Models

In Stratix III and later devices (for example, Cyclone III and Stratix IV), you can
specify different temperature and voltage parameters to generate the timing
simulation netlist files. If you enable the Quartus II Classic Timing Analyzer or
Quartus II TimeQuest Timing Analyzer when generating the timing simulation netlist
files (*.vo or *.vho and *.sdo), different timing models for different operating
conditions are used by default. Multi-corner timing analysis is run by default during
the full compilation.
Table 2–11 shows an example of default-available operating conditions (model,
voltage, and temperature) for Stratix III and Cyclone III devices.
Table 2–11. Default Available Operating Conditions for Stratix III and Cyclone III Devices
Device Family Model Voltage Temperature (°C)
Slow 1100 mV 85°
Stratix III Slow 1100 mV 0°
Fast 1100 mV 0°
Slow 1200 mV 85°
Cyclone III Slow 1200 mV 0°
Fast 1200 mV 0°
If multi-corner timing analysis is not run during full compilation, perform the
following steps to manually generate the simulation netlist files (*.vo or *.vho and
*.sdo) for the three different operating conditions listed in Table 2–11:
1. Generate all the available corner models at all operating conditions. Type the
following command at a command prompt:
quartus_sta <project name> --multicorner r
2. Generate the timing simulation netlist files for all three corners specified in
Table 2–11. Perform steps 2 through 8 in “Generate Gate-Level Timing Simulation
Netlist Files” on page 2–14. The output files are generated in the simulation output
directory.
The following examples show the timing simulation netlist files generated for the
operating conditions of the preceding steps, when Verilog is selected as the output
netlist format:
First slow corner (slow, 1100 mV, 85° C):

■ .vo file—<revision name>.vo
■ .sdo file—<revision name>_v.sdo
1 The <revision_name>.vo and <revision name>_v.sdo are generated for backward

compatibility in case there are existing scripts that still use them.
■ .vo file—<revision name>_<speedgrade>_1100mv_85c_slow.vo

■ .sdo file—<revision name>_<speedgrade>_1100mv_85c_v_slow.sdo
Second slow corner (slow, 1100 mV, 0° C):

■ .vo file—<revision name>_<speedgrade>_1100mv_0c_slow.vo
■ .sdo file—<revision name>_<speedgrade>_1100mv_0c_v_slow.sdo
Fast corner (fast, 1100 mV, 0° C):

■ .vo file—<revision name>_min_1100mv_0c_fast.vo
■ .sdo file—<revision name>_min_1100mv_0c_v_fast.sdo
For older devices, a slow-corner (worst case) timing model is used by default. There
are only two timing models available: slow-corner and fast-corner. To generate the
timing simulation netlist files using a different timing model, you must run the
Quartus II Classic Timing Analyzer or the Quartus II TimeQuest Timing Analyzer
with a different timing model before you start the EDA Netlist Writer.
To run the Quartus II Classic Timing Analyzer with the best-case model, on the
Processing menu, point to Start and click Start Classic Timing Analyzer (Fast Timing
Model). After timing analysis is complete, the Compilation Report appears.
You can also type the following command at a command prompt:
quartus_tan <project_name> --fast_model=on r
To run the Quartus II TimeQuest Timing Analyzer with a best-case model, use the
-fast_model option after you create the timing netlist.
The following command enables the fast timing models:
create_timing_netlist --fast_model r
After running the Quartus II Classic or Quartus II TimeQuest Timing Analyzer,
perform steps 2 through 8 in “Generate Gate-Level Timing Simulation Netlist Files”
on page 2–14 to generate the timing simulation netlist file. For fast corner timing
models, the -fast post fix is added to the *.vo or *.vho and *.sdo file (for example,
my_project_fast.vo or my_project_fast.vho and my_project_fast.sdo).
f For more information about running multi-corner timing analysis, refer to the
Quartus II Classic Timing Analyzer or the Quartus II TimeQuest Timing Analyzer chapter
in volume 3 of the Quartus II Handbook.
Disable Timing Violation on Registers

In certain situations, a timing violation can be ignored and you might want to disable
timing violations on registers. For example, timing violations that occur in internal
synchronization registers used for asynchronous clock domain crossing.
By default, the x_on_violation_option logic option is On, which means simulation
shows “x” whenever a timing violation occurs. To disable showing the timing
violation on certain registers, set the x_on_violation_option logic option to Off on
those registers. The following command is the Quartus II Tcl Command to disable
timing violation on registers. This Tcl command is also stored in the .qsf file.
set_instance_assignment -name X_ON_VIOLATION_OPTION OFF –to <register_name>
Compile Libraries Using the EDA Simulation Library Compiler

The EDA Simulation Library Compiler is used to compile Verilog HDL and VHDL
simulation libraries for all Altera devices and supported third-party simulators. You
can use this tool to compile all libraries required by RTL and gate-level simulation.
When the compilation targets third-party simulation tools such as ModelSim and
NC-Sim, the compiled libraries are kept in either the directory you set or the default
directory. When you perform the simulation using these simulators, you can use or
re-use the compiled libraries and avoid the overhead associated with redundant
library compilations.
However, if the Synopsys VCS or VCS-MX software performs the compilation while
running the EDA Simulation Library Compiler, the option files (simlib_comp.vcs) are
generated after compilation. You can then include your design and testbench files in
the option files and invoke them with the vcs command.
Before using this option, ensure the appropriate simulation tools are already installed
and their paths are specified. To specify the path, refer to “Setting Up NativeLink” on
page 2–70.
Run the EDA Simulation Library Compiler through the GUI

Starting with the Quartus II software 9.0 release, the EDA Simulation Library
Compiler contains a GUI. To compile libraries with the EDA Simulation Library
Compiler GUI, perform the following steps:
1. On the Tools menu, click EDA Simulation Library Compiler. The EDA
Simulation Library Compiler dialog box appears.
2. In the Tool name entry box under EDA simulation tool, select a simulation tool.
The Executable location box displays location of the simulation tool you specified.
This location must be set before running the EDA Simulation Library Compiler.
3. Under Library families, select one or more device families for your design
compilation and move them to the Selected families box.
4. Under Library language, select VHDL, Verilog, or both.
5. In the Output directory field, specify a location in which to store the compiled
libraries or option files.
6. Click Start Compilation.
For example, if you want to simulate a Verilog HDL design on a Stratix II device in the
ModelSim simulator, do the following:
■ Select ModelSim in the Tool name field.
■ Move Stratix II from the Available families list to the Selected families list.
■ Select Verilog in the Library language field.
■ Specify a location in the Output directory field in which to keep the user-compiled
libraries.
■ Click Start Compilation.
Perform Simulation Using the ModelSim-Altera Software
When the EDA Simulation Library Compiler finishes, all required libraries are
compiled and stored in the output location you specified. The next time you perform
simulation in ModelSim, you only have to compile your design and testbench files.
You do not have to compile the Altera libraries again.
The EDA Simulation Library Compiler supports only ModelSim SE/PE. It does not
support ModelSim-Altera, because ModelSim-Altera already contains precompiled
libraries.
If you use NativeLink to run the simulation, refer to “Using the NativeLink Feature
with ModelSim-Altera or ModelSim Software” on page 2–70.
Run EDA Simulation Library Compiler In Command Line

To run the EDA Simulation Library Compiler in the command line, type the following
command:
quartus_sh --simlib_comp -family <device> -tool <simulation tool name>
-language <language> -directory <directory> r
For more information about the command’s options and how to define them, type the
following command:
quartus_sh --help=simlib_comp r

Simulation of Verilog HDL or VHDL designs with ModelSim-Altera software can be
done at various levels to verify designs from different aspects. Simulation is divided
into three categories: RTL functional simulation, post-synthesis simulation, and
gate-level timing simulation. Simulation helps you verify your designs and debug
them against any possible errors in the designs.
You can perform the simulation through the GUI or on the command line. The
following sections provide step-by-step instructions to perform the simulation
through the GUI and on the command line.
For high-speed simulation, you must select ps in the Resolution list for your
simulator resolutions. If you choose slower than ps, the high-speed simulation may
fail.
Simulating the VHDL Designs through the GUI

Simulating the VHDL design using the ModelSim-Altera GUI is user-friendly. You do
not have to remember the commands to compile the libraries, or load and simulate the
VHDL design files. You can use the ModelSim-Altera GUI to perform RTL functional
simulation, post-synthesis simulation, and gate-level timing simulation. The
following sections show how to perform simulation at various levels through the
ModelSim-Altera GUI.
Perform RTL Functional Simulation

RTL functional simulation is typically performed to verify the syntax of the code and
to check the functionality of the design. The following sections show how to perform
RTL functional simulation in the ModelSim-Altera software for VHDL designs.
Use the following instructions to perform an RTL functional simulation for VHDL
designs in the ModelSim-Altera software.
1 The ModelSim-Altera software includes pre-compiled simulation libraries. Creating

simulation libraries and compiling simulation models are not required.
Compile Testbench and Design Files into the Work Library

The following instructions show you how to compile your testbench and design files
into the work library using the ModelSim-Altera GUI.
1. In the ModelSim-Altera software, on the File menu, click Change Directory. The
Choose Folder dialog box appears.
2. Browse to the directory where your designs are located.
3. Click OK.
To create the work library, perform the following steps:
1. In the ModelSim-Altera software, on the File menu, point to New and click
Library. The Create a New Library dialog box appears.
2. Select a new library and a logical mapping to it.
3. In the Library Name box, type the library name Work in the text box.
4. Click OK.
To compile the testbench and design files into the work library, perform the following
steps:
1. On the Compile menu, click Compile. The Compile Source Files dialog box
appears.
2. Select the library Work. The design files and testbench file should be compiled into
the Work library.
3. Select the design files and testbench file, and click Compile.
4. Click Done.
1 Resolve compile-time errors before proceeding to the next section.
Loading the Design

To load a design, perform the following steps:
1. On the Simulate menu, click Start Simulation. The Start Simulation dialog box
appears.
2. In the Start Simulation dialog box, click the Design tab. In the Resolution list,
select ps.
3. In the Library list, select and expand the Work library.
4. Select the top-level design unit (your testbench).
5. In the Resolution list, select ps.
6. For VHDL designs, if you have not included the libraries’ mapped name in your
design files or sub-files, perform the following steps:
a. Click the Libraries tab.
b. In the Search Libraries text box, click the Add button.
c. Browse to the required pre-compiled library in the ModelSim-Altera software.
You can either click Browse and go to the path <ModelSim-Altera installation
directory>/altera/vhdl/<pre-compiled library> or you can just click the arrow
button to select the <pre-compiled library mapped name>.
Examples of <pre-compiled library> or <pre-compiled library mapped name> are
altera_mf and lpm. The functional RTL simulation libraries are usually
required for performing RTL functional simulation. For the complete set of
libraries, refer to “Pre-Compiled Simulation Libraries in the ModelSim-Altera
Software” on page 2–5.
d. Click OK to add the libraries to the Search Libraries text box.
7. Click OK.
Running the Simulation

To run a simulation, perform the following steps:
1. On the View menu, point to Debug Windows and click Objects. This command
displays all objects in the current scope.
2. On the View menu, point to Debug Windows and click Wave.
3. Drag signals to monitor from the Objects window and drop them into the Wave
window.
4. On the Processing menu, point to Run and click Run 100 ps to run the simulation
for 100 ps.
Perform Post-Synthesis Simulation

Post-synthesis simulation verifies that functionality of the design is not lost after
synthesis. You can create the post-synthesis netlist in the Quartus II software and use
the netlist to perform post-synthesis simulation with the ModelSim-Altera software.
Before running post-synthesis simulation, generate post-synthesis simulation netlist
files. Refer to the instructions in “Generate Post-Synthesis Simulation Netlist Files” on
page 2–13.
The following sections help you perform a post-synthesis simulation for a VHDL
design in the ModelSim-Altera software.

Compile Testbench and VHDL Output File into the Work Library
The following instructions show how you can compile your testbench and *.vho file
To change to the simulation output directory, perform the following steps:

2. Browse to the directory where your testbench or *.vho file is located. By default,
the *.vho file is located in <project directory>/simulation/modelsim.
3. Click OK.
4. Click OK.
To compile the testbench and VHDL output (*.vho) files into the work library, perform
appears.
2. Select the library Work. The testbench and VHDL output (*.vho) files should be
compiled into the Work library.
3. Select the testbench and *.vho design files and click Compile.
4. Click Done.
Loading the Design

appears.
select ps.
stratixiii and cycloneiii. The gate-level simulation libraries are usually
required for performing post-synthesis simulation. For the complete set of
7. Click OK.

window.
for 100 ps.
Perform Gate-Level Simulation

Gate-level simulation is a very important step in ensuring that the FPGA device’s
functionality is still correct and meets all required timing requirements after the
design was placed and routed. You can create the gate-level netlist in the Quartus II
software and use the netlist to perform gate-level simulation with the
ModelSim-Altera software.
Before running gate-level simulation, generate gate-level timing simulation netlist
files. Refer to the instructions in “Generate Gate-Level Timing Simulation Netlist
Files” on page 2–14.
The following sections help you perform a gate-level simulation for a VHDL design in
the ModelSim-Altera software.

The following instructions show how you can compile your testbench and *.vho file

3. Click OK.
4. Click OK.
To compile the testbench and VHDL output (*.vho) files into the work library, perform
appears.
2. Select the library Work. The testbench and VHDL output (*.vho) files should be
compiled into the Work library.
3. Select the testbench and VHDL output (*.vho) design files, and click Compile.
4. Click Done.
Loading the Design

appears.
2. Click the SDF tab, and click Add. The Add SDF Entry dialog box appears.
3. In the Add SDF Entry dialog box, click Browse and select the *.sdo file. By default,
the *.sdo file is located in <project directory>/simulation/modelsim.
4. In the Apply to Region dialog box, type the instance path to which the *.sdo file is
to be applied. For example, if you are using a testbench exported into the
Quartus II software from a Vector Waveform File, the instance path is set to /i1.
1 You do not have to choose from the Delay list because the Quartus II EDA Netlist
Writer generates the *.sdo file using the same value for the triplet (minimum, typical,
and maximum timing values).
5. Click OK.
select ps.

stratixiii and cycloneiii. The gate-level simulation libraries are usually
required for performing gate-level simulation. For the complete set of libraries,
refer to “Pre-Compiled Simulation Libraries in the ModelSim-Altera Software”
on page 2–5.
11. Click OK.

window.
for 100 ps.
Simulating Verilog HDL Designs through the GUI

Simulating the Verilog HDL design using the ModelSim-Altera GUI is user-friendly.
You do not have to remember the commands to compile the libraries or load and
simulate the Verilog HDL design files. You can use the ModelSim-Altera GUI to
perform RTL functional simulation, post-synthesis simulation, and gate-level timing
simulation. The following sections show how to perform simulation at various levels
through the ModelSim-Altera GUI.

RTL functional simulation in ModelSim-Altera for Verilog HDL designs.
Use the following instructions to perform an RTL functional simulation for Verilog
HDL designs in the ModelSim-Altera software.


The followings instructions show you how to compile your testbench and design files
To change to the design directory, perform the following steps:
3. Click OK.
4. Click OK.
steps:
appears.
the Work library.
3. Select the design files and testbench file and click Compile.
4. Click Done.
Loading the Design

appears.
select ps.
6. Click the Libraries tab.
7. In the Search Libraries text box, click the Add button.
8. Browse to the required pre-compiled library in the ModelSim-Altera software. You

can either click Browse and go to the path <ModelSim-Altera installation
directory>/altera/verilog/<pre-compiled library> or you can just click the arrow
altera_mf_ver and lpm_ver. The RTL simulation libraries are usually required for
performing RTL functional simulation. For the complete set of libraries, refer to
“Pre-Compiled Simulation Libraries in the ModelSim-Altera Software” on
page 2–5.
9. Click OK to add the libraries to the Search Libraries text box.
10. Click OK.

window.
for 100 ps.

Post-synthesis simulation can be performed to verify that functionality of the design
is not lost after synthesis. You can create the post-synthesis netlist in the Quartus II
software and use the netlist to perform post-synthesis simulation with the
page 2–13.
The following sections help you perform a post-synthesis simulation for a Verilog
HDL design in the ModelSim-Altera software.

Compile Testbench and Verilog HDL Output File into the Work Library
The following instructions show how you can compile your testbench and Verilog
HDL output file (*.vo) into the work library using the ModelSim-Altera GUI.
2. Browse to the directory where your testbench or *.vo file is located. By default, the
*.vho file is located in <project directory>/simulation/modelsim.
3. Click OK.
4. Click OK.
To compile the testbench and Verilog HDL output (*.vo) files into the work library,
perform the following steps:
appears.
2. Select the library Work. The testbench and Verilog HDL output (*.vo) files should
be compiled into the Work library.
3. Select the testbench and *.vo design files, and click Compile.
4. Click Done.
Loading the Design

appears.
select ps.
stratixiii_ver and cycloneiii_ver. The gate-level simulation libraries are usually
required for performing post-synthesis simulation. For the complete set of
10. Click OK.

window.
for 100 ps.

The following sections help you perform a gate-level simulation for a Verilog HDL

Compile Testbench and Verilog HDL Output File into the Work Library
The following instructions show how you can compile your testbench and *.vo file
*.vo file is located in <project directory>/simulation/modelsim.
3. Click OK.
4. Click OK.
To compile the testbench and *.vo files into the work library, perform the following
steps:
appears.
2. Select the library Work. The testbench and *.vo files should be compiled into the
Work library.
4. Click Done.
Loading the Design

When simulating in Verilog HDL, the *.sdo file does not have to be manually
specified. In the $sdf_annotate task, when the Quartus II software generates the *.vo
file, the ModelSim-Altera software looks for the *.sdo file in the folder in which the
VSIM was run. If your *.sdo file is not in the same directory in which you ran VSIM,
copy the *.sdo file into your current directory.
appears.
select ps.
Examples of <pre-compiled library> are altera_mf_ver and lpm_ver. The gate-level
simulation libraries are usually required for performing gate-level simulation. For
the complete set of libraries, refer to “Pre-Compiled Simulation Libraries in the
ModelSim-Altera Software” on page 2–5.
10. Click OK.


window.
for 100 ps.
Simulating the VHDL Designs at the Command Line

Simulating VHDL designs using the ModelSim-Altera command line gives you more
flexibility and control to compile the libraries, and load and simulate the VHDL
design files. All simulation commands are Tcl commands, which can be put into the
ModelSim Macros file (*.do). Using the *.do file allows you to run simulation in batch
mode. You only have to execute the *.do file and the ModelSim-Altera tool
automatically executes all commands in the *.do script macro file.
You can use the ModelSim-Altera command line to perform RTL functional
simulation, post-synthesis simulation, and gate-level simulation. The following
sections show how to perform simulation at various levels through the
ModelSim-Altera command line.

RTL functional simulation in ModelSim-Altera for VHDL designs.


The following commands show how to compile your testbench and design files into
the work library in the ModelSim-Altera command prompt.
To change to the design library, type the following command:
cd <your_design_directory> r
(for example, cd:/designs)
To create the work library, type the following commands:
vlib work r
vmap work work r
To compile the testbench and design files into the work library, type the following
command:
vcom -work work <my_testbench.vhd> <my_design_files.vhd> r
Loading the Design

To load a design, type the following command:
vsim -t ps -L <pre-compiled-library1> -L <pre-compiled-library2> work.<my_testbench> r
The <pre-compiled-library1> and <pre-compiled-library2> variables are the libraries

required to compile your testbench. If you have multiple libraries, use the -L option
for each library in the vsim command.
Examples of <pre-compiled library> are altera_mf and lpm. The functional RTL
simulation libraries are usually required for performing RTL functional simulation.
For the complete set of libraries, refer to “Pre-Compiled Simulation Libraries in the
You can choose not to invoke -L in the vsim command for VHDL designs if you have
already included the libraries’ mapped name in your design files or sub-files.

To run a simulation, type the following commands:
add wave <signal name> r
run <time period> r
1 To add all signals in your testbench hierarchy, type the following command:
add wave * r
To run the simulation for 100 ps, type the following command:
run 100 ps r

software and use the netlist to perform post-synthesis simulation with the

page 2–13.
The following instructions show how to compile your testbench and *.vho file into the
work library using the ModelSim-Altera GUI.
To change to the simulation output directory, type the following command:
cd <simulation_output_directory> r
(for example, cd:/designs/modelsim/simulation)
1 This directory contains the *.vho file, which is generated by the netlist writer.

vlib work r
vmap work work r
To compile the testbench and *.vho files into the work library, type the following
command:
vcom -work work <my_testbench.vhd> <my_design_netlists.vho> r
Loading the Design

vsim -t ps -L <pre-compiled-library1> -L <pre-compiled-library2> work.<my_testbench> r
Examples of <pre-compiled library> are stratixiii and cycloneiii. The gate-level
simulation libraries are usually required for performing post-synthesis simulation.
For the complete set of libraries, refer to “Pre-Compiled Simulation Libraries in the

run <time period> r
add wave * r
run 100 ps r

the ModelSim-Altera software.

The following instructions show how to compile your testbench and *.vho file into the
work library using the ModelSim-Altera GUI.

vlib work r
vmap work work r
To compile the testbench and *.vho files into the work library, type the following
command:
vcom -work work <my_testbench.vhd> <my_design_netlists.vho> r
Loading the Design

vsim -t ps -sdftyp <design instance> = <path to *.sdo file> -L \
<pre-compiled-library1> -L <pre-compiled-library2> work.<my_testbench> r
Examples of <pre-compiled library> are stratixiii and cycloneiii. The gate-level
simulation libraries are usually required for performing gate-level simulation. For the
complete set of libraries, refer to “Pre-Compiled Simulation Libraries in the
1 You do not have to set the value (minimum, average, maximum) for the *.sdo file
because the Quartus II EDA Netlist Writer generates the *.sdo file using the same
value for the triplet (minimum, average, and maximum timing values).
1 If your design under test is instantiated in the testbench file under the i1 label, the
<design instance> should be “i1” (for example, /i1=<my design>.sdo).

run <time period> r
add wave * r
run 100 ps r
Simulating the Verilog HDL Designs at the Command Line

Simulating Verilog HDL design using the ModelSim-Altera command line gives you
more flexibility and control to compile the libraries, and load and simulate the Verilog
HDL design files. All simulation commands are Tcl commands which can be put into
the ModelSim Macros file (*.do). Using the *.do file allows you to run simulation in
batch mode. You only have to execute the *.do file and the ModelSim-Altera tool
automatically executes all the commands in the *.do script macro file.
You can use the ModelSim-Altera command line to perform the RTL functional
simulation, post-synthesis simulation, and gate-level simulation. The following
sections show how to perform simulation at various levels on the ModelSim-Altera
command line.

RTL functional simulation in ModelSim-Altera for Verilog HDL designs.


The following commands compile your testbench and design files into the work
library at the ModelSim-Altera command prompt.
vlib work r
vmap work work r
command:
vlog -work work <my_testbench.v> <my_design_files.v> r
Loading the Design

vsim –t ps –L <library1> –L <library2> work.<my_testbench> r
1 The <library1> and <library2> variables are the required libraries to compile your
testbench. If you have multiple libraries, use the –L option multiple times in the vsim
command.
1 Examples of <pre-compiled library> are altera_mf_ver and lpm_ver. The functional

RTL simulation libraries are usually required for performing RTL functional
simulation. For the complete set of libraries, refer to “Pre-Compiled Simulation
Libraries in the ModelSim-Altera Software” on page 2–5.

run <time period> r
add wave * r
run 100 ps r

Post-synthesis simulation can be done to verify that functionality of the design is not
lost after synthesis. You can create the post-synthesis netlist in the Quartus II software
and use the netlist to perform post-synthesis simulation with the ModelSim-Altera
software.
HDL design in the ModelSim-Altera software.

Compile Testbench and Verilog Output File into the Work Library
page 2–13.
The following instructions show how to compile your testbench and *.vo file into the
work library using the ModelSim-Altera software.
1 This directory contains the *.vo file, which is generated by the netlist writer.

vlib work r
vmap work work r
To compile the testbench and *.v files into the work library, type the following
command:
vlog -work work <my_testbench.v> <my_design_netlists.vo> r
Loading the Design

testbench. Examples of <pre-compiled library> are stratixiii_ver, stratixii_ver, and
stratixiigx_ver. Gate-level libraries are usually required for performing post-synthesis
simulation. If you have multiple libraries, use the -L option multiple times in the
vsim command. For the complete set of libraries, refer to “Pre-Compiled Simulation
Libraries in the ModelSim-Altera Software” on page 2–5.

run <time period> r
add wave * r
run 100 ps r


The following instructions show how to compile your testbench and *.vo file into the
work library using the ModelSim-Altera software.


vlib work r
vmap work work r
To compile the testbench and VHDL output (*.vho) files into the work library, type the
following command:
Loading the Design

testbench. Examples of pre-compiled libraries are stratixiii_ver, stratixii_ver, and
stratixiigx_ver. Gate-level libraries are usually required for performing gate-level
timing simulation. If you have multiple libraries, use the -L option multiple times in
the vsim command. For the complete set of libraries, refer to “Pre-Compiled
Simulation Libraries in the ModelSim-Altera Software” on page 2–5.

run <time period> r
add wave * r
run 100 ps r
Perform Simulation Using the ModelSim Software

Simulation of Verilog HDL or VHDL designs with ModelSim software can be done at
various levels to verify designs from different aspects. Simulation is divided into three
categories: RTL functional simulation, post-synthesis simulation, and gate-level
simulation. Simulation helps you verify your designs and debug them against any
possible errors in the designs.
You can perform the simulation through the GUI or command line. The following
sections provide step-by-step instructions to perform the simulation through the GUI
and the command line. You can proceed to the specific section that meets your needs.
fail.
Simulating the VHDL Designs Using the GUI

Simulating VHDL design using the ModelSim GUI is user-friendly. You do not have
to remember the commands to compile the libraries or load and simulate the VHDL
design files. You can use the ModelSim GUI to perform RTL functional simulation,
post-synthesis simulation, and gate-level timing simulation. The following sections
show how to perform simulation at various levels through the ModelSim GUI.

RTL functional simulation in ModelSim for VHDL designs.
Use the following instructions to perform an RTL functional simulation for VHDL
designs in the ModelSim software.
Create Simulation Libraries

Simulation libraries are required to simulate a design that contains an Altera
primitive, LPM function, or Altera megafunction. Depending on your design, you
must create the required simulation libraries and link them to your design correctly.
1. In the ModelSim software, on the File menu, click Change Directory. The Choose
Folder dialog box appears.
3. Click OK.
If you are not using the EDA Simulation Library Compiler, perform the following
steps to create the simulation library. (If you are using this utility, you can skip these
steps.)
1. In the ModelSim software, on the File menu, point to New and click Library. The
Create a New Library dialog box appears.
3. In the Library Name box, type the library name of the newly created library.
1 For example, the library name for Altera megafunctions is altera_mf, and the library
name for LPM is lpm. To see all the functional simulation library files, refer to “RTL
Functional Simulation Libraries” on page 2–6.
4. Click OK.
Compile Simulation Models into Simulation Libraries

If you are not using the Altera Simulation Library Compiler, perform the following
steps to compile simulation models into simulation libraries. (If you are using this
utility, you can skip these steps.)
appears.
2. Select the library that you created (for example, altera_mf, lpm).
3. Browse to the <Quartus II installation directory>/eda/sim_lib and add the necessary
simulation model files to your project. Select the simulation model files and click
Compile.
1 The altera_mf_components.vhd and altera_mf.vhd model files should be compiled

into the altera_mf library. The 220pack.vhd and 220model.vhd model files should be
compiled into the lpm library.
4. Repeat step 2 and step 3 to compile other simulation models.

5. Click Done.

into the work library using the ModelSim GUI.
4. Click OK.
steps:
appears.
the Work library.
3. Select the design files and the testbench file and click Compile.
4. Click Done.
Loading the Design

appears.
select ps.
b. In the Search Libraries (-L) text box, click the Add button.
c. Browse to the required simulation library that you previously compiled (for
example, altera_mf, lpm, or altera).
d. Click OK to add the libraries to the Search Libraries (-L) text box.
7. Click OK.

window.
for 100 ps.

software and use the netlist to perform post-synthesis simulation with the ModelSim
software.
page 2–13.
design in the ModelSim software.

Simulation libraries are required to simulate a design that is mapped to post-synthesis
primitives. Depending on the device family you are using, you must create the
required simulation libraries and link them to your design correctly.
3. Click OK.
steps to create the simulation library. (If you are using this utility, you can skip these
steps.)
1 For example, the library name for Stratix III family is stratixiii. To see all the gate-level
timing simulation library files, refer to “Gate-Level Simulation Library Files” on
page 2–10.
4. Click OK.

appears.
2. Select the library that you created (for example, stratixiii).
Compile.
1 The stratixiii_components.vhd and stratixiii.vhd model files are compiled into the
stratixiii library.

5. Click Done.
The following instructions show you how to compile your testbench and *.vho file

4. Click OK.
To compile the testbench file and *.vho file into the work library, perform the
following steps:
appears.
2. Select the library Work. The testbench and *.vho file should be compiled into the
Work library.
3. Select the testbench and *.vho file design files and click Compile.
4. Click Done.
Loading the Design

appears.
select ps.
example, stratixii, stratixiii, or cycloneiii).
7. Click OK.

window.
for 100 ps.

software and use the netlist to perform gate-level simulation with the ModelSim
software.
the ModelSim software.

the *.vho file is located in <project directory>/simulation/modelsim>.
3. Click OK.
1 For example, the library name for Stratix III family is stratixiii. To see all gate-level
timing simulation library files, refer to “Gate-Level Simulation Libraries” on page 2–6.
4. Click OK.

appears.
2. Select the library that you created (for example, stratixiii).

Compile.
1 The stratixiii_components.vhd and stratixiii.vhd model files should be compiled into

the stratixiii library.

5. Click Done.

The following instructions show you how to compile your testbench and *.vho file
4. Click OK.
To compile the testbench file and *.vho file into the work library, perform the
following steps:
appears.
2. Select the library Work. The testbench and *.vho file should be compiled into the
Work library.
3. Select the testbench and *.vho design files and click Compile.
4. Click Done.
Loading the Design

appears.
2. Click the SDF tab and click Add.
3. In the Add SDF Entry dialog box, click Browse and select the *.sdo file. By default,
the *.sdo file is located in <project directory>/simulation/modelsim.
4. In the Apply to Region dialog box, type in the instance path to which the *.sdo file
is to be applied. For example, if you are using a testbench exported into the
Quartus II software from a Vector Waveform File, the instance path is set to /i1.
1 You do not have to choose from the Delay list because the Quartus II EDA
Netlist Writer generates the *.sdo file using the same value for the triplet
(minimum, typical, and maximum timing values).
5. Click OK.
6. Click the Design tab. In the Resolution list, select ps.

7. In the Library list, select the Work library.
8. In the Start Simulation dialog box, expand the Work library.
example, stratixii, stratixiii, or cycloneiii).
12. Click OK.

window.
for 100 ps.
Simulating the Verilog HDL Designs Using the GUI

Simulating Verilog HDL design using the ModelSim GUI is user-friendly. You do not
have to remember the commands to compile the libraries or load and simulate the
Verilog HDL design files. You can use the ModelSim GUI to perform RTL functional
simulation, post-synthesis simulation, and gate-level timing simulation. The
following sections show how to perform simulation at various levels through the
ModelSim GUI.

RTL functional simulation in ModelSim for Verilog HDL designs.
Use the following instructions to perform an RTL functional simulation for
Verilog HDL designs in the ModelSim software.

3. Click OK.
To create the simulation library, perform the following steps:
1 For example, the library name for Altera megafunctions is altera_mf_ver, and the
library name for LPM is lpm_ver. To see all the functional simulation library files,
refer to “RTL Functional Simulation Libraries” on page 2–6.
4. Click OK.

appears.
2. Select the library that you created (for example, altera_mf_ver or lpm_ver).
Compile.
1 The altera_mf.v model files should be compiled into the altera_mf_ver library. The
220model.v model files should be compiled into the lpm_ver library.

5. Click Done.


3. Click OK.
steps:
appears.
the Work library.
3. Select the design files and the testbench file and click Compile.
4. Click Done.
Loading the Design

appears.
7. In the Search Libraries (-L) text box, click the Add button to browse to the
required simulation library that you previously compiled (for example,
altera_mf_ver, lpm_ver, or altera_ver) and click OK to add them into the Search
Libraries (-L) text box.
8. Click OK.

window.
for 100 ps.

software.
page 2–13.
HDL design in the ModelSim software.

3. Click OK.
To create the simulation library, perform the following steps:
page 2–10.
4. Click OK.

appears.
2. Select the library that you created (for example, stratixiii_ver).
Compile.
1 The stratixiii_atoms.v model files should be compiled into the stratixiii_ver library.
4. Repeat step 2 and step 3 to compile other simulation models, if needed.

5. Click Done.
The following instructions show you how to compile your testbench and *.vo into the
work library using the ModelSim GUI.
4. Click OK.
To compile the testbench file and *.vo file into the work library, perform the following
steps:
appears.
2. Select the library Work. The testbench and *.vo file should be compiled into the
Work library.
4. Click Done.
Loading the Design

appears.
3. In the Library list, select the Work library.
4. In the Start Simulation dialog box, expand the Work library.
stratixiii_ver or stratixiiigx_ver) and click OK to add them into the Search
9. Click OK.

window.
for 100 ps.

software.

3. Click OK.
3. Click OK.
steps to create the simulation library. (If you are using the utility, you can skip these
steps.)
page 2–10.
4. Click OK.

appears.
2. Select the library that you created (for example, stratixiii_ver).
Compile.
1 The stratixiii_atoms.v model files should be compiled into the stratixiii_ver library.
4. Repeat step 2 and step 3 to compile other simulation models, if needed.

5. Click Done.
The following instructions show you how to compile your testbench and *.vo file into
the work library using the ModelSim GUI.
4. Click OK.
To compile the testbench file and Verilog HDL output file (*.vo) into the work library,
appears.
2. Select the library Work. The testbench and *.vo file should be compiled into the
Work library.
3. Select the testbench and *.vo design files and click Compile.
4. Click Done.
Loading the Design

appears.
stratixiii_ver or stratixiiigx_ver) and click OK to add them into the Search
8. Click OK.

window.
for 100 ps.
Simulating the VHDL Designs at the Command Line

Simulating VHDL design using the ModelSim command line gives you more
flexibility and control to compile the libraries and load and simulate the VHDL design
files. All simulation commands are Tcl commands which can be put into the
ModelSim Macros file (*.do). Using the *.do file allows you to run simulation in batch
mode. You only have to execute the *.do file and the ModelSim tool automatically
executes all the commands in the *.do script macro file.
You can use the ModelSim command line to perform RTL functional simulation,
post-synthesis simulation, and gate-level simulation. The following sections show
how to perform simulation at various levels through the ModelSim command line.

RTL functional simulation in ModelSim for VHDL designs.

To create the simulation libraries, type the following commands:
vlib <library_name> r
vmap <logical_library_name> <library_name> r
1 For example, the library name for Altera megafunction is altera_mf, and the library
name for LPM is lpm. To see all the functional simulation library files, refer to “RTL
Functional Simulation Library Files” on page 2–9.
To create simulation libraries for altera_mf, lpm, and altera, type the following
commands:
vlib altera_mf r
vmap altera_mf altera_mf r
vlib lpm r
vmap lpm lpm r
vlib altera r
vmap altera altera r

To compile simulation models into simulation libraries, type the following command:
vcom –work <simulation_library> <Quartus II installation directory> \
/eda/sim_lib/<simulation_library_files> r
For example, the altera_mf_components.vhd and altera_mf.vhd model files should
be compiled into the altera_mf library. The 220pack.vhd and 220model.vhd model
files should be compiled into the lpm library.
Use Example 2–1 to compile the simulation model files to the simulation libraries for
altera_mf, lpm, and altera.
Example 2–1.
vcom -work altera_mf <Quartus II installation directory> \
/eda/sim_lib/altera_mf_components.v <Quartus II installation directory> \
/eda/sim_lib/altera_mf.vhd r
vcom -work lpm <Quartus II installation directory>/eda/sim_lib/220model.vhd \

<Quartus II installation dir>/eda/sim_lib/220model.vhd r
vcom -work altera <Quartus II installation directory> \

/eda/sim_lib/altera_primitives_components.vhd \
<Quartus II installation directory>/eda/sim_lib/altera_primitives.vhd r
If you are using the EDA Simulation Library Compiler, skip the steps for creating and
compiling the simulation libraries.

the work library using the ModelSim software.
vlib work r
vmap work work r
command:
vcom -work work <my_testbench.vhd> <my_design_files.vhd> r
Loading the Design

vsim -t ps -L <compiled-library1> -L <compiled-library2> work.<my_testbench> r
The <compiled-library1> and <compiled-library2> variables are the libraries you
compiled previously (for example, altera_mf or lpm) that are required to compile
your testbench. RTL libraries are usually required for performing RTL simulation. If
you have multiple libraries, use the -L option for each library in the vsim command.

run <time period> r
add wave * r
run 100 ps r

software.
page 2–13.

1 For example, the library name for the Stratix III family is stratixiii. To see all the
gate-level timing simulation library files, refer to “Gate-Level Simulation Libraries”
on page 2–6.
To create simulation libraries for stratixiii, type the following commands:

vlib stratixiii r
vmap stratixiii stratixiii r

vcom -work <simulation_library> <Quartus II installation directory> \
For example, the stratixiii_atoms_components.vhd and stratixiii_atoms.vhd model
files should be compiled into the stratixiii library.
stratixiii:
Example 2–2.
vcom -work stratixiii <Quartus II installation directory> \
/eda/sim_lib/stratixiii_atoms_components.vhd <Quartus II installation directory> \
/eda/sim_lib/stratixiii_atoms.vhd r
Compile Testbench and VHDL Output Files into the Work Library
The following commands show how to compile your testbench and *.vho file into the
work library using the ModelSim software.
vlib work r
vmap work work r
To compile the testbench and *.vho file into the work library, type the following
command:
vcom -work work <my_testbench.vhd> <my_design_files.vho> r
Loading the Design

vsim -t ps -L <compiled-library1> -L <compiled-library2> work.<my_testbench> r
compiled previously (for example, stratixiii or cycloneiii) that are required to compile
your testbench. Gate-level libraries are usually required for performing post-synthesis
simulation. If you have multiple libraries, use the -L option for each library in the
vsim command.

run <time period> r
add wave * r
run 100 ps r

software.
the ModelSim software.

primitives. Depending on the device family that you are using, you must create the
1 For example, the library name for the Stratix III family is stratixiii. To see all the
on page 2–6.
To create simulation libraries for stratixiii, type the following commands:

vlib stratixiii r
vmap stratixiii stratixiii r

vcom –work <simulation_library> <Quartus II installation directory> \
For example, the stratixiii_atoms_components.vhd and stratixiii_atoms.vhd model
files should be compiled into the stratixiii library.
stratixiii.
Example 2–3.
vcom -work stratixiii <Quartus II installation directory> \
/eda/sim_lib/stratixiii_atoms_components.vhd <Quartus II installation directory> \
/eda/sim_lib/stratixiii_atoms.vhd r
Be sure that the user-compiled libraries are stored using the same path as the design
and testbench files you want to compile.
Compile Testbench and VHDL Output Files into the Work Library
The following commands show how to compile your testbench and *.vho file into the
work library using the ModelSim GUI.
vlib work r
vmap work work r
To compile the testbench and *.vho file into the work library, type the following
command:
vcom -work work <my_testbench.vht> <my_design_files.vho> r
Loading the Design

vsim -t ps -sdftyp <design instance> = <path to *.sdo file> -L <compiled-library1> \
-L <compiled-library2> work.<my_testbench> r
compiled previously (for example, stratixiii or cycloneiii) that are required to compile
your testbench. Gate-level libraries are usually required for performing gate-level
simulation. If you have multiple libraries, use the -L option for each library in the
vsim command.
1 You do not have to set the value (minimum, average, maximum) for the *.sdo file
because the Quartus II EDA Netlist Writer generates the *.sdo file using the same
value for the triplet (minimum, average, and maximum timing values).
1 If your design under test is instantiated in the testbench file under the i1 label, the
<design instance> should be “i1” (for example, /i1=<my design>.sdo).

run <time period> r
add wave * r
run 100 ps r
Simulating the Verilog HDL Designs at the Command Line

Simulating Verilog HDL design using the ModelSim command line gives you more
flexibility and control to compile the libraries, and load and simulate the Verilog HDL
design files. All simulation commands are Tcl commands which can be put into the
*.do file. Using the *.do file allows you to run simulation in batch mode. You only
have to execute the *.do file and the ModelSim tool automatically executes all the
commands in the *.do script macro file.
You can use the ModelSim command line to perform RTL functional simulation,
post-synthesis simulation, and gate-level simulation. The following sections show
how to perform simulation at various levels through the ModelSim command line.

RTL functional simulation in ModelSim for Verilog HDL designs.

1 For example, the library name for Altera megafunction is altera_mf_ver, and the
library name for LPM is lpm_ver. To see all the functional simulation library files,
refer to “RTL Functional Simulation Library Files” on page 2–9.
To create simulation libraries for altera_mf, lpm_ver, and altera_ver, type the
following commands:
vlib altera_mf_ver r
vmap altera_mf altera_mf_ver r
vlib lpm_ver r
vmap lpm lpm_ver r
vlib altera_ver r
vmap altera altera_ver r

vlog –work <simulation_library> <Quartus II installation directory>\
For example, the altera_mf.v model files should be compiled into the altera_mf_ver
library. The 220model.v model files should be compiled into the lpm_ver library.
To compile the simulation model files to the simulation libraries for altera_mf_ver,
lpm_ver, and altera_ver, type the following commands:
vlog -work altera_mf_ver \
<Quartus II installation directory>/eda/sim_lib/altera_mf.v r
vlog -work lpm_ver \

<Quartus II installation directory>/eda/sim_lib/220model.v r
vlog -work altera_ver \

<Quartus II installation directory>/eda/sim_lib/altera_primitives.v r

the work library in the ModelSim command prompt.

vlib work r
vmap work work r
command:
vlog -work work <my_testbench.v> <my_design_files.v> r
Loading the Design

vsim -t ps -L <library1> -L <library2> work.<my_testbench> r
testbench. If you have multiple libraries, use the -L option multiple times in the vsim
command.

run <time period> r
add wave * r
To run the simulation for 100 ps, type the following the command:
run 100 ps r

Post-synthesis simulation can be done to verify that functionality of the design is not
lost after synthesis. You can create the post-synthesis netlist in the Quartus II software
and use the netlist to perform post-synthesis simulation with the ModelSim software.
page 2–13.
HDL design in the ModelSim software.


1 For example, the library name for the Stratix III family is stratixiii_ver. To see all the
on page 2–6.
To create simulation libraries for stratixiii_ver, type the following commands:

vlib stratixiii_ver r
vmap stratixiii_ver stratixiii_ver r

vlog –work <simulation_library> <Quartus II installation dir> \
For example, the stratixiii_atoms.v model files should be compiled into the
stratixiii_ver library.
To compile the simulation model files to the simulation libraries for stratixiii_ver,
type the following command:
vlog -work stratixiii_ver <Quartus II installation directory> \
/eda/sim_lib/stratixiii_atoms.v r
If you are using the Altera Simulation Library Compiler, skip the steps for creating
and compiling the simulation libraries.
Compile Testbench and Verilog Output Files into the Work Library
The following commands show how to compile your testbench and *.vo file into the
work library using the ModelSim software.
vlib work r
vmap work work r
To compile the testbench and *.vo file into the work library, type the following
command:
vlog -work work <my_testbench.vt> <my_design_netlists.vo> r
Loading the Design

1 The <library1> and <library2> variables are the libraries you compiled previously (for
example, stratixiii or stratixiigx) that are required to compile your testbench.
Gate-level libraries are usually required for performing post-synthesis simulation. If
you have multiple libraries, use the -L option multiple times in the vsim command.

run <time period> r
add wave * r
run 100 ps r

software.

primitives. Depending on the device family that you are using, you must create the
1 This directory contains the *.vo file, which is generated by the netlist writer.

1 For example, the library name for the Stratix III family is stratixiii_ver. To see all the
on page 2–6.
To create simulation libraries for stratixiii_ver, type the following commands:

vlib stratixiii_ver r
vmap stratixiii_ver stratixiii_ver r

vlog -work <simulation_library> <Quartus II installation directory> \
For example, the stratixiii_atoms.v model files should be compiled into the
stratixiii_ver library.
Use the following example to compile the simulation model files to the simulation
libraries for stratixiii_ver:
vlog -work stratixiii <Quartus II installation directory> \
/eda/sim_lib/stratixiii_atoms.v r
Compile Testbench and Verilog Output Files into the Work Library
The following commands show how to compile your testbench and *.vo file into the
work library using the ModelSim command line.
vlib work r
vmap work work r
To compile the testbench and *.vo files into the work library, type the following
command:
Loading the Design

1 The <library1> and <library2> variables are the libraries you compiled previously (for
example, stratixiii_ver or stratixiigx_ver) that are required to compile your testbench.
Gate-level libraries are usually required for performing gate-level timing
simulation. If you have multiple libraries, use the -L option multiple times in the
vsim command.

Perform the following commands to run a simulation:
run <time period> r
Simulating Designs that Include Transceivers
add wave * r
run 100 ps r

If your design includes a Stratix GX, Stratix II GX, Stratix IV, Arria II GX, or Arria GX
transceiver, you must compile additional library files to perform RTL functional or
gate-level timing simulations. The following example shows how to perform
simulation on designs that include transceivers in Stratix GX and Stratix II GX
devices.
Performing simulation with transceivers in Arria GX and Stratix II GX are very
similar. You only have to replace stratixiigx_atoms and stratixiigx_hssi_atoms model
files with arriagx_atoms and arriagx_hssi_atoms model files.
fail.
Stratix GX RTL Functional Simulation

To perform an RTL functional simulation of your design that instantiates the ALTGXB
megafunction, which enables the gigabit transceiver block on Stratix GX devices,
compile the stratixgx_mf model file into the altgxb library.
1 The stratixiigx_mf model file references the lpm and sgate libraries. If you are using
ModelSim PE/SE, you must create these libraries to perform a simulation.
Perform RTL Functional Simulation for Stratix GX in VHDL

If you are using the ModelSim-Altera software, compiling the libraries is not
necessary. You can simulate the design directly by typing the commands in
Example 2–4.
Example 2–4.
vcom -work <my design>.vhd <my testbench>.vhd r
vsim -L lpm -L altera_mf -L sgate -L altgxb work.<my testbench> r
If you are using ModelSim SE/PE, you must compile the necessary libraries before
you can simulate the designs. To compile and simulate the design, type the
commands in Example 2–5 at the ModelSim command prompt.
Example 2–5.
vcom -work altera_mf altera_mf_components.vhd altera_mf.vhd r
vcom -work lpm 220pack.vhd 220model.vhd r
vcom -work sgate sgate_pack.vhd sgate.vhd r
vcom -work altgxb stratixgx_mf.vhd stratixgx_mf_components.vhd r
vsim -L lpm -L altera_mf -L sgate -L altgxb work.<my testbench> r
Perform RTL Functional Simulation for Stratix GX in Verilog HDL

Example 2–6.
Example 2–6.
vlog -work <my design>.v <my testbench>.v r
vsim -L lpm_ver -L altera_mf_ver -L sgate_ver -L altgxb work.<my testbench> r
Example 2–7.
vlib work_ver r
vlib lpm_ver r
vlib altera_mf_ver r
vlib sgate_ver r
vlib altgxb_ver r
vlog -work lpm_ver 220model.v r
vlog -work altera_mf_ver altera_mf.v r
vlog -work sgate_ver sgate.v r
vlog -work altgxb_ver stratixgx_mf.v r
vsim -L lpm_ver -L sgate_ver-L altgxb_ver work.<my testbench> r
Stratix GX Gate-Level Timing Simulation

Perform a gate-level timing simulation of your design that includes a Stratix GX
transceiver by compiling the stratixgx_atoms and stratixgx_hssi_atoms model files
into the stratixgx and stratixgx_gxb libraries, respectively.
1 The stratixgx_hssi_atoms model file references the lpm and sgate libraries. If you are
using ModelSim PE/SE, you must create these libraries to perform a simulation.
Perform Gate-Level Timing Simulation for Stratix GX in VHDL

Example 2–8.
Example 2–8.
vcom -work <my design>.vho <my testbench>.vhd r
vsim -L lpm -L altera_mf -L sgate -L stratixgx -L stratixgx_gxb \
-sdftyp <design instance>=<path to .sdo file>.sdo work.<my testbench> \
-t ps - +transport_int_delays+transport_path_delays r
Example 2–9.
vcom -work stratixgx stratixgx_atoms.vhd stratixgx_components.vhd r
vcom -work stratixgx_gxb stratixgx_hssi_atoms.vhd \
stratixgx_hssi_components.vhd r
vsim -L lpm -L altera_mf -L sgate -L stratixgx -L stratixgx_gxb \
-t ps +transport_int_delays +transport_path_delays r
Perform Gate-Level Timing Simulation for Stratix GX in Verilog HDL

necessary. You can simulate the design directly by typing the command in
Example 2–10.
Example 2–10.
vlog -work <my design>.vo <my testbench>.v r
vsim -L lpm_ver -L altera_mf_ver -L sgate_ver -L stratixgx_ver -L \
stratixgx_gxb_ver work.<my testbench> -t ps +transport_int_delays \
+transport_path_delays r
Example 2–11.
vlog -work stratixgx_ver stratixgx_atoms.v r
vlog -work stratixgx_gxb_ver stratixgx_hssi_atoms.v r
vsim -L lpm_ver -L altera_mf_ver -L sgate_ver -L stratixgx_ver \
-L stratixgx_gxb_ver work.<my testbench> -t ps +transport_int_delays \
+transport_path_delays r
Stratix II GX RTL Functional Simulation

Stratix II GX function simulation is similar to Arria GX functional simulation. The
following example shows only the functional simulation for designs that include
transceivers in Stratix II GX devices. To simulate transceivers in Arria GX devices, you
only have to replace the stratixiigx_hssi model file with the arriagx_hssi model file.
To perform a functional simulation of your design that instantiates the ALT2GXB
megafunction, which enables the gigabit transceiver block on Stratix II GX devices,
compile the stratixiigx_hssi model file into the stratixiigx_hssi library.
1 The stratixiigx_hssi_atoms model file references the lpm and sgate libraries. If you
are using ModelSim PE/SE, you must create these libraries to perform a simulation.
Generate a functional simulation netlist by turning on Generate Simulation Model in

the Simulation Library tab of the ALT2GXB MegaWizard Plug-In Manager
(Figure 2–2). The <alt2gxb entity name>.vho or <alt2gxb module name>.vo is generated
in the current project directory.
1 The Quartus II-generated ALT2GXB functional simulation library file references

stratixiigx_hssi wysiwyg atoms.
Figure 2–2. ALT2GXB MegaWizard Plug-In Manager, Generate Simulation Model
Perform RTL Functional Simulation for Stratix II GX in VHDL

Example 2–12.
Example 2–12.
vcom -work work <alt2gxb entity name>.vho r
vsim -L lpm -L altera_mf -L sgate -L stratixgx_hssi work.<my design> r
Example 2–13.
vcom -work stratixiigx_hssi stratixiigx_hssi_components.vhd \
stratixiigx_hssi_atoms.vhd r
vcom -work work <alt2gxb entity name>.vho r
vsim -L lpm -L altera_mf -L sgate -L stratixgx_hssi work.<my testbench> r
Perform RTL Functional Simulation for Stratix II GX in Verilog HDL

Example 2–14.
Example 2–14.
vlog -work work <alt2gxb module name>.vo r
vsim -L lpm_ver -L altera_mf_ver -L sgate_ver -L stratixgx_hssi_ver \
work.<my testbench> r
Example 2–15.
vlog -work stratixiigx_hssi_ver stratixiigx_hssi_atoms.v r
vlog -work work <alt2gxb module name>.vo r
vsim -L lpm_ver -L altera_mf_ver -L sgate_ver -L stratixgx_hssi_ver \
work.<my testbench> r
Stratix II GX Gate-Level Timing Simulation

Stratix II GX gate-level timing simulation is similar to Arria GX gate-level timing
simulation. The following example shows only the gate-level timing simulation for
designs that include transceivers in Stratix II GX devices. To simulate transceivers in
Arria GX devices, you only have to replace the stratixiigx_hssi model file with the
arriagx_hssi model file.
To perform a gate-level timing simulation of your design that includes a Stratix II GX
transceiver, compile stratixiigx_atoms and stratixiigx_hssi_atoms into the stratixiigx
and stratixiigx_hssi libraries, respectively.
1 The stratixiigx_hssi_atoms model file references the lpm and sgate libraries. If you
are using ModelSim PE/SE, you must create these libraries to perform a simulation.
Perform Gate-Level Timing Simulation for Stratix II GX in VHDL

Example 2–16.
Example 2–16.
vsim -L lpm -L altera_mf -L sgate -L stratixiigx -L stratixiigx_hssi \
Example 2–17.
vcom -work stratixiigx stratixiigx_atoms.vhd \
stratixiigx_components.vhd r
vcom -work stratixiigx_hssi stratixiigx_hssi_components.vhd \
stratixiigx_hssi_atoms.vhd r
vsim -L lpm -L altera_mf -L sgate -L stratixiigx -L stratixiigx_hssi \
Perform Gate-Level Timing Simulation for Stratix II GX in Verilog HDL

Example 2–18.
Example 2–18.
vsim -L lpm_ver -L altera_mf_ver -L sgate_ver -L stratixiigx_ver \
-L stratixiigx_hssi_ver work.<my testbench> -t ps \
+transport_int_delays +transport_path_delays r
Example 2–19.
vlog -work stratixiigx_ver stratixiigx_atoms.v r
vlog -work stratixiigx_hssi_ver stratixiigx_hssi_atoms.v r
vsim -L lpm_ver -L altera_mf_ver -L sgate_ver -L stratixiigx_ver \
-L stratixiigx_hssi_ver work.<my testbench> -t ps \
+transport_int_delays +transport_path_delays r
Using the NativeLink Feature with ModelSim-Altera or ModelSim Software
Transport Delays
By default, the ModelSim software filters out all pulses that are shorter than the
propagation delay between primitives. Turning on the transport delay options in the
ModelSim software prevents the simulation tool from filtering out these pulses. Use
the following options to ensure that all signal pulses are seen in the simulation results.
+transport_path_delays
Use this option when the pulses in your simulation are shorter than the delay within a
gate-level primitive.
+transport_int_delays
Use this option when the pulses in your simulation are shorter than the interconnect
delay between gate-level primitives.
The +transport_path_delays and +transport_int_delays options are also used by
default in the NativeLink feature for gate-level timing simulation.
f For more information about either of these options, refer to the ModelSim-Altera
Command Reference installed with the ModelSim software.
The following ModelSim software command shows the command line syntax to
perform a gate-level timing simulation with the device family library:
vsim -t 1ps -L stratixii -sdftyp /i1=filtref_vhd.sdo work.filtref_vhd_vec_tst \
+transport_int_delays +transport_path_delays
Using the NativeLink Feature with ModelSim-Altera or ModelSim

Software
The NativeLink feature in the Quartus II software facilitates the seamless transfer of
information between the Quartus II software and EDA tools and allows you to run
ModelSim within the Quartus II software.
Setting Up NativeLink
To run ModelSim automatically from the Quartus II software using the NativeLink
feature, you must specify the path to your simulation tool by performing the
following steps:
1. On the Tools menu, click Options. The Options dialog box appears.
2. In the Category list, select EDA Tool Options.
3. Double-click the entry under Location of executable beside the name of your EDA
Tool.
4. Type or browse to the directory containing the executables of your EDA tool.
1 For ModelSim-Altera software and ModelSim SE/PE, executable files are stored in the
win32aloem and win32 directories, respectively.
c:\<ModelSim-Altera installation path>\win32aloem

c:\<ModelSim installation path>\win32
5. Click OK.
You can also specify the path to the simulator’s executables by using the
set_user_option Tcl command:
set_user_option -name EDA_TOOL_PATH_MODELSIM <path to executables> r
set_user_option -name EDA_TOOL_PATH_MODELSIM_ALTERA <path to executables> r
Perform an RTL Simulation Using NativeLink

To run an RTL functional simulation with the ModelSim software in the Quartus II
software, perform the following steps:
appears.
2. In the Category list, select Simulation. The Simulation page appears (Figure 2–3).
Figure 2–3. Simulation Page in the Settings Dialog Box
3. In the Tool name list, select one of the following options:

■ ModelSim
■ ModelSim-Altera
4. If your design is written entirely in Verilog HDL or VHDL, the NativeLink feature
automatically chooses the correct language and Altera simulation libraries. If your
design is written with mixed languages, the NativeLink feature uses the default
language specified in the Format for output netlist list. To change the default
language when there is a mixed language design, under EDA Netlist Writer
options, in the Format for output netlist list, select VHDL or Verilog. Table 2–12
shows the design languages for output netlists and simulation models.
Table 2–12. NativeLink Design Languages

Design File Format for Output Netlist Simulation Models Used
Verilog HDL Any Verilog HDL
VHDL Any VHDL
Mixed Verilog HDL Verilog HDL
Mixed VHDL VHDL
1 For mixed language simulation, choose the same language that was used to
generate your megafunctions to ensure correct parameter passing between
the megafunctions and the Altera libraries. For example, if your
ALTSYNCRAM megafunction was generated in VHDL, choose VHDL as
the format for the output netlist.
When creating mixed language designs, it is important to be aware of the

following:
■ EDA simulation tools do not allow seamless passing of parameters when a
VHDL entity is instantiated in Verilog HDL designs.
■ The ModelSim and ModelSim-Altera software does not allow the use of
Verilog User Defined Primitives (UDPs) to be instantiated in VHDL designs.
5. If you have testbench files or macro scripts, enter the information under
NativeLink settings.
For more information about setting up a testbench file with NativeLink, refer to
“Setting Up a Testbench” on page 2–75.
6. If you have compiled libraries using the EDA Simulation Library Compiler,
a. On the Simulation page, click More EDA Netlist Writer Settings. The More
EDA Netlist Writer Settings dialog box appears.
b. Under Existing option settings, click Location of user compiled simulation
library.
c. In the Setting field, type the path that contains the user-compiled libraries that
are generated from the EDA Simulation Library Compiler; for example,
c:<design_path>/simulation/modelsim.
1 For more information about the EDA Simulation Library Compiler, refer to
“Compile Libraries Using the EDA Simulation Library Compiler” on
page 2–17.
7. Click OK.
8. On the Processing menu, point to Start and click Start Analysis & Elaboration to
perform an Analysis and Elaboration. This command collects all your file name
information and builds your design hierarchy in preparation for simulation.
9. On the Tools menu, point to Run EDA Simulation Tool and click EDA RTL
Simulation to automatically run ModelSim, compile all necessary design files, and
complete a simulation.
10. If you want to run ModelSim in command-line mode when running it
automatically after full compilation, perform the following steps:
a. On the Simulation page, click More NativeLink Settings. The More
NativeLink Settings dialog box appears.
b. Under Existing option settings, click Launch third-party EDA tool in
command-line mode.
c. In the Setting field, select On.
d. Click OK.
11. If you want to generate only the .do script without launching ModelSim during
the NativeLink process, you can perform the following steps:
b. Under Existing option settings, click Generate third-party EDA tool
command scripts without running the EDA tool.
If you turn this option on and run NativeLink, the .do file for ModelSim
simulation is generated without launching ModelSim. You can then run the
simulation by typing the following command:
do <your_design_name>_run_msim_rtl_level_<verilog/vhdl>.do
Perform a Gate-Level Simulation Using NativeLink

To run a gate-level timing simulation with the ModelSim software in the Quartus II
software, perform the following steps:
appears.
2. In the Category list, select Simulation. The Simulation page appears (Figure 2–3
on page 2–71).
3. In the Tool name list, select one of the following options:
■ ModelSim
■ ModelSim-Altera
4. Under EDA Netlist Writer options, in the Format for output netlist list, choose
VHDL or Verilog. You can also modify where you want the post-synthesis netlist
generated by editing or browsing to a directory in the Output directory box.
5. To run a gate-level simulation after each full compilation, turn on Run gate-level
simulation automatically after compilation.
6. If you have testbench files or macro scripts, enter the information under
NativeLink settings.
7. If you have compiled libraries using the EDA Simulation Library Compiler,
a. On the Simulation page, click More EDA Netlist Writer Settings. The More
EDA Netlist Writer Settings dialog box appears.
b. Under Existing option settings, click Location of user compiled simulation
library.
c. In the Setting field, type the path that contains the pre-compiled libraries that
are generated from the EDA Simulation Library Compilation tool; for example,
c:<design_path>/simulation/modelsim.
8. Click OK.
9. On the Processing menu, point to Start and click Start EDA Netlist Writer to
generate a simulation netlist of your design.
1 If you must run full compilation after you set the EDA Tool Settings, the
Start EDA Netlist Writer command is not required.
10. On the Tools menu, point to Run EDA Simulation Tool and click EDA Gate Level
Simulation to automatically run ModelSim, compile all necessary design files, and
complete a simulation.
1 If multi-corner Timing Analysis is performed, a dialog box appears, asking

you to select the timing corner to run simulation. Select the timing corner
and click Run.
1 A *.do file is generated in the <project_directory>\simulation\modelsim

directory while running NativeLink. You can perform a simulation with the
*.do file directly from ModelSim when you rerun a simulation without
using NativeLink. To perform the simulation directly without NativeLink,
type the following command in the ModelSim console:
do <generated_do_file>.do.
11. If you want to run ModelSim in command-line mode when running it

automatically after full compilation, you can perform the following steps:
b. Under Existing option settings, click Launch third-party EDA tool in
command-line mode.
d. Click OK.
12. If you want to generate only the .do script without launching ModelSim during
the NativeLink process, you can perform the following steps:
b. Under Existing option settings, click Generate third-party EDA tool
command scripts without running the EDA tool.
If you turn this option on and run the NativeLink, the .do file for the simulation
process is generated without showing the results in the GUI. You can then run the
simulation by typing the following command:
do <your_design_name>_run_msim_rtl_level_<verilog/vhdl>.do
Setting Up a Testbench
You can use NativeLink to compile your design files and testbench files, and run an
EDA simulation tool to automatically perform a simulation.
To set up NativeLink for simulation, perform the following steps:
1. On the Assignments menu, click Settings. The Settings dialog box appears.
2. In the Category list, click the “+” icon to expand EDA Tool Settings and select
Simulation. The Simulation page appears.
3. Under NativeLink settings, select None, Compile test bench, or Script to
compile test bench (Table 2–13).
Table 2–13. NativeLink Settings

Settings Description
None Compile simulation models and design files.
Compile test bench NativeLink compiles simulation models, design files, testbench files, and starts simulation.
Script to compile test NativeLink compiles the simulation models and design files. The script you provide is sourced after
bench design files compile. Use this option when you want to create your own script to compile your
testbench and perform simulation.
4. If you select Compile test bench, select your testbench setup from the Compile
test bench list. You can use different testbench setups to specify different test
scenarios. If there are no testbench setups entered, create a testbench setup by
performing the following steps:
a. Click Test Benches. The Test Benches dialog box appears.
b. Click New. The New Test Bench Settings dialog box appears.
c. In the Test Bench name box, type in the testbench setup name that identifies
the different testbench setups.
d. In the Test level module box, type in the top-level testbench entity name. For
example, for a Quartus II-generated VHDL testbench, type in <Vector Waveform
File name>_vhd_vec_tst.
e. In the Instance box, type in the full instance path to the top level of your FPGA
design. For example, for a Quartus II-generated VHDL testbench, type in i1.
f. Under Simulation period, select Run simulation until all vector stimuli are
used or specify the end time of the simulation.
g. Under Test bench files, browse and add all your testbench files in the File
name box. Use the Up and Down button to reorder your files. The script used
by NativeLink compiles the files in order from top to bottom.
1 You can also specify the library name and HDL version to compile the
testbench file. NativeLink compiles the testbench to a library name using
the specified HDL version.
h. Click OK.
i. In the Test Benches dialog box, click OK.
5. Under NativeLink settings, turn on Use script to set up simulation and browse to
your script. Your script is executed to set up and run simulation after loading the
design using the vsim command.
6. If you choose Script to compile test bench, browse to your script and click OK.
Creating a Testbench
In the Quartus II software, you can create a Verilog HDL or VHDL testbench from a
Vector Waveform File. The generated testbench includes the behavior of the input
stimulus and applies it to your instantiated top-level FPGA design.
1. On the File menu, click Open. The Open dialog box appears.
2. Click the Files of type arrow and select Waveform/Vector Files. Select your Vector
Waveform File.
3. Click Open.
4. On the File menu, click Export. The Export dialog box appears.
5. Click the Save as type arrow and select VHDL Test Bench File (*.vht) or Verilog
Test Bench File (*.vt).
6. Turn on Add self-checking code to file to check your simulation results against
your Vector Waveform File.
7. Click Export. Your VHDL or Verilog HDL testbench file is generated in your
project directory.
Generate Simulation Script from EDA Netlist Writer

In the Quartus II software version 9.0 and later, you can generate the simulation script
(including the .do file, Tcl script, and option file) when you run the EDA Netlist
Writer. You can use the simulation script to run your simulation in the preferred
simulator in stand-alone mode.
To generate a simulation script with the EDA Netlist Writer, perform the following
steps:
1. On the Simulation page, click More EDA Netlist Writer Settings. The More EDA
Netlist Writer Settings dialog box appears.
2. Under Existing option settings, click Generate third-party EDA tool command
script for RTL simulation (if you want to generate an RTL simulation script) or
click Generate third-party EDA tool command script for Gate-Level simulation
(if you want to generate a Gate-Level simulation script).
3. In the Setting field, select On.
4. Click OK.
5. Follow the steps in “Generate Gate-Level Timing Simulation Netlist Files” on
page 2–14.
In the command-line, to generate the simulation script with the EDA Netlist Writer,
type the following command:
quartus_eda --simulation --tools=<Your decided tool> --format=<vhdl or verilog>
--gen_script=<rtl or gate_level> <Project Name> -c <Revision name>
ModelSim Error Message Verification

ModelSim error and warning messages are tagged with a vsim or vcom code. To find
out the cause and resolution for a vsim or vcom error or warning, use the verror
command.
For example, ModelSim may display the following error message:
# ** Error:
C:/altera_trn/DUALPORT_TRY/simulation/modelsim/DUALPORT_TRY.vho(31):
(vcom-1136) Unknown identifier "stratixiii".
In this case, type the following command:
verror 1136 r
At that point, the error message appears as follows:
# vcom Message # 1136:
# The specified name was referenced but was not found. This indicates
# that either the name specified does not exist or is not visible at
# this point in the code.
Generating a Timing VCD File for PowerPlay
Generating a Timing VCD File for PowerPlay

To generate a timing Value Change Dump (*.vcd) file for PowerPlay, you must first
generate a *.vcd script file in the Quartus II software and run the *.vcd script file from
the ModelSim or ModelSim-Altera software to generate a timing *.vcd file. This
timing *.vcd file can then be used by PowerPlay for power estimation. The following
instructions show you step-by-step how to generate a timing *.vcd file.
To generate timing VCD Scripts in the Quartus II software, perform the following
steps:
1. In the Quartus II software, on the Assignments menu, click Settings. The Settings
dialog box appears.
2. In the Category list, under EDA Tool Settings, select Simulation. The Simulation
page appears.
3. Choose the appropriate third-party simulation tool (ModelSim or
ModelSim-Altera) in the Tool name list. Turn on the Generate Value Change
Dump (VCD) file script option.
4. To generate the *.vcd script file, perform a full compilation.
To generate a timing *.vcd file in the ModelSim-Altera or ModelSim software, perform
1. In the ModelSim or ModelSim-Altera software, before simulating your design,
source the <revision_name>_dump_all_vcd_nodes.tcl script. To source the Tcl
script, run the following command before running the vsim command. For
example:
source <revision_name>_dump_all_vcd_nodes.tcl r
2. Continue to run the simulation as usual until the end of the simulation. Exit the
ModelSim or ModelSim-Altera software. If you do not exit the software, the
ModelSim software may end the writing process of the timing *.vcd files
improperly, resulting in a corrupted timing *.vcd file.
f For more information about using the timing *.vcd file for power estimation, refer to
the PowerPlay Power Analysis chapter in volume 3 of the Quartus II Handbook.
Viewing a Waveform from a .wlf File

A .wlf file is automatically generated when your simulation is done. The .wlf file is
not readable. It is used for generating the waveform view through ModelSim.
To view a waveform from a .wlf file through ModelSim, perform the following steps:
1. Type vsim on a command line. The ModelSim dialog box appears.
2. On the View menu, click Datasets. The Datasets Browser dialog box appears.
3. Click Open and browse to the directory that contains your .wlf file.
4. If you have found your .wlf file, click Open, then click OK.
5. Click Done.
6. In the Object browser, select the signals that you want to observe.
Scripting Support
7. On the Add menu, click Wave and then click Selected Signals.
You cannot view a waveform from a .vcd file in ModelSim directly. The .vcd file must
first be converted to a .wlf file.
1. Use the vcd2wlf command to convert the file. For example, type the following on
a command-line:
vcd2wlf <example>.vcd <example>.wlf r
2. After you convert the .vcd file to a .wlf file, follow the procedures for viewing a
waveform from a .wlf file through ModelSim.
You can also convert your .wlf file to a .vcd file by using the wlf2vcd command.
Scripting Support
You can run procedures and create settings described in this chapter in a Tcl script.
You can also run some procedures at the command line prompt.
f For more information about Tcl scripting, refer to the Tcl Scripting chapter in volume 2
of the Quartus II Handbook.
f For more information about command line scripting, refer to the Command Line
Scripting chapter in volume 2 of the Quartus II Handbook.
For detailed information about scripting command options, refer to the Qhelp
command line and Tcl API help browser. To access this information, type the
following command to start the Qhelp browser:
quartus_sh --qhelp r
Generating a Post-Synthesis Simulation Netlist for ModelSim

You can use the Quartus II software to generate a post-synthesis simulation netlist
with Tcl commands or with a command at the command-line prompt. The following
example assumes that you are selecting ModelSim (Verilog HDL output from the
Quartus II software).
Tcl Commands
Use the following Tcl commands to set the output format to Verilog HDL, the
simulation tool to ModelSim for Verilog HDL, and to generate a functional netlist:
set_global_assignment-name EDA_SIMULATION_TOOL "ModelSim (Verilog)" r
set_global_assignment-name EDA_GENERATE_FUNCTIONAL_NETLIST ON r
Command Prompt
Use the following command to generate a simulation output file for the ModelSim
simulator. Specify VHDL or Verilog HDL for the format:
quartus_eda <project name> --simulation=on --format=<format> \
--tool=ModelSim --functional r
Software Licensing and Licensing Setup in ModelSim-Altera Subscription
Generating a Gate-Level Timing Simulation Netlist for ModelSim

Use the Quartus II software to generate a gate-level timing simulation netlist with Tcl
commands or with a command at the command prompt.
Tcl Commands
Use one of the following Tcl commands:
■ set_global_assignment -name EDA_SIMULATION_TOOL \
"ModelSim-Altera (Verilog)" r
"ModelSim-Altera (VHDL)" r
"ModelSim (Verilog)" r
"ModelSim (VHDL)" r
Command Line
Generate a simulation output file for the ModelSim simulator by specifying VHDL or
Verilog HDL for the format by typing the following command at the command
prompt:
quartus_eda <project name> --simulation=on --format=<format> \
--tool=ModelSim r
Software Licensing and Licensing Setup in ModelSim-Altera

Subscription Edition
License the ModelSim-Altera Subscription Edition software subscription with a
parallel port FIXEDPC license, or a network FLOATNET or FLOATPC license. Each
Altera software subscription includes a license for both VHDL and Verilog HDL. The
ModelSim-Altera Subscription Edition software supports both VHDL and Verilog
HDL, but the software does not support mixed language simulation.
1 The USB software guard is not supported by versions earlier than Mentor Graphics
ModelSim software 5.8d.
You can obtain a license for the ModelSim-Altera Subscription Edition software from
the Altera website at www.altera.com. Get licensing information for the
Mentor Graphics ModelSim software directly from Mentor Graphics. Refer to
Figure 2–4 for the set-up process.
1 For ModelSim-Altera software versions prior to 5.5b, use the PCLS utility included
with the software to set up the license.
For the Quartus II software version 8.1 and later, the no-cost entry level of the
ModelSim-Altera software does not require a license file. However, you must request
a license file to use the ModelSim-Altera Subscription Edition software.
Conclusion
Figure 2–4. ModelSim-Altera Subscription Edition Software Licensing Set Up Process
Start
Initial Installation
Using
the ModelSim-Altera yes
Starter Edition
software?
no
Is the ModelSim-Altera yes

software properly licensed?
no
Set the LM_LICENSE_FILE Variable
End
LM_LICENSE_FILE Variable
Altera recommends setting the LM_LICENSE_FILE environment variable to the
location of the license file. For example, the value for the LM_LICENSE_FILE
environment variable should point to <path to license file>\license.dat.
f For more information about setting up the license for ModelSim-Altera Subscription
Edition software, refer to AN 340: Altera Software Licensing.
Conclusion
Using the ModelSim and ModelSim-Altera simulation software within the Altera
FPGA design flow enables Altera software users to easily and accurately perform RTL
functional simulations, post-synthesis simulations, and gate-level simulations on their
designs. Proper verification of designs at the functional, post-synthesis, and post
place-and-route stages using the ModelSim and ModelSim-Altera software helps
ensure design functionality and success and, ultimately, a quick time-to-market.
Referenced Documents
This chapter references the following documents:
■ AN 340: Altera Software Licensing
■ Command Line Scripting chapter in volume 2 of the Quartus II Handbook
■ PowerPlay Power Analysis chapter in volume 3 of the Quartus II Handbook
Document Revision History
■ Quartus II Classic Timing Analyzer chapter in volume 3 of the Quartus II Handbook

■ Quartus II TimeQuest Timing Analyzer chapter in volume 3 of the Quartus II
Handbook
■ Tcl Scripting chapter in volume 2 of the Quartus II Handbook

Table 2–14 shows the revision history for this chapter.
Table 2–14. Document Revision History (Part 1 of 2)

Date and Document
Version Changes Made Summary of Changes
March 2009 Added the following sections: Updated for the Quartus II
v9.0.0 ■ “Compile Libraries Using the EDA Simulation Library Compiler” on software version 9.0
page 2–17 release.
■ “Generate Simulation Script from EDA Netlist Writer” on page 2–77

■ “Viewing a Waveform from a .wlf File” on page 2–78
Updated the following:
■ Table 2–1, Table 2–2, Table 2–5, Table 2–6, Table 2–7, Table 2–8,
Table 2–9, Table 2–10
■ Figure 2–4 on page 2–81
■ All sections titled “Loading the Design”
Table 2–14. Document Revision History (Part 2 of 2)

Date and Document
Version Changes Made Summary of Changes
November 2008 Updated the following: Updated for the Quartus II
v8.1.0 ■ Table 2–2, Table 2–3, Table 2–4, Table 2–5, Table 2–6 software version 8.1
release.
■ Removed --zero_ic_delays from quartus_sta option in
“Generate Post-Synthesis Simulation Netlist Files” on page 2–11
■ Removed steps to include the library when the simulation is run in
VHDL mode from all procedures; this is no longer necessary
■ Added information about the Altera Simulation Library Compiler
throughout the chapter
■ Added “Compile Libraries Using the Altera Simulation Library
Compiler” on page 2–15
■ Added “Disabling Simulation” on page 2–72
■ Minor editorial updates
■ Updated entire chapter using 8½” × 11” chapter template
May 2008 ■ Updated “Altera Design Flow with ModelSim-Altera or ModelSim Updated for the Quartus II
v8.0.0 Software” on page 2–3 software version 8.0.
■ Updated “Simulation Libraries” on page 2–4
■ Updated “Simulation Netlist Files” on page 2–11
■ Updated “Perform Simulation Using ModelSim-Altera Software” on
page 2–15
■ Updated “Perform Simulation Using ModelSim Software” on
page 2–33
■ Updated “Simulating Designs that Include Transceivers” on
page 2–57
■ Updated “Using the NativeLink Feature with ModelSim-Altera or
ModelSim Software” on page 2–63
■ Updated “Generating a Timing VCD File for PowerPlay” on page 2–68
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
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2.

Mentor Graphics ModelSim Support

Table 2–1. Comparison of ModelSim Software Versions

Table 2–2. Compatibility Between Software Versions

Altera Design Flow with ModelSim-Altera or ModelSim Software

Testbench .v/.vhd RTL Functional Simulation (1)

Post-Synthesis Simulation (2)

Verilog Output Standard Delay

Gate-Level Timing Simulation (3)

Notes to Figure 2–1:

Simulating the Transceiver Megafunction (for example, ALT2GXB) is also another

Pre-Compiled Simulation Libraries in the ModelSim-Altera Software

RTL Functional Simulation Libraries

Gate-Level Simulation Libraries

FLEX 6000 flex6000 <ModelSim-Altera installation directory>\altera\vhdl\flex6000\

Simulation Library Files in the Quartus II Software

RTL Functional Simulation Library Files

Gate-Level Simulation Library Files

Simulation Netlist Files

Generate Post-Synthesis Simulation Netlist Files

■ quartus_sta <project name> -c <revision name> --post_map r

Generate Gate-Level Timing Simulation Netlist Files

Generating Timing Simulation Netlist Files with Different Timing Models

First slow corner (slow, 1100 mV, 85° C):

1 The <revision_name>.vo and <revision name>_v.sdo are generated for backward

■ .vo file—<revision name>_<speedgrade>_1100mv_85c_slow.vo

Second slow corner (slow, 1100 mV, 0° C):

Fast corner (fast, 1100 mV, 0° C):

Disable Timing Violation on Registers

Compile Libraries Using the EDA Simulation Library Compiler

Run the EDA Simulation Library Compiler through the GUI

Run EDA Simulation Library Compiler In Command Line

Perform Simulation Using the ModelSim-Altera Software

Simulating the VHDL Designs through the GUI

Perform RTL Functional Simulation

1 The ModelSim-Altera software includes pre-compiled simulation libraries. Creating

Compile Testbench and Design Files into the Work Library

1 Resolve compile-time errors before proceeding to the next section.

Loading the Design

Running the Simulation

Perform Post-Synthesis Simulation

1 The ModelSim-Altera software includes pre-compiled simulation libraries. Creating

To change to the simulation output directory, perform the following steps:

1 Resolve compile-time errors before proceeding to the next section.

Loading the Design

Running the Simulation

Perform Gate-Level Simulation

1 The ModelSim-Altera software includes pre-compiled simulation libraries. Creating

To change to the simulation output directory, perform the following steps:

1 Resolve compile-time errors before proceeding to the next section.

Loading the Design

8. Select the top-level design unit (your testbench).

Running the Simulation

Simulating Verilog HDL Designs through the GUI

Perform RTL Functional Simulation

1 The ModelSim-Altera software includes pre-compiled simulation libraries. Creating

Compile Testbench and Design Files into the Work Library

1 Resolve compile-time errors before proceeding to the next section.

Loading the Design

8. Browse to the required pre-compiled library in the ModelSim-Altera software. You

Running the Simulation

Perform Post-Synthesis Simulation

1 The ModelSim-Altera software includes pre-compiled simulation libraries. Creating