Artificial Neural Network Modelling

for Cryo-CMOS Devices

Pascal A. ‘t Hart, Job van Jianjun Xu, David E. Root Masoud Babaie
Staveren, Fabio Sebastiano Keysight Laboratories Dept. of Microelectronics
2021 IEEE 14th Workshop on Low Temperature Electronics (WOLTE) | 978-1-7281-9306-9/21/$31.00 ©2021 IEEE | DOI: 10.1109/WOLTE49037.2021.9555438

Dept. of Quantum & Computing Keysight Technologies Inc. Delft University of Technology
Engineering; QuTech Santa Rosa, CA USA Delft, The Netherlands
Delft University of Technology
Delft, The Netherlands
f.sebastiano@tudeft.nl

Abstract—Quantum-based systems, such as quantum

computers and quantum sensors, typically require a cryogenic
electrical interface, which can be conveniently implemented using
CMOS integrated circuits operating at cryogenic temperatures
(cryo-CMOS). Reliable simulation models are required to design
complex circuits, but CMOS transistor electrical characteristics at
cryogenic temperatures substantially deviate from the behavior at
room temperature, and no standard physics-based model exists for
cryo-CMOS devices. To circumvent those limitations, this paper
proposes the use of Artificial Neural Networks (ANN) and an
associated training (extraction) procedure that automatically
generates cryo-CMOS device models directly from experimental
data. A device model for the DC characteristics of 40-nm CMOS
transistors over a wide range of bias conditions, device geometries
and temperatures from 4 K to 300 K has been generated and used
to simulate voltage-reference circuits over a wide temperature
range (4 K – 300 K). The potential application to dynamic/high-
frequency circuits is demonstrated by enhancing the basic model
with ANN-based nonlinear multi-terminal capacitive elements to
simulate a ring oscillator. Preliminary results showing a good Fig. 1. Device characteristics for an NMOS transistors (W=1.2 µm, L=40 nm)
match between simulations and experiments demonstrate the in a 40-nm CMOS process, highlighting both strong-inversion (left) and weak-
feasibility and practicality of the proposed approach. inversion (right) behavior.

significant self-heating can occur in cryo-CMOS integrated

Keywords—cryo-CMOS; cryogenics; semiconductor device
models; quantum computing; quantum sensing; CMOS integrated
circuits.
I. INTRODUCTION
CMOS integrated circuits operating at cryogenic
temperature (cryo-CMOS) are among the best alternatives for
the control electronics for future large-scale cryogenic quantum
computers and quantum sensors since they can integrate
extremely complex functionality on a single chip and can
operate down to sub-K temperature [1-6]. Such cryo-CMOS
circuits required to interface future quantum processors must
achieve high enough control and readout quality, in terms of
noise, accuracy, and speed, not to degrade the performance of
the quantum devices while dissipating a power complying with
the limited cooling capabilities of existing cryogenic
refrigeration technologies. However, designing a complex
CMOS circuit fulfilling the low-power high-performance
requirements requires reliable simulation models, describing
both the static and dynamic device behavior over a wide range
of bias conditions, device geometries, and temperatures, as
circuits [7]. While highly sophisticated device models for circuit
simulation are available for commercial CMOS processes, the
electrical characteristics for CMOS devices at cryogenic
temperatures significantly deviate from the room-temperature
behavior, as shown in Fig. 1. Although the physics of the cryo-
CMOS devices is mostly understood [8,9], there is not yet a
consensus on a standard cryo-CMOS model, and it is unclear
whether existing model extraction procedures can be effectively
applied to those cryogenic characteristics.
As an alternative, we propose the use of Artificial Neural
Networks (ANN) and associated training (extraction) techniques
to automatically generate cryo-CMOS simulation models
without requiring any physics-based device model [10]. ANNs
only require a discrete set of experimental data, e.g., the
transistor drain current for a limited set of bias points. Since
those data can be scattered, e.g., sampled without any gridding
constraints over temperature, bias, and device geometry,
significant cryogenic characterization effort can be saved. From
these data, the ANNs that are automatically generated provide
infinitely differentiable functions describing the device

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nonlinear current/voltage and charge/voltage relations, hence
are well-suited for accurate analog-circuit simulations. Flexible
output formats for the ANN models, including self-generated
standard Verilog-A code, enable the models to be immediately
accessed and evaluated by most modern circuit simulators.
This paper explores the potential of ANN models for cryo-
CMOS devices by applying such modeling methodology to
experimental data. After describing the basics of the ANN
modeling flow, both for static (Section II.A) and dynamic
(Section II.B) characteristics, Section III.A assesses the quality
of the proposed model for a large number of cryo-CMOS
devices. The performance of those models in predicting the
behavior of practical circuits is benchmarked by comparing the
simulations using the proposed models with the experimental
data for a static circuit (section III.B) and with simulations using
the foundry-provided model for a dynamic circuit (Section
III.C), respectively.
(a)
(b)
Fig. 2. (a) ANN structure illustrating the ANN layer structure, its
mathematical description and a plot of typical univariate neuron
nonlinearity (sigmoid and threshold functions). (b) Modeling flow: Given
the measured data, an ANN model is automatically trained (constructed).
The trained model is easily linked to a circuit simulator, e.g., Keysight
ADS, for high-level circuit simulation and design.
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II. ANN-BASED MODELS FOR CRYO-CMOS DEVICES
A. ANN Models for CMOS devices
ANNs are a powerful computational paradigm inspired by
the human nervous system [11]. They have become mainstream
tools of the artificial intelligence and machine learning
communities. The Universal Approximation Theorem [11]
proves that an ANN of at least one hidden layer with a sufficient
number of univariate processing functions, or neurons, can
arbitrarily fit any nonlinear function of any number of
independent variables. ANN training is an automatic process of
adjusting the internal weights and biases (parameters) of the
ANN to enable the model to match the training data. A typical
single hidden layer structure is shown in Fig. 2a, along with a
mathematical formula and a plot of a typical univariate neuron
nonlinearity, or threshold function.
There are no equation development or user-defined parameter
extraction processes needed. The general modeling flow is
(a)
(b)
Fig. 3 (a) Adjoint ANN training of the model gate terminal charge function
from CGG and -CGD data. The Adjoint training method utilizes a more
complicated ANN network, but ultimately returns an ANN model for the
terminal charge Qg (this figure) and similarly for Qd, the drain charge,
assuming a three-terminal device structure with the bulk node shorted to
the source. (b) Quasi-static model obtained by combining the voltage-
controlled current source ANN for the drain current with the two
independent terminal charge ANN model functions for gate and drain.
shown in Fig. 2b. Given the measured data, e.g., drain current
from sampled bias points and over a wide range of temperatures
and geometries (widths, lengths), an ANN model is
automatically trained (constructed). The trained model is easily
linked to a circuit simulator, e.g., Keysight ADS, for high-level
circuit simulation and design.
B. ANN-based Nonlinear Charge-based Capacitor Modeling
Unlike drain currents that can be directly measured at
different bias conditions and used to train ANN functions with
standard techniques to produce voltage-controlled current
source elements, the charge stored by device bias-dependent
capacitances cannot be directly measured. Instead, the nonlinear
charge functions (modeled by voltage-controlled nonlinear
capacitors) can be generated by training ANNs to
simultaneously fit the partial derivatives of the desired charge
Fig. 4. Examples of extracted models compared to measured results for 3
seelcted devices; red circle: experimental data; blue line: model.
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functions to bias-dependent capacitances (e.g. CGG and CGD)
that can be obtained from S-parameter data [12]. This requires
a unique kind of automated “Adjoint training” [10] that
essentially performs line-integration of measured data and is
illustrated in Fig. 3. This approach is generally superior to a
direct numerical line-integration approach for several reasons,
as described in [13].
The implementation in this work, however, ignores the effect
of independently biasing internal nodes (e.g. the bulk node), and
effectively treats the device as having two independent terminal
voltages, drain-source (VDS) and gate-source (VGS) voltages,
assuming the bulk node to be tied to the source.
III. EXPERIMENTAL RESULTS
A. DC Characteristics
Experimental cryogenic data were obtained from an array of
NMOS and PMOS devices fabricated in the TSMC 40-nm bulk
CMOS process and comprising 400 different device geometries,
ranging from minimum (W=120 nm, L=40 nm) to large size
(W=10 µm, L=10 µm). The drain and source of all devices share
the same Kelvin connections, respectively. Individual transistors
are digitally selected by either shorting their gate to the
appropriate supply rail or an external gate voltage. Assembled in
a ceramic DIP package and mounted on a PCB, the die
temperature has been swept by inserting the sample inside a
liquid-Helium dewar and varying its height in the Helium vapor
or in the liquid Helium. The chip temperature is monitored by an
external Cernox reference sensor in thermal contact with the
package.
The drain current has been measured with two Keithley
2636B Source Measurement Units (SMUs) by sweeping both
VDS and VGS over the range from 0 to the nominal supply voltage
(VDD=1.1 V) with the source shorted to the bulk potential
(ground for the NMOS, VDD for the PMOS). Although the data
has been acquired on a regular grid for VDS and VGS, this is not
strictly necessary for the ANN training. For instance, the width
and length of the 400 geometries are not linearly spaced but
logarithmically scaled from 40 nm to 10 µm, in order to sample
the region closer to the minimum size more accurately, since
those devices are more relevant for circuit design and more
significant variations in their electrical behavior are expected.
The ANN model has been trained over the drain current data
measured at 4 K, 100 K and 300 K, over a bias grid of 12 VDS
values × 151 VGS values, and for the 400 geometries to learn the
constitutive relation ID(VDS, VGS, W, L, T). The training required
24 hours on a 4-core intel i7 workstation with 32-GB RAM. The
resulting model fitted the measured DC characteristics within a
1% RMS error. Examples from a few selected devices and
temperatures are shown in Fig. 4, demonstrating the quality of
the resulting models.
B. Model Validation with Static Circuits over a Wide
Temperature Range
To demonstrate the potential of ANN models for circuits
designed to operate over a wide temperature range, the ANN
models have been used to simulate the cryo-CMOS voltage
reference described in [14], which has been designed and tested
over the ultra-wide temperature range from 4 K to 300 K. Four
devices (2 NMOS and 2 PMOS) from the test chip described in
Section II.A and with geometry closely matching the devices
used in the circuit were measured over multiple temperatures (4
K, 20 K, 40 K, 80 K, 120 K, 160 K, 190 K, 220 K, 300 K) to get
a smoother temperature behavior. Circuit simulations with the
resulting ANN models showed a good match with the
experimental data over the whole range from 4 K to 300 K, as
shown in Fig. 5.
C. Model Validation with a Dynamic Circuit
A dynamic ANN model based on the quasi-static approach
described in Section II.B was generated from S-parameters
obtained from simulations of the same devices using the
foundry-provided models at 300 K (the foundry models are not
valid at 4 K) and measured I-V data, and has been benchmarked
by simulating a 500-MHz inverter-based ring oscillator
employing 142 digital inverters (and a NAND gate). Although
the dynamic model is limited to 300 K due to the present lack of
measured cryogenic S-parameters, the oscillation frequency
predicted by the ANN models for 300 K (525 MHz) accurately
matched (within 6%) the predictions of the foundry-provided
models (559 MHz).
Fig. 5. Comparison of the simulated and measured reference voltage. The
reference voltage Vref is obtained by combining a CTAT voltage
(complementary-to-absolute-temperature) and a PTAT voltage
(proportional-to-absolute-temperature). There are some discrepancies at
very high temperatures, e.g., simulated results have more curvature than
the measured data, which is due to the sparse sampling of the temperature
in the training data (red dots indicate the temperatures used in the
measurements).
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IV. CONCLUSIONS
These results demonstrate the utility of automatically
generated ANN models for cryo-CMOS applications. By
avoiding developing specific physics-based models and
minimizing the required characterization data, the proposed
modeling approach can significantly accelerate the development
of the complex cryo-CMOS electrical interfaces for future large-
scale quantum processors.
ACKNOWLEDGMENTS
The authors thank the legal teams of the TU Delft and
Keysight Technologies, and Keysight Laboratories and
Keysight Quantum Engineering Solutions organizations for
encouragement and support. The authors at TU Delft would like
to thank Intel for funding.
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