IMPLEMENTATION

IMPLEMENTATION OF UART IN VERILOG

A Mini project report

Submitted in partial fulfillment of the

Requirements for the award of the degree

Bachelor of Technology
Technology

in

ELECTRONICS& COMMUNICATION Engineering

BY

R.Swathi 08QR1A0449
N.Srilatha 08QR1A0440
Under the guidance of 

Y.Ramakrishna

H.O.D of ECE Department

DEPARTMENT OF ELECTRONICS AND COMUNICATIONS ENGINEERING

KITE WOMEN’S COLLEGE OF PROFESSIONAL

ENGINEERING
ENGINEERING SCIENCES (KPSW)

(Approved By AICTE and Affliated to JNTU, HYD)

SHABAD, Ranga Reddy District – 509217, Tel: 08417-279053

 DEPARTMENT OF ELECTRONICS AND COMUNICATIONS ENGINEERING

KITE WOMEN’S COLLEGE OF PROFESSIONAL

ENGINEERING SCIENCES

SHABAD, Ranga Reddy District  – 509217, Tel: 08417- 279053

DECLARATION BY THE CANDIDATE

I, hereby declare that the Mini project work entitled

IMPLEMENTATION OF UART IN VERILOG is being submitted in partial fulfillment

IMPLEMENTATION

of the requirements for the award of the Degree BACHELOR OF TECHNOLOGY in

ELECTRONICS AND COMUNICATIONS ENGINEERING

This is a Mini Project report work carried out by me under the guidance of ,

Y.Rama krishna H.O.D Professor of of ECE Department and the results embodied

in this project have not been reproduced or copied from any source. The results

embodied in this project have not been submitted to any other University or

Institute for the award of any other Degree or Diploma.

.
 DEPARTMENT OF ELECTRONICS AND COMUNICATIONS ENGINEERING

KITE WOMEN’S COLLEGE OF PROFESSIONAL

ENGINEERING SCIENCES

SHABAD, Ranga Reddy District  – 509217, Tel: 08417- 279053

CERTIFICATE

This is to certify that the Mini project report entitled

“IMPLEMENTATION OF UART ALGORITHM CODE IN VERILOG ” is record of 

bonafide work carried out by R.Swathi bearing 08QR1A0411 , and is being

submitted in partial fulfillment of the requirements for the award of the degree

BACHELOR OF TECHNOLOGY in ELECTRONICS AND COMUNICATIONS

ENGINEERING

The results of investigations enclosed in this report have been Verified and found

Satisfactory. The results embodied in this project have not been submitted to any

other University or Institute for the award of any other Degree or Diploma .

Internal Examiner Head of the Department

External Examiner
 ACKNOWLEDGEMENTS

First and foremost, we express our sincere thanks for the guidance and encouragement

rendered by Y.Rama krishna H.O.D Professor of ECE Department Department of 

Computer Science & Engineering & Information Technology, KITE WOMEN’S COLLEGE OF PROFESSIONAL

ENGINEERING SCIENCES, Shabad. We extend our gratitude for his advice and guidance during the

progress of this Mmini-project.

We express my profound gratitude to our indebtedness to our Management for providing

State of the Art Laboratories and Infrastructure.

We wish to express our profound thanks to our Director- Academics Dr. K.S.R.K. Prasad ,
KITE, Shabad, for providing necessary facilities to make t his mini-project a success.

We thank all the members of Teaching Staff members, and also who have assisted us directly or

indirectly for successful completion of this mini-project.

Finally, we would like to express our sincere gratitude to our Parents who are constantly encouraging us

throughout our life and completion of this mini-project.

 UART

ABSTRACT

Serial communications is the process of sending data one bit at one time,
sequentially, over a communication channel or computer bus. Serial
communications is used for all long haul communications and most computer
networks, where the cost of cable and synchronization difficulties make parallel
communications impractical. Serial transmission is commonly used with modems
and for non-networked communication between computers, terminals and other
devices. The Universal Asynchronous Receiver/Transmitter (UART) controller is
the key component of the serial communications subsystem of a computer. The
UART takes bytes of data and transmits the individual bits in a sequential fashion.
At the destination, a second UART re-assembles the bits into complete bytes.
Introduction

UART - Universal Asynchronous Receiver/Transmitter (UART) An integrated

circuit used for serial communications, containing a transmitter (parallel-to-serial
converter) and a receiver (serial-to-parallel converter), each clocked separately.
The UART takes bytes of data and transmits the individual bits in a sequential
fashion. At the destination, a second UART re-assembles the bits into complete
bytes.

The CPU communicates with the UART by reading or writing one of eight bytes
called ports. A computer system normally has more than one UART, so the port
addresses depend on the particular UART being accessed. Each UART is
associated with a different base address, and a particular port is specified by adding
a specific index to that base address. The index for a particular port is independent
of the UART, so we can characterize the ports by indices 0 through 7.

Serial Data Transmission

Why is a UART necessary for a computer modem?

A modem is composed of two basic parts, the UART and the analog modulator-
demodulator,which is where the term (Modem) comes from. During transmission
of data the UART is responsible for taking the data from the host machine and
turning it into a serial bit stream that can be sent by the modem over the phone
line. During reception of data the UART takes the serial data from the modem and
converts it into parallel data that can be used by the host machine.
The parallel side of a UART's usually connected to the bus of a computer. When
the computer writes a byte to the UART's transmit data register (TDR), the UARTs
will start to transmit it on the serial line. The UART's status register contains a flag
bit which the computer can read to see if the UART is ready to transmit another
byte. Another status register bit says whether the UART has received a byte from
the serial line, in which case the computer should read it from the receive data
register (RDR).

The UART's serial connections usually go via separate line driver and line receiver
integrated circuits which provide the power and voltages required to drive the
serial line and give some protection against noise on the line.

Data on the serial line is formatted by the UART according to the setting of the
UART's control register. This may also determine the transmit and receive baud
rates if the UART contains its own clock circuits or "baud rate generators".

UART is the most commonly used host controller interface because of following
reasons:

 If UART is used software overhead is very less

 Its highly cost effective.
 Simple way to send data from one system to another system
 Add functional to applications

1.General usage of UART is : For our purposes, UART is a relatively simple

device that illustrates the nature of device controllers (DCs).

2.Interface of UART:A UART acts as the interface between an I/O bus and a
serial device, such as a mouse or modem, which communicate with a computer one
bit at a time. On a PC, there are two UARTs that connect to the COM1 and COM2
ports on the back of the computer.

3.The job of a UART is to accept bytes of data from the CPU 8 bits at a time
(in parallel) and to transmit them one bit at a time (serially) to whatever device is
plugged into its connector on the back of the computer. At the same time, it
Transmitting and receiving serial data

UART transmitter controls transmission by fetching a data word in parallel format

and directing the UART to transmit it in a serial format. Likewise, the Receiver
must detect transmission, receive the data in serial format, strip of the start and
stop bits, and store the data word in a parallel format.

Since the UART is asynchronous in working, the receiver does not know when the
data will come, so receiver generate local clock in order to synchronize to
transmitter whenever start bit is received.

The UART usually does not directly generate or receive the external signals used
between different items of equipment. Separate interface devices are used to
convert the logic level signals of the UART to and from the external signaling
levels. External signals may be of many different forms. Examples of standards for
voltage signaling are RS-232, RS-422 and RS-485 from the EIA. Historically,
current (in current loops) was used in telegraph circuits. Some signaling schemes
do not use electrical wires. Examples of such are optical fiber, IrDA (infrared), and
(wireless) Bluetooth in its Serial Port Profile (SPP). Some signaling schemes use
modulation of a carrier signal (with or without wires). Examples are modulation of 
audio signals with phone line modems, RF modulation with data radios, and the
DC-LIN for power line communication.

Communication may be "full duplex" (both send and receive at the same time) or
"half duplex" (devices take turns transmitting and receiving).

Character framing

Each character is sent as a logic low start bit, a configurable number of data bits
(usually 7 or 8, sometimes 5), an optional parity bit, and one or more logic high
stop bits. The start bit signals the receiver that a new character is coming. The next
five to eight bits, depending on the code set employed, represent the character.
Following the data bits may be a parity bit. The next one or two bits are always in
the mark (logic high, i.e., '1') condition and called the stop bit(s). They signal the
receiver that the character is completed. Since the start bit is logic low (0) and the
stop bit is logic high (1) then there is always a clear demarcation between the
previous character and the next one.
Asynchronous Serial Transmission:

Asynchronous transmission allows data to be transmitted without the sender

having to send a clock signal to the receiver. Instead, the sender and receiver must
agree on timing parameters in advance and special bits are added to each word
which are used to synchronize the sending and receiving units.

When a word is given to the UART for Asynchronous transmissions, a bit called
the "Start Bit" is added to the beginning of each word that is to be transmitted. The
Start Bit is used to alert the receiver that a word of data is about to be sent, and to
force the clock in the receiver into synchronization with the clock in the
transmitter. These two clocks must be accurate enough to not have the frequency
drift by more than 10% during the transmission of the remaining bits in the word.
(This requirement was set in the days of mechanical teleprinters and is easily met
by modern electronic equipment.)

After the Start Bit, the individual bits of the word of data are sent, with the Least
Significant Bit (LSB) being sent first. Each bit in the transmission is transmitted
for exactly the same amount of time as all of the other bits, and the receiver
``looks'' at the wire at approximately halfway through the period assigned to each
bit to determine if the bit is a 1 or a 0. For example, if it takes two seconds to send
each bit, the receiver will examine the signal to determine if it is a 1 or a 0 after
one second has passed, then it will wait two seconds and then examine the value of 
the next bit, and so on.The sender does not know when the receiver has ``looked''
at the value of the bit. The sender only knows when the clock says to begin
transmitting the next bit of the word.

When the entire data word has been sent, the transmitter may add a Parity Bit that
the transmitter generates. The Parity Bit may be used by the receiver to perform
simple error checking. Then at least one Stop Bit is sent by the transmitter.

When the receiver has received all of the bits in the data word, it may check for the
Parity Bits (both sender and receiver must agree on whether a Parity Bit is to be
used), and then the receiver looks for a Stop Bit. If the Stop Bit does not appear
when it is supposed to, the UART considers the entire word to be garbled and will
report a Framing Error to the host processor when the data word is read. The usual
cause of a Framing Error is that the sender and receiver clocks were not running at
the same speed, or that the signal was interrupted.

Regardless of whether the data was received correctly or not, the UART
automatically discards the Start, Parity and Stop bits. If the sender and receiver are
configured identically, these bits are not passed to the host.

If another word is ready for transmission, the Start Bit for the new word can be
sent as soon as the Stop Bit for the previous word has been sent.Because
asynchronous data is “self synchronizing”, if there is no data to transmit, the
transmission line can be idle.

Advantages and disadvantages:

Advantages Disadvantages

Simple, doesn't require

synchronization of both
communication sides

Cheap, timing is not as critical as

Large relative overhead, a high
for synchronous transmission,
proportion of the transmitted
Asynchronous therefore hardware can be made
bits are uniquely for control
transmission cheaper
purposes and thus carry no
Set-up is very fast, so well suited useful information
for applications where messages
are generated at irregular
intervals, for example data entry
from the keyboard
Slightly more complex
Synchronous Lower overhead and thus, greater
transmission throughput
Hardware is more expensive
MCR: Modem control register

Handshaking actions with the attached device are accomplished by the Modem
Control Register (MCR). In the UART series 16550, setting and resetting of the
control signals must be done by software. But in the new 16750, flow control
automatically handled.

LSR: Line status register

The Line Status Register (LSR) shows the current state of communication. Errors,
the state of the receiver and transmit buffers are available.

MSR: Modem status register

The Modem Status Register (MSR) contains information about the four incoming
modem control lines on the device. The four most significant bits contain
information about the current state of the inputs. The least four significant bits are
used to indicate state changes. Each time the register is read the four LSB's are
reset.

DLL and DLM: Divisor latch registers

The communication speed of the UART is changed by using a programmable

value stored in Divisor Latch Registers DLL and DLM which contains the least
and most significant registers.

Key Functions of a UART

• Serial to Parallel Conversion

• Buffering
• Data Communication Baud Rate Generation
• Communication Handshaking
• Start/Stop Bits
• Parity Generation
Other UART Functions

 In addition to the basic job of converting data from parallel to serial for
transmission and from serial to parallel on reception, a UART will usually
provide additional circuits for signals
 That signals can be used to indicate the state of the transmission media, and
to regulate the flow of data in the event that the remote device is not
prepared to accept more data.

Example:

• When the device connected to the UART is a modem, the modem may
report the presence of a carrier on the phone line while the computer may be
able to instruct the modem to reset itself or to not take calls by raising or
lowering one more of these extra signals.
• The function of each of these additional signals is defined in the EIA RS232-
C standard.

UART Errors

Overrun Error:

An "overrun error" occurs when the UART cannot process the byte that just came
in before the next one arrives. The host processor must service the UART in order
to remove characters from the buffer. If the host processor does not service the
UART and the buffer becomes full, then Overrun Error will occur.

Framing Error:

A "Framing Error" occurs when the designated "start" and "stop" bits are not valid.
Start bit acts as a reference for the remaining bits. When the "stop" bit is expected
if the data line is not in the expected idle state a Framing Error will occur.

Parity Error:

A "Parity Error" occurs when the number of "active" bits does not agree with the
specified parity configuration of the UART.

Underrun error:

In "underrun error" occurs when the UART transmitter has completed sending
character and the transmit buffer is empty. In asynchronous modes this is treated as
an indication that no data remains to be transmitted, rather than an error, since
additional stop bits can be appended. This error indication is commonly found in
USARTs, since an underrun is more serious in synchronous systems.

Key Features of UART:

 Choice of 1.8V, 2.5-V, 3.3-V, or 5-V supply

 Single-, dual-, and quad-channel devices available
 Transmit and Receive FIFOs of either 16-Byte or 64-Byte depth
 Patented hardware and software auto-flow control
 Programmable sleep mode and low-power mode.
 Industrial temperature characterization available

Types of UARTS

8250

The first UART in this line. It doesn't contain any scratch registers. 8250A is a
modernized version of 8250, its bus operating speed is very fast.

8250A

The bus operating speed of this UART is greater than 8250's. It is used in the
same way as 16450 in the sphere of software.

8250B

Very similar to that of the 8250 UART.

16450

Used in AT's (Improved bus speed over 8250's). Works stable at 38.4KBPS.
Widespread today.

16550

This line is the first generation of buffered UART. This line has 16-byte buffer,
however it doesn't work and is replaced with the 16550A.

16550A

This line is the most widespread UART version used for high-speed connection of 
modems with 14.4KBPS and 28.8KBPS rates. They made sure the FIFO buffers
worked on this UART.

16650
 UART Receiver RCV_shftreg

Serial_in

RCV_datareg

RECEIVER D
a
Read_not_ready_in CONTROLLER t
a
Read_not_ready_out 

B
Error1
u
Error2 s

To / From
Sys_Clock Sample_clk  Host

UART Clock 
Reset_ Clock 
Generator 

Bit_count 

Byte_ready clear clear 

Transmitter 
T_byte controller  shift 

start 

Load_XMT_shftreg

 XMT_shiftreg

Serial_out  1

Load_XMT_datareg

 XMT_datareg
 Uart_transmitter_arch

Byte_ready UART Load_XMT_shftreg

Transmitter start
Load_XMT_datareg

Bit_count Datapath Shift

Clear
T_BYTE
Controller

The controller has the following inputs.For simplicity,Load_XMT_datareg is

shown connected directly to XMT_datareg:

Byte_ready asserted by host machine to indicate that Data_Bus has

valid data

Load_XMT_datareg assertion transfers Data_Bus to the transmitter data

storage register,XMT_datareg.

T_byte assertion intiates transmission of a byte of 

data,includuing the stop,start,and parity bits

Bit_count counts bits in the word during transmission

The state machine of the controller forms the following output signals that

control the datapath of the transmitter

Load_XMT_shftreg assertion loads the contens of XMT_data_reg into

XMT_shftreg

Start signals thestart of transmission

Shift directs XMT_shftreg to shift by one bit towards the LSB

and to backfill with a stop bit(1)

Clear clears bit_count

 Read_not_ready_in

Read_not_ready_in
Clr_Sample_Counter

UART Inc_Bit_counter

Clr_Bit_Counter
Serial_in Receiver
Inc_Sample_Counter
Datapath
shift
Controller
Sample_Count
load

Error1

Bit_Counter Error2

The state machine produces the following inputs:

Read_not_ready_in signals that the host is not ready to receive data

Serial_in serial bit stream received by the unit

Reset active low reset

Sample_counter counts the bits that have been sampled

case (state)

idle: if(Serial_in == 0)next_state = starting;

starting if(Serial_in == 1) begin

next_state = idle;

clr_Sample_counter = 1;

end else

if(Sample_counter == half_word - 1) begin

next_state = receiving

clr_Sample_counter = 1;

end else inc_Sample_counter = 1;

receiving: if(Sample_counter < word_size - 1) inc_Sample_counter = 1;

else begin

clr_Sample_counter = 1;

if(Bit_counter ! =word_size)begin

shift = 1;

inc_Bit_counter = 1;

end

else begin

next_state = idle;

read_not_ready_out = 1;

clr_Bit_counter = 1;

if(read_not_ready_in == 1) Error1 = 1;

ela=se if(Sample_in == 0) Error = 1;

else load = 1;
 end

end

default: next_state = idle;

endcase

end

always @ (posedge Sample_clk) begin

if(reset_ == 0)begin state <= idle;

Sample_counter <= 0;

Bit_counter <= 0;

RCV_datareg <= 0;

RCV_shftreg <= 0;

end

else begin

state <= next_state;

if(clr_Sample_counter == 1) Sample_counter <= 0;

else if (inc_Sample_counter ==1) Sample_counter <= Sample_counter + 1;

if(clr_Bit_counter == 1) Sample_counter <= 0;

else if (inc_Bit_counter == 1) Bit_counter <= Bit_counter + 1;

if(shift == 1) RCV_shftreg <= {Serial_in, RCV_shftreg[word_size - 1:1]}

if(load == 1) RCV_datareg <= RCV_shftreg

end

end
 endmodule

APPLICATIONS OF UART :

1. Serial data communications applications.

2. Modem interface

3. Embedded microprocessor r boards

4. Serial or modem computer interface

5. Serial interface within modems and other devices

References

1.Advanced Digital Design with the Verilog HDL by Michael D.Ciletti

2. www.edaboard.com

3. www.classle.net/projects/project_ideas

4. www.scribd.com

5.www.asic-world.com

6.www.vlsi.com

7.projectsuniversal.in

8.only-vlsi.blogspot.com

9.www.thesatya.com

10.en.pudn.com