DECODER

A. If statement with multiple else-if clause

B. Case statement

C. Gate level modeling

2:4 LINE DECODER

DATA FLOW

module decoder_2_4(a,b,w,x,y,z);

output w,x,y,z;
input a,b;

assign w = (~a) & (~b);

assign x = (~a) & b;
assign y = a & (~b);
assign z = a & b;
endmodule

Behave
module decoder2_4 ( din ,dout );

output [3:0] dout ;

reg [3:0] dout ;

input [1:0] din ;

wire [1:0] din ;

always @ (din) begin

if (din==0)
dout = 8;
else if (din==1)
dout = 4;
else if (din==2)
dout = 2;
else
dout = 1;
end

endmodule

module decoder_2_to_4(
input a0,
input a1,
output d0,
output d1,
output d2,
output d3
);
not(an0,a0),(an1,a1);
and(d0,an0,an1),(d1,a0,an1),(d2,an0,a1),(d3,a0,a1
);
endmodule
3: 8 DECODER

module decoder3_to_8(
input x,
input y,
input z,
output d0,
output d1,
output d2,
output d3,
output d4,
output d5,
output d6,
output d7
);
and (d0,xn,yn,zn),(d1,xn,yn,z),(d2,xn,y,zn),(d3,xn,y,z),(d4,x,yn
,zn),(d5,x,yn,z),(d6,x,y,zn),(d7,x,y,z);
not (xn,x),(yn,y),(zn,z);
endmodule

A. If statement with multiple else-if clause

module dec38 (I, Y);

input [2:0] I;

output [7:0] Y;
reg [7:0] Y;

always @ (I)

begin

if (I= = 3’d0) Y=8'b00000001;

else if (I= = 3’d1) Y=8'b00000010;

else if (I= = 3’d2) Y=8'b00000100;

else if (I= = 3’d3) Y=8'b00001000;

else if (I= = 3’d4) Y=8'b00010000;

else if (I= = 3’d5) Y=8'b00100000;

else if (I= = 3’d6) Y=8'b01000000;

else Y=8'b10000000;

end

endmodule

B. Case statement

module dec38 (I,Y);

input [2:0] I;

output [7:0] Y;

reg [7:0] Y;

always @ (I)

begin

case (I)

0 : Y=8'b00000001;

1 : Y=8'b00000010;

2 : Y=8'b00000100;

3 : Y=8'b00001000;

4 : Y=8'b00010000;

5 : Y=8'b00100000;

6 : Y=8'b01000000;
7 : Y=8'b10000000;

default : Y=8'b00000001;

endcase

end

endmodule

Gate Level MOdel

module decoder3_to_8(input x, input y, input z, output d0, output d1, output d2, output d3, output d4,
output d5, output d6, output d7);

and (d0,xn,yn,zn),(d1,xn,yn,z),(d2,xn,y,zn),(d3,xn,y,z),(d4,x,yn,zn),(d5,x,yn,z),(d6,x,y,zn),(d7,x,y,z);

not (xn, x),(yn, y),(zn, z);

endmodule

Verilog Code in Dataflow Modeling:

module decoder_3to8(
input [2:0] a,
output [7:0] d );
assign d[0]=(~a[2])&(~a[1])&(~a[0]);
assign d[1]=(~a[2])&(~a[1])&(a[0]);
assign d[2]=(~a[2])&(a[1])&(~a[0]);
assign d[3]=(~a[2])&(a[1])&(a[0]);
assign d[4]=(a[2])&(~a[1])&(~a[0]);
assign d[5]=(a[2])&(~a[1])&(a[0]);
assign d[6]=(a[2])&(a[1])&(~a[0]);
assign d[7]=(a[2])&(a[1])&(a[0]);
endmodule

Verilog Code in Structural Modeling:

module decoder_struct(
input [2:0] a,
output [7:0] d
);
wire x,y,z;
not g1(z,a[0]);
not g2(y,a[1]);
not g3(x,a[2]);
and g4(d[0],x,y,z);
and g5(d[1],x,y,a[0]);
and g6(d[2],x,a[1],z);
and g7(d[3],x,a[1],a[0]);
and g8(d[4],a[2],y,z);
and g9(d[5],a[2],y,a[0]);
and g10(d[6],a[2],a[1],z);
and g11(d[7],a[2],a[1],a[0]);
endmodule

4:16 Decoder