DR-140T/E/TE1/TE2 Service Manual CONTENTS @ SPECIFICATIONS @ PARTS LIST 1) Genera. 2 Main Unit 21-22 2) Transmitter 2 Packing 2a 3) Receiver 3 (PU Unt 23 SP Unit 23 Veo unit 23 @ CIRCUIT DESCRIPTION essa rasa 23 1) Receiver Sytem 4-5 u-200 24 2) Transmitter System, 5-8 3) PLL Circuit : 6 4) Terminal Function of CPU 7 @ ADJUSTMENT 1) Required Test Equipment. 25 (@ SEMICONDUCTOR DATA ae sy 23) TX Adjustment 28 1) AKe341 10 4) AK Adjustment. ar 2) ANTBLOSN ” 5) Adjustment Point, 28 3) LAGA25A, " 4) M5218FP 1 5) M56760FP. 12 @PcBoaD view 8) M07746. 13 1) Main Unit Side A . 29 7) Mea702H. 13 2) Main Unit Side B 20 8) Me8702t. 13 3) CPU Unit Sde A 31 8) Mo7B08CrT. ‘4 4) CPU Unit Side 8. at 10) RHSVL32AAt ‘4 5) VCO Unit Side A 92 11) RHSVLASAATH 14 6) VCO Unit Side B 32 12) TK10930VTL 15 7) 68-200 (CTOSS Unit: Option). 33 13) uPCarioT 16 14) 24Lc168 18 15) Transistor Diode and LED Outine Drawings ....17 bedeaciaae aca 16) LoD. e @ SCHEMATIC DIAGRAM 1) Main Unit TE. 35-96 @ EXPLODED VIEW 2) Main Unit TEWTE2. inane 7-88 1) Bottom View 19 3) $PU Unit 39 2) LCD Assombiy 20 410 Unt, a 3) Top, and Front View 2 8) E-20U (CTCSS Unit Option) a ALINGGO inc.SPECIFICATIONS 1) General TX Frequency Range: RX Frequency Range: CTCSS Encode: CTCSS Decode: Microphone: Frequency Resolution Antenna impedance: Power input: Current Drain @13.8V DC: Dimensions: Weight: Memory Channels: Display: Tone Bursts: Time Out Timer: Busy Channel Lock Out Penalty Timer: Scan Function: 2) Transmitter Output Power (approx.): Emission: Modulation System: Max. Frequency Deviation: ‘Spurious Emission: Operations: TX/RX Offset Range: T 144,000 ~ 147.995MHz E 144,000 ~ 145.995MHz TE1 136.000 ~ 155.000MHz TE2 — 150.000 ~ 173.995MHz T 118.000 ~ 135.995MHz (AM), 136.000 ~ 173.995MHz (FM) E 144,000 ~ 145, 995MHz (FM) TE1 136,000 ~ 173.995MHz (FM) TE2 136,000 ~ 173.995MHz (FM) Standard 50 Tones Optional 50 Tones Electret Cond, with DTMF 5, 10, 12.5, 15, 20, 30, 5OkHz steps, user adjustable 502 unbalanced 13.8V DC + 10% AX Squelched: less than 800mA TX High: approx. 10.5A, Low: approx. 3.58 441mm(W) x 41mmy(H) x 1S4mm(D) (without projections) approx. 0.86kg 50 Channels plus GALL channel; each stores RX; TX offset, CTCSS encode, optional CTCSS decode and alphanumeric display information Alphanumeric, English and Cyrillic alphabets, numbers 0-9, figures, upto 7 characters; backlit LCD 1000, 1450, 1750, 2100 Hz 30 to 450 seconds; selectable in 30 second increments Available - Requires Optional EJ20U CTCSS Tone Decode Unit 0 ~ 15 seconds Busy or Timed; Up or Down, memory or VFO High 50W / Low 5W (T/E), High 35W / Low SW (TE1/TE2) FSE FM Variable Reactance Frequency Modulation + 5kHz -604B or under below carrier ‘Simplex or Semi-Duplex Modes From 0 up to + 99.995MHz (full tuning range of radio) Offset may be saved as part of information stored in any memory channel3) Receiver Receiving System Dual Conversion Superheterodyne IF Frequencies: First: 30.85MHz; Second: 455kHz Sensitivity: 1208 SINAD -15dBp. Selectivity: More than + GkHz at 6dB; Less than + 15kHz at -60dB Autia Output: More than 2.5 Watts @10% distortion Speaker Impedance: 80 ‘Specifications are subject to change without notice or obligation. Performance specifications apply only to transmit bands. Names of certain products mentioned in this catalog are used for identification purposes only and may be trademarks or registered trademarks of their respective company.CIRCUIT DESCRIPTION 1) Receiver System 4 Antenna Switching Circuit (Main unit) The signal rom the antenna is input to RF ampliier circuit passing through the 5 stages low-pass liter (LIS ~ L18, C76 ~ C80, C148), the antenna switehing crcl (09, 011, L14, C63), T type high-pass fiter (L11, L12, C57, €64, C58, C58) and bband switch circuit (020, E version only), The antenna switching circuit uses M4 diode switch circuit. 2. RF Amplifier Circuit (Main unity AF signa is ampliied approximately 2008 by FF amplier. FF ampiir circuit 4328 dual gate FET to get good inter-moduiation characteristics, The AF amplifier Consists of voltage tuned band-pass filter (L1, L2, L4, LS, 02, DQ, D5, 06) and AF AMP (Q6). The signal is amplified attr eliminating unwanted signals so that image inleterence characteristics are improved 3. 1st Mixer Gircuit (Main unit) ‘The amplifiod signal is converted into the first IF signal of 30.85MHz by mixer Circuit (QS). Mixer circuit uses dual gate FET to improve multifrequency character- Isties such as inter-modulation. The output signal from mixer circull is led to 1st IF cireut. 4. Air Band Circuit (Main unit /T, E version) “The output signal trom band switch circuits ld fo low-pass filer circuit (L7, LB, ‘€85, C58) and input to RF ampllior crcut (Qt). There the signal is ampliied ‘approximately 2048 and input to the mixer cuit 5. 18tIF Circuit (Main unit) ‘The output tst IF signal from mixer circuit is lad to crystal filter XY Unwanted frequency band of IF signal is eliminated by a crystal titer. The result- ing signal is led to the 2nd IF ampliter, and the signal is oulpat to 2nd IF circuit 6, 2nd IF Circuit and Detector Circuit (ain unity Tho 1st IF signals ied to 2nd mixer circuit of 161, then itis converted into the 2nd IF signa! (455KHz) by 2nd local signal. 1C1 has the 2nd mixer, 2nd local oscillator circuit, quadrature detector circuit and AM detector circuit. The 2nd focal osclator cscilales 2nd local signal (30.395MH2). The 2nd IF output signal from mixer (pin 3ofIC4) circult Is led to ceramic filer (FL1). Unwanted frequency band of 2nd IF signal is efminated by a ceramic fiter. Tho resulling FM signa! is ed tothe limiter ampier (pin 7 of 1C1) circuit and quadrature detector circu (pin 11 of IG1 and ‘coramic discriminator X1), and the 2nd IF signals converted to AF signal. The FM AF signal is output fram pin 12 of {C1 to AF circuit. The AM signal is input fo AM dotector circuit pin $ of IC), and tho AM AF signal is output trom pin 13 of 1017. AF and Mute Cirouit ‘Main unit 8, Squelch Circuit (CPU unity ‘The AF signal from IC1 istered by the low-pass titer amplifier {G2) and fed tothe high-pass fiter amplifier (Q1), and output te the AF gain volume, Q3 and Q4 are ‘switched ON)OFF by AFC signal rom CPU, then AF signal is muted when the squetch is ON. ICt has the noise ampli, rectifer circuit and comparator circuit. The noise signal from pint? of 1C1 is input to the nose amplifier (pint9 of IC1) and passed through butler ampitier (228), rected by D8, then itis input to comparator crcut (pin 21 ‘of C1). When the noise signal is decreased by the receiving signal, the compara- {or output SD becomes lov. 2) Transmitter System 1. Microphone Amplifier Circuit (CPU unity 2, Limiter Amplifier Circuit, (Main unity 3. Modulation Circuit (VCO unit) 4, Drive Amplifier Circuit (Main unity 5. RF Younger Amplifier Circuit (Main unit) ‘The voice from external microphone is amplified by the microphone ampitier (C303), and passed through the microphone mute circuit (304), the signal is. input to the microphone gain potentiometer (VR3) in the main unit The signal from microphone gain potentiometer (VR3) is amplified by limiter ‘arupfer and low-pass (IC4). The resulting signal is passed through the modula~ tion adjustment potentiometer (VR), then input to VCO unit. IC4A is limiter amplifier with pre-emphasis characteristics, IC4B is low-pass fiter. ‘The adjusted AF signal in VR¢ is led to the VCO unit. The frequency modulation is ‘executed when the audio signal is supplied to the D207. The signal from VCO units input to the drive amplifier ((C3). 163 has high gain of approximately 30dB and high level of approximately 10dBm wide band amplifier. The signal from IG3 is passed through diode switch 012, and input to younger ‘amplifar Q13. Q13 has approximately 15dB gain and output level is 400mW. The ‘output signal of younger amplifier is led to the PA ampilier(IC2)6. RF Power Amplifier Circuit (tain unity 7, Antenna Switch Circuit (RF unity 8. APC Circuit (RF unit) 3) PLL Circuit 1. Summary 2. Reference Oscillator Circuit (Main unity 9 Loop Fitter Circuit, (VCO unity 4.VC0 circuit {VCO unit) 1C2 is the power madule, which obtains stable output power (SOW TIE, 25W TET/ ‘TE2) within the band. The signal of younger amplifier is amplified by the PA ampilfier (102), and ther fed to the antenna switch circuit, When transmitting, D11 and D9 are ON in the antenna switch circuit, L14 becomes pparaitel components. This causes the output signal of 102 nt to go to the RX Girouit. The signal is led to the antenna connector passing through the low-pass fiter (L15 ~ L18, C76 ~ C80, C148). When the TX signal s passed through the low-pass fier, matching voltage and mismatching voltage are detected by the D4 and 015. When the antenna impedance is 500, the detected voltage of D14 and D15 are minimum. But when the antenna impedance is not 500, the detected voltage becomes higher. The dotected voltage is passed through the power setting potentiometer (VR1), and the signal is ampitied by Q17, Q16 and Q14. The iransiitting power is controlled by the voltage of V1(1C2) and cotiector voltage of Q13. When the temperature of the unit goes high, the power down circuit (R104, THQ) prevents the device trom being damaged. ‘The PLL circuit uses PLL IC (1C201) equipped with builtin dual modulus prescater. ‘The PLL IC serial data is sent from CPU. The VCO output trequency divided by N is compared with reference frequency in the phrase comparator. ‘The reference kequoncy is obtained by X3 (12.8MHz), and its output is led tothe VCO unit The phase error of phase comparator is integrated to DC voltage by loop ter Circuit, and supplied to D201, D202 of varicap diode in VCO unit. The time constant ofthe active oop fiter (consisting of 202 and @210) is determined by €211, C212, R228, R210, Tho outputis passed through the lag titer (R213, £208}, and input to VCO unit. The circuit isthe Hartley oscillator circuit (Q201), and the signal is output passing through the buffer ampliier (2204). C247 is switched by D205 to vary the capaci- tance, and the oscilating frequency range is shifted.4) Terminal function of CPU No. | Name | PinName | vO ‘Description 4 = Laz Pull UP SEES te ae — bw pa pe ee ep es ties = [6 INT2 RE2 1 [Rotary encoder down input OFF ‘ON 2| 3S eee a = oe te enema —f re | 25 RST RST | | Reset signal input ‘at work ee eS eS, a z 35 P23 KEY2 | | Key 2SET OFF ON, fe)No. | Name | PinName | vO Description ¥ t wiz__[ Purp En KEYS | | [Key CALL ‘OFF ‘ON ° a7 | Pat Keys [1 [Keyavaa OFF ‘ON ° 36 [P20 Keys | | [KeySFUN OFF ‘ON ° ao | sa sot © | Segment 31 output Pulse 40 | sc 820 [0 | Segment 30 output Pulse a | = 820 | 0 [Segment 29 output Pulse a | S28 826 | 0 | Segment 28 output Puise [as | ser 827 | 0. | Segment 27 output Pulse a | S26 826 | 0 [Segment 26 output Puse | cn 825 | 0 | Seament 25 output Pulse 46 | sea 824 | 0 | Segment 24 output Pulse a7 | sa 823 | 0 [Segment 23 oupu Pulse 4 | sa 822 | 0 | Segment 22 output Pulse 49 | sav ‘sat (© [Segment 21 output Pulse so | seo 2a | 0 [Segment 20 output Pulse st] si9 819 [ © [Segment 19 output Pulse a] swe 818 | 0 [Segment 18 output Pulse 3 | si7 817 | © [Segment 17 ouput Pulse oa | sie 816 [0 [Segment 16 oviput Puise Eo 815 | © [Segment 15 output Pulse se | sia 814 [0 | Segment 14 output Puise | sv | sia 819 | 0 | Segment 19 output Pulse we | sa S12 [0 [Segment 12 ouput Pulse so | osu sit (© | Segment 11 output Pulse 60 | sto 810 | 0 | Segment 10 output Pulse er 88 s3 (© [Segment 9 output Pulse 2 88 88 (© [Segment & output Pulse 63, 7 7 0 [Segment 7 output Puse 64 86 56 (© | Segment 6 output Pulse 5 85 38 (© [Segment 5 output Pulse 6 4 Ey 0 [Segment 4 ouput Pulse 67 83 3 © [Seament 3 ouput Pulse 8 s 2 [Segment 2 output Pulse [69 si si (© [Segment # output Pulse 70 80 80 © | Segment 0 output Puise |No. | Name | PinName | vO Description " wiz | Pulue oe oO |_| | Power supply Dar [ar [ae t 7 | aves | ono | 1 [ono 7 | coms | cons [0 [LcDcommon 3 output Pulse 7% | come | come | 0 [Lod common2 ouput Pulse 7% | com | cow | 0 [ucdcammen) opt Pulse 7 [como | como | 0 |icd common 0 ouput Pulse 7 | ws vis [1 [LOD power supp input wm | we viz [1 [LCD power suppiy input 2 fw vir 1 [ted power soppy inputSEMICONDUCTOR DATA 1) AK2341 (XA0239) CTCSS Encoder/Decoder rey Pe ho) Funeton wn ft 7 aks coe FR Sigal put ee es = [mawo_[o 7RaP2 Opa 3 [ two [Oo "ANP Ouput m™Nno 43 a © [mn fT i Ao out = | Fxout [o Be Auio Owed es aby = [our fo "x A Osi 7 [woo Power Sippy (18 650) rxour 5 aot 8 [xn [ 1 | Casal Terminal (@.6064MH2) > @ | xouT-[0| — cyt Femina seh) ror Jo wks io|_ ste Graber Sal Baa 8 1 | SATA | Sorel Dale vO a ae wi] scx [7 ‘Serial Cock = 13 [oes [1 005 input xn fs Wo 14 [DETOUT | | Tone Dstecton Output (Ooace tow) is] WSs ‘Ground xour 9 6h 16 | OAEF_[ 1 | Tone Detection Lover adpst apa 17 | _TUNP | 7 | AX Tone Signal Reference input ‘STB qo 15F ie | TUN [7 RX Tone Sgn np 19 [| TuNO [O "AMPS Oviput spata C11 we 20_[RXTONE[O | Fx Teno Sonal Opa 21 [TXTONE | 0 [Tx Tone Sora! Outpt sox ye wh 2 [AGNOW | 1 [| Anaig Grond np 2a_[ KONO [| Arai Ground Out 32] Bas [1 as put Block Diagram 3 i BIAS AGND AGNOIN ‘TXTONE RXTONE UNO TUNN TUN DREF vss bETOUT bes 102) AN78LO5M (XA0238) 5V Voltage Regulator 2 Output Common Input AN78LO05M 3) LA4425A (XA0410) 5W Audio Power Amplifiers Test Circuit Q Veo [> ——5T,0 ts Laaa25 et Input 2.2uF put 2.2yf - [1As250 >> +¥——f 2| og 1000uF ia Voc =13.2V_RL=40 Po =5W Gain = 4508 12345 4) M5218FP (XA0068) Dual Low Noise 0 os tout er Supply Ps Operational Amplifiers oe i teeemaede Invern input 1 2 7 Output 2 Non imverting input 1 3 5. lnvoring input 2 Power Supply Minus. 4 [Non inverting input 212 5) M56760FP (XA0235) 540MHz Frequency Synthesizer Serial data input sits 16 Avec term! het = 55V tama (Glock input terminal ops 2 15 F5xin forfelarborgrat Reselinputterminal AST} 9 14 Favour Relaanc sar = Phase detector output Relerence Bias rer} 4 = Gt ts 706K terminal . put terinad 2 ‘on cked Low LocatOsetaorit NE 6 «Baa PD _—_—Pasetlactrode terminal fax -540MH2 a v Output port erminat SWI} 6 1 Faure pase iter input Output porterminal §=—s SW2 L] 7 10 Foro Geman (Ground trina Gn} 6 9 [SPN Phase svitch input terminal of phase comparator Function Tabie P/N input | “Phase [PD output High or Low [ Locked | HiZ High Lead | High High lag Low Low lead | Low Low Lag High Biock Diagram om yoo aw ise bie | fot Freon Heh Hts a er ae sri > | sin restorer00) Later son6) M67746 (XA0412) 144 ~ 148MHz 6OW RF Power Module = . Ratings ‘Symbot_[ Ratings [Unit g [soppy votage Vee. 7 v ss M67746 SG & Protatcurent vee 20 a & ‘ E [input power Pinas) [600 nw Output power Poiman) [__70 Ww Operation casetemperature | Totop) | sorortso | ale Storage temperature Taig | 4 rit0 | z fe Z9-2i-500 : 83 3? 3 se Be = ga 65 7) M68702H (XA0444) 150 ~ 175MHz 60W RF Power Module (TE2) : Ratings Symbol [Ratings [Unit Oo) F 5 & | Supniy votage ec. 7 v e M68702H & [Total curont vee 20 a E 34 = [inputpower Pinas) [| __ 600 rw Output power Powman) | __75 w Operation case temperature | Te(op) | 01010 | © ae Storage tomperalure ie ? Ho: yom E ro & gs 68 8) M68702L (XA0445) 135 ~ 160MHz 60W RF Power Module (TE1) a Na Ratings Symbol [Ratings | _ Unt 5 | Scppiy vonage vee 7 v g M68702L & [Totaicurent tee 20 a E A a ee oy a Outpxt power Powran |__75 Ww Operation case temperature | Tolop) | a0to«t10 | “O a Storage temperate Tag | ororito | © z e§ Zp-Zi-608 i ae # ze Be & ES 659) MC7808CT (XA0082) 8V Voltage Regulator Test Circuit 10) RH5VL32AA-T1 (XA0198) C-MOS Voltage Detector Equivalent Circuit 11) RH5VL45AA-T1 (XA0208) C-MOS Voltage Detector Equivalent Circuit 78L08 Output ——$—= Input Ground “Cc c2 e voo vss RHSVL32AA, our vod vss RHS5VL45AA_12) TK10930VTL (XA0223) Narrow Band FM IF IC ~ sozernis 08a, Q-O-$ Se ivy ae i Panett Tyee [Raton or le eee ate geseaae fie | tae a ream | sme be ad aes 2a ee see : cone fe = — ees =e aoe tee ee tS eee unter = eee aoe oP Snonenee fe pare par fern ee Seer ee Se ‘Sensitvty us 2 | 1s w Set 1516 13) wPC2710T (XA0449) RF Amplifier Parana | Simba Caen Fatnss_[_ Unt Sup vate ves a Crest oon tes 2 | na Power gan on =| 3s Satuatedoopctpower | Pts |__vee¥.1500WH, Pm 8m =95_| en aie Foe NF He a [Le Urper tomer (308) w ecu Releere g =1000F@ rooo | lation 1st | ves. 500m » | @ router es fun | ves 5000 spe Ospiteemniass [Rua | _Veosv, stow 2 [Le Gan taess Go| Veexsv 0 0Gra za | Test Circuit Tepiew ono [ 7] ovpu os eno [2] x [Bano sai o Input [7] 8] Veo 1k -Oour cs 14) 24L616B (XA0351) 16K bits CMOS Serial EEPROM Block Diagram AO 1 8 vec we XJ a ce & 7h w = 2. 4 2 ob 3 sot . = oueae veo he 55 sox Comets [—] 288 4 soe, oo (Cire [sen i ve | Saree ae I eas vee wssove as lies 7a come15) Transistor, Diode and LED Outline Drawings Top View Map SSKISIVI2 c c c c O° Cc c Mo || (8 az ]| bel |[ wo JI{E a is ror | aio we | eo =a] Eejece|sce| sce |sceluce|se| Be 2564089, DIATaYU | DTC114EU MCE UMS 1716) LCD LCD Pattern ENC, DEC.+- amg FAM WAN ANT ANT LANI TANI (2) Gt 8 LOW g LCD connection table No._| como | coma | comz [coms [No | como | coms | comz | coma 1 [como I 2 8a [eg |e z CoM 2 M ot ¥e_[ a 3 CORE [9a] sg 4 ‘cous 34 Ti Tm | —tn_[m- =| como 25 | — 7 Te a 3 oT i 3 7 25 5 a 7 i 7 te | tow | a7 | oF 6a ea 3 2 [2g 21 28 i sh SoS 9 za [2 | 2 | -susy | 29 [bec [a1 a ed 0 3 ae EJ 30 a a aa Tr A ae aa 12 a a) ag a 2 3. 3h [ana 3 |_4a_[| # | & [e@] 3 | eO] 3 30 a 5 a a 34 i zr | aa | a Ea OO Za Ba 16 ol a é | a 38 i ih iam 7 | 6a_[ | 6 | m@ [37 | Fnc |W Te 1d 3% 7 7 | 79 a 19_[ va] 7 ve | FULL I 20 | ae [ a ee [ad IEXPLODED VIEW 4) Bottom View Sorew Torque: Skgem svaoor 2) LCD Assemblyfe: Skgom crew Tora 3) Top and Front Views Screw Torqu888 888858 HHNGRSBSSBSSBISRRBATTLILSRIIGBB | seer] | wm] tere] =| 1] S| =| 5] te] | =| eo] scam] of 2 2] ove | = 2} fore] | S| 3] San Ol 3] om} | a] sn] fescue} exo] ng sora 2 wn =e se so a eel 2 = fe =| = foo vonavoree] ones] 8 a 21 Lsi SLuvdESPESEE BE | A 2 sal ose ce zegeveree H855558 sa8S 5358 sasas fal J i23 2 eauoriaa “\ i21onNg “2 BOrINO “4 aro 1 zatoivo "1 310%i¥0 7 sorta 4 0eI80 ‘war iesiore gee bes BESEDESEDSSASSRSSSSSagEO2E ET 8s TH cl We] B23 283 2R 552082 auoriuo "t aIbHiWO 'S Bortwa “Lum IHO sa] 9] 2} sso] te29 B20 105 leeADJUSTMENT 1) Required Test Equipment 1. Digital Multimeter 2. Regulated Power Supply ‘Supply voltage: 13.8VDC Current: 15A of more 3. Oscilloscope Measurable frequency: Audio Frequency 4, Spectrum Analyzer Measuring range: Up to 2GHz or more 5. Tracking Generator Output frequency: Up to 2GHz or more 6. Dummy Road Measurable frequency: Up to SOOMHz Impedance: 502 Power: 60W or more 7. Speaker Impedance: 8a 8. SSG Output frequency: Up to 1GHz Output level: -206B/0.1 pV to1200B/1V Modulation: AMFM 9, Transceiver Tester Up to SOOMHz a. Frequency Counter b. Power Meter Impedance: 02 Measuring range: GOW or more c. Audio Voltmeter Measurable frequency: 50Hz ~ 10kHz Sensitivity tmv ~ 10V 28 d. Distortion Meter Measurable frequency: Input level: Distortion level: e. Audio Generator Output frequency: Output impedance: 1. Linear Detector tkHz Up to 4006 1% ~ 100% kHz ~ 10kHz, 6002 2526 Test Equipment 1. All SSG output is indicated by EMF. 2. Audio Output level: 50mW~100mW at 80 3. Power supply voltage: 13.8V 3. Test frequency can be variable +1 00kHz 2) PLL Adjustment Measurement Adjustment tem Condition Specifications Equipment [Ferminal| Parts Method Y=148 00MM (7, E, TET) Refer req. Counter 1 45.00Mie (TE, TE1 weference Vy rez.oomms (vex) Fe COUMIET) any | acy bedi yrs Frequency Power Meter 162.00NtHz (12) ut i —_ T17aa0Nra Dgtal veo PD Tov ov le Multimeter L302 : 3) TX Adjustment 45,00MHez(T, €, TEN) OW i Power Meter : pat |terezcownic res) | COMME | awe | vrs | Sot fe 40.5A or below (T, High Tx _ ; 85A orbelow (TE12) Tow | 146.002 CE, TEN) {162.00MH2 (TE2) Re ssw 55205W Power Low 1x e146.00MH2 (ETEN | Linear Det 62.00MHz (TE2) | Oscilloscope Deviat vera] az7kHeiDEV + V ovation |e ane Teal 4.7kH2 4 O.2KH2IDE AG: tki4z 40mV emt AG Mic Gain | AG: tkHz 4m emt vrs | aokHaDev | s.0KHe + 02kH/DEV 7-145 00MAe (ETEN) 1 162.00MH cress ooMHz (TE2) Tone [LOW TX Check 1H Tone le OFF ed 0.6~1.1KH/0EV TONE SW: ENC oa.sHz Tone | rast oN 17504 oh an 4 eck 25 ~3.9KHH/DEV4) RX Adjustment Measurement ‘Adjustment tem Condition Specifications Equipment ]Terminal] Pars Method 144,002 (TE) 356 Tur the col '37.00MHz (TE) | SINAD Meter ee hae Sensitivity |{-150.00MH2 (TE2) | Osclioscope | sm |tr-ts]‘*'"- : in order. Adjust the $86 OUT: -10081 (o2vibev) peapatnaan tkHz 3.5kH2/Dev Level Meter omen 44 00M (T, E) 37.00MHe (TE1) IAD i $50.00MHez (TE2) Check - peed - $8G OUT: -8.548 tkHz 3.5kHt/Dev 00MHE (T, E, TEN) i Set tothe point wher SSG OUT: 18.008, Meter pe Mod: OFF be 886 OFF Check Does not light 1=145.00MAz (7, ETE) Set tothe threshold sat ives {= 162.000H2 (TE) ol eae Busy OFF §8@ OUT: -12d8H Busy . = SQL L mode Mod: OFF ae Busy $86 OFF ped Check Busy OFF at5) Adjustment Points1) Main Unit Side A2) Main Unit Side B3) CPU Unit Side A 4) CPU Unit Side B5) VCO Unit Side A 2029 Rees. cees Rese 6) VCO Unit Side B 327) Eu-20U (CTCSS Unit:Option) 33BLOCK DIAGRAM LINA NIVW1) Main Unit TE 38 tf 28 Yatesunaba2) Main Unit TE1/TE2 Ce ie atvsinabir®3) CPU Unit4) VCO Unit t Sm 7 i ver | cata | c2a7 100° Ter | 150° P P ° Pp Tez | 120° av | 200 Sa mye Leyte TE bevel eh oo Ste wees] # BF acu5) EJ-20U(CTCSS Unit: Option) 41ALINCO, INC. Head office: “TWIN 21" MID Tower Building 25F 1-61, 2-Chome, Shiromi, Chuo-ku, Osaka 540-8580, Japan Phone: 06-6946-8150 Fax: 06-6946-8175, E-mail: export@alinco.co.jp U.S.A: 438 Amapola Avenue, Unit 130, Torrance, CA 90501-6201, U.S.A. Phone: 310-618-8616 Fax: 310-618-8758 hittp://www.alinco.com/ Germany: Eschborner Landstrasse 55, 60489 Frankfurt am Main, Germany Phone: 069-786018 Fax: 069-789-60766. http://www.alinco.de/ Dealer/Distributor {© Copyright 2000 Anco, ne. Osaka pan Pretedindapan PMoosa8