6 GHz to 18 GHz, Front-End IC

Data Sheet ADTR1107

FEATURES FUNCTIONAL BLOCK DIAGRAM
VDD_LNA VGG_LNA VSS_SW CTRL_SW VDD_SW
Operates from 6 GHz to 18 GHz
25 dBm typical transmit state PSAT
22 dB typical transmit state small signal gain RX_OUT
18 dB typical receive state small signal gain
2.5 dB typical receive state noise figure ADTR1107 ANT

Coupled power amplifier output for power detection

TX_IN
APPLICATIONS

22146-001
Phased array antenna
VGG_PA VDD_PA CPLR_OUT
Military radar
Figure 1.
Weather radar
Communication links
Electronic warfare

GENERAL DESCRIPTION
The ADTR1107 is a compact, 6 GHz to 18 GHz, front-end IC
with an integrated power amplifier, low noise amplifier (LNA),
and a reflective single-pole double-throw (SPDT) switch. These
integrated features make the device ideal for phased array antenna
and radar applications. The front-end IC offers 25 dBm of
saturated output power (PSAT) and 22 dB small signal gain in
transmit state, and 18 dB small signal gain and 2.5 dB noise
figure in receive state. The device has a directional coupler for
power detection. The input/outputs (I/Os) are internally matched
to 50 Ω. The ADTR1107 is supplied in a 5 mm × 5 mm,
24-terminal, land grid array (LGA) package.

Rev. A Document Feedback

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ADTR1107 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1  Transmit State................................................................................9 
Applications ...................................................................................... 1  Receive State................................................................................ 16 
Functional Block Diagram .............................................................. 1  Theory of Operation ...................................................................... 23 
General Description ......................................................................... 1  Applications Information ............................................................. 24 
Revision History ............................................................................... 2  Recommended Bias Sequencing .............................................. 24 
Specifications .................................................................................... 3  Typical Application Circuit ...................................................... 25 
Absolute Maximum Ratings ........................................................... 6  Interfacing the ADTR1107 to the ADAR1000 X Band and KU
Thermal Resistance ...................................................................... 6  Band Beamformer............................................................................ 26 

ESD Caution.................................................................................. 6  Outline Dimensions ....................................................................... 28 

Pin Configuration and Function Descriptions ............................ 7  Ordering Guide .......................................................................... 28 

Interface Schematics .................................................................... 8 

Typical Performance Characteristics ............................................. 9 

REVISION HISTORY
4/2020—Rev. 0 to Rev. A
Changes to VDD_LNA Parameter, Table 4 ................................. 5

1/2020—Revision 0: Initial Version

Rev. A | Page 2 of 28
Data Sheet ADTR1107

SPECIFICATIONS
Transmit state, VDD_PA = 5 V, IDQ_PA = 220 mA, VDD_SW = 3.3 V, VSS_SW = −3.3 V, CTRL_SW = 0 V, receive state off (VDD_LNA = 0 V,
VGG_LNA = 0 V), TA = 25°C, unless otherwise noted.

Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
OVERALL FUNCTION
Frequency Range 6 14 GHz
TRANSMIT STATE
Small Signal Gain 19.5 21.5 dB TX_IN to ANT
Gain Flatness ±0.8 dB
Input Return Loss 13 dB TX_IN to ANT
Output Return Loss 15 dB TX_IN to ANT
Output 1 dB Compression (OP1dB) 21 23 dBm TX_IN to ANT
Saturated Output Power (PSAT) 25 dBm
Output Third-Order Intercept (OIP3) 31 dBm TX_IN to ANT output power (POUT) per tone = 8 dBm
Noise Figure 9 dB TX_IN to ANT
Coupling Factor 23.5 dB Coupling factor = ANT POUT − CPLR_OUT POUT
Isolation
TX_IN to RX_OUT 40 dB Receive state off
ANT to RX_OUT 64 dB Receive state off
RF Settling Time
0.1 dB 17 ns 50% CTRL_SW to 0.1 dB of final RF output
0.05 dB 22 ns 50% CTRL_SW to 0.05 dB of final RF output
Switching Speed
Rise and Fall Time tRISE, tFALL 2 ns 10% to 90% of RF output
Turn On and Turn Off Time tON, tOFF 10 ns 50% CTRL_SW to 90% of RF output
VDD_PA 3.3 5.0 5.5 V
Quiescent Current (IDQ_PA) 220 mA Adjust VGG_PA voltage between −1.75 V and
−0.25 V to achieve the desired IDQ_PA

Transmit state, VDD_PA = 5 V, IDQ_PA = 220 mA, VDD_SW = 3.3 V, VSS_SW = −3.3 V, CTRL_SW = 0 V, receive state off, TA = 25°C,
unless otherwise noted.

Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
OVERALL FUNCTION
Frequency Range 14 18 GHz
TRANSMIT STATE
Small Signal Gain 20 22 dB TX_IN to ANT
Gain Flatness ±0.6 dB
Input Return Loss 12 dB TX_IN to ANT
Output Return Loss 11 dB TX_IN to ANT
OP1dB 19 21.5 dBm TX_IN to ANT
PSAT 24 dBm TX_IN to ANT
OIP3 31.5 dBm TX_IN to ANT POUT per tone = 8 dBm
Noise Figure 6.5 dB TX_IN to ANT
Coupling Factor 18 dB Coupling factor = ANT POUT − CPLR_OUT POUT
Isolation
TX_IN to RX_OUT 39 dB Receive state off
ANT to RX_OUT 64 dB Receive state off

Rev. A | Page 3 of 28
ADTR1107 Data Sheet
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
RF Settling Time
0.1 dB 17 ns 50% CTRL_SW to 0.1 dB of final RF output
0.05 dB 22 ns 50% CTRL_SW to 0.05 dB of final RF output
Switching Speed
Rise and Fall Time tRISE, tFALL 2 ns 10% to 90% of RF output
Turn On and Turn Off Time tON, tOFF 10 ns 50% CTRL_SW to 90% of RF output
VDD_PA 3.3 5.0 5.5 V
IDQ_PA 220 mA Adjust VGG_PA voltage between −1.75 V and −0.25 V to
achieve the desired IDQ_PA

Receive state, self biased, VDD_LNA = 3.3 V, VGG_LNA = 0 V, VDD_SW = 3.3 V, VSS_SW = −3.3 V, CTRL_SW = 3.3 V, transmit state
off (VDD_PA = 0 V, VGG_PA = −1.75 V), TA = 25°C, unless otherwise noted.

Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
OVERALL FUNCTION
Frequency Range 6 14 GHz
RECEIVE STATE
Small Signal Gain 15.5 17.5 dB ANT to RX_OUT
Gain Flatness ±0.6 dB
Input Return Loss 13 dB ANT to RX_OUT
Output Return Loss 14 dB ANT to RX_OUT
OP1dB 12 14 dBm ANT to RX_OUT
PSAT 16 dBm
OIP3 26 dBm ANT to RX_OUT POUT per tone = 0 dBm
Noise Figure 2.5 dB ANT to RX_OUT
Isolation
ANT to TX_IN 32 dB Transmit state off
RX_OUT to TX_IN 48 dB Transmit state off
RF Settling Time
0.1 dB 17 ns 50% CTRL_SW to 0.1 dB of final RF output
0.05 dB 22 ns 50% CTRL_SW to 0.05 dB of final RF output
Switching Speed
Rise and Fall Time tRISE, tFALL 2 ns 10% to 90% of RF output
Turn On and Turn Off Time tON, tOFF 10 ns 50% CTRL_SW to 90% of RF output
VDD_LNA 2.0 3.3 3.6 V
IDQ_LNA 80 mA Self biased

Receive state, self biased, VDD_LNA = 3.3 V, VGG_LNA = 0 V, VDD_SW = 3.3 V, VSS_SW = −3.3 V, CTRL_SW = 3.3 V, transmit state
off, TA = 25°C, unless otherwise noted.

Table 4.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
OVERALL FUNCTION
Frequency Range 14 18 GHz
RECEIVE STATE
Small Signal Gain 16 18 dB ANT to RX_OUT
Gain Flatness ±0.9 dB
Input Return Loss 13 dB ANT to RX_OUT
Output Return Loss 18 dB ANT to RX_OUT
OP1dB 12 14 dBm ANT to RX_OUT
PSAT 16.5 dBm ANT to RX_OUT
Rev. A | Page 4 of 28
Data Sheet ADTR1107
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
OIP3 25.5 dBm ANT to RX_OUT POUT per tone = 0 dBm
Noise Figure 3 dB ANT to RX_OUT
Isolation
ANT to TX_IN 26 dB Transmit state off
RX_OUT to TX_IN 46 dB Transmit state off
RF Settling Time
0.1 dB 17 ns 50% CTRL_SW to 0.1 dB of final RF output
0.05 dB 22 ns 50% CTRL_SW to 0.05 dB of final RF output
Switching Speed
Rise and Fall Time tRISE, tFALL 2 ns 10% to 90% of RF output
Turn On and Turn Off Time tON, tOFF 10 ns 50% CTRL_SW to 90% of RF output
VDD_LNA 2.0 3.3 3.6 V
IDQ_LNA 80 mA Self biased

SPDT switch bias at VDD_SW = 3.3 V, VSS_SW = −3.3 V.

Table 5.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SUPPLY CURRENT VDD_SW and VSS_SW
Positive IDD_SW 14 μA
Negative ISS_SW 120 μA
DIGITAL CONTROL INPUTS CTRL_SW
Voltage
Low 0 0.8 V
High 1.2 3.3 V
Current (Low and High) <1 μA

Rev. A | Page 5 of 28
ADTR1107 Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 6. Stresses at or above those listed under Absolute Maximum
Parameter Rating Ratings may cause permanent damage to the product. This is a
Transmit State (PA On), Receive State Off stress rating only; functional operation of the product at these
VDD_PA 5.5 V or any other conditions above those indicated in the operational
VGG_PA −2 V to +0 V section of this specification is not implied. Operation beyond
Continuous Wave (CW) RF Input Power 20 dBm the maximum operating conditions for extended periods may
(RFIN) at TX_IN affect product reliability.
Continuous Power Dissipation (PDISS) 1.71 W
(TA = 85°C, Derate 18.98 mW/°C
THERMAL RESISTANCE
Above 85°C) Thermal performance is directly linked to printed circuit board
Receive State (LNA On), Transmit State Off (PCB) design and operating environment. Careful attention to
VDD_LNA 4V PCB thermal design is required.
VGG_LNA −2 V to +0.2 V θJC is the thermal resistance from the operating portion of the
CW RFIN at ANT 20 dBm device to the outside surface of the package (case) closest to the
PDISS (TA = 85°C, Derate 5.04 mW/°C 0.453 W device mounting area.
Above 85°C)
Transmit and Receive States Table 7. Thermal Resistance1
Output Load Voltage Standing Wave 7:1 Package Type θJC Transmit State θJC Receive State Unit
Ratio (VSWR) CC-24-8 52.7 198.4 °C/W
VDD_SW Range −0.3 V to +3.6 V
1
Thermal impedance simulated values are based on a JEDEC 2S2P thermal
VSS_SW Range −3.6 V to +0.3 V test board with 36 thermal vias. Refer to the JEDEC standard JESD51 for
VDD_CTRL Range −0.3 V to VDD + 0.3 V additional information.
Channel Temperature 175°C ESD CAUTION
Maximum Peak Reflow Temperature 260°C
(Moisture Sensitivity Level 3, MSL3)1
Storage Temperature Range −40°C to +125°C
Operating Temperature Range −40°C to +85°C
ESD Sensitivity (Human Body Model) Class 1B
(Passed ±500 V)
1
See the Ordering Guide section for more information.

Table 8. Signal Path Truth Table

State CTRL_SW RF Signal Path
Transmit Low TX_IN to ANT
Receive High ANT to RX_OUT

Rev. A | Page 6 of 28
Data Sheet ADTR1107

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VGG_LNA

CTRL_SW
VDD_LNA

VDD_SW
VSS_SW
GND
24
23
22
21
20
19
GND 1 18 GND
RX_OUT 2 17 ANT
GND 3 ADTR1107 16 GND
TOP VIEW
GND 4 (Not to Scale) 15 GND
TX_IN 5 14 GND
GND 6 13 GND

NIC 10
GND 11
12
7
8
9
VGG_PA

NIC

CPLR_OUT
VDD_PA
NOTES
1. NIC = NO INTERNAL CONNECTION.
SOLDER THESE PINS TO A LOW

22146-002
IMPEDANCE GROUND PLANE.
2. EXPOSED PAD. MUST BE CONNECTED
TO RF/DC GROUND.

Figure 2. Pin Configuration

Table 9. Pin Function Descriptions

Pin No. Mnemonic Description
1, 3, 4, 6, 11, 13 GND Ground. Solder these pins to a low impedance ground plane.
to 16, 18, 22
2 RX_OUT Receive Path Output. This pin is dc-coupled to ground and ac matched to 50 Ω.
5 TX_IN Transmit Path Input. This pin is dc-coupled to ground and ac matched to 50 Ω.
7 VGG_PA Power Amplifier Gate Bias. This pin is used to set the desired quiescent current of the amplifier.
8 VDD_PA Power Amplifier Drain Bias Voltage.
9, 10 NIC No Internal Connection. Solder these pins to a low impedance ground plane.
12 CPLR_OUT Transmit Path Coupled Port. This port is used in connection with a detector to monitor transmitted power.
17 ANT RF Common Port. This pin is dc-coupled to 0 V and ac matched to 50 Ω.
19 VDD_SW SPDT Switch Positive Bias Voltage.
20 CTRL_SW Switch Digital Control. This pin controls the state of the SPDT switch.
21 VSS_SW SPDT Switch Negative Bias Voltage.
23 VGG_LNA LNA Gate Voltage Bias. This pin is used to set the desired quiescent current of the LNA. If this pin is
supplied with 0 V or is connected to ground, the LNA runs in self bias mode at a typical current of 80 mA.
24 VDD_LNA LNA Drain Voltage Bias.
EPAD Exposed Pad. Must be connected to RF/dc ground.

Rev. A | Page 7 of 28
ADTR1107 Data Sheet
INTERFACE SCHEMATICS
GND VDD_LNA

22146-003

22146-008
Figure 3. GND Interface Schematic Figure 8. VDD_LNA Interface Schematic

22146-004
ANT

22146-009
VGG_LNA

Figure 4. ANT Interface Schematic Figure 9. VGG_LNA Interface Schematic

VDD_SW RX_OUT

22146-010
VDD_SW 8kΩ

CTRL_SW
22146-005

Figure 5. CTRL_SW and VDD_SW Interface Schematic Figure 10. RX_OUT Interface Schematic

VDD_PA TX_IN

22146-011
2.5kΩ
22146-006

Figure 6. VDD_PA Interface Schematic Figure 11. TX_IN Interface Schematic

22146-007

VGG_PA

Figure 7. VGG_PA Interface Schematic

Rev. A | Page 8 of 28
Data Sheet ADTR1107

TYPICAL PERFORMANCE CHARACTERISTICS

TRANSMIT STATE
30 26
BROADBAND GAIN AND RETURN LOSS (dB)

25
24
20

15 S11 (dB) 22
S21 (dB)
10 S22 (dB)

GAIN (dB)
20
5
18
0
+85°C
–5 16 +25°C
–40°C
–10
14
–15

–20 12

22146-012

22146-015
0 2 4 6 8 10 12 14 16 18 20 22 24 26 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz) FREQUENCY (GHz)

Figure 12. Broadband Gain and Return Loss vs. Frequency, 10 MHz to 26 GHz, Figure 15. Gain vs. Frequency for Various Temperatures, Transmit State, Path =
Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off
Receive State Off

26 26

24 24

22 22
GAIN (dB)

GAIN (dB)

20 20

18 18

5.0V
16 4.0V 16 250mA
3.3V 220mA
200mA
14 14 180mA
150mA

12 12
22146-013

22146-016
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz) FREQUENCY (GHz)

Figure 13. Gain vs. Frequency for Various VDD_PA, Transmit State, Path = Figure 16. Gain vs. Frequency for Various IDQ_PA, Transmit State, Path =
TX_IN to ANT, IDQ_PA = 220 mA, Receive State Off TX_IN to ANT, VDD_PA = 5 V, Receive State Off

0 0

+85°C +85°C
+25°C +25°C
–4 –40°C –4 –40°C
OUTPUT RETURN LOSS (dB)
INPUT RETURN LOSS (dB)

–8 –8

–12 –12

–16 –16

–20 –20
22146-014

22146-017

5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz) FREQUENCY (GHz)

Figure 14. Input Return Loss vs. Frequency for Various Temperatures, Transmit Figure 17. Output Return Loss vs. Frequency for Various Temperatures, Transmit
State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off

Rev. A | Page 9 of 28
ADTR1107 Data Sheet
0 36
34
–10 +85°C +85°C
+25°C 32 +25°C

CLRP_OUT COUPLING FACTOR (dB)

–40°C –40°C
–20 30
REVERSE ISOLATION (dB)

28
–30
26

–40 24
22
–50 20
18
–60
16
–70 14
12
–80
10
–90 8

22146-018

22146-021
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz) FREQUENCY (GHz)

Figure 18. Reverse Isolation vs. Frequency for Various Temperatures,Transmit Figure 21. CLPR_OUT Coupling Factor vs. Frequency for Various
State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off Temperatures, Transmit State, Coupling Factor = ANT POUT − CPLR_OUT POUT,
VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off

0 0

+85°C –10 +85°C

–10 +25°C +25°C
TX_IN TO RX_OUT ISOLATION (dB)

ANT TO RX_OUT ISOLATION (dB)

–40°C –40°C
–20
–20
–30

–30 –40

–40 –50

–60
–50
–70
–60
–80

–70 –90
22146-019

22146-022
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz) FREQUENCY (GHz)

Figure 19. TX_IN to RX_OUT Isolation vs. Frequency for Various Temperatures, Figure 22. ANT to RX_OUT Isolation vs. Frequency for Various Temperatures,
Transmit State, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off Transmit State, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off

16 16

+85°C 5.0V
14 +25°C 14 4.0V
–40°C 3.3V
NOISE FIGURE (dB)

NOISE FIGURE (dB)

12 12

10 10

8 8

6 6

4 4
22146-020

22146-023

6 7 8 9 10 11 12 13 14 15 16 17 18 6 7 8 9 10 11 12 13 14 15 16 17 18
FREQUENCY (GHz) FREQUENCY (GHz)

Figure 20. Noise Figure vs. Frequency for Various Temperatures, Transmit Figure 23. Noise Figure vs. Frequency for Various VDD_PA, Transmit State,
State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off Path = TX_IN to ANT, IDQ_PA = 220 mA, Receive State Off

Rev. A | Page 10 of 28
Data Sheet ADTR1107
16 28

26 +85°C
14 +25°C
250mA –40°C
220mA 24
200mA
180mA
NOISE FIGURE (dB)

12 150mA 22

OP1dB (dBm)
20
10
18

8 16

14
6
12

4 10

22146-024

22146-027
6 7 8 9 10 11 12 13 14 15 16 17 18 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz) FREQUENCY (GHz)

Figure 24. Noise Figure vs. Frequency for Various IDQ_PA, Transmit State , Path = Figure 27. OP1dB vs. Frequency for Various Temperatures,Transmit State, Path =
TX_IN to ANT, VDD_PA = 5 V, Receive State Off TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off

28 28

26 5.0V 26
4.0V
3.3V
24 24

22 22
OP1dB (dBm)

20 OP1dB (dBm) 20

18 18 250mA
220mA
16 16 200mA
180mA
150mA
14 14

12 12

10 10
22146-025

22146-028
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz) FREQUENCY (GHz)

Figure 25. OP1dB vs. Frequency for Various VDD_PA, Transmit State, Path = Figure 28. OP1dB vs. Frequency for Various IDQ_PA, Transmit State, Path =
TX_IN to ANT, IDQ_PA = 220 mA, Receive State Off TX_IN to ANT, VDD_PA = 5 V, Receive State Off

30 30

28 28

26 26

24 24

22 22
PSAT (dBm)

PSAT (dBm)

20 20

18 18 5.0V
4.0V
16 16 3.3V
+85°C
14 +25°C 14
–40°C
12 12

10 10
22146-026

22146-029

5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz) FREQUENCY (GHz)

Figure 26. PSAT vs. Frequency for Various Temperatures, Transmit State, Path = Figure 29. PSAT vs. Frequency for Various VDD_PA, Transmit State, Path =
TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off TX_IN to ANT, IDQ_PA = 220 mA, Receive State Off

Rev. A | Page 11 of 28
ADTR1107 Data Sheet
30 35

28 +85°C
30 +25°C
26 –40°C

24 25

22
PSAT (dBm)

20

PAE (%)
20
15
18 250mA
220mA
16 200mA
180mA 10
150mA
14
5
12

10 0

22146-030

22146-033
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz) FREQUENCY (GHz)

Figure 30. PSAT vs. Frequency for Various IDQ_PA,Transmit State, Path = TX_IN Figure 33. PAE vs. Frequency for Various Temperatures, Transmit State, Path =
to ANT, VDD_PA = 5 V, Receive State Off TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off, PAE
Measured at PSAT

35 35

5.0V
30 4.0V 30
3.3V

25 25

20 20
PAE (%)

PAE (%)

15 15 250mA
220mA
200mA
10 10 180mA
150mA

5 5

0 0
22146-031

22146-034
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz) FREQUENCY (GHz)

Figure 31. Power Added Efficiency (PAE) vs. Frequency for Various VDD_PA, Figure 34. PAE vs. Frequency for Various IDQ_PA, Transmit State, Path = TX_IN
Transmit State, Path = TX_IN to ANT, IDQ_PA = 220 mA, Receive State Off, PAE to ANT, VDD_PA = 5 V, Receive State Off, PAE Measured at PSAT
Measured at PSAT

30 330 30 450
POUT
GAIN
25 310 25 PAE 410
POUT (dBm), GAIN (dB), PAE (%)

POUT (dBm), GAIN (dB), PAE (%)

IDD_PA

20 290 20 370
POUT
IDD_PA (mA)

IDD_PA (mA)

GAIN
15 PAE 270 15 330
IDD_PA

10 250 10 290

5 230 5 250

0 210 0 210
22146-032

22146-035

–20 –16 –12 –8 –4 0 4 8 –20 –16 –12 –8 –4 0 4 8

INPUT POWER (dBm) INPUT POWER (dBm)

Figure 32. POUT, Gain, PAE and Power Amplifier Supply Current (IDD_PA) vs. Input Figure 35. POUT, Gain, PAE and IDD_PA vs. Input Power, 10 GHz, Transmit State,
Power, 6 GHz, Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off
220 mA, Receive State Off

Rev. A | Page 12 of 28
Data Sheet ADTR1107
30 450 30 330
POUT
GAIN
25 PAE 410 25 310
POUT (dBm), GAIN (dB), PAE (%)

POUT (dBm), GAIN (dB), PAE (%)

IDD_PA

20 370 20 POUT 290

GAIN

IDD_PA (mA)

IDD_PA (mA)
PAE
IDD_PA
15 330 15 270

10 290 10 250

5 250 5 230

0 210 0 210

22146-036

22146-039
–20 –15 –10 –5 0 5 10 –20 –15 –10 –5 0 5
INPUT POWER (dBm) INPUT POWER (dBm)

Figure 36. POUT, Gain, PAE and IDD_PA vs. Input Power, 14 GHz, Transmit State, Figure 39. POUT, Gain, PAE and IDD_PA vs. Input Power, 18 GHz, Transmit State,
Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off

2.0 40

35

1.5 MAX PDISS 30

POWER DISSIPATION (W)

25
OIP3 (dBm)
1.0 20

6GHz
8GHz 15
10GHz
12GHz +85°C
0.5 14GHz 10 +25°C
16GHz –40°C
18GHz
5

0 0
22146-037

22146-040
–20 –15 –10 –5 0 5 10 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
INPUT POWER (dBm) FREQUENCY (GHz)

Figure 37. Power Dissipation vs. Input Power at TA = 85°C, Transmit State, Figure 40. OIP3 vs. Frequency for Various Temperatures, POUT/Tone = 8 dBm,
Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA,
Receive State Off

40 40

35 35

30 30

25 25
OIP3 (dBm)

OIP3 (dBm)

20 20

5.0V 250mA
15 4.0V 15 220mA
3.3V 200mA
180mA
10 10 150mA

5 5

0 0
22146-038

22146-041

5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz) FREQUENCY (GHz)

Figure 38. OIP3 vs. Frequency for Various VDD_PA, POUT/Tone = 8 dBm, Figure 41. OIP3 vs. Frequency for Various IDQ_PA, POUT/Tone = 8 dBm,
Transmit State, Path = TX_IN to ANT, IDQ_PA = 220 mA, Receive State Off Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, Receive State Off

Rev. A | Page 13 of 28
ADTR1107 Data Sheet
40 70

35 60

30
50

25
OIP3 (dBm)

40

IM3 (dBc)
20
30 6GHz
8GHz
15 10GHz
8dBm 12GHz
6dBm 20 14GHz
10 16GHz
4dBm
18GHz
5 10

0 0

22146-042

22146-045
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 4 5 6 7 8
FREQUENCY (GHz) POUT/TONE (dBm)

Figure 42. OIP3 vs. Frequency for Various POUT/Tone, Transmit State, Path = Figure 45. Third-Order Intermodulation Distortion Relative to Carrier (IM3)
TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off vs. POUT/Tone, Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA =
220 mA, Receive State Off

70 70

65 65

60 60

55 55

50 50
OIP2 (dBm)
OIP2 (dBm)

45 45

40 40

35 35 5.0V
+85°C 4.0V
30 30 3.3V
+25°C
25 –40°C 25

20 20

15 15

10 10

22146-046
22146-043

6 7 8 9 10 11 12 13 14 15 16 17 18 6 7 8 9 10 11 12 13 14 15 16 17 18
FREQUENCY (GHz) FREQUENCY (GHz)

Figure 43. Output Second-Order Intercept (OIP2) vs. Frequency for Various Figure 46. OIP2 vs. Frequency for Various VDD_PA, POUT/Tone = 8 dBm,
Temperatures, POUT/Tone = 8 dBm, Transmit State, Path = TX_IN to ANT, Transmit State, Path = TX_IN to ANT, IDQ_PA = 220 mA, Receive State Off
VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off

70 70

65 65

60 60

55 55

50 50
OIP2 (dBm)
OIP2 (dBm)

45 45

40 40

35 250mA 35 8dBm
220mA 6dBm
30 200mA 30 4dBm
180mA
25 150mA 25

20 20

15 15

10 10
22146-047
22146-044

6 7 8 9 10 11 12 13 14 15 16 17 18 6 7 8 9 10 11 12 13 14 15 16 17 18
FREQUENCY (GHz) FREQUENCY (GHz)

Figure 44. OIP2 vs. Frequency for Various IDQ_PA, POUT/Tone = 8 dBm, Figure 47. OIP2 vs. Frequency for Various POUT/Tone, Transmit State, Path =
Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, Receive State Off TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off

Rev. A | Page 14 of 28
Data Sheet ADTR1107
400 0.2
6GHz
375 8GHz
10GHz 0.1
12GHz
350 14GHz
16GHz 0
18GHz
325

IGG_PA (mA)
IDD_PA (mA)

–0.1
300
–0.2
275
6GHz
8GHz
–0.3 10GHz
250
12GHz
14GHz
225 –0.4 16GHz
18GHz

200 –0.5

22146-048

22146-050
–20 –15 –10 –5 0 5 10 –20 –15 –10 –5 0 5 10
INPUT POWER (dBm) INPUT POWER (dBm)

Figure 48. IDD_PA vs. Input Power for Various Frequencies, Transmit State, Figure 50. Power Amplifier Gate Current (IGG_PA) vs. Input Power for Various
Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off Frequencies, Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA =
220 mA, Receive State Off

800

700

600

500
IDQ_PA (mA)

400

300

200

100

–100
22146-049

–1.75 –1.50 –1.25 –1.00 –0.75 –0.50 –0.25

VGG_PA (V)

Figure 49. IDQ_PA vs. VGG_PA, VDD_PA = 5 V, Transmit State, Path = TX_IN to
ANT, VDD_PA = 5 V, Receive State Off

Rev. A | Page 15 of 28
ADTR1107 Data Sheet
RECEIVE STATE
25 22
BROADBAND GAIN AND RETURN LOSS (dB)

20
20
15
S11 (dB) 18
10 S21 (dB)
S22 (dB)

GAIN (dB)
5 16

0 14

–5 +85°C
12 +25°C
–10 –40°C

10
–15

–20 8

22146-051

22146-054
0 2 4 6 8 10 12 14 16 18 20 22 24 26 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz) FREQUENCY (GHz)

Figure 51. Broadband Gain and Return Loss vs. Frequency, 10 MHz to 26 GHz, Figure 54. Gain vs. Frequency for Various Temperatures, Receive State,
Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V,
VGG_LNA = 0 V, Transmit State Off Transmit State Off

22 22

20 20

18 18
GAIN (dB)

GAIN (dB)

16 16

14 14
50mA
100mA
12 2.0V 12 85mA, SELF BIAS MODE
3.0V
3.3V
10 3.6V 10

8 8
22146-052

22146-055
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz) FREQUENCY (GHz)

Figure 52. Gain vs. Frequency for Various VDD_LNA, Receive State, Path = Figure 55. Gain vs. Frequency for Various IDQ_LNA, Receive State, Path =
ANT to RX_OUT, Self Biased Mode, VGG_LNA = 0 V, Transmit State Off ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, Controlled VGG_LNA,
Transmit State Off

0 0

+85°C +85°C
+25°C +25°C
–4 –40°C –4 –40°C
OUTPUT RETURN LOSS (dB)
INPUT RETURN LOSS (dB)

–8 –8

–12 –12

–16 –16

–20 –20
22146-053

22146-056

5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz) FREQUENCY (GHz)

Figure 53. Input Return Loss vs. Frequency for Various Temperatures, Figure 56. Output Return Loss vs. Frequency for Various Temperatures,
Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V,
VGG_LNA = 0 V, Transmit State Off VGG_LNA = 0 V, Transmit State Off

Rev. A | Page 16 of 28
Data Sheet ADTR1107
0 0

+85°C +85°C
+25°C –10 +25°C

RX_OUT TO TX_IN ISOLATION (dB)

–10 –40°C –40°C
REVERSE ISOLATION (dB)

–20
–20

–30
–30
–40

–40
–50

–50
–60

–60 –70

22146-057

22146-060
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz) FREQUENCY (GHz)

Figure 57. Reverse Isolation vs. Frequency for Various Temperatures, Receive Figure 60. RX_OUT to TX_IN Isolation vs. Frequency for Various
State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = Temperatures, Receive State, Path = ANT to RX_OUT, Self Biased Mode,
0 V, Transmit State Off VDD_LNA = 3.3 V, VGG_LNA = 0 V, Transmit State Off

0 6.0

+85°C 5.5
+25°C
–40°C 5.0
–10
ANT TO TX_IN ISOLATION (dB)

4.5

NOISE FIGURE (dB)

4.0
–20 3.5
3.0

–30 2.5
2.0
+85°C
1.5 +25°C
–40 –40°C
1.0
0.5
–50 0
22146-058

22146-061
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 4 6 8 10 12 14 16 18 20
FREQUENCY (GHz) FREQUENCY (GHz)

Figure 58. ANT to TX_IN Isolation vs. Frequency for Various Temperatures, Figure 61. Noise Figure vs. Frequency for Various Temperatures, Receive
Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V,
VGG_LNA = 0 V, Transmit State Off VGG_LNA = 0 V, Transmit State Off

6.0 6.0
5.5 5.5
5.0 5.0
4.5 4.5
NOISE FIGURE (dB)

NOISE FIGURE (dB)

4.0 4.0
3.5 3.5
3.0 3.0
2.5 2.5
2.0 2.0
2.0V
1.5 3.0V 1.5 50mA
3.3V 100mA
1.0 3.6V 1.0 85mA, SELF BIAS MODE
0.5 0.5
0 0
22146-059

22146-062

4 6 8 10 12 14 16 18 20 4 6 8 10 12 14 16 18 20
FREQUENCY (GHz) FREQUENCY (GHz)

Figure 59. Noise Figure vs. Frequency for Various VDD_LNA, Receive State, Figure 62. Noise Figure vs. Frequency for Various IDQ_LNA, Receive State,
Path = ANT to RX_OUT, Self Biased Mode, VGG_LNA = 0 V, Transmit State Off Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, Controlled
VGG_LNA, Transmit State Off

Rev. A | Page 17 of 28
ADTR1107 Data Sheet
22 22

20 20

18 18

16 16

14 14
OP1dB (dBm)

OP1dB (dBm)
12 12

10 10

8 8

6 +85°C 6 2.0V
+25°C 3.0V
4 –40°C 4 3.3V
3.6V
2 2

0 0

22146-063

22146-066
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz) FREQUENCY (GHz)

Figure 63. OP1dB vs. Frequency for Various Temperatures, Receive State, Path = Figure 66. OP1dB vs. Frequency for Various VDD_LNA, Receive State, Path =
ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V, ANT to RX_OUT, Self Biased Mode, VGG_LNA = 0 V, Transmit State Off
Transmit State Off

22 22

20 20

18 18

16 16

14 14
OP1dB (dBm)

PSAT (dBm)

12 12

10 50mA 10
100mA
8 85mA, SELF BIAS MODE 8

6 6 +85°C
+25°C
4 4 –40°C

2 2

0 0
22146-064

22146-067
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz) FREQUENCY (GHz)

Figure 64. OP1dB vs. Frequency for Various IDQ_LNA, Receive State, Path = Figure 67. PSAT vs. Frequency for Various Temperatures, Receive State, Path =
ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, Controlled VGG_LNA, ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V,
Transmit State Off Transmit State = Off

22 22

20 20

18 18

16 16

14 14
PSAT (dBm)

PSAT (dBm)

12 12

10 10 50mA
100mA
8 8 85mA, SELF BIAS MODE
6 2.0V 6
3.0V
4 3.3V 4
3.6V
2 2

0 0
22146-065

22146-068

5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz) FREQUENCY (GHz)

Figure 65. PSAT vs. Frequency for Various VDD_LNA, Receive State, Path = Figure 68. PSAT vs. Frequency for Various IDQ_LNA, Receive State, Path =
ANT to RX_OUT, Self Biased Mode, VGG_LNA = 0 V, Transmit State Off ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, Controlled VGG_LNA,
Transmit State Off

Rev. A | Page 18 of 28
Data Sheet ADTR1107
25 25

20 20

15 15
PAE (%)

PAE (%)
10 10

+85°C 2.0V
+25°C 3.0V
5 –40°C 5 3.3V
3.6V

0 0

22146-069

22146-072
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz) FREQUENCY (GHz)

Figure 69. PAE vs. Frequency for Various Temperatures, Receive State, Path = Figure 72. PAE vs. Frequency for Various VDD_LNA, Receive State, Path =
ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V, ANT to RX_OUT, Self Biased Mode, VGG_LNA = 0 V, Transmit State Off, PAE
Transmit State Off, PAE Measured at PSAT Measured at PSAT

25 25 110

20 105

POUT (dBm), GAIN (dB), PAE (%)

20

15 POUT 100
GAIN

IDD_LNA (mA)
15
PAE
PAE (%)

IDD_LNA
10 95

10
5 90
50mA
5 100mA
85mA, SELF BIAS MODE 0 85

0 –5 80
22146-070

22146-073
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 –20 –18 –16 –14 –12 –10 –8 –6 –4 –2 0 2
FREQUENCY (GHz) INPUT POWER (dBm)

Figure 70. PAE vs. Frequency for Various IDQ_LNA, Receive State, Path = Figure 73. POUT, Gain, PAE and IDD_LNA vs. Input Power, 6 GHz, Receive State,
ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, Controlled VGG_LNA, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA= 0 V,
Transmit State Off, PAE Measured at PSAT Transmit State Off

25 110 25 110

20 105 20 105
POUT (dBm), GAIN (dB), PAE (%)

POUT (dBm), GAIN (dB), PAE (%)

15 POUT 100 15 POUT 100

GAIN GAIN
IDD_LNA (mA)

PAE PAE IDD_LNA (mA)

IDD_LNA IDD_LNA
10 95 10 95

5 90 5 90

0 85 0 85

–5 80 –5 80
22146-071

22146-074

–20 –16 –12 –8 –4 0 4 –20 –15 –10 –5 0 5

INPUT POWER (dBm) INPUT POWER (dBm)

Figure 71. POUT, Gain, PAE and IDD_LNA vs. Input Power, 10 GHz, Receive State, Figure 74. POUT, Gain, PAE and IDD_LNA vs. Input Power, 14 GHz, Receive State,
Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA= 0 V, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA= 0 V,
Transmit State Off Transmit State Off

Rev. A | Page 19 of 28
ADTR1107 Data Sheet
25 110 0.5

20 105
MAX PDISS
POUT (dBm), GAIN (dB), PAE (%)

0.4

POWER DISSIPATION (W)

15 POUT 100
GAIN

IDD_LNA (mA)
0.3
PAE
IDD_LNA
10 95

0.2 6GHz
8GHz
5 90 10GHz
12GHz
14GHz
0.1 16GHz
0 85 18GHz

–5 80 0

22146-075

22146-078
–20 –18 –16 –14 –12 –10 –8 –6 –4 –2 0 2 –20 –18 –16 –14 –12 –10 –8 –6 –4 –2 0 2 4 6
INPUT POWER (dBm) INPUT POWER (dBm)

Figure 75. POUT, Gain, PAE and IDD_LNA vs. Input Power, 18 GHz, Receive State, Figure 78. Power Dissipation vs. Input Power at TA = 85°C, Receive State,
Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V,
Transmit State Off Transmit State Off

30 30

27 27

24 24
OIP3 (dBm)

OIP3 (dBm)

21 21

+85°C 2.0V
+25°C 3.0V
18 –40°C 18 3.3V
3.6V

15 15
22146-076

22146-079
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz) FREQUENCY (GHz)

Figure 76. OIP3 vs. Frequency for Various Temperatures, POUT/Tone = 0 dBm, Figure 79. OIP3 vs. Frequency for Various VDD_LNA, POUT/Tone = 0 dBm,
Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, Receive State, Path = ANT to RX_OUT, Self Biased Mode, VGG_LNA = 0 V,
VGG_LNA = 0 V, Transmit State Off Transmit State Off

30 30

25 25

20 20
OIP3 (dBm)

OIP3 (dBm)

15 15
50mA
100mA
85mA, SELF BIAS MODE 0dBm
10 10 5dBm

5 5

0 0
22146-077

22146-080

5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz) FREQUENCY (GHz)

Figure 77. OIP3 vs. Frequency for Various IDQ_LNA, POUT/Tone = 0 dBm, Figure 80. OIP3 vs. Frequency for Various POUT/Tone, Receive State, Path =
Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V,
Controlled VGG_LNA, Transmit State Off Transmit State Off

Rev. A | Page 20 of 28
Data Sheet ADTR1107
70 45

40
60
35
50
30

OIP2 (dBm)
40
IM3 (dBc)

25

30 6GHz 20
8GHz
10GHz
12GHz 15
20 14GHz +85°C
16GHz 10 +25°C
18GHz –40°C
10
5

0 0

22146-084
22146-081
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
POUT/TONE (dBm) FREQUENCY (GHz)

Figure 81. IM3 vs. POUT/Tone, Receive State, Path = ANT to RX_OUT, Self Figure 84. OIP2 vs. Frequency for Various Temperatures, POUT/Tone = 0 dBm,
Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V, Transmit State Off Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V,
VGG_LNA = 0 V, Transmit State Off

45 45

40 40

35 35

30 30
OIP2 (dBm)

OIP2 (dBm)
25 25

20 20 50mA
100mA
15 15 85mA, SELF BIAS MODE
2.0V
10 3.0V 10
3.3V
3.6V
5 5

0 0
22146-082

22146-085
6 7 8 9 10 11 12 13 14 15 16 17 18 6 7 8 9 10 11 12 13 14 15 16 17 18
FREQUENCY (GHz) FREQUENCY (GHz)

Figure 82. OIP2 vs. Frequency for Various VDD_LNA, POUT/Tone = 0 dBm, Figure 85. OIP2 vs. Frequency for Various IDQ_LNA, POUT/Tone = 0 dBm,
Receive State, Path = ANT to RX_OUT, Self Biased Mode, VGG_LNA = 0 V, Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V,
Transmit State Off Controlled VGG_LNA, Transmit State Off

45 90

40 6GHz
8GHz
10GHz
35 12GHz
85 14GHz
16GHz
30 18GHz
IDD_LNA (mA)
OIP2 (dBm)

25
80
0dBm
20 5dBm

15

75
10

0 70
22146-083

22146-086

6 7 8 9 10 11 12 13 14 15 16 17 18 –20 –15 –10 –5 0 5

FREQUENCY (GHz) INPUT POWER (dBm)

Figure 83. OIP2 vs. Frequency for Various POUT/Tone, Receive State, Path = Figure 86. IDD_LNA vs. Input Power for Various Frequencies, Receive State,
ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V,
Transmit State Off Transmit State Off

Rev. A | Page 21 of 28
ADTR1107 Data Sheet
120 120

100
100

80
80
IDQ_LNA (mA)

IDQ_LNA (mA)
60
60
40

40
20

20
0

–20 0

22146-088
22146-087
–1.5 –1.0 –0.5 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6
VGG_LNA (V) VDD_LNA (V)

Figure 87. IDQ_LNA vs. VGG_LNA, VDD_LNA = 3.3 V, Controlled VGG_LNA, Figure 88. IDQ_LNA vs. VDD_LNA, Self Biased Mode, VGG_LNA = 0 V, Receive
Receive State, Path = ANT to RX_OUT, Transmit State Off State, Path = ANT to RX_OUT, Transmit State Off

Rev. A | Page 22 of 28
Data Sheet
THEORY OF OPERATION
The ADTR1107 is a multichip transmit/receive module that
consists of an LNA, a medium power amplifier, and a silicon
SPDT reflective switch. The ANT antenna port is dc-coupled to
0 V and no dc block is required at this port when the RF line
potential is equal to 0 V. The switch has an integrated driver to
perform logic functions internally and provides a simplified
complementary metal-oxide semiconductor (CMOS)/low
voltage transistor to transistor logic (LVTTL)-compatible
control interface. The driver features a single digital control
input pin, CTRL_SW. The logic level applied to CTRL_SW
determines whether the ADTR1107 is in transmit state or
receive state (see Table 8).
Rev. A | Page 23 of 28
ADTR1107
The receive path contains a self biased LNA with optional bias
control using the VGG_LNA pin for bias adjustment. For self
biased operation, the VGG_LNA pin is set to 0 V or connected
to ground. The receive path output (RX_OUT) is dc-coupled to
ground through an 8 kΩ resistor. No dc block is required at this
port when the RF line potential is equal to 0 V.
The transmit path contains a power amplifier. The bias
current is set using VGG_PA. The transmit path input (TX_IN)
is dc-coupled to ground through a 2.5 kΩ resistor. No dc block
is required at this port when the RF line potential is equal to 0 V.
A directional coupler is incorporated into the ADTR1107 to
allow for monitoring of the transmit power level.
ADTR1107 Data Sheet

APPLICATIONS INFORMATION
The basic connections for operating the ADTR1107 are shown The recommended bias sequence during receive state power-up
in Figure 89. The power amplifier on the transmit path is biased is as follows:
with +5 V on the VDD_PA pin and a voltage from −1.75 V to 1. Connect all GND pins to ground.
−0.25 V is applied to the VGG_PA pin to achieve 220 mA 2. Set the VDD_SW pin to 3.3 V.
quiescent current. 3. Set the VSS_SW pin to −3.3 V.
The LNA on the receive path operates as either self biased or 4. Set the CTRL_SW pin to 3.3 V.
external biased mode. For self biased mode, apply 3.3 V to the 5. Set the VGG_PA pin to −1.75 V.
VDD_LNA pin and leave the VGG_LNA pin supplied with 0 V 6. Set the VDD_PA pin to 0 V.
or connected to ground. For external biased mode, apply +3.3 V 7. Set the VGG_LNA pin to 0 V.
to the VDD_LNA pin and adjust the VGG_LNA pin with a voltage 8. Set the VDD_LNA pin to 3.3 V.
range of −1.5 V to 0 V to achieve the desired IDQ_PA. 9. Apply the RF signal to the ANT pin.
The SPDT switch is biased with +3.3 V on the VDD_SW pin The recommended receive state bias sequence during
and −3.3 V on the VSS_SW pin. The CTRL_SW pin sets the power-down is as follows:
path state shown in Table 8. High logic state is set at 3.3 V and 1. Turn off the RF signal.
low logic state is set at 0 V. 2. Set the VDD_LNA pin to 0 V.
All required decoupling capacitors for the dc power supply 3. Set the CTRL_SW pin to 0 V.
lines are internal to the ADTR1107. 4. Set the VSS_SW pin to 0 V.
5. Set the VDD_SW pin to 0 V.
RECOMMENDED BIAS SEQUENCING
The recommended bias sequence during transmit state All measurements and data shown in this data sheet were taken
power-up is as follows: using the typical application circuit (see Figure 89) and biased
per the conditions in this section, unless otherwise noted. The
1. Connect all GND pins to ground. bias conditions described in this section are the operating
2. Set the VDD_SW pin to 3.3 V. points recommended to optimize the overall device performance.
3. Set the VSS_SW pin to −3.3 V. Operation using other bias conditions can result in performance
4. Set the CTRL_SW pin to 0 V. that differs from what is shown in the Typical Performance
5. Set the VGG_LNA pin to 0 V. Characteristics section. To obtain optimal performance while
6. Set the VDD_LNA pin to 0 V. not damaging the device, follow the recommended biasing
7. Set the VGG_PA pin to −1.75 V. sequences described in this section and adhere to the values
8. Set the VDD_PA pin to 5 V. shown in the Absolute Maximum Ratings section.
9. Increase the VGG_PA voltage to achieve the desired
IDQ_PA.
10. Apply the RF signal to the TX_IN pin.
The recommended transmit state bias sequence during
power-down is as follows:
1. Turn off the RF signal.
2. Decrease the VGG_PA voltage to −1.75 V.
3. Set the VDD_PA pin to 0 V.
4. Set the VSS_SW pin to 0 V.
5. Set the VDD_SW pin to 0 V.

Rev. A | Page 24 of 28
Data Sheet ADTR1107
TYPICAL APPLICATION CIRCUIT
+3.3V

0V/+3.3V
–3.3V

0V

+3.3V

PAD
24
23
22
21
20
19
VGG_LNA
GND
PAD

VSS_SW
CTRL_SW
VDD_LNA

VDD_SW
RECEIVE PATH OUTPUT
1 GND GND 18
2 RX_OUT ANT 17
3 GND GND 16
GND ADTR1107
4 15
GND
5 14
6 TX_IN GND 13

CPLR_OUT
GND GND

VGG_PA
VDD_PA
TRANSMIT PATH INPUT

GND
NIC
NIC
7
8
9
10
11
12
COUPLED
OUTPUT

GND

+5V

22146-090
–1.75V TO –0.25V

Figure 89. Typical Application Circuit

Rev. A | Page 25 of 28
ADTR1107 Data Sheet

INTERFACING THE ADTR1107 TO THE ADAR1000 X BAND AND KU BAND BEAMFORMER

ADTR1107 can be interfaced to the ADAR1000 X band and Ku
band quad beamformer IC, as shown in Figure 91. Note that
only a single channel of the ADAR1000 is shown in Figure 91
and additional components have been omitted for clarity. The
ADAR1000 provides multiple bias voltages and control signals,
resulting in a glueless interface and no need for any additional
control signals to the ADTR1107. The gate voltage for the
ADTR1107 power amplifier (VGG_PA) is provided by the
ADAR1000 PA_BIAS3 pin. One of four independent negative
gate voltages is needed for power amplifier gate biasing. Each
voltage is set by an 8-bit digital-to-analog converter (DAC)
with an output voltage range of 0 V to −4.8 V. The typical gate
voltage required to bias the ADTR1107 power amplifier is −1.1 V
(see Figure 49). This voltage can be asserted by the ADAR1000
The ADTR1107 CPLR_OUT coupler output can be tied back to
one of the four ADAR1000 RF detector inputs (DET1 to DET4).
These diode based RF detectors have an input range of −20 dBm to
+10 dBm. The coupling factor of the ADTR1107 directional
coupler ranges from 28 dB at 6 GHz to 18 dB at 18 GHz. At
12 GHz, with a coupling factor of 22 dB and a maximum power
amplifier output of 26 dBm, the coupled output power is a
maximum of 4 dBm. If the coupler output is connected directly
to the detector input, this connection provides a detection range of
24 dB. Figure 90 shows the relationship between the ADTR1107
output power and the ADC code of the ADAR1000 detector at
12 GHz. In this case, the ADTR1107 output power is swept to a
maximum level of approximately 22 dBm.
100

ADAR1000 RF DETECTOR OUTPUT CODE (Decimal)

TR input pin (rising edge enables the power amplifier) or by a
serial peripheral interface (SPI) write. Asserting the ADAR1000
TR pin switches the polarity of the ADAR1000 TR_SW_NEG pin
and TR_SW_POS pin. The TR_SW_POS pin can drive the 10
gates of up to four switches and can be used to control the
ADTR1107 SPDT switch.
While the ADTR1107 LNA gate voltage is self biased (the
VGG_LNA pin is connected to 0 V or grounded), the voltage 1

can also be controlled from the ADAR1000. In this case, there

is a single LNA_BIAS voltage (0 V to −4.8 V) controlled by an
8-bit DAC that can be used to bias four ADTR1107 devices
0.1
connected to each ADAR1000.

22146-091
5 7 9 11 13 15 17 19 21 23
ADTR1107 OUTPUT POWER (dBm)

Figure 90. ADAR1000 RF Detector Output Code vs. ADTR1107 Output Power
at 12 GHz

Rev. A | Page 26 of 28
Data Sheet ADTR1107
–5V +3.3V

PA_ON
AVDD1 AVDD3

TO PA ADAR1000
BIAS
LDO DET3
ADC
1.8V +5V
100kΩ VGG_PA
PA_BIAS3 VDD_PA CPLR_OUT
PA BIAS

TX_IN
TX3
ANT
ADTR1107
RX3 RX_OUT

LNA_BIAS 1 VGG_LNA
LNA BIAS
VDD_LNA VSS_SW VDD_SW

CTRL_SW
+3.3V –3.3V +3.3V

TR_SW_POS

SPI TO ADDITIONAL LNA

GATES
TR
TX_LOAD
SCLK

GND
RF_IO

SDIO

SDO
CSB

RX_LOAD
ADDR0
ADDR1

22146-092
1 LNA_BIAS IS A SINGLE PIN THAT CAN DRIVE UP TO FOUR GATES AND
IS AN OPTIONAL CONNECTION THAT CAN BE USED TO VARY THE BIAS
CURRENT OF THE ADTR1107.

Figure 91. Interfacing the ADTR1107 to the ADAR1000 X and Ku Band Beamformer, One Channel Shown

Rev. A | Page 27 of 28
ADTR1107 Data Sheet

OUTLINE DIMENSIONS
5.10 0.35
5.00 SQ 0.30
PIN 1 0.50
INDICATOR 4.90 0.25
AREA 0.45 PIN 1
INDICATOR
0.40 19 24 C 0.30 × 0.45°
18 1

3.25 REF EXPOSED

3.30 SQ
SQ PAD BSC

0.65
13 6

BSC 12 7

TOP VIEW BOTTOM VIEW

0.15
REF
1.13 0.70 REF FOR PROPER CONNECTION OF
MAX
SIDE VIEW THE EXPOSED PADS, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.356 SECTION OF THIS DATA SHEET.

03-26-2019-B
SEATING 0.326
PKG-005635

PLANE 0.296

Figure 92. 24-Terminal Land Grid Array [LGA]

(CC-24-8)
Dimensions shown in millimeters

ORDERING GUIDE
Model1 Temperature Range MSL Rating2 Package Description3 Package Option
ADTR1107ACCZ −40°C to +85°C 3 24-Terminal Land Grid Array [LGA] CC-24-8
ADTR1107ACCZ-R7 −40°C to +85°C 3 24-Terminal Land Grid Array [LGA] CC-24-8
ADTR1107-EVAL Evaluation Board
1
Z = RoHS Compliant Part.
2
See the Absolute Maximum Ratings section for additional information.
3
The lead finish of the ADTR1107ACCZ and the ADTR1107ACCZ-R7 is nickel palladium gold (NiPdAu).

©2020 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D22146-4/20(A)

Rev. A | Page 28 of 28