TECHNICAL ARTICLE TA83-3 Correlating The Charge-Transfer Characteristics Of Power MOSFETs With Switching Speed INTRODUCTION All power MOSFETS boast of high input impedances: yet when we are involved in high-speed switching, the power MOSFET — like the power bipolar transistor — is a ‘charge-coupled transistor. ‘There are, of course fundamental differences beween power MOSFETs and bipolar transistors we do not address. Our goal is co resolve the apparent correlation problem between the charge-transfer characteristies and the switch- ing speed of a power MOSFET Since the beginning of 1981 an inereasing number of power MOSFET vendors have added charge-transfer characteris- tic curves to their data sheets but they have failed to offer supporting information leaving the user to question the usefulness of these curves. In pursuing our goal we develop an appreciation for these data and we recognize some very interesting anomalies pertaining to power MOSFETs, Most importantly, we find that these curves offer us an effective tool to determine switching times. (CHARGE-TRANSFER CHARACTERISTIC Defined All power MOSFETs without zener gate protection, display 1 d input resistance of many megohms (typically > 1012 Ohms), When used as a switch the power required to oop it either ON or OFF is negligible, whereas with a Fd Oxner September 1983 power bipolar transistor, it is not, Coupled with this high: input resistance we have an equivalent input capacitance ‘consisting of © Gate t0 Source Capacitane Cys 1 to Drain Capacitance, Cy Since all commercially-available power MOSFET enhancement-mode, we must first raise the gate bias before conduction occurs. For an n-channel device this, means a positive bias whereas for a p-channel device we ‘would bias neyatively. By understanding the charge char: acteristics of a capacitor we can appreciate that as we prepare to turn-ON our normally-OFF power MOSFET, we ‘must first charge the equivalent input capacity’ to the gate bias potential necessary for conduction. If we knew the equivalent input capacity (Cjq) and the change in gate bias (gs) we could calculate the required energy; W= 1 2Cin aVgy? Wate-seconds 1) However, since it is not easy to determine the equivalent input eapacity—and well soon understand why=a herter method is to have the gate charge charaeteristies av a Function of Vy. The difference in charge hetween the OFF state andl the ON state will give us the energy needed 19 rnaake hw change W > 1 25Qg Ag Wateseeonds (2) si onixTA83-3 Itis this characteristic that we now see on power MOSFET. data sheets, Figure 1 shows the typical charge-transfer characteristies for a Silconix VN4000A, 400V, | Ohm MOS- POWER FET. gw eieaeay § 3 Vos -Ov i g 3, Lxost- ttt av, & & 3002 t 12 < Cake 7’ ‘300v] °° 5 t 1 SSE 400] 3 3 ryt 08 @ on, LOS 1, 8 200 4 8 @ 3 t coe 68 2 sol pr. 2 ed & Cry 2 L ped {scam ae ee meee Bo L og s 05 10 20 25 30 é @ CHARGE (ne) mgune'! Explained Figure 1 provides more information than is newded for our discussion, Since this igure offers us data for three supply voltages we need only familiarize ourselves with any one to, ‘understand them all. As we focus our attention on Figure. 2. where we have reproduced the 200V data, we find three. distinct regions. In region 1, the gate voltage, Vig, has risen to the level where drain current conduction commences (the beginning ofthe rise time where our drain voltage has dropped to .9Vps, whieh in our example is 180V), Ln region 2, turn-ON is nearly complete with the drain voltage falling to 0.1Vpg. In region 3 we witness the kate voltage eventually rising to its maximum drive potential and the drain voltage settling down to Vs.sr. The power MOSFET. has completed its turn-ON cycle. What we have witnessed as we have followed the gate ‘charge eyele is che initial turn-ON delay (region 1) followed. by the rise time (region 2). Before reaching region 2 we sew the gate voltage charging up the equivalent input capacity which in the pre-threshold region is mevely Cys; thus the. fairly constant slope. We can calculate Cys from the equation: Region 3 identifies two interesting phenomena; first, the eventual settling of the drain voltage to Vsqr (which we will examine in detail later), and, second, an abrupt Increase in the gate-source voltage as we overdrive the ate. Now, let us re-examine Region 2 where we see the rise time and that portion of Region 3 where the drain voltage set tes to Vga. The most obvious event that distinguishes Region 2 from Region 1 is the abrupt increase in equivalent input capacity (identified by the fattening of the charge- transfer curve). As our power MOSFET turns ON the Miller effect comes into play and our equivalent input capacity rises according to the equation: Cin = Cgs + Cya = Av) w We can also calculate this equivalent input capacity using the data available to us from Figure 2 = Og “Ve 8 10% | 05 10 15 20 25 Vps~ORAIN-SOURCE VOLTAGE (VOLTS) B (s110A) aDv110A aoUNOS-aLvo~S9A Tum-On Charge Transter Characteristics FIGURE 2 ‘We might. at first, dismiss Region'3 if we didn't question the ‘magnitude of the Miler effect evident from either Ea. (4) or (5), or from the excessively ong’ flat charge region so ‘obvious in either Figure 1 or 2. Since Eq, (4) appears to contain “explainable” wlements, we need to assure ou selves that we. indeed, can explain each element! Cys, Which we can derive fom B43) consists of both Geld capacity combined with depletion-dependent capacity (voltage dependent. Voltaue gain, Ay, may be derived on remains tbe expla racy. Cy SiliconixEFFECT OF GATS DRIVE ON FEEDBACK CAPACITY On every power MOSFET data sheet we can find three capacitances, Css, Crs and Coss, given within the Blectri- cal Characteristies table as well as plotted showing typical values (Fig). Since all three are depletion-dependent they are, therefore, voltage dependent. Since our interest is in understanding the effects upon Miller capacitance, we will limit our discussion to Crs, also known as the gate-drain feedback capacitance, Cy. But before we proceed further in this discussion we must first return to Figure 2 and carefully examine what appears as ‘the settling down of the drain voltage to Vs and ask why we see a settling at all? Why not see the drain voltage dropping immediately to Vga? By magnifying that portion of Figure 2 (Region 3), as we have done in Figure 4, we observe that a sharp knew in drain voltage occurs at approximately 10V with a slow 1000 decay to Vs Meanwhile, we observe that, simultaneously with the above, the charge slope quickly decays and ‘remains essentially flat until Vsqr is reached, whereupon the Miller capacitance is removed and the gate charges up to the gate supply voltage, Vac. It is no coincidence that this knee occurs at 10V, What has happened is that during turn-ON as our drain voltage drops, the voltage across Cgq has also dropped. Futher- more, once Vpp has passed V@g the polarity across Cyd raversos! If we examine Fig. 3 we see that Cygq rises drama- tically as Vpp decreases. What happens as VG approaches zero and reverses polarity is best seen in Fig. 5 where we see Cyd eventually saturating at approximately 1800 pF As Cgd rises the Miller effect climbs rapidly and once our rise-time has passed 0.1Vpp even though our voltage gain ears unity nevertheless the many-magnitude inerease in| Cyd Keeps the yate-chare characteristics nearly flat until, Vgar is finally reached, ¢ g g 3 8 z 3 é 3 8 5 8 2 3 2 z= 8 5 E100 a a 5 ¥ g 2 2 S eee ae : 3 é 0 feiss = gs * Cga — 3 5 Coss = Cas - £08 Cad E 8 Cas ~ Cod Lg 2 Crss=Cgd (PF) L g 8 5 o 1 10 100 20 5 10 3 & Vos VOLTS @ CHARGE TRANSFER (nC) FIGURE 2 Expanded View FIGURE 4 108 103 102 wot Cgq~GATE-TO-DRAIN CAPACITANCE (pF) 6 4 2 0 2 4 6 8 Vos DRAIN-TO-GATE VOLTAGE (VOLTS) FIGURE 5 e-€8VL Tur On wit late whe 7 te of Xb We Tw Ii weal cul fall | ae | et Siliconix= eee | sarge decay char SWITCHING ‘TIME CALCULATIONS ‘Turn-On Delay & Turn-On (Rise) Times On every power MOSFET data sheet we generally can find switching times referencing a switehing-time test circuit, Without further ado, we should confess that correlating such measurements is no easy task. However, we can calcu- late the switching times using the following equations Qa voc 7 acon) = Yar Ren eg — vay o Qe - Be Voo Nu te PE Rgen in eee 3 Ve -Vat Voo We where . Ren isthe source resistance in Ohms. Using Eas (7 and (S) with Figure 2 we ean compare calculated data Ultom Fig 2) swith measured data, taken from an average uf 10 devices CHARGE-DECAY CHARACTERISTICS A.careful study of the charge-decay characteristics for the ‘VN4O00A, shown in Figure 6, will reveal that aside from the ‘obvious shift of the charge-characteristic curves (where in igure 2 they begin at 0 nC and in Figure 6 at VG) we see the drain-source rise time (at turn-ON) shown in Figure 2. Again, we must be careful to note the effect of a negative drain-to-gate voltage. Where, in Figure 2, we observed a settling of the drain voltage in region 3, now the effect is quite the opposite: an apparent retarding of the turn-OFF cycle. Aside from this delay that we ean attribute to the Miller effect (Bq (4)], it appears that our calculation of {all-time goes awry for two possible reasons First, we have ‘a slightly longer drain voltage fall-time at turn-OFF than at ‘turn-ON arising from a combination of drain-source capac: ikanee, Coss, and package strays which, on turn-ON (Fig ure I and 2) only needs to discharge through the rpsion) ‘of the MOSFET but upon turn-OFF must now charge to the supply through the load resistance CORRELATING TURN-OFF (FALL) TIME, i eee | eee {Using Equation (10) with the data derived from both Pig ures 2 and 6, we can make the following eomparison tacony | 299 | ans | wiz | ass us comp ses | asss | tos | onus as mea | gale from | wale: trom ee sea Lt = ‘ Fi Fue 8 Vs = 2000 gen = 50-Obims | Ryn = 100 Ohms a 58 m2 46 We should note that our calculated data fall within the average measured data. Curn-Off Delay & Turn-Of€ (Pall) Times In is here where problems arise, Where we were able to caleulate both turn-ON delay (gion) and rise time (te) \with good precision, we discover that although we ean cal alate turn-OFF delay (tq; off) we find that our calculated {all-time (cp) to bein error ifwe use Bigure 2. Our equations, Noo Qs Uae ten 1n Vig «apy yen tn Vy nur dilemma arises te sitfers from the furn-OFF phenor hharge-transfer eharaeterrsties, sre unable te istinuist teristic. we the tuen-ON phenomenon on, and by using the wwe show an Fi litorence, What wee nee i. 300 200 100 Vgs~—GATE-SOURCE VOLTAGE (VOLTS) (s110A) apvL10A gouNOS-NIva SOA 10 15 20 25 30 (@ CHARGE (nc) ‘Turn-Off Charge Decay Characteristics FIGURE 5 e-esvlCONCLUSION Although we may never replace measured switching data with calculated data taken from such charge characteris- tics as represented here; nonetheless, the relative ease by which we can generate such data affords the designer quick access to what otherwise tends to be tedious and ‘ime consuming. Certainly a cursory examination of such charge curves will allow us the option of evaluating the switching times ofa variety of power MOSFETs without the expense in time and money to construct critical test circuits, However, these charge curves bring us a warning that we need to heed. Switching times, according to custom —as ‘well as we have done here—are measured between 0.9V. and 0.1V,. If as we have observed, a drawn out settling occurs wien our drain-to-gate voltage crosses zero to a negative value, we must wateh that we maintain V, suffi ciently high to preclude any possibility of having 0.1V. fall below the knee as we earlier witnessed in Figure 4, Other: ‘wise our turn-ON time will stretch out well beyond any. specified swit Material originally prepared for and presented at “Proceedings of Powercon 9", July 1982 Siliconix 2201 Laurelwood Road Santa Clara, CA 95088 (408) 988 8000" TW" 910 338-0227 iim ate anv cel daca Pron dah prenentavon ht ‘hey ae rom patent iningement eee