Acer TravelMate 7740 7740Z 1 Quanta ZYD - Rev3B

5 4 3 2 1
=<'6<67(0%/2&.',$*5$0
Channel A
64MB/128MB x 8
D
intel Channel B
P19, 20
D
<MCH Processor>
Arrandale(UMA) HDMI
Dual Channel DDR III ATI GPU
DDRIII-SODIMM1
800/1066/1333 MHZ
Clarksfield (Discrete) PCIEX16 LVDS
DDRIII-SODIMM2 IMC GFX Madison/Park M2
P14,15 2.5GT/s Madison LP/PRO 1GB CRT
rPGA 989
(37.5mm X 37.5mm) P16~P23
P4,5,6,7 X'TAL
27.0MHz
X'TAL FDI DMI
14.318MHz
*[Arrandale Only] DMI(x4)
SLG8LV595
FDI DMI INT_CRT *[Arrandale Only] CRT P24
CLK GEN CLK
P3 Display
SATA 0
INT_LVDS *[Arrandale Only] LVDS
C SATA - HDD P24 C
P29
SATA
INT_HDMI
SATA - ODD SATA 1 Level shift HDMI P25
P29
PCIE-6
PCI-E x1
USB-1 MINI CARD
USB Port X1 USB Ibex Peak-M USB-13
WLAN
P33
P28
PCH
USB-8
CCD
P24 P8, 9, 10, 11, 12, 13 PCIE-2
USB-4 USB-10
MINI CARD
Bluetooth Con. P28
P33 X'TAL
32.768KHz
AU6437-GBL USB-3/11/12 PCIE-1 AR8151

Cardreader X'TAL 25MHz
RJ45
B
P31
GIGA LAN P26
B
BATTERY RTC P27
USB Port X2 X'TAL

25MHz
P31 ISL88731A MAX8792ETD+T
DB Azalia SPI SPI ROM
IHDA Batery Charger P37 +VGPU_CORE P43
P8
LPC
RT8206B ISL62872
LPC 3V/5V P38 +VGPU_IO P44
ISL62882 ISL62881HRZ-T
CX20672-11Z NPCE781 CPU core P39 +VGFX_AXG P45
AUDIO CODEC EC
P30 P36 UP6111AQDD HPA00835RTER*2
+1.1V_VTT P40 +1.8V/+1V P46
Power Touch Pad

UP6111AQDD Discharger
Speaker INT. MIC +1.05V P41 P46
P30 P30 Board Con. Board Con.
A A
P33 P34
BOM Option Table RT8207A Thermal Protection
Dr-Bios.com
Reference Description +1.5V_SUS P42 P47
IV@ for UMA only SKU K/B Con. SPI FLASH HALL SENSOR Fan Driver
for Discrete Graphic only SKU MIC JACK HP
EV@
P30 P30
W25X16VSS1G (PWM Type)
SP@ special case component P34 P36 P24 P34 Quanta Computer Inc.
* do not stuff PROJECT : ZYD
Size Document Number Rev
3B
Block Diagram
Date: Tuesday, April 06, 2010 Sheet 1 of 50
5 4 3 2 1
1 2 3 4 5 6 7 8
GPU PWR CTRL Option 1 (Default/ VDDR3 before VDDC)

+3.3V VIN VIN +1.5V +1.5V_SUS +1.8V
VDDR3 +3V_D VDDC PG_GPUIO_EN VDDCI PG_1V_EN +1V (DP PLL PWR) PG_1.5V_EN VDDR1 +1.5V_GPU VDDR4 +1.8V_GPU BJT dGPU_PWROK
MAINON
MOS (AO3413) ISL6264 ISL62872 G9334ADJ & MOS MOS (AO4710) MOS (AO6402)
P21 P42 P43 P45 P41 P45 P21
A
+3_D (0.5A) +VGPU_CORE (20A) +VGPU_IO (4.5A) +1V (3A) +1.5V_GPU (10A) +1.8V_GPU (3A) A
GPU PWR CTRL Option 2 (VDDR3 after VDDR1)

VIN VIN +1.5V +1.5V_SUS +3.3V +1.8V
VDDC PG_GPUIO_EN VDDCI PG_1V_EN +1V (DP PLL PWR) PG_1.5V_EN VDDR1 +1.5V_GPU VDDR3 +1.5V_GPU VDDR4 +1.8V_GPU BJT dGPU_PWROK
MAINON
ISL6264 ISL62872 G9334ADJ & MOS MOS (AO4710) MOS (AO3413) MOS (AO6402)
P42 P43 P45 P41 P21 P45 P21
+VGPU_CORE (20A) +VGPU_IO (4.5A) +1V (3A) +1.5V_GPU (10A) +3_D (0.5A) +1.8V_GPU (3A)
Power States Thermal Follow Chart

CONTROL
POWER PLANE VOLTAGE DESCRIPTION ACTIVE IN
SIGNAL
VIN +10V~+19V MAIN POWER ALWAYS ALWAYS
B B
+VCCRTC +3V~+3.3V RTC POWER ALWAYS ALWAYS NTC

+3VPCU +3.3V EC POWER ALWAYS ALWAYS Thermal
Protection
+5VPCU +5V CHARGE POWER ALWAYS ALWAYS
+15V +15V CHARGE PUMP POWER ALWAYS ALWAYS
+3V_S5 +3.3V LAN/BT/PCH S5_ON S0-S5

CPU H_ORICHOT# PM_THRMTRIP# SYS_SHDN# 3V/5 V
+5V_S5 +5V USB POWER S5_ON S0-S5
CORE PWR H/W Throttling
CPU WIRE-AND SYS PWR
+5V +5V HDD/ODD/Codec/TP/CRT MAINON S0
+3V +3.3V CLK GEN/PCH/GPU/LVDS/Mini card/Codec/card MAINON

Reader S0
+1.5V_SUS +1.5V CPU/SODIMM CORE POWER SUSON S0-S3 SML1ALERT#
+0.75V_DDR_VTT +0.75V SODIMM Termination POWER MAINON S0 PCH FAN Driver FAN
+VGFX_AXG variation Internal GPU POWER GFX_ON S0
+1.8V +1.8V CPU/PCH/Braidwood POWER MAINON S0 SM-Bus

C C
+1.5V +1.5V MINI CARD/NEW CARD POWER MAINON S0
+1.1V_VTT +1.05V or +1.1V CPU VTT POWER MAINON S0 EC

CPUFAN#
+1.05V +1.05V PCH CORE POWER MAINON S0
+VCC_CORE variation CPU CORE POWER VRON S0
LCDVCC +3.3V LCD POWER LVDS_VDDEN S0

Discrete enable
+5V_GPU +5V SWITCHABLE PWM IC POWER dGPU_PWR_EN#
+3V_D +3.3V I/O POWER for 3.3V pins dGPU_VRON Discrete enable
+VGPU_CORE +0.9V~+1.1V GPU CORE POWER +3V_D Discrete enable
+VGPU_IO +0.9V~+1.1V GPU I/O POWER PG_GPUIO_EN Discrete enable
+1V +1V DP/PEG POWER PG_1V_EN Discrete enable
+1.5V_GPU +1.5V VRAM CORE POWER PG_1.5V_EN Discrete enable
+1.8V_GPU +1.8V GPU_CRE/LVDS/PLL POWER +1.5V_GPU Discrete enable
D D
1 2
Dr-Bios.com
3 4 5 6
Size
Date:
7
Document Number
Quanta Computer Inc.
PROJECT : ZYD
PWR Status & GPU PWR CRL & THRM
Tuesday, April 06, 2010 Sheet
8
2 of 50
Rev
3B
5 4 3 2 1
D D
150mA(30mil)
+1.5V L53 595@PBY160808T-181Y-N/2A/180ohm_6 +1.5V_CLK 80mA(20mil)
+VDDIO_CLK L51 PBY160808T/2A/180ohm_6+1.05V
C692 C693 C714
C760 C689 C700 C688 C695
*1u/10V_4.1u/16V_4 .1u/16V_4 .1u/16V_4
R549 .1u/16V_4 .1u/16V_4 10u/Y5V_8 10u/Y5V_8
*585@0_6 U27
Place each 0.1uF cap as close as
modify 1202 1 VDD_DOT possible to each VDD IO pin. Place
17 VDD_SRC VDD_SRC_I/O 15 the 10uF caps on the VDD_IO plane.
24 VDD_CPU VDD_CPU_I/O 18
20mil 5 VDD_27
+3V L56 BLM18AG601SN1D/200mA/600ohm_6 +3V_CLK 29 3
VDD_REF DOT_96 CLK_BUF_DREFCLK 10
DOT_96# 4 CLK_BUF_DREFCLK# 10
CLK_SDATA 31
C726 C431 C718 CLK_SCLK SDA R257 *EV@33_4
32 SCL 27M 6 27M_CLK 17
7 CLK_VGA_27M_SS R542 *EV@33_4 CLK_27M_SS 17
4.7u/10V_8 .1u/16V_4 .1u/16V_4 27M_SS C715 *EV@10p/50V_4
R545 33_4 CPU_SEL 30 10
10 CLK_ICH_14M REF_0/CPU_SEL SRC_1/SATA CLK_BUF_PCIE_3GPLL 10
SRC_1#/SATA# 11 CLK_BUF_PCIE_3GPLL# 10
C701 33p/50V_4 13
SRC_2 CLK_BUF_DREFSSCLK 10
C SRC_2# 14 CLK_BUF_DREFSSCLK# 10 C
XTAL_IN 28
Y4 XTAL_IN +3V
14.318MHz XTAL_OUT 27 16 R525 10K_4
XTAL_OUT *CPU_STOP#
C697 33p/50V_4 2 20
VSS_DOT CPU_1 TP51
8 VSS_27 CPU_1# 19 TP50
9 VSS_SATA CPU_0 23 CLK_BUF_BCLK 10
12 VSS_SRC CPU_0# 22 CLK_BUF_BCLK# 10
21 VSS_CPU
IDT: AL003197001 (ICS9LVS3197AKLFT) 26 25 CK_PWRGD_R
VSS_REF CKPWRGD/PD#
33
Realtek: AL000890000 (RTM890N-632-GRT) GND
Silego: AL000595000 (SLG8LV595VTR)
SLG8LV595V
+3V
CPU_CLK select SMBus
B
+1.05V
CLK Enable +3V B
R279
R522
2
R544 2.2K_4 1K/F_4
*10K_4
3 1 CLK_SDATA CLK_SDATA 14,15,28
10 ICH_SMBDATA
CK_PWRGD_R
CPU_SEL Q21
3
2N7002K Q29
2N7002K
R550 C729
+3V 39 VR_PWRGD_CK505# 2 R521
10K_4 *10p/50V/COG_4 100K/F_4
1
R278
2
2.2K_4
0 1
3 1 CLK_SCLK CLK_SCLK 14,15,28
10 ICH_SMBCLK
A CPU_SEL CPU0/1=133MHz CPU0/1=100MHz Q20 A
2N7002K
(default)

PROJECT : ZYD
3B
Clock Generator
Dr-Bios.com
5 4 3 2 1
5 4 3 2 1
AUBURNDALE/CLARKSFIELD PROCESSOR (DMI,PEG,FDI) AUBURNDALE/CLARKSFIELD PROCESSOR (CLK,MISC,JTAG)
Processor Compensation Signals

U26A U26B
B26 R444 49.9/F_4 R476 20/F_4 H_COMP3 AT23
PEG_ICOMPI COMP3
A26 A16 CLK_CPU_BCLK 11
PEG_ICOMPO BCLK
MISC
A24 B27 R475 20/F_4 H_COMP2 AT24 B16 CLK_CPU_BCLK# 11
8 DMI_TXN0 DMI_RX#[0] PEG_RCOMPO COMP2 BCLK#
C23 A25 R445 750/F_4
8 DMI_TXN1 DMI_RX#[1] PEG_RBIAS R124 49.9/F_4 H_COMP1 T55
CLOCKS
8 DMI_TXN2 B22 PEG_RXN[0..15] 16 G16 AR30
DMI_RX#[2] PEG_RXN0 COMP1 BCLK_ITP T59
8 DMI_TXN3 A21 K35 AT30
D DMI_RX#[3] PEG_RX#[0] PEG_RXN1 R473 49.9/F_4 H_COMP0 BCLK_ITP# D
J34 AT26
PEG_RX#[1] PEG_RXN2 COMP0
8 DMI_TXP0 B24
DMI_RX[0] PEG_RX#[2]
J33
PEG_RXN3 PEG_CLK
E16 CLK_PCIE_3GPLL 10 Amos 1013
8 DMI_TXP1 D23 G35 D16 CLK_PCIE_3GPLL# 10
DMI_RX[1] PEG_RX#[3] PEG_CLK#
DMI
B23 G32 PEG_RXN4 T63 AH24
8 DMI_TXP2 DMI_RX[2] PEG_RX#[4] SKTOCC#
A22 F34 PEG_RXN5 A18 DPLL_REF_SSCLK_R R438 IV@0_4 DPLL_REF_SSCLK 10
8 DMI_TXP3 DMI_RX[3] PEG_RX#[5] DPLL_REF_SSCLK
F31 PEG_RXN6 A17 DPLL_REF_SSCLK#_R R440 IV@0_4 DPLL_REF_SSCLK# 10
PEG_RX#[6] PEG_RXN7 H_CATERR# DPLL_REF_SSCLK# R442 EV@0_4
D24 D35 AK14
8 DMI_RXN0 DMI_TX#[0] PEG_RX#[7] Use reverse type CATERR#
THERMAL
G24 E33 PEG_RXN8 R443 EV@0_4
8 DMI_RXN1 DMI_TX#[1] PEG_RX#[8]
F23 C33 PEG_RXN9 Layout Note: Place
8
8
DMI_RXN2
DMI_RXN3 H23
DMI_TX#[2]
DMI_TX#[3]
PEG_RX#[9]
PEG_RX#[10]
D32 PEG_RXN10
PEG_RXN11
(at GPU side) SM_DRAMRST#
F6 CPU_DDR3_DRAMRST# CPU_DDR3_DRAMRST# 35 these resistors
B32 11 H_PECI AT15
PEG_RX#[11] PEG_RXN12 PECI SM_RCOMP_0 R156 100/F_4 R127 near Processor
*100K_4
8 DMI_RXP0 D25 C31 AL1
DMI_TX[0] PEG_RX#[12] PEG_RXN13 SM_RCOMP[0] SM_RCOMP_1 R158 24.9/F_4
8 DMI_RXP1 F24 B28 AM1
DMI_TX[1] PEG_RX#[13] PEG_RXN14 SM_RCOMP[1] SM_RCOMP_2 R160 130/F_4
8 DMI_RXP2 E23 B30 AN1
DMI_TX[2] PEG_RX#[14] PEG_RXN15 H_PROCHOT# SM_RCOMP[2]
8 DMI_RXP3 G23
DMI_TX[3] PEG_RX#[15]
A31 39 H_PROCHOT# AN26
PROCHOT# 1017 modify
PEG_RXP[0..15] 16 AN15 PM_EXTTS#0 14
PM_EXT_TS#[0]
DDR3
MISC
J35 PEG_RXP0 AP15 R174 10K_4
PEG_RX[0] PEG_RXP1 PM_EXT_TS#[1] R165 10K_4
H34 +1.1V_VTT
PEG_RX[1] PEG_RXP2
H33 11 PM_THRMTRIP# AK15 PM_EXTTS#1 15
PEG_RX[2] PEG_RXP3 THERMTRIP#
8 FDI_TXN0 E22 F35
FDI_TX#[0] PEG_RX[3] PEG_RXP4
8 FDI_TXN1 D21 G33
FDI_TX#[1] PEG_RX[4] PEG_RXP5 XDP_PRDY# T52
8 FDI_TXN2 D19 E34 AT28
FDI_TX#[2] PEG_RX[5] PEG_RXP6 PRDY# XDP_PREQ# T87
8 FDI_TXN3 D18 F32 AP27
FDI_TX#[3] PEG_RX[6] PEG_RXP7 PREQ#
8 FDI_TXN4 G21 D34
FDI_TX#[4] PEG_RX[7] PEG_RXP8 XDP_TCLK T56
8 FDI_TXN5 E19 F33 AN28
FDI_TX#[5] PEG_RX[8] TCK
PCI EXPRESS -- GRAPHICS
F21 B33 PEG_RXP9 H_CPURST# AP26 AP28 XDP_TMS T60
8 FDI_TXN6 FDI_TX#[6] PEG_RX[9] RESET_OBS# TMS
Intel(R) FDI
PWR MANAGEMENT
G18 D31 PEG_RXP10 AT27 XDP_TRST# T88
8 FDI_TXN7 FDI_TX#[7] PEG_RX[10] TRST#
PEG_RXP11
JTAG & BPM

A32
PEG_RX[11] PEG_RXP12 XDP_TDI_R T91
C30 8 PM_SYNC AL15 AT29
PEG_RX[12] PEG_RXP13 PM_SYNC TDI XDP_TDO_R T89
8 FDI_TXP0 D22 A28 AR27
FDI_TX[0] PEG_RX[13] PEG_RXP14 TDO XDP_TDI_M T90
8 FDI_TXP1 C21 B29 PEG_TXN[0..15] 16 AR29
FDI_TX[1] PEG_RX[14] PEG_RXP15 TDI_M XDP_TDO_M T92
8 FDI_TXP2 D20 A30 AN14 AP29
FDI_TX[2] PEG_RX[15] VCCPWRGOOD_1 TDO_M
8 FDI_TXP3 C18
FDI_TX[3] CPEG_TXN0 C279 EV@0.1u/10V_4_X7R PEG_TXN0 H_DBR#_R R176 *Short_4
8 FDI_TXP4 G22 L33 AN25 XDP_DBRST# 8
C FDI_TX[4] PEG_TX#[0] CPEG_TXN1 C625 EV@0.1u/10V_4_X7R PEG_TXN1 DBR# C
8 FDI_TXP5 E20 M35 11 H_PWRGOOD AN27
FDI_TX[5] PEG_TX#[1] CPEG_TXN2 C268 EV@0.1u/10V_4_X7R PEG_TXN2 VCCPWRGOOD_0
8 FDI_TXP6 F20 M33
FDI_TX[6] PEG_TX#[2] CPEG_TXN3 C261 EV@0.1u/10V_4_X7R PEG_TXN3 XDP_OBS0 T51
8 FDI_TXP7 G19 M30 AJ22
FDI_TX[7] PEG_TX#[3] CPEG_TXN4 C263 EV@0.1u/10V_4_X7R PEG_TXN4 BPM#[0] XDP_OBS1 T54
L31 8,35 PM_DRAM_PWRGD AK13 AK22
FDI_FSYNC0_R PEG_TX#[4] CPEG_TXN5 C260 EV@0.1u/10V_4_X7R PEG_TXN5 SM_DRAMPWROK BPM#[1] XDP_OBS2 T50
F17 K32 AK24
FDI_FSYNC1_R FDI_FSYNC[0] PEG_TX#[5] CPEG_TXN6 C264 EV@0.1u/10V_4_X7R PEG_TXN6 BPM#[2] XDP_OBS3 T57
E17 M29 AJ24
FDI_FSYNC[1] PEG_TX#[6] CPEG_TXN7 C256 EV@0.1u/10V_4_X7R PEG_TXN7 H_VTTPWRGD BPM#[3] XDP_OBS4 T62
J31 AM15 AJ25
FDI_INT_R PEG_TX#[7] CPEG_TXN8 C611 EV@0.1u/10V_4_X7R PEG_TXN8 VTTPWRGOOD BPM#[4] XDP_OBS5 T58
C17 K29 AH22
FDI_INT PEG_TX#[8] CPEG_TXN9 C600 EV@0.1u/10V_4_X7R PEG_TXN9 BPM#[5] XDP_OBS6 T61
H30 AK23
FDI_LSYNC0_R PEG_TX#[9] CPEG_TXN10 C602 EV@0.1u/10V_4_X7R PEG_TXN10 T53 BPM#[6] XDP_OBS7 T64
F18 H29 AM26 AH23
FDI_LSYNC1_R FDI_LSYNC[0] PEG_TX#[10] CPEG_TXN11 C592 EV@0.1u/10V_4_X7R PEG_TXN11 TAPPWRGOOD BPM#[7]
D17 F29
FDI_LSYNC[1] PEG_TX#[11] CPEG_TXN12 C604 EV@0.1u/10V_4_X7R PEG_TXN12
E28
PEG_TX#[12] CPEG_TXN13 C594 EV@0.1u/10V_4_X7R PEG_TXN13 R171 1.5K/F_4 CPU_PLTRST# AL14
D29 10,11,26,28,31,36 PLTRST#
PEG_TX#[13] CPEG_TXN14 C606 EV@0.1u/10V_4_X7R PEG_TXN14 RSTIN#
D27 PEG_TXP[0..15] 16
PEG_TX#[14] CPEG_TXN15 C596 EV@0.1u/10V_4_X7R PEG_TXN15 R166
C26
PEG_TX#[15] 750/F_4
L34 CPEG_TXP0 C271 EV@0.1u/10V_4_X7R PEG_TXP0 Clarksfield/Auburndale
PEG_TX[0] CPEG_TXP1 C624 EV@0.1u/10V_4_X7R PEG_TXP1
M34
M32
L30
M31
K31
M28
PEG_TX[6] CPEG_TXP7 C254 EV@0.1u/10V_4_X7R PEG_TXP7 R516 IV@0_4 FDI_FSYNC0_R
H31 8 FDI_FSYNC0
PEG_TX[7] CPEG_TXP8 C612 EV@0.1u/10V_4_X7R PEG_TXP8 R511 IV@0_4 FDI_FSYNC1_R
K28 8 FDI_FSYNC1
G30
PEG_TX[9] CPEG_TXP10 C603 EV@0.1u/10V_4_X7R PEG_TXP10 R507 IV@0_4 FDI_INT_R
G29 8 FDI_INT
F28
PEG_TX[11] CPEG_TXP12 C605 EV@0.1u/10V_4_X7R PEG_TXP12 R513 IV@0_4 FDI_LSYNC0_R
E27 8 FDI_LSYNC0
PEG_TX[12] CPEG_TXP13 C595 EV@0.1u/10V_4_X7R PEG_TXP13 R509 IV@0_4 FDI_LSYNC1_R
D28 8 FDI_LSYNC1
C27
PEG_TX[14] CPEG_TXP15 C597 EV@0.1u/10V_4_X7R PEG_TXP15 R501 EV@1K_4
C25
PEG_TX[15] R503 EV@1K_4
R505 EV@1K_4
B R502 EV@1K_4 B
Clarksfield/Auburndale R504 EV@1K_4
Amos 1013
Processor pull-up JTAG MAPPING

Thermaltrip protect VTT PWR_Good
XDP_TDI_R R491 *Short_4 XDP_TDI
+1.1V_VTT
XDP_TDO_M XDP_TDO
XDP_TDO R482 51/F_4 R489 *0_4
+1.1V_VTT H_CATERR# R144 49.9/F_4
H_PROCHOT# R474 68_4
H_CPURST# R179 *68_4 R488
3
XDP_TMS R177 *51_4 *Short_4

+3V XDP_TDI_R R497 *51_4
XDP_PREQ# R480 *51_4 XDP_TDI_M
2 Q16 XDP_TCLK R169 *51_4 R487 *0_4
8,39 DELAY_VR_PWRGOOD
XDP_TRST# R477 51/F_4 XDP_TDO_R R481 *Short_4
FDV301N C385
0.1u/10V_4
1
Scan Chain STUFF -> R469, R491, R507

5
R175 (Default) NO STUFF -> R489, R490

1K_4 36 MPWROK 2 R173 +1.5V_CPUVDDQ
4 H_VTTPWRGD
1 CPU Only STUFF -> R490, R491
2K/F_4 Use a voltage divider with VDDQ NO STUFF -> R469, R489, R507
U8 R168 (1.5V) rail (ON in S3) and
3
2
A R164 1.1K/F_4 A
resistor combination of 4.75K (to
Q15 TC7SH08FU 1K_4 GMCH Only STUFF -> R489, R507
VDDQ)/12K(to GND) to generate the
PM_THRMTRIP# 1 3 MMBT3904 SYS_SHDN# 38,47
PM_DRAM_PWRGD NO STUFF -> R491, R490, R469
required voltage.
R167 Note: CRB uses a 3.3V (always ON)
3K/F_4 rail with 2K and 1K combination.

PM_DRAM_PWRGD: PROJECT : ZYD
Never drive hight before DDR3 voltage ramp to stable Size Document Number Rev
3B
AUBURNDA 1/4
5 4 3 2 1
Dr-Bios.com
5 4 3 2 1
AUBURNDALE/CLARKSFIELD PROCESSOR (DDR3) U26D
U26C
15 M_B_DQ[63:0] SB_CK[0] W8 M_B_CLK0 15

SB_CK#[0] W9 M_B_CLK0# 15
M_B_DQ0 B5 M3 M_B_CKE0 15
M_B_DQ1 SB_DQ[0] SB_CKE[0]
A5 SB_DQ[1]
AA6 M_B_DQ2 C3
SA_CK[0] M_A_CLK0 14 SB_DQ[2]
AA7 M_B_DQ3 B3 V7
SA_CK#[0] M_A_CLK0# 14 SB_DQ[3] SB_CK[1] M_B_CLK1 15
P7 M_A_CKE0 14 M_B_DQ4 E4 V6 M_B_CLK1# 15
D 14 M_A_DQ[63:0] SA_CKE[0] SB_DQ[4] SB_CK#[1] D
M_A_DQ0 A10 M_B_DQ5 A6 M2 M_B_CKE1 15
M_A_DQ1 SA_DQ[0] M_B_DQ6 SB_DQ[5] SB_CKE[1]
C10 A4
M_A_DQ2 SA_DQ[1] M_B_DQ7 SB_DQ[6]
C7 SA_DQ[2] C4 SB_DQ[7]
M_A_DQ3 A7 Y6 M_B_DQ8 D1
SA_DQ[3] SA_CK[1] M_A_CLK1 14 SB_DQ[8]
M_A_DQ4 B10 Y5 M_B_DQ9 D2
SA_DQ[4] SA_CK#[1] M_A_CLK1# 14 SB_DQ[9]
M_A_DQ5 D10 P6 M_A_CKE1 14 M_B_DQ10 F2 AB8 M_B_CS#0 15
M_A_DQ6 SA_DQ[5] SA_CKE[1] M_B_DQ11 SB_DQ[10] SB_CS#[0]
E10 SA_DQ[6] F1 SB_DQ[11] SB_CS#[1] AD6 M_B_CS#1 15
M_A_DQ7 A8 M_B_DQ12 C2
D8 F5
F10 SA_DQ[9] SA_CS#[0] AE2 M_A_CS#0 14 F3 SB_DQ[14]
M_A_DQ10 E6 AE8 M_A_CS#1 14 M_B_DQ15 G4 AC7 M_B_ODT0 15
M_A_DQ11 SA_DQ[10] SA_CS#[1] M_B_DQ16 SB_DQ[15] SB_ODT[0]
F7 H6 AD1 M_B_ODT1 15
M_A_DQ12 SA_DQ[11] M_B_DQ17 SB_DQ[16] SB_ODT[1]
E9 G2
B7 SA_DQ[13] J6 SB_DQ[18]
M_A_DQ14 E7 AD8 M_B_DQ19 J3
SA_DQ[14] SA_ODT[0] M_A_ODT0 14 SB_DQ[19]
M_A_DQ15 C6 AF9 M_A_ODT1 14 M_B_DQ20 G1 M_B_DM[7:0] 15
M_A_DQ16 SA_DQ[15] SA_ODT[1] M_B_DQ21 SB_DQ[20] M_B_DM0
H10 SA_DQ[16] G5 SB_DQ[21] SB_DM[0] D4
M_A_DQ17 G8 M_B_DQ22 J2 E1 M_B_DM1
M_A_DQ18 SA_DQ[17] M_B_DQ23 SB_DQ[22] SB_DM[1] M_B_DM2
K7 J1 H3
J8 SA_DQ[19] J5 SB_DQ[24] SB_DM[3] K1
M_A_DQ20 G7 M_B_DQ25 K2 AH1 M_B_DM4
G10 SA_DQ[21] M_A_DM[7:0] 14 L3 SB_DQ[26] SB_DM[5] AL2
M_A_DQ22 J7 B9 M_A_DM0 M_B_DQ27 M1 AR4 M_B_DM6
M_A_DQ23 SA_DQ[22] SA_DM[0] M_A_DM1 M_B_DQ28 SB_DQ[27] SB_DM[6] M_B_DM7
J10 D7 K5 AT8
M_A_DQ24 SA_DQ[23] SA_DM[1] M_A_DM2 M_B_DQ29 SB_DQ[28] SB_DM[7]
L7 SA_DQ[24] SA_DM[2] H7 K4 SB_DQ[29]
M_A_DQ25 M6 M7 M_A_DM3 M_B_DQ30 M4
M_A_DQ26 SA_DQ[25] SA_DM[3] M_A_DM4 M_B_DQ31 SB_DQ[30]
M8 SA_DQ[26] SA_DM[4] AG6 N5 SB_DQ[31]
M_A_DQ27 L9 AM7 M_A_DM5 M_B_DQ32 AF3
M_A_DQ28 SA_DQ[27] SA_DM[5] M_A_DM6 M_B_DQ33 SB_DQ[32]
L6 AN10 AG1 M_B_DQS#[7:0] 15
M_A_DQ29 SA_DQ[28] SA_DM[6] M_A_DM7 M_B_DQ34 SB_DQ[33] M_B_DQS#0
K8 AN13 AJ3 D5
M_A_DQ30 SA_DQ[29] SA_DM[7] M_B_DQ35 SB_DQ[34] SB_DQS#[0] M_B_DQS#1
N8 SA_DQ[30] AK1 SB_DQ[35] SB_DQS#[1] F4
M_A_DQ31 P9 M_B_DQ36 AG4 J4 M_B_DQS#2
C M_A_DQ32 SA_DQ[31] M_B_DQ37 SB_DQ[36] SB_DQS#[2] M_B_DQS#3 C
AH5 SA_DQ[32] AG3 SB_DQ[37] SB_DQS#[3] L4
M_A_DQ33 AF5 M_B_DQ38 AJ4 AH2 M_B_DQS#4
SA_DQ[33] M_A_DQS#[7:0] 14 SB_DQ[38] SB_DQS#[4]
DDR SYSTEM MEMORY - B

M_A_DQ34 AK6 C9 M_A_DQS#0 M_B_DQ39 AH4 AL4 M_B_DQS#5
SA_DQ[34] SA_DQS#[0] SB_DQ[39] SB_DQS#[5]
DDR SYSTEM MEMORY A
M_A_DQ35 AK7 F8 M_A_DQS#1 M_B_DQ40 AK3 AR5 M_B_DQS#6

M_A_DQ36 SA_DQ[35] SA_DQS#[1] M_A_DQS#2 M_B_DQ41 SB_DQ[40] SB_DQS#[6] M_B_DQS#7
AF6 SA_DQ[36] SA_DQS#[2] J9 AK4 SB_DQ[41] SB_DQS#[7] AR8
M_A_DQ37 AG5 N9 M_A_DQS#3 M_B_DQ42 AM6
M_A_DQ38 SA_DQ[37] SA_DQS#[3] M_A_DQS#4 M_B_DQ43 SB_DQ[42]
AJ7 SA_DQ[38] SA_DQS#[4] AH7 AN2 SB_DQ[43]
M_A_DQ39 AJ6 AK9 M_A_DQS#5 M_B_DQ44 AK5
AJ10 AP11 AK2
AJ9 SA_DQ[41] SA_DQS#[7] AT13 AM4 SB_DQ[46]
M_A_DQ42 AL10 M_B_DQ47 AM3
SA_DQ[42] SB_DQ[47] M_B_DQS[7:0] 15
M_A_DQ43 AK12 M_B_DQ48 AP3 C5 M_B_DQS0
M_A_DQ44 SA_DQ[43] M_B_DQ49 SB_DQ[48] SB_DQS[0] M_B_DQS1
AK8 SA_DQ[44] AN5 SB_DQ[49] SB_DQS[1] E3
M_A_DQ45 AL7 M_B_DQ50 AT4 H4 M_B_DQS2
M_A_DQ46 SA_DQ[45] M_A_DQS0 M_A_DQS[7:0] 14 M_B_DQ51 SB_DQ[50] SB_DQS[2] M_B_DQS3
AK11 SA_DQ[46] SA_DQS[0] C8 AN6 SB_DQ[51] SB_DQS[3] M5
M_A_DQ47 AL8 F9 M_A_DQS1 M_B_DQ52 AN4 AG2 M_B_DQS4
M_A_DQ48 SA_DQ[47] SA_DQS[1] M_A_DQS2 M_B_DQ53 SB_DQ[52] SB_DQS[4] M_B_DQS5
AN8 H9 AN3 AL5
M_A_DQ49 SA_DQ[48] SA_DQS[2] M_A_DQS3 M_B_DQ54 SB_DQ[53] SB_DQS[5] M_B_DQS6
AM10 SA_DQ[49] SA_DQS[3] M9 AT5 SB_DQ[54] SB_DQS[6] AP5
M_A_DQ50 AR11 AH8 M_A_DQS4 M_B_DQ55 AT6 AR7 M_B_DQS7
M_A_DQ51 SA_DQ[50] SA_DQS[4] M_A_DQS5 M_B_DQ56 SB_DQ[55] SB_DQS[7]
AL11 SA_DQ[51] SA_DQS[5] AK10 AN7 SB_DQ[56]
M_A_DQ52 AM9 AN11 M_A_DQS6 M_B_DQ57 AP6
M_A_DQ53 SA_DQ[52] SA_DQS[6] M_A_DQS7 M_B_DQ58 SB_DQ[57]
AN9 AR13 AP8
M_A_DQ54 SA_DQ[53] SA_DQS[7] M_B_DQ59 SB_DQ[58]
AT11 AT9
AP12 AT7
AM12 AP9
AN12 M_A_A[15:0] 14 AR10 M_B_A[15:0] 15
M_A_DQ58 SA_DQ[57] M_A_A0 M_B_DQ63 SB_DQ[62] M_B_A0
AM13 SA_DQ[58] SA_MA[0] Y3 AT10 SB_DQ[63] SB_MA[0] U5
M_A_DQ59 AT14 W1 M_A_A1 V2 M_B_A1
M_A_DQ60 SA_DQ[59] SA_MA[1] M_A_A2 SB_MA[1] M_B_A2
AT12 AA8 T5
AL13 AA3 V3
AR14 V1 R1
AP14 SA_DQ[63] SA_MA[5] AA9 15 M_B_BS#0 AB1 SB_BS[0] SB_MA[5] T8
B M_A_A6 M_B_A6 B
SA_MA[6] V8 15 M_B_BS#1 W5 SB_BS[1] SB_MA[6] R2
T1 M_A_A7 15 M_B_BS#2 R7 R6 M_B_A7
SA_MA[7] M_A_A8 SB_BS[2] SB_MA[7] M_B_A8
Y9 R4
SA_MA[8] M_A_A9 SB_MA[8] M_B_A9
14 M_A_BS#0 AC3 SA_BS[0] SA_MA[9] U6 SB_MA[9] R5
AB2 AD4 M_A_A10 AC5 AB5 M_B_A10
14 M_A_BS#1 SA_BS[1] SA_MA[10] 15 M_B_CAS# SB_CAS# SB_MA[10]
14 M_A_BS#2 U7 T2 M_A_A11 15 M_B_RAS# Y7 P3 M_B_A11
SA_BS[2] SA_MA[11] M_A_A12 SB_RAS# SB_MA[11] M_B_A12
U3 15 M_B_WE# AC6 R3
SA_MA[12] M_A_A13 SB_WE# SB_MA[12] M_B_A13
AG8 AF7
T3 P5
14 M_A_CAS# AE1 SA_CAS# SA_MA[15] V9 SB_MA[15] N1
14 M_A_RAS# AB3
SA_RAS#
14 M_A_WE# AE9
SA_WE#
Clarksfield/Auburndale Clarksfield/Auburndale
Channel A DQ[15,32,48,54], DM[5] Channel B DQ[16,18,36,42,56,57,60,61,62]

Requires minimum 12mils spacing Requires minimum 12mils spacing
with all other signals, including data signals. with all other signals, including data signals.
A A
5
Dr-Bios.com
4 3 2
Size
Date:
Document Number
AUBURNDA 2/4
PROJECT : ZYD
Tuesday, April 06, 2010 Sheet

1
5 of 50
Rev
3B
5 4 3 2 1
CPU Core Power U26F
VTT Rail Values are AUBURNDALE/CLARKSFIELD PROCESSOR (GRAPHICS POWER)

ARD:48A Auburndal VTT=1.05V
+VCC_CORE Clarksfield VTT=1.1V
CFD:52A
18A
C315 22U/6.3V_8 AG35 AH14 +1.1V_VTT U26G
C656 22U/6.3V_8 VCC1 VTT0_1
AG34 AH12
C317 22U/6.3V_8 AG33
VCC2 VTT0_2
AH11 +VGFX_AXG
22A AT21
C282 22U/6.3V_8 VCC3 VTT0_3 C652 10U/6.3V_8 VAXG1
AG32 AH10 AT19 AR22 VCC_AXG_SENSE 45
D C643 22U/6.3V_8 VCC4 VTT0_4 C647 10U/6.3V_8 VAXG2 VAXG_SENSE D
SENSE
LINES
AG31 J14 AT18 AT22 VSS_AXG_SENSE 45
C648 22U/6.3V_8 VCC5 VTT0_5 C628 10U/6.3V_8 VAXG3 VSSAXG_SENSE
AG30 J13 AT16
AG29 H14 AR21
AG28 H12 AR19
C320 22U/6.3V_8 VCC8 VTT0_8 C630 10U/6.3V_8 + VAXG6
AG27 G14 AR18
C637 22U/6.3V_8 VCC9 VTT0_9 C629 10U/6.3V_8 C675 C325 C324 VAXG7
AG26 G13 AR16 AM22 GFX_VID0 45
C288 22U/6.3V_8 VCC10 VTT0_10 C657 22U/6.3V_8 IV@330U/2V_7343 IV@22u/6.3V_8 IV@22u/6.3V_8 VAXG8 GFX_VID[0] GFX_DPRSLPVR
AF35 G12 AP21 AP22 GFX_VID1 45
VCC11 VTT0_11 VAXG9 GFX_VID[1]
GRAPHICS VIDs
C333 22U/6.3V_8 AF34 G11 C599 22U/6.3V_8 AP19 AN22 GFX_VID2 45
C303 10U/6.3V_8 VCC12 VTT0_12 C298 22U/6.3V_8 VAXG10 GFX_VID[2] GFX_ON
AF33 F14 AP18 AP23 GFX_VID3 45
C305 10U/6.3V_8 VCC13 VTT0_13 VAXG11 GFX_VID[3]
AF32 F13 AP16 AM23 GFX_VID4 45
C296 10U/6.3V_8 VCC14 VTT0_14 VAXG12 GFX_VID[4] R494 R493
AF31 F12 C284 AN21 AP24 GFX_VID5 45
VCC15 VTT0_15 VAXG13 GFX_VID[5]
GRAPHICS
C646 10U/6.3V_8 AF30 F11 AN19 AN24 GFX_VID6 45 *IV@4.7K_4 *IV@10K_4
C635 10U/6.3V_8 VCC16 VTT0_16 VAXG14 GFX_VID[6]
+
AF29 E14 AN18
C654 10U/6.3V_8 VCC17 VTT0_17 VAXG15
AF28 E12 AN16
C651 10U/6.3V_8 VCC18 VTT0_18 VAXG16
AF27 D14 AM21 AR25 GFX_ON 45
C352 10U/6.3V_8 VCC19 VTT0_19 330u/2V_7343 VAXG17 GFX_VR_EN
AF26 D13 AM19 AT25 GFX_DPRSLPVR 45
C638 10U/6.3V_8 VCC20 VTT0_20 VAXG18 GFX_DPRSLPVR
AD35 D12 AM18 AM24
1.1V RAIL POWER

VCC21 VTT0_21 + VAXG19 GFX_IMON GFX_IMON 45
C322 10U/6.3V_8 AD34 D11 AM16 Amos 1013
C323 10U/6.3V_8 VCC22 VTT0_22 C673 C326 C327 VAXG20
AD33 C14 AL21
C294 10U/6.3V_8 VCC23 VTT0_23 IV@330U/2V_7343 IV@10u/6.3V_8 IV@10u/6.3V_8 VAXG21 R492 EV@1K_4
C640 10U/6.3V_8
AD32
VCC24 VTT0_24
C13 AL19
VAXG22 ARD:3A
AD31 C12 AL18
C297 10U/6.3V_8 VCC25 VTT0_25 VAXG23 CFD:6A
AD30 C11 AL16
C290 10U/6.3V_8 VCC26 VTT0_26 VAXG24
AD29 B14 AK21 AJ1 +1.5V_CPUVDDQ
C653 10U/6.3V_8 VCC27 VTT0_27 VAXG25 VDDQ1
AD28 B12 AK19 AF1
C312 0.1u/10V_4_X7R VCC28 VTT0_28 VAXG26 VDDQ2
- 1.5V RAILS
AD27 A14 AK18 AE7
C287 0.1u/10V_4_X7R VCC29 VTT0_29 VAXG27 VDDQ3 C334 C281 C286 C343
AD26 A13 AK16 AE4
VCC30 VTT0_30 VAXG28 VDDQ4
AC35 A12 AJ21 AC1
+
C289 330u/2V_7343 AC34 A11 AJ19 AB7 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4
AC33 AJ18 AB4
VCC33 VAXG31 VDDQ7
+
C309 330u/2V_7343 AC32 +1.1V_VTT R490 EV@0_4 AJ16 Y1

VCC34 VAXG32 VDDQ8
AC31 AH21 W7
VCC35 VAXG33 VDDQ9
POWER
AC30 AF10 AH19 W4
C VCC36 VTT0_33 VAXG34 VDDQ10 C342 C329 C291 + C253 C
AC29
VCC37 VTT0_34
AE10 Amos 1013 AH18
VAXG35 VDDQ11
U1
AC28 AC10 AH16 T7
CPU CORE SUPPLY

AC27 AB10 C272 22U/6.3V_8 T4 1U/6.3V_4 22U/6.3V_8 22U/6.3V_8 330U/2V_7343
VCC39 VTT0_36 VDDQ13
AC26 Y10 P1
VCC40 VTT0_37 C273 22U/6.3V_8 VDDQ14
AA35 W10 N7
AA34 U10 N4
VCC42 VTT0_39 +1.1V_VTT VDDQ16
DDR3
AA33 T10 L1
AA32 J12 J24 H1
VCC44 VTT0_41 VTT1_45 VDDQ18
FDI
AA31 J11 J23
VCC45 VTT0_42 VTT1_46
AA30 J16 H25
AA29 J15
VCC47 VTT0_44
AA28
VCC48 C275 C639
AA27 P10 +1.1V_VTT
VCC49 22u/6.3V_8 22u/6.3V_8 VTT0_59
AA26 N10
VCC50 VTT0_60 C631 10U/6.3V_8
Y35 L10
VCC51 VTT0_61 C636 10U/6.3V_8
Y34 K10
VCC52 VTT0_62
Y33
VCC53
Y32
VCC54
Y31
VCC55
Y30
VCC56
1.1V
Y29 J22
VCC57 VTT1_63 22U/6.3V_8 C626
Y28 K26 J20
VCC58 VTT1_48 VTT1_64 22U/6.3V_8 C627
Y27 J27 J18
PEG & DMI

Y26 J26 H21
VCC60 H_PSI# C313 C644 C274 C304 VTT1_50 VTT1_66
V35 AN33 H_PSI# 39 J25 H20
VCC61 PSI# 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 VTT1_51 VTT1_67
V34 H27 H19
POWER

V33 G28
VCC63 H_VID0 VTT1_53
V32 AK35 H_VID0 39 G27
VCC64 VID[0] H_VID1 VTT1_54
V31
VCC65 VID[1]
AK33
H_VID2
H_VID1 39 G26
VTT1_55 0.6A
V30 AK34 H_VID2 39 F26
VCC66 VID[2] H_VID3 VTT1_56
V29 AL35 H_VID3 39 E26 L26 +1.8V
VCC67 VID[3] VTT1_57 VCCPLL1
CPU VIDS
1.8V
V28 AL33 H_VID4 H_VID4 39 E25 L27
B VCC68 VID[4] H_VID5 VTT1_58 VCCPLL2 22U/6.3V_8 C276 B
V27 AM33 H_VID5 39 M26
VCC69 VID[5] H_VID6 VCCPLL3 4.7U/6.3V_6 C277
V26 AM35 H_VID6 39
VCC70 VID[6] H_DPRSLPVR 2.2U/6.3V_6 C249
U35 AM34 H_DPRSLPVR 39
VCC71 PROC_DPRSLPVR 1U/6.3V_4 C251
U34
VCC72 1U/6.3V_4 C250
U33
VCC73
U32
VCC74 H_VTTVID1
U31 G15 T48
VCC75 VTT_SELECT
U30
VCC76 Clarksfield/Auburndale
U29
VCC77 H_VTTVID1=Low, 1.1V
U28
VCC78 H_VTTVID1=High, 1.05V
U27
VCC79
U26
VCC80
R35
VCC81
R34
VCC82
R33
VCC83
R32 AN35 I_MON 39
VCC84 ISENSE
R31
VCC85
R30
VCC86 R145 100/F_4
R29 +VCC_CORE
VCC87
R28 AJ34
SENSE LINES
VCC88 VCC_SENSE VCCSENSE 39

R27 AJ35 VSSSENSE 39
1 H_VID0 R496 1K_4 +1.1V_VTT
VCC89 VSS_SENSE R495 *1K/F_4
R26
VCC90 R146 100/F_4 1 H_VID1 R499 1K_4
P35
VCC91 VTT_SENSE R498 *1K/F_4
P34 B15 T85
VCC92 VTT_SENSE VSS_SENSE_VTT 1 H_VID2 R185 1K_4
P33 A15 T86
VCC93 VSS_SENSE_VTT R184 *1K/F_4
P32
VCC94 0 H_VID3 R486 *1K/F_4
P31
VCC95 R485 1K_4
P30
VCC96 0 H_VID4 R180 *1K/F_4
P29
VCC97 R181 1K_4
P28
VCC98 1 H_VID5 R479 1K_4
P27
VCC99 R472 *1K/F_4
P26
A VCC100 0 H_VID6 R484 *1K/F_4 A
R483 1K_4
1 H_DPRSLPVR R187 1K_4
R186 *1K/F_4
0 H_PSI# R478 *1K/F_4
R471 1K_4
Clarksfield/Auburndale
Note:
For Validating IMVP VR R6451 should be STUFF
HFM_VID : Max 1.4V
and R2N1 NO_STUFF LFM_VID : Min 0.65V PROJECT : ZYD
AUBURNDALE/CLARKSFIELD PROCESSOR (POWER) Size Document Number Rev
3B
AUBURNDA 3/4 (PWR)
5 4 3 2 1
Dr-Bios.com
5 4 3 2 1
AUBURNDALE/CLARKSFIELD PROCESSOR (GND) AUBURNDALE/CLARKSFIELD PROCESSOR( RESERVED, CFG)

U26H U26I U26E
AT20 VSS1 VSS81 AE34 RSVD32 AJ13

AT17 VSS2 VSS82 AE33 RSVD33 AJ12
AR31 VSS3 VSS83 AE32 K27 VSS161
AR28 VSS4 VSS84 AE31 K9 VSS162 AP25 RSVD1
AR26 VSS5 VSS85 AE30 K6 VSS163 AL25 RSVD2 RSVD34 AH25
AR24 VSS6 VSS86 AE29 K3 VSS164 AL24 RSVD3 RSVD35 AK26
AR23 VSS7 VSS87 AE28 J32 VSS165 AL22 RSVD4
AR20 VSS8 VSS88 AE27 J30 VSS166 AJ33 RSVD5 RSVD36 AL26
AR17 AE26 J21 R126 *EV@100K_4 AG9 AR2
VSS9 VSS89 VSS167 RSVD6 RSVD_NCTF_37
AR15 VSS10 VSS90 AE6 J19 VSS168 M27 RSVD7
D AR12 VSS11 VSS91 AD10 H35 VSS169 L28 RSVD8 RSVD38 AJ26 D
AR9 VSS12 VSS92 AC8 H32 VSS170 14,35 VREF_DQ_DIMM0 J17 SA_DIMM_VREF RSVD39 AJ27
AR6 VSS13 VSS93 AC4 H28 VSS171 15,35 VREF_DQ_DIMM1 H17 SB_DIMM_VREF
AR3 VSS14 VSS94 AC2 H26 VSS172 G25 RSVD11
AP20 VSS15 VSS95 AB35 H24 VSS173 G17 RSVD12
AP17 AB34 H22 R125 *EV@100K_4 E31 AP1
VSS16 VSS96 VSS174 RSVD13 RSVD_NCTF_40
AP13 VSS17 VSS97 AB33 H18 VSS175 E30 RSVD14 RSVD_NCTF_41 AT2
AP10 VSS18 VSS98 AB32 H15 VSS176
AP7 VSS19 VSS99 AB31 H13 VSS177 RSVD_NCTF_42 AT3
AP4 VSS20 VSS100 AB30 H11 VSS178 RSVD_NCTF_43 AR1
AP2 VSS21 VSS101 AB29 H8 VSS179 Modify 1017
AN34 VSS22 VSS102 AB28 H5 VSS180
AN31 VSS23 VSS103 AB27 H2 VSS181
AN23 VSS24 VSS104 AB26 G34 VSS182 RSVD45 AL28
AN20 AB6 G31 CFG0 AM30 AL29
VSS25 VSS105 VSS183 CFG[0] RSVD46
AN17 VSS26 VSS106 AA10 G20 VSS184 AM28 CFG[1] RSVD47 AP30
AM29 VSS27 VSS107 Y8 G9 VSS185 AP31 CFG[2] RSVD48 AP32
AM27 Y4 G6 CFG3 AL32 AL27
VSS28 VSS108 VSS186 CFG4 CFG[3] RSVD49
AM25 VSS29 VSS109 Y2 G3 VSS187 AL30 CFG[4] RSVD50 AT31
AM20 VSS30 VSS110 W 35 F30 VSS188 AM31 CFG[5] RSVD51 AT32
AM17 VSS31 VSS111 W 34 F27 VSS189 AN29 CFG[6] RSVD52 AP33
AM14 W 33 F25 CFG7 AM32 AR33
VSS32 VSS112 VSS190 CFG[7] RSVD53
AM11 VSS33 VSS113 W 32 F22 VSS191 AK32 CFG[8] RSVD_NCTF_54 AT33
AM8 W 31 F19 AK31 AT34
RESERVED
VSS34 VSS114 VSS192 CFG[9] RSVD_NCTF_55
AM5 VSS35 VSS115 W 30 F16 VSS193 AK28 CFG[10] RSVD_NCTF_56 AP35
AM2 VSS36 VSS116 W 29 E35 VSS194 AJ28 CFG[11] RSVD_NCTF_57 AR35
AL34 W 28 E32 AN30 AR32
AL31
AL23
VSS37
VSS38
VSS39
VSS VSS117
VSS118
VSS119
W 27
W 26
E29
E24
VSS195
VSS196
VSS197
VSS AN32
AJ32
CFG[12]
CFG[13]
CFG[14]
RSVD58
AL20 VSS40 VSS120 W6 E21 VSS198 AJ29 CFG[15] RSVD_TP_59 E15

AL17 VSS41 VSS121 V10 E18 VSS199 AJ30 CFG[16] RSVD_TP_60 F15
C AL12 U8 E13 AK30 A2 C
VSS42 VSS122 VSS200 CFG[17] KEY
AL9 VSS43 VSS123 U4 E11 VSS201 H16 RSVD_TP_86 RSVD62 D15
AL6 VSS44 VSS124 U2 E8 VSS202 RSVD63 C15
AL3 VSS45 VSS125 T35 E5 VSS203 RSVD64 AJ15 TP5
AK29 VSS46 VSS126 T34 E2 VSS204 VSS_NCTF1 AT35 RSVD65 AH15 TP6
AK27 VSS47 VSS127 T33 D33 VSS205 VSS_NCTF2 AT1
AK25 VSS48 VSS128 T32 D30 VSS206 VSS_NCTF3 AR34 TP4 B19 RSVD15
AK20 VSS49 VSS129 T31 D26 VSS207 VSS_NCTF4 B34 TP2 A19 RSVD16
AK17 T30 D9 B2 TP45
NCTF
VSS50 VSS130 VSS208 VSS_NCTF5
AJ31 VSS51 VSS131 T29 D6 VSS209 VSS_NCTF6 B1 TP43 A20 RSVD17
AJ23 VSS52 VSS132 T28 D3 VSS210 VSS_NCTF7 A35 TP44 B20 RSVD18
AJ20 VSS53 VSS133 T27 C34 VSS211 RSVD_TP_66 AA5
AJ17 VSS54 VSS134 T26 C32 VSS212 U9 RSVD19 RSVD_TP_67 AA4
AJ14 VSS55 VSS135 T6 C29 VSS213 T9 RSVD20 RSVD_TP_68 R8
AJ11 VSS56 VSS136 R10 C28 VSS214 RSVD_TP_69 AD3
AJ8 VSS57 VSS137 P8 C24 VSS215 AC9 RSVD21 RSVD_TP_70 AD2
AJ5 VSS58 VSS138 P4 C22 VSS216 AB9 RSVD22 RSVD_TP_71 AA2
AJ2 VSS59 VSS139 P2 C20 VSS217 RSVD_TP_72 AA1
AH35 VSS60 VSS140 N35 C19 VSS218 RSVD_TP_73 R9
AH34 VSS61 VSS141 N34 C16 VSS219 RSVD_TP_74 AG7
AH33 VSS62 VSS142 N33 B31 VSS220 C1 RSVD_NCTF_23 RSVD_TP_75 AE3
AH32 VSS63 VSS143 N32 B25 VSS221 A3 RSVD_NCTF_24
AH31 VSS64 VSS144 N31 B21 VSS222
AH30 VSS65 VSS145 N30 B18 VSS223 RSVD_TP_76 V4
AH29 VSS66 VSS146 N29 B17 VSS224 RSVD_TP_77 V5
AH28 VSS67 VSS147 N28 B13 VSS225 RSVD_TP_78 N2
AH27 VSS68 VSS148 N27 B11 VSS226 J29 RSVD26 RSVD_TP_79 AD5
AH26 VSS69 VSS149 N26 B8 VSS227 J28 RSVD27 RSVD_TP_80 AD7
AH20 VSS70 VSS150 N6 B6 VSS228 RSVD_TP_81 W3
AH17 VSS71 VSS151 M10 B4 VSS229 A34 RSVD_NCTF_28 RSVD_TP_82 W2
AH13 VSS72 VSS152 L35 A29 VSS230 A33 RSVD_NCTF_29 RSVD_TP_83 N3
B B
AH9 VSS73 VSS153 L32 A27 VSS231 RSVD_TP_84 AE5
AH6 VSS74 VSS154 L29 A23 VSS232 C35 RSVD_NCTF_30 RSVD_TP_85 AD9
AH3 VSS75 VSS155 L8 A9 VSS233 B35 RSVD_NCTF_31
AG10 VSS76 VSS156 L5
AF8 VSS77 VSS157 L2 VSS AP34 TP3
AF4 VSS78 VSS158 K34
AF2 K33 AP34 can be NC on CRB; EDS/DG suggestion to GND
VSS79 VSS159
AE35 VSS80 VSS160 K30
Clarksfield/Auburndale
Clarksfield/Auburndale Clarksfield/Auburndale
Processor Strapping
1 0 DEFAULT
CFG0 CFG0 R172 *3.01K_NC
(PCI-Epress Single PEG Bifurcation enabled 1
Configuration Select)
CFG3
(PCI-Epress Static Normal Operation Lane Numbers Reversed CFG3 R159
1 *3.01K/F_4
Lane Reversal)
A CFG4 Enabled; An external Display port A
(Embended Disabled; No Physical Display Port device is connected to the Embedded CFG4 R157
1 *3.01K
Display Port Presence) attached to Embedded Diplay Port Display port
㪫
Dr-Bios.com
㪠㪿 CFG7 R161 *3.01K/F_4
㪼
㪸㫅 Quanta Computer Inc.
㫋㩷
㫅
㪺
㪚
㪻㪼
㫆 PROJECT : ZYD
㩷㫃
㫄 Size Document Number Rev
㩷㪸
㫇㪙 3B
㫉
㪞
㫆 AUBURNDA 4/4
5
㫂
㪼
㪘
㫅 4 3 2
Date: Tuesday, April 06, 2010
1
Sheet 7 of 50
㪽
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㪼
㫀
㫆
㫅
㪼
㫋㫄
5 4 3 2 1
IBEX PEAK-M (DMI,FDI,GPIO)
Amos 1013
IBEX PEAK-M (LVDS,DDI)
U28C
BA18 FDI_TXN0_R R236 IV@0_4
FDI_RXN0 FDI_TXN0 4
BC24 BH17 FDI_TXN1_R R212 IV@0_4 U28D
4 DMI_RXN0 DMI0RXN FDI_RXN1 FDI_TXN1 4
BJ22 BD16 FDI_TXN2_R R210 IV@0_4 T48 BJ46
4 DMI_RXN1 DMI1RXN FDI_RXN2 FDI_TXN2 4 24 INT_LVDS_BLON L_BKLTEN SDVO_TVCLKINN
D AW20 BJ16 FDI_TXN3_R R208 IV@0_4 T47 BG46 D
4 DMI_RXN2 DMI2RXN FDI_RXN3 FDI_TXN3 4 24 INT_LVDS_DIGON L_VDD_EN SDVO_TVCLKINP
BJ20 BA16 FDI_TXN4_R R229 IV@0_4
4 DMI_RXN3 DMI3RXN FDI_RXN4 FDI_TXN4 4
BE14 FDI_TXN5_R R217 IV@0_4 Y48 BJ48
FDI_RXN5 FDI_TXN5 4 24 INT_LVDS_BRIGHT L_BKLTCTL SDVO_STALLN
BD24 BA14 FDI_TXN6_R R228 IV@0_4 BG48
4 DMI_RXP0 DMI0RXP FDI_RXN6 FDI_TXN6 4 SDVO_STALLP
BG22 BC12 FDI_TXN7_R R221 IV@0_4 AB48
4 DMI_RXP1 DMI1RXP FDI_RXN7 FDI_TXN7 4 24 INT_LVDS_EDIDCLK L_DDC_CLK
4 DMI_RXP2 BA20 24 INT_LVDS_EDIDDATA Y45 BF45
DMI2RXP FDI_TXP0_R R234 IV@0_4 L_DDC_DATA SDVO_INTN
4 DMI_RXP3 BG20 BB18 FDI_TXP0 4 BH45
DMI3RXP FDI_RXP0 FDI_TXP1_R R213 IV@0_4 R267 IV@10K_4 SDVO_INTP
BF17 FDI_TXP1 4 +3V AB46
FDI_RXP1 FDI_TXP2_R R211 IV@0_4 R274 IV@10K_4 L_CTRL_CLK
4 DMI_TXN0 BE22 BC16 FDI_TXP2 4 V48
DMI0TXN FDI_RXP2 FDI_TXP3_R R209 IV@0_4 L_CTRL_DATA
4 DMI_TXN1 BF21
DMI1TXN FDI_RXP3
BG16
FDI_TXP4_R R232 IV@0_4
FDI_TXP3 4 Amos 1013 R249 IV@2.37K/F_4 LCD_IBG AP39
4 DMI_TXN2 BD20 AW16 FDI_TXP4 4 T51 SDVO_CTRLCLK 25
DMI2TXN FDI_RXP4 FDI_TXP5_R R215 IV@0_4 LVD_IBG SDVO_CTRLCLK
4 DMI_TXN3 BE18 BD14 FDI_TXP5 4 AP41 T53 SDVO_CTRLDAT 25
DMI3TXN FDI_RXP5 FDI_TXP6_R R225 IV@0_4 LVD_VBG SDVO_CTRLDATA
BB14 FDI_TXP6 4
FDI_RXP6 FDI_TXP7_R R218 IV@0_4 R239 IV@0_4 LVD_VREFH AT43
4 DMI_TXP0 BD22 BD12 FDI_TXP7 4
DMI0TXP FDI_RXP7 R235 IV@0_4 LVD_VREFL AT42 LVD_VREFH
4 DMI_TXP1 BH21 BG44 TP47
DMI1TXP LVD_VREFL DDPB_AUXN
4 DMI_TXP2 BC20 BJ44 TP46
DMI2TXP DDPB_AUXP
4 DMI_TXP3 BD18 BJ14 FDI_INT 4 AU38 INT_HDMI_HPD 25
DMI3TXP FDI_INT DDPB_HPD
LVDS
R508 *EV@1K_4 24 INT_TXLCLKOUT- INT_TXLCLKOUT- AV53
DMI
FDI
INT_TXLCLKOUT+ AV51 LVDSA_CLK#
BF13 FDI_FSYNC0 4 24 INT_TXLCLKOUT+ BD42 INT_HDMITX2N_R C781 IV@0.1u/10V_4_X7R
INT_HDMITX2N 25
FDI_FSYNC0 R515 *EV@1K_4 LVDSA_CLK DDPB_0N C782 IV@0.1u/10V_4_X7R
BH25 BC42 INT_HDMITX2P_R INT_HDMITX2P 25
DMI_ZCOMP INT_TXLOUT0- DDPB_0P
BH13 FDI_FSYNC1 4 24 INT_TXLOUT0- BB47 BJ42 INT_HDMITX1N_R C778 IV@0.1u/10V_4_X7R
INT_HDMITX1N 25
R500 49.9/F_4 FDI_FSYNC1 R512 *EV@1K_4 INT_TXLOUT1- LVDSA_DATA#0 DDPB_1N C784 IV@0.1u/10V_4_X7R
BF25 BA52 BG42 INT_HDMITX1P_R
Digital Display Interface

+1.05V DMI_IRCOMP 24 INT_TXLOUT1- LVDSA_DATA#1 DDPB_1P INT_HDMITX1P 25
BJ12 INT_TXLOUT2- AY48 BB40 INT_HDMITX0N_R C779 IV@0.1u/10V_4_X7R
FDI_LSYNC0 FDI_LSYNC0 4 24 INT_TXLOUT2- LVDSA_DATA#2 DDPB_2N INT_HDMITX0N 25
R514 *EV@1K_4 AV47 BA40 INT_HDMITX0P_R C780 IV@0.1u/10V_4_X7R
LVDSA_DATA#3 DDPB_2P INT_HDMITX0P 25
BG14 AW38INT_HDMICLK-_R C783 IV@0.1u/10V_4_X7R
FDI_LSYNC1 FDI_LSYNC1 4 DDPB_3N INT_HDMICLK- 25
R510 *EV@1K_4 24 INT_TXLOUT0+ INT_TXLOUT0+ BB48 BA38 INT_HDMICLK+_R C785 IV@0.1u/10V_4_X7R
LVDSA_DATA0 DDPB_3P INT_HDMICLK+ 25
24 INT_TXLOUT1+ INT_TXLOUT1+ BA50
INT_TXLOUT2+ LVDSA_DATA1
C 24 INT_TXLOUT2+ AY49 C
LVDSA_DATA2
modify 1024 AV48
LVDSA_DATA3 DDPC_CTRLCLK
Y49
AB49
DDPC_CTRLDATA
INT_TXUCLKOUT- AP48
24 INT_TXUCLKOUT- LVDSB_CLK#
XDP_DBRST# T6 J12 INT_TXUCLKOUT+ AP47 BE44
4 XDP_DBRST# SYS_RESET# WAKE# PCIE_WAKE# 26,28 24 INT_TXUCLKOUT+ LVDSB_CLK DDPC_AUXN
BD44
INT_TXUOUT0- DDPC_AUXP
24 INT_TXUOUT0- AY53 AV40
SYS_PWROK INT_TXUOUT1- LVDSB_DATA#0 DDPC_HPD
M6 Y1 CLKRUN# 36 24 INT_TXUOUT1- AT49
SYS_PWROK CLKRUN# / GPIO32 INT_TXUOUT2- LVDSB_DATA#1
24 INT_TXUOUT2- AU52 BE40
LVDSB_DATA#2 DDPC_0N
Amos 1014 AT53
LVDSB_DATA#3 DDPC_0P
BD40
System Power Management
B17 BF41
PWROK INT_TXUOUT0+ DDPC_1N
24 INT_TXUOUT0+ AY51 BH41
INT_TXUOUT1+ LVDSB_DATA0 DDPC_1P
24 INT_TXUOUT1+ AT48 BD38
SUS_STAT# INT_TXUOUT2+ LVDSB_DATA1 DDPC_2N
K5 P8 TP24 24 INT_TXUOUT2+ AU50 BC38
MEPWROK SUS_STAT# / GPIO61 LVDSB_DATA2 DDPC_2P
AT51 BB36
LVDSB_DATA3 DDPC_3N
BA36
RSV_ICH_LAN_RST# A10 DDPC_3P
F3 ICH_SUSCLK 36
LAN_RST# SUSCLK / GPIO62
INT_CRT_BLU AA52 U50 Amos 1013
24 INT_CRT_BLU CRT_BLUE DDPD_CTRLCLK
D9 E4 SLP_S5#_R TP36 INT_CRT_GRN AB53 U52
4,35 PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 24 INT_CRT_GRN CRT_GREEN DDPD_CTRLDATA
INT_CRT_RED AD53
24 INT_CRT_RED CRT_RED
36 ICH_RSMRST# C16 H7 SUSC# 36 BC46

RSMRST# SLP_S4# DDPD_AUXN
24 INT_CRT_DDCCLK V51
CRT_DDC_CLK DDPD_AUXP
BD46 R place close to PCH
24 INT_CRT_DDCDAT V53 AT38
SUS_PWR_ACK_R CRT_DDC_DATA DDPD_HPD R554 IV@150_4 INT_CRT_BLU
M1 P12 SUSB# 36
SUS_PWR_DN_ACK / GPIO30 SLP_S3#
B BJ40 B
DDPD_0N R553 IV@150_4 INT_CRT_GRN
24 INT_HSYNC Y53 BG40
SLP_M# R299 *0_4 CRT_HSYNC DDPD_0P
36 DNBSWON# P5 K8 24 INT_VSYNC Y51 BJ38
PWRBTN# SLP_M# CRT_VSYNC DDPD_1N R548 IV@150_4 INT_CRT_RED
BG38
DDPD_1P
CRT
BF37
R312 *0_4 ACIN_R DAC_IREF DDPD_2N
36 PCH_ACIN P7 N2 TP53 AD48 BH37
ACPRESENT / GPIO31 TP23 DAC_IREF DDPD_2P
AB51 BE36
CRT_IRTN DDPD_3N
BD36
PM_BATLOW# R258 DDPD_3P
A6 BJ10 PM_SYNC 4
BATLOW# / GPIO72 PMSYNCH 1K/F_4 IbexPeak-M_R1P0
PM_RI# F14 F6 PM_SLP_LAN# TP39

RI# SLP_LAN# / GPIO29
IbexPeak-M_R1P0
PCH Pull-high/low +3V_S5

System PWR_OK
+3V
PM_RI# R321 10K_4

CLKRUN# R530 8.2K_4 +3V_S5
modify 1022
PM_BATLOW# R577 8.2K_4 '(/$<B95B3:5*22'QHHG38.WR9
A XDP_DBRST# R273 10K_4 change to 8.2 K C759 *.1u_4
38DWSRZHUVLGH A
PCIE_WAKE# R329 10K_4
modify 1026 Amos 1014
5
ICH_RSMRST# R569 10K_4 PM_SLP_LAN# R330 *10K_4 1
change to 10 K DELAY_VR_PWRGOOD 4,39
SYS_PWROK 4
RSV_ICH_LAN_RST# R571 10K_4 SUS_PWR_ACK_R R565 10K_4 2
U31
PWROK_EC 36
3
SYS_PWROK R591 10K_4 ACIN_R R295 10K_4 R597 100K_4
TC7SH08FU
PROJECT : ZYD
3B
IBEX PEAK-M 1/6
5 4 3 2 1
Dr-Bios.com
5 4 3 2 1
RTC Circuitry C758

15p/50V_4
+VCCRTC
2
1
CR1 Y6
R594
+3VPCU U28A
R207 20K/F_4 RTC_RST# 32.768KHZ 10M_4
VCCRTC_1
3
4
C756
1
RTC_X1 B13 D33
RTCX1 FWH0 / LAD0 LPC_LAD0 28,36
BAT54C C402 J2 15p/50V_4 RTC_X2 D13 B33
RTCX2 FWH1 / LAD1 LPC_LAD1 28,36
1u/10V_4 *SHORT_ PAD1 C32
FWH2 / LAD2 LPC_LAD2 28,36
A32 LPC_LAD3 28,36
2
RTC_RST# FWH3 / LAD3
C14
RTCRST#
C34 LPC_LFRAME# 28,36
SRTC_RST# FWH4 / LFRAME#
D17
D
R216 20K/F_4 SRTC_RST# SRTCRST# D
A34
RTC
LPC
R570 1M_4 SM_INTRUDER# LDRQ0#
+VCCRTC A16 F34
INTRUDER# LDRQ1# / GPIO23
1
R205 R262 10K_4 +3V
1K_4 C406 C403 J1 PCH_INVRMEN A14 AB9
INTVRMEN SERIRQ IRQ_SERIRQ 36
1u/10V_4 1u/10V_4 *SHORT_ PAD1
2
HDA_SYNC (PCH strap pin) ACZ_BIT_CLK A30
HDA_BCLK SATA_RXN0_C
AK7 SATA_RXN0_C 29
ACZ_SYNC SATA0RXN SATA_RXP0_C
Internal weak pull-down D29 AK6 SATA_RXP0_C 29
HDA_SYNC SATA0RXP
VCCVRM=>+1.8V (default) AK11 SATA_TXN0 29
VCCRTC_2 SATA0TXN
1 3 RTC_N01 R204 *22K_6
+5V_S5 external pull-up 30 SPKR
SPKR P1 AK9 SATA_TXP0 29
SPKR SATA0TXP
Q19 R201 VCCVRM=>+1.5V ACZ_RST# C30
HDA_RST# SATA_RXN1_C
AH6 SATA_RXN1_C 29
*MMBT3904 *68.1K/F_4 SATA1RXN SATA_RXP1_C
AH5 SATA_RXP1_C 29
SATA1RXP
30 PCH_AZ_CODEC_SDIN0 G30 AH9 SATA_TXN1 29
2
HDA_SDIN0 SATA1TXN
1
RTC_N03 AH8 SATA_TXP1 29

CN14 TP32 SATA1TXP
F30
BAT_CONN HDA_SDIN1
AF11
R200 TP31 SATA2RXN
E32 AF9
IHDA
2
HDA_SDIN2 SATA2RXP
AF7
*150K/F_6 TP29 SATA2TXN
F32
HDA_SDIN3 SATA2TXP
AF6 Note:
SATA port2/3 may not be available on all PCH sku
AH3
ACZ_SDOUT B29
SATA3RXN
AH1
(HM55 support 3 port only)
HDA_SDO SATA3RXP
AF3
SATA3TXN
AF1
PCH_GPIO33 SATA3TXP
H32
SATA
HDA_DOCK_EN# / GPIO33
AD9
R582 *10K_4 PCH_GPIO13 SATA4RXN
+3V_S5 J30 AD8
HDA_DOCK_RST# / GPIO13 SATA4RXP
AD6
SATA4TXN
AD5
HDA Bus 25 HDMI_HPD_PCH#
SATA4TXP
M3 AD3
JTAG_TCK SATA5RXN
AD1
SATA5RXP
K3 AB3
R583 33_4 ACZ_SYNC JTAG_TMS SATA5TXN
C
30 PCH_AZ_CODEC_SYNC AB1 C
SATA5TXP
K1
JTAG_TDI
JTAG
R587 33_4 ACZ_RST# J2 AF16
30 PCH_AZ_CODEC_RST# JTAG_TDO SATAICOMPO
J4 AF15 R260 37.4/F_4 +1.05V
R586 33_4 ACZ_SDOUT TRST# SATAICOMPI
30 PCH_AZ_CODEC_SDOUT
SPI_CLK_R BA2
SPI_CLK
R584 33_4 ACZ_BIT_CLK SPI_CS0#_R AV3
30 PCH_AZ_CODEC_BITCLK SPI_CS0# SATA_ACT# 32
+3VPCU R523 *10K_4 SPI_CS1# AY3 T3

C755 SPI_CS1# SATALED#
*27p_4
SPI_SI_R AY1 Y9 R250 10K_4 +3V
SPI_MOSI SATA0GP / GPIO21
SPI
SPI_SO_R AV1 V1 R541 10K_4 +3V
SPI_MISO SATA1GP / GPIO19
Amos 1014
IbexPeak-M_R1P0 change to 10K
3&+6WUDS3LQ&RQILJXUDWLRQ7DEOH
INTVRMEN Integrated 1.05V VRM Enable / 1 = Integrated VRM is enabled
R593 330K_6 PCH_INVRMEN
Disable 0 = Integrated VRM is disabled +VCCRTC
SPI_MOSI TPM Functionality 1 = Enabled

Disable R559 *1K_4 SPI_SI_R
0 = Disable +3V
SPKR Reboot option at power-up 0 = Default Mode (Internal weak Pull-down)

MDC Bus 1 = No Reboot Mode with TCO Disabled +3V R307 *1K/F_4 SPKR
0 = Flash Descriptor Security will be overridden J3 *SHORT_ PAD1

B B
HDA_DOCK_EN Flash Descriptor 1 = Security measure defined in the Flash PCH_GPIO33 1 2
#/GPIO33 Security Override Descriptor will be enabled.
R322 10K_4 +3V
+3V
U30
SPI_CS0#_R 1 8
SPI_CLK_R CE# VDD R315 1K_4
6
SCK GNT0#, (0,0) = LPC (0,1) = Reserved NAND 10 PCI_GNT0#
SPI_SI_R 5 Boot BIOS Strap
SPI_SO_R 2
SI
7 R557 3.3K/F_4 GNT1# (1,0) = PCI (1,1) = SPI R310 1K_4
SO HOLD# 10 PCI_GNT1#
3
WP# VSS
4 GNT2#/ ESI compatible mode is for server
Amos 1014 C731 C734 ESI Strap
*22p/50V_4 W25X16AVSSIG .1u/10V_4 GPIO53 platforms only R313 *1K/F_4
(Server Only) Modify 1019 10 PCI_GNT2#
GNT3#/ Top-Block 0 = Top Block Swap Mode

R556 3.3K/F_4 Modify 1128 R560 *10K/F_4
+3V
GPIO55 Swap Override 1 = Default Mode (Internal pull-up) 10 PCI_GNT3#
IntelR Anti-Theft Technology

HDD Data Protection 1 = Enabled
NV_ALE R231 *1K/F_4
(Intel AT-d) Enable 0 = Disabled (Default) 10 NV_ALE +1.8V
NV_CLE DMI Termination DMI termination voltage. Weak

R230 *1K/F_4
Voltage internal pull-up. Do not pull low. 10 NV_CLE +1.8V
PCH SPI
GPIO8 Reserved This signal has a weak internal pull up.
R325 10K_4
NOTE: This signal should not be pulled low 11 RSV_GPIO8 +3V_S5
R320 *1K_4
0 = Intel ME Crypto Transport Layer Security

(TLS) cipher suite with no confidentiality
GPIO15 Reserved
A 1 = Intel ME Crypto Transport Layer Security11 CR_WAKE# R282 1K_4 +3V_S5 A
(TLS) cipher suite with confidentiality
Dr-Bios.com
GPIO27 On-Die PLL Voltage 0 = Disables the VccVRM.
Regulator 1 = Enables the internal VccVRM to have
<internal weak pull-up> a clean supply for analog rails. 11 PCH_GPIO27 R263 *10K_4

PROJECT : ZYD
3B
IBEX PEAK-M 2/6
5 4 3 2 1
5 4 3 2 1
U28B
U28E
H40 AY9 BG30 B9 RSV_SMBALERT#
AD0 NV_CE#0 26 PCIE_RX1- PERN1 SMBALERT# / GPIO11
N34 BD1 26 PCIE_RX1+ BJ30
AD1 NV_CE#1 C680 0.1u/10V_4_X7R PCIE_TXN1_C PERP1 ICH_SMBCLK
C44 AP15 26 PCIE_TX1- BF29 H14 ICH_SMBCLK 3
AD2 NV_CE#2 C681 0.1u/10V_4_X7R PCIE_TXP1_C PETN1 SMBCLK
A38 BD8 26 PCIE_TX1+ BH29 DIMM0/1, CLK GEN.
AD3 NV_CE#3 PETP1 ICH_SMBDATA
C36 C8 ICH_SMBDATA 3
AD4 SMBDATA
J34 AV9 28 PCIE_RX2- AW30
AD5 NV_DQS0 PERN2
A40 BG8 28 PCIE_RX2+ BA30
AD6 NV_DQS1 C405 0.1u/10V_4_X7R PCIE_TXN2_C PERP2 RSV_SML0ALERT#
D45 28 PCIE_TX2- BC30 J14
D AD7 C404 0.1u/10V_4_X7R PCIE_TXP2_C PETN2 SML0ALERT# / GPIO60 D
E36 AP7 28 PCIE_TX2+ BD30
AD8 NV_DQ0 / NV_IO0 PETP2 SMB_CLK_ME0
H48 AP6 C6 SMB_CLK_ME0 26
AD9 NV_DQ1 / NV_IO1 SML0CLK
E40 AT6 AU30 Giga LAN
SMBus
AD10 NV_DQ2 / NV_IO2 PERN3 SMB_DATA_ME0
C40 AT9 AT30 G8 SMB_DATA_ME0 26
AD11 NV_DQ3 / NV_IO3 PERP3 SML0DATA
M48 BB1 AU32
AD12 NV_DQ4 / NV_IO4 PETN3
M45 AV6 AV32
AD13 NV_DQ5 / NV_IO5 PETP3 RSV_SML1ALERT# R292 *0_4
F53 BB3 M14 SML1ALERT# 11,34,36
AD14 NV_DQ6 / NV_IO6 SML1ALERT# / GPIO74
M40 BA4 BA32
AD15 NV_DQ7 / NV_IO7 PERN4 SMB_CLK_ME1
NVRAM
M43 BE4 BB32 E10
AD16 NV_DQ8 / NV_IO8 PERP4 SML1CLK / GPIO58
J36 BB6 BD32 EC
AD17 NV_DQ9 / NV_IO9 PETN4 SMB_DATA_ME1
K48 BD6 BE32 G12
AD18 NV_DQ10 / NV_IO10 PETP4 SML1DATA / GPIO75
F40 BB7
PCI-E*
AD19 NV_DQ11 / NV_IO11
C42 BC8 BF33
AD20 NV_DQ12 / NV_IO12 PERN5 CL_CLK1
K46 BJ8 BH33 T13 CL_CLK1 28
AD21 NV_DQ13 / NV_IO13 PERP5 CL_CLK1
Controller
M51 BJ6 BG32
AD22 NV_DQ14 / NV_IO14 PETN5 CL_DATA1
J52 BG6 BJ32 T11 CL_DATA1 28
AD23 NV_DQ15 / NV_IO15 PETP5 CL_DATA1
K51
Link
AD24 NV_ALE CL_RST1#
L34 BD3 NV_ALE 9 28 PCIE_RX6- BA34 T9 CL_RST1# 28
AD25 NV_ALE NV_CLE PERN6 CL_RST1#
F42 AY6 NV_CLE 9 28 PCIE_RX6+ AW34
AD26 NV_CLE C410 0.1u/10V_4_X7R PCIE_TXN6_C PERP6
J40 28 PCIE_TX6- BC34
AD27 C409 0.1u/10V_4_X7R PCIE_TXP6_C PETN6
G46 28 PCIE_TX6+ BD34
AD28 PETP6
F44 AU2 NV_RCOMP R524 *32.4/F_4 H1 PEG_CLKREQ#_R R573 *0_4
PEG_CLKREQ# 17
AD29 NV_RCOMP PEG_A_CLKRQ# / GPIO47
M47 AT34
AD30 PERN7
PCI
H36 AV7 Amos 1014 AU34
AD31 NV_RB# PERP7
AU36 AD43 CLK_PCIE_VGA# 16
PETN7 CLKOUT_PEG_A_N
J50 AY8 AV36 AD45 CLK_PCIE_VGA 16
C/BE0# NV_WR#0_RE# PETP7 CLKOUT_PEG_A_P
G42 AY5
C/BE1# NV_WR#1_RE#
H47 BG34 AN4 CLK_PCIE_3GPLL# 4
C/BE2# PERN8 CLKOUT_DMI_N
PEG
G34 AV11 BJ34 AN2 CLK_PCIE_3GPLL 4
C/BE3# NV_WE#_CK0 PERP8 CLKOUT_DMI_P
BF5 BG36
PCI_PIRQA# NV_WE#_CK1 PETN8
G38 BJ36
PCI_PIRQB# PIRQA# PETP8
H51 AT1 DPLL_REF_SSCLK# 4
PCI_PIRQC# PIRQB# CLKOUT_DP_N / CLKOUT_BCLK1_N
B37
PIRQC# USBP0N
H18 TP35 Port1 and port9 can be used on debug mode CLKOUT_DP_P / CLKOUT_BCLK1_P
AT3 DPLL_REF_SSCLK 4
PCI_PIRQD# A44 J18 AK48
PIRQD# USBP0P TP28 CLKOUT_PCIE0N
A18 USBP1- 33 AK47
USBP1N CLKOUT_PCIE0P
From CLK BUFFER

Amos 1014 PCI_REQ0# F51 C18 MB USB modify 1223_B AW24
C PCI_REQ1# REQ0# USBP1P USBP1+ 33 CLK_PCIE_REQ0# CLKIN_DMI_N CLK_BUF_PCIE_3GPLL# 3 C
A46 N20 TP26 P9 BA24 CLK_BUF_PCIE_3GPLL 3
PCI_REQ2# REQ1# / GPIO50 USBP2N PCIECLKRQ0# / GPIO73 CLKIN_DMI_P
B45 P20 TP23
PCI_REQ3# REQ2# / GPIO52 USBP2P
M53 J20 USBP3- 31
REQ3# / GPIO54 USBP3N R202 *Short_4 CLK_PCH_SRC1N
USBP3P
L20 USBP3+ 31 USB/B 28 CLK_PCH_SRC1# AM43
CLKOUT_PCIE1N CLKIN_BCLK_N
AP3 CLK_BUF_BCLK# 3
PCI_GNT0# F48 F20 EHCI1 R203 *Short_4 CLK_PCH_SRC1P AM45 AP1
9 PCI_GNT0# PCI_GNT1# GNT0# USBP4N USBP4- 33 28 CLK_PCH_SRC1 CLKOUT_PCIE1P CLKIN_BCLK_P CLK_BUF_BCLK 3
9 PCI_GNT1# K45
GNT1# / GPIO51 USBP4P
G20 USBP4+ 33 BLUETOOTH
Amos 1014 PCI_GNT2# F36 A20 R540 *Short_4 CLK_PCIE_REQ1#_R U4
9 PCI_GNT2# GNT2# / GPIO53 USBP5N TP42 28 CLKREQ_3G# PCIECLKRQ1# / GPIO18
PCI_GNT3# H53 C20 Modify 1014 F18
9 PCI_GNT3# GNT3# / GPIO55 USBP5P TP41 CLKIN_DOT_96N CLK_BUF_DREFCLK# 3
M22 E18 CLK_BUF_DREFCLK 3
PCI_PIRQE# USBP6N USB port6/7 may not be available on all PCH sku CLKIN_DOT_96P
B41 N22 28 CLK_PCH_SRC2# AM47
PCI_PIRQF# PIRQE# / GPIO2 USBP6P CLKOUT_PCIE2N
K53 B21 (HM55 support 12port only) 28 CLK_PCH_SRC2 AM48
PCI_PIRQG# PIRQF# / GPIO3 USBP7N CLKOUT_PCIE2P
A36 D21 AH13 CLK_BUF_DREFSSCLK# 3
PCI_PIRQH# PIRQG# / GPIO4 USBP7P R566 *Short_4 CLK_PCIE_REQ2#_R CLKIN_SATA_N / CKSSCD_N
A48 H22 USBP8- 24 28 PCIE_CLK_REQ2# N4 AH12 CLK_BUF_DREFSSCLK 3
PIRQH# / GPIO5 USBP8N PCIECLKRQ2# / GPIO20 CLKIN_SATA_P / CKSSCD_P
USBP8P
J22 USBP8+ 24 Camera
USB
PCI_RST# K6 E22 USBP9-

28 PCI_RST# PCIRST# USBP9N TP40
F22 USBP9+ AH42 P41
USBP9P TP38 CLKOUT_PCIE3N REFCLK14IN CLK_ICH_14M 3
PCI_SERR# E44 A22 AH41
PCI_PERR# SERR# USBP10N USBP10- 28 CLKOUT_PCIE3P
E50 C22 Mini Card (3G) C705 18p/50V_4
PERR# USBP10P USBP10+ 28 CLK_PCIE_REQ3# CLK_PCI_FB
USBP11N
G24 USBP11- 31 EHCI2 A8
PCIECLKRQ3# / GPIO25 CLKIN_PCILOOPBACK
J42
USBP11P
H24 USBP11+ 31 USB and cardreader/B
1
PCI_IRDY# A42 L24
PCI_PAR IRDY# USBP12N USBP12- 31 XTAL25_IN
TP34 H44 M24 Card Reader AM51 AH51 R537 Y5
PCI_DEVSEL# PAR USBP12P USBP12+ 31 CLKOUT_PCIE4N XTAL25_IN XTAL25_OUT
F46 A24 AM53 AH53 1M_4 25MHz
PCI_FRAME# DEVSEL# USBP13N USBP13- 28 CLKOUT_PCIE4P XTAL25_OUT
C46 C24 Mini Card (WLAN)
2
FRAME# USBP13P USBP13+ 28 CLK_PCIE_REQ4# M9 AF38 XCLK_RCOMP R253 90.9/F_4 +1.05V C708 18p/50V_4
PCI_PLOCK# PCIECLKRQ4# / GPIO26 XCLK_RCOMP
D49
PLOCK#
B25 USB_BIAS R581 22.6/F_4
PCI_STOP# USBRBIAS# CLK_FLEX0 T66
D41 AJ50 T45
PCI_TRDY# STOP# CLKOUT_PCIE5N CLKOUTFLEX0 / GPIO64
C48 D25 AJ52
TRDY# USBRBIAS CLKOUT_PCIE5P
ICH_PME# M7 CLK_PCIE_REQ5# H6 P43 CLK_FLEX1 T68
Clock Flex
TP37 PME# PCIECLKRQ5# / GPIO44 CLKOUTFLEX1 / GPIO65
N16 USB_OC0#
PCI_PLTRST# OC0# / GPIO59 USB_OC0# 33 Modify 1016
D5 J16 USB_OC1_5# 31
PLTRST# OC1# / GPIO40 USB_OC2# CLK_FLEX2 T65
F16 TP16 26 CLK_PCIE_LOM# AK53 T42
R555 22_4 CLK_LPC_DEBUG_C OC2# / GPIO41 USB_OC3# CLKOUT_PEG_B_N CLKOUTFLEX2 / GPIO66
28 CLK_LPC_DEBUG N52 L16 TP15 Modify 26 CLK_PCIE_LOM AK51
TP30
CLK_PCI_PCCARD P53
CLKOUT_PCI0 OC3# / GPIO42
E14 USB_OC4#
TP17
1019 CLKOUT_PEG_B_P
B CLK_PCI_775_C CLKOUT_PCI1 OC4# / GPIO43 PCIE_CLK_REQB# B
36 CLK_PCI_775
R304 22_4 P46 G16 Modify 1020 26 CLK_PCIE_LAN_REQ# R547 *Short_4 P13 N50 CLK_FLEX3 T67 modify 1014
CLK_PCI_FB R296 22_4 CLK_PCI_FB_C CLKOUT_PCI2 OC5# / GPIO9 USB_OC6# PEG_B_CLKRQ# / GPIO56 CLKOUTFLEX3 / GPIO67
P51 F12 TP18
CLKOUT_PCI3 OC6# / GPIO10 USB_OC7#
P48 T15 TP20
CLKOUT_PCI4 OC7# / GPIO14 IbexPeak-M_R1P0
IbexPeak-M_R1P0
SMB Pull up
+3V_S5
+3V_S5
Modify 1019 +3V_S5
RP2 R291 10K_4 CLK_PCIE_REQ0#
USB_OC7# 6 5 R580 10K_4 CLK_PCIE_REQ3# R334
USB_OC6# 7 4 USB_OC0# R303 10K_4 CLK_PCIE_REQ4#
2
8 3 USB_OC1_5# Modify 1022 R308 10K_4 CLK_PCIE_REQ5# 2.2K_4
USB_OC4# 9 2 USB_OC2# R552 10K_4 PCIE_CLK_REQB#
+3V_S5 10 1 USB_OC3# R575 IV@10K_4 PEG_CLKREQ#_R +3V_S5 1 3 SMB_CLK_ME1
+3V_S5 36 2ND_MBCLK
Q22
8.2K_10P8R +3V R572 10K_4 RSV_SMBALERT# 2N7002K
R339 10K_4 RSV_SML0ALERT#
C463 R543 10K_4 CLK_PCIE_REQ1#_R R297 10K_4 RSV_SML1ALERT# +3V_S5
+3V R326 2.2K_4 ICH_SMBCLK
.1u/10V_4 RP3 +3V R579 2.2K_4 ICH_SMBDATA
PCI_PIRQD# 6 5 R578 2.2K_4 SMB_CLK_ME0
5
PCI_REQ1# 7 4 PCI_REQ3# R331 2.2K_4 SMB_DATA_ME0

PCI_PLTRST# 2 PCI_FRAME# 8 3 PCI_PIRQB# Amos 1014 R335
4 PCI_TRDY# 9 2 PCI_REQ0# R318 8.2K_4 PCI_REQ2#
PLTRST# 4,11,26,28,31,36
2
1 10 1 PCI_PIRQH# R323 8.2K_4 PCI_PIRQE# 2.2K_4
A
+3V A
R558 8.2K_4 PCI_PIRQF#
U12 R301 8.2K_10P8R R596 8.2K_4 PCI_PIRQG# 1 3 SMB_DATA_ME1
3
CLK_PCIE_REQ2#_R 36 2ND_MBDATA
TC7SH08FU R567 10K_4 Q23
100K_4 2N7002K
+3V R574 EV@10K/F_4 PEG_CLKREQ#_R
RP4
PCI_PIRQC# 6 5
R300 *0_4 PCI_PIRQA# 7 4 PCI_PERR#
PCI_STOP# 8 3 PCI_PLOCK#
PCI_IRDY# 9 2 PCI_DEVSEL#
+3V 10 1 PCI_SERR# Quanta Computer Inc.
8.2K_10P8R
PROJECT : ZYD
3B
IBEX PEAK-M 3/6
5 4 3 2 1
Dr-Bios.com
5 4 3 2 1
GPU RST#
R406 *Short_4
D +3V D
IBEX PEAK-M (GPIO,VSS_NCTF,RSVD) C578 *EV@.1u_4
U28F
5
TP52 BMBUSY# Y3 AH45 1
BMBUSY# / GPIO0 CLKOUT_PCIE6N PLTRST# 4,10,26,28,31,36
CLKOUT_PCIE6P AH46 16 GPU_RST# 4
36 SIO_EXT_SMI# SIO_EXT_SMI# C38 2 dGPU_HOLD_RST#
TACH1 / GPIO1
3
36 SIO_EXT_SCI# SIO_EXT_SCI# D37 U22
TACH2 / GPIO6 *EV@TC7SH08FU R411
CLKOUT_PCIE7N AF48
MISC
TP54 BOARD_ID0 J32 AF47 *EV@100K_4
TACH3 / GPIO7 CLKOUT_PCIE7P
RSV_GPIO8 F10
9 RSV_GPIO8 GPIO8
TP27 LAN_DISABLE# K9 U2
LAN_PHY_PWR_CTRL / GPIO12 A20GATE SIO_A20GATE 36
CR_WAKE# T7
9 CR_WAKE# GPIO15
dGPU_HOLD_RST# AA2 AM3
SATA4GP / GPIO16 CLKOUT_BCLK0_N / CLKOUT_PCIE8N CLK_CPU_BCLK# 4
21,36 dGPU_PWROK R327 dGPU_PWROK_R

*EV@0_4 F38 AM1
TACH0 / GPIO17 CLKOUT_BCLK0_P / CLKOUT_PCIE8P CLK_CPU_BCLK 4
modify 1024 TP19 GPIO22 Y7 BG10

SCLOCK / GPIO22 PECI H_PECI 4
GPIO
TP33 H10 T1
GPIO Pull-up/Pull-down
GPIO24 RCIN# SIO_RCIN# 36
PCH_GPIO27 AB12 BE10
9 PCH_GPIO27 GPIO27 PROCPWRGD H_PWRGOOD 4
CPU
+3V_S5
TP_PCH_GPIO28 V13 BD10 PCH_THRMTRIP#_R R227 56/F_4
GPIO28 THRMTRIP# PM_THRMTRIP# 4
C C
STP_PCI# M11 R219 56/F_4 +1.1V_VTT
STP_PCI# / GPIO34 TP_PCH_GPIO28 R284 10K_4
R272 *EV@0_4 dGPU_VRON_R V6 GPIO45 R576 10K_4
21,43 dGPU_VRON SATACLKREQ# / GPIO35 RST_GATE# R348 10K_4
38 dGPU_PWR_EN# R255 dGPU_PWR_EN#_R
*EV@0_4 AB7 BA22 GPIO57 R332 *10K_4
SATA2GP / GPIO36 TP1 LAN_DISABLE# R285 10K_4
modidy 1019 TP14 dGPU_PRSNT# AB13 AW22
SATA3GP / GPIO37 TP2 +3V
GPIO38 V3 BB22
SLOAD / GPIO38 TP3 SIO_EXT_SMI# R337 10K_4
modify 1019 GPIO39 P3 AY45 SIO_EXT_SCI# R588 10K_4
SDATAOUT0 / GPIO39 TP4
GPIO45 H3 AY46 dGPU_PWR_EN#_R R265 10K_4
PCIECLKRQ6# / GPIO45 TP5 dGPU_PWROK_R R336 10K_4
35 RST_GATE# F1 AV43
PCIECLKRQ7# / GPIO46 TP6
SV_SET_UP
modify 1024 +3V
modify 1223_B AB6 SDATAOUT1 / GPIO48 TP7 AV45
10,34,36 SML1ALERT# R283 *Short_4 SATA5GP AA4 AF13 SIO_RCIN# R562 10K_4
SATA5GP / GPIO49 TP8 SIO_A20GATE R563 10K_4
EC suggestion use GPIO49 for FAN control GPIO57 F8 M18 dGPU_HOLD_RST# R532 10K_4
GPIO57 TP9 SATA5GP R275 10K_4
N18 GPIO22 R276 10K_4
TP10
A4 AJ24 GPIO39 R564 10K_4
VSS_NCTF_1 TP11 STP_PCI# R280 10K_4
A49
NCTF
VSS_NCTF_2
RSVD
SATA5GP / GPIO49 / TEMP_ALERT# is used to A5

VSS_NCTF_3 TP12
AK41
A50 GPIO38 R538 10K_4
alert for EC when CPU or Graph/Memory A52
VSS_NCTF_4
AK42
VSS_NCTF_5 TP13
B
controllers' temperature go out of limit. A53 VSS_NCTF_6
BMBUSY# R531 8.2K_4
B
So connecting GPIO49 to EC and avoid this B2 VSS_NCTF_7 TP14 M32
B4 SV_SET_UP R268 10K_4
pin to be used for other purpose VSS_NCTF_8
B52 N32
VSS_NCTF_9 TP15
B53 VSS_NCTF_10
BE1 VSS_NCTF_11 TP16 M30 SV_SET_UP 1-X High = Strong (Default)
BE53
VSS_NCTF_12
BF1 N30
VSS_NCTF_13 TP17
BF53 VSS_NCTF_14
BH1 H12 GPIO57 stuff PD and not stuff PU for Intel suggestion at 6/1
VSS_NCTF_15 TP18
BH2
VSS_NCTF_16 GPIO57 R319 10K_4
BH52 AA23
VSS_NCTF_17 TP19
BH53 VSS_NCTF_18
BJ1 AB45 dGPU_VRON_R R271 *10K_4
VSS_NCTF_19 NC_1
BJ2 VSS_NCTF_20 modify 1116
BJ4 VSS_NCTF_21 NC_2 AB38
BJ49
VSS_NCTF_22 R592 EV@10K_4
BOARD_ID0 R595 IV@10K_4
BJ5 AB42 +3V
VSS_NCTF_23 NC_3
BJ50 VSS_NCTF_24
BJ52 AB41 R251 IV@10K_4dGPU_PRSNT# R254 EV@10K_4
VSS_NCTF_25 NC_4
BJ53
VSS_NCTF_26 dGPU always exist
D1 T39
VSS_NCTF_27 NC_5
D2 VSS_NCTF_28
D53 VSS_NCTF_29
E1 P6 TP_INT3_3V modify 1116 Integrated Clock Chip Enable
VSS_NCTF_30 INIT3_3V# TP21
E53
VSS_NCTF_31 High = Discrete
C10
TP24 BOARD_ID0
IbexPeak-M_R1P0 Low = IV
High = Disable
A RSV_GPIO8 A
Low = Enable
5
Dr-Bios.com 4 3 2
Size
Date:
Document Number
IBEX PEAK-M 4/6
Tuesday, April 06, 2010
PROJECT : ZYD
1
Sheet 11 of 50
Rev
3B
5 4 3 2 1
IBEX PEAK-M (POWER) U28G POWER VCCADAC= 69mA(15mils)

+1.05V R290 *Short_8 +1.05V_VCCCORE_ICH AB24 AE50 +VCCA_DAC_1_2 L57 +3V
VCCCORE[1] VCCADAC[1] PBY160808T/2A/180ohm_6
AB26
R289 *Short_8 VCCCORE[2]
AB28 AE52
C442 C439 VCCCORE[3] VCCADAC[2] C720 C732 C789 C786 C721
AD26
VCCCORE[4]
CRT
AD28 AF53
modify 1223_B 10u/6.3V_8 1u/6.3V_4 AF26
VCCCORE[5]
VCCCORE[6]
VSSA_DAC[1] .01u/25V_4 10u/6.3V_6 1U/10V/X5R_6 10u/6.3V_6 0.1u/10V_4_X7R U28J POWER VCCIO = 3.208A(150mils)
VCC CORE
AF28
VCCCORE[7] VSSA_DAC[2]
AF51 VCCACLK= 52mA(15mils)
AF30 VCCALVDS= 1mA +1.05V L32 *10uh_8 +V1.1LAN_VCCA_CLK AP51 V24 +1.05V
VCCCORE[8] VCCALVDS R264 IV@0_4 C428 *10u/6.3V_6 VCCACLK[1] VCCIO[5]
AF31 +3V V26
VCCCORE[9] R256 C429 *1u/6.3V_4 VCCIO[6] C454 1U/6.3V_4
AH26 AP53 Y24
VCCCORE[10] VCCACLK[2] VCCIO[7]
VCCCORE(+1.05V) = 1.432A(80mils) AH28 Y26
VCCCORE[11] EV@0_4 VCCIO[8]
AH30
VCCCORE[12] Amos 1014 VCCLAN = 320mA(30mils)
AH31 AH38 C436 +1.05V R259 *Short_6 +1.05V_VCCAUX AF23 V28 +3V_S5_VCCPUSB R324 *Short_8 +3V_S5
D VCCCORE[13] VCCALVDS IV@0.1u/10V_4 VCCLAN[1] VCCSUS3_3[1] D
AJ30 U28
VCCCORE[14] VCCSUS3_3[2] C464 0.1u/10V_4_X7R
AJ31 AH39 AF24 U26
VCCCORE[15] VSSA_LVDS VCCLAN[2] VCCSUS3_3[3] C465 0.1u/10V_4_X7R
U24
C443 VCCSUS3_3[4] C470 0.022U/16V_4
VCCTX_LVDS= 59mA(15mils) VCCSUS3_3[5]
P28
AP43 1U/6.3V_4 TP_PCH_VCCDSW Y20 P26
VCCTX_LVDS[1] VCCTX_LVDS L54 IV@0.1UH_8/250mA DCPSUSBYP VCCSUS3_3[6]
AP45 +1.8V N28
VCCTX_LVDS[2] C451 VCCSUS3_3[7]
AT46 N26
LVDS
R220 *Short_6+1.05V_PCH_VCCDPLL_EXP VCCTX_LVDS[3] C424 C707 C709 R528 VCCSUS3_3[8]
+1.05V AK24 AT45 AD38 M28
VCCIO[24] VCCTX_LVDS[4] 0.1u/10V_4 VCCME[1] VCCSUS3_3[9]
EV@0_4 M26
IV@.01u/25V_4 IV@.01u/25V_4 IV@22u/6.3V_8 VCCSUS3_3[10]
AD39 L28
VCCSUS3_3 = 0.163A(20mils)
USB
L29 *1uh_6 +V1.1LAN_VCCAPLL_EXP VCCME[2] VCCSUS3_3[11]
40mA(15mils) +1.05V BJ24 L26
VCCAPLLEXP VCCSUS3_3[12]
AB34 AD41 J28
C408 *10u/6.3V_6 VCC3_3[2] VCCME[3] VCCSUS3_3[13]
J26
VCCSUS3_3[14] R287 *Short_6
AN20
VCCIO[25] VCC3_3[3]
AB35 VCC3_3 = 357mA(30mils) AF43
VCCME[4] VCCSUS3_3[15]
H28 +1.05V
AN22 H26
HVCMOS
VCCIO[26] +3V_VCC_GIO R281 *Short_6 VCCSUS3_3[16]
AN23 AD35 VCCME(+1.05V) = 1.849A(100mils) AF41 G28
AN24
VCCIO[27]
VCCIO[28]
VCC3_3[4] +3V VCCME[5] VCCSUS3_3[17]
VCCSUS3_3[18]
G26 V5REF_SUS< 1mA
AN26 C445 +1.05V R266 *Short_8 +1.05V_VCCEPW AF42 F28 R585 100/F_4 +5V_S5
VCCIO[29] VCCME[6] VCCSUS3_3[19]
VCCIO = 3.062A(150mils) AN28
VCCIO[30] VCCSUS3_3[20]
F26
+1.05V BJ26 .1u/16V_4 R302 *Short_8 V39 E28 D22 RB500V-40 +3V_S5
Clock and Miscellaneous

BJ28 E26
VCCIO[32] VCCSUS3_3[22] C749 1U/6.3V_4
AT26 V41 C28
AT28 C26
VCCIO[34] C449 22U/6.3V_8 VCCSUS3_3[24]
AU26 V42 B27
AU28
VCCIO[36]
VCCVRM= 196mA(15mils) VCCSUS3_3[26]
A28
C427 10U/6.3V_8 AV26 C456 22U/6.3V_8 Y39 A26
C414 1U/6.3V_4 VCCIO[37] +VCCVRM R244 *Short_6 VCCME[10] VCCSUS3_3[27]
AV28 AT24
C419 1U/6.3V_4 AW26
VCCIO[38]
VCCIO[39]
VCCVRM[2] +V1.5S_1.8S
C452 1U/6.3V_4 Y41
VCCME[11] VCCSUS3_3[28]
U23 V5REF< 1mA
C437 1U/6.3V_4 AW28 R316 100/F_4 +5V
VCCIO[40]
DMI
C417 1U/6.3V_4 BA26 AT16 +VCCDMI R237 *Short_4 +1.1V_VTT VCCDMI= 61mA(15mils) C455 1U/6.3V_4 Y42 V23
VCCIO[41] VCCDMI[1] VCCME[12] VCCIO[56] D14 RB500V-40
BA28 +3V
VCCIO[42] V5REF_SUS
BB26 AU16 F24
C VCCIO[43] VCCDMI[2] V5REF_SUS C468 1U/6.3V_4 C
BB28
VCCIO[44] +VCCRTCEXT
BC26 V9
VCCIO[45] DCPRTC
PCI E*
BC28 C423 C457 0.1u/10V_4_X7R
VCCIO[46] 1u/10V_4
BD26
VCCIO[47] V5REF
BD28 K49
VCCIO[48] V5REF
BE26 AM16 +V1.5S_1.8S AU24
PCI/GPIO/LPC
VCCIO[49] VCCPNAND[1] VCCVRM[3]
BE28
VCCIO[50] VCCPNAND[2]
AK16 VCCPNAND= 156mA(15mils)
BG26 AK20 J38 +3V_VCCPPCI R309 *Short_6 +3V
VCCIO[51] VCCPNAND[3] VCCPNAND R226 *Short_8 VCC3_3[8]
BG28 AK19 +1.8V BB51
VCCIO[52] VCCPNAND[4] +V1.1LAN_VCCA_A_DPL VCCADPLLA[1]
BH27
VCCIO[53] VCCPNAND[5]
AK15 68mA(15mils) BB53
VCCADPLLA[2] VCC3_3[9]
L38 VCC3_3 = 0.357A(30mils)
AK13 C432 C469 0.1u/10V_4_X7R
VCCPNAND[6]
AN30 AM12 M36
VCCIO[54] VCCPNAND[7] VCC3_3[10]
NAND / SPI
AN31 AM13 .1u/16V_4 69mA(15mils) +V1.1LAN_VCCA_B_DPL BD51
VCCIO[55] VCCPNAND[8] VCCADPLLB[1]
AM15 BD53 N36
VCCPNAND[9] VCCADPLLB[2] VCC3_3[11] C466 0.1u/10V_4_X7R
+3V R527 *Short_6 +3V_VCCA3GBG AN35 +1.05V AH23 P36
VCC3_3[1] VCCIO[21] VCC3_3[12]
AJ35
VCCIO[22]
37mA(15mils) VCCIO = 3.062A(150mils) AH35
VCCIO[23] VCC3_3[13]
U35
+V1.5S_1.8S R240 *Short_6 +VCCAFDI_VRM AT22
VCCVRM[1] C434 1U/6.3V_4
VCCME3_3= 85mA(15mils) AF34
VCCIO[2]
+1.05V L30 *1uH_6 +V1.1LAN_VCCAPLL_FDI BJ18 AM8 C435 1U/6.3V_4 AD13
VCCFDIPLL VCCME3_3[1] +3V_VCCME_SPI R246 *Short_6 C438 1U/6.3V_4 VCC3_3[14]
AM9 +3V AH34
VCCME3_3[2] VCCIO[3]
FDI
AM23
VCCIO[1] VCCME3_3[3]
AP11 31mA(15mils)
C407 AP9 C430 AF32
*10u/6.3V_6 VCCME3_3[4] VCCIO[4] +V1.1LAN_VCCAPLL L55 *10uh_8
AK3 +1.05V
.1u/16V_4 +VCCSST VCCSATAPLL[1]
V12 AK1
C458 0.1u/10V_4_X7R DCPSST VCCSATAPLL[2] C698 C717
IbexPeak-M_R1P0 *1u/6.3V_4 *10u/6.3V_6
+V1.1LAN_INT_VCCSUS Y22 VCCIO = 3.062A(150mils)

C446 0.1u/10V_4_X7R DCPSUS +V1.1LAN_VCC_SATA R261 *Short_1206
AH22 +1.05V
R245 *Short_6 +1.05V_VCCDPLL_FDI VCCIO[9]
B
+1.05V B
VCCSUS3_3 = 163mA(20mils) P18 AT20 +V1.5S_1.8S C441
VCCSUS3_3[29] VCCVRM[4] 1u/10V_4
VCCVRM=196mA(15mils) HDA_SYNC (PCH strap pin) +3V_S5 R328 *Short_6 +3V_S5_VCCPSUS U19
SATA
VCCSUS3_3[30]
PCI/GPIO/LPC
AH19
R222 *Short_6 VCCIO[10]
+1.8V +V1.5S_1.8S Internal weak pull-down U20
VCCSUS3_3[31]
VCCVRM=>+1.8V (default) AD20
C459 0.1u/10V_4_X7R U22 VCCIO[11]
C413 C412
external pull-up VCCSUS3_3[32]
AF22
.1u/16V_4 .1u/16V_4 VCCVRM=>+1.5V VCCIO[12]
VRM enable by strap pin GPIO27 VCC3_3 = 0.357A(30mils) VCCIO[13]
AD19
+3V R293 *Short_6 +3V_VCCPCORE V15 AF20
which supply clean 1.05V for VCC3_3[5] VCCIO[14]
AF19
[VCCACLK,VCCAPLLEXP,VCCFDIPLL,VCCSATAPLL] VCCIO[15]
V16 AH20
VCC3_3[6] VCCIO[16]
C450 0.1u/10V_4_X7R Y16 AB19
VCC3_3[7] VCCIO[17]
AB20
L50 10uh_8 +V1.1LAN_VCCA_A_DPL VCCIO[18]
+1.05V AB22
VCCIO[19]
V_CPU_IO >1mA(15mils) AD22
C696 + R233 *Short_6 +VTT_VCCPCPU VCCIO[20]
+1.1V_VTT AT18
V_CPU_IO[1]
VCCME = 1.849A(100mils)
220u_3528 C418 R520 AA34 +1.05V_VCCEPW
CPU
1u/10V_4 C420 4.7U/6.3V_6 VCCME[13]
*0_8 Y34
C421 0.1u/10V_4_X7R VCCME[14]
AU18 Y35
L49 10uh_8 +V1.1LAN_VCCA_B_DPL C422 0.1u/10V_4_X7R V_CPU_IO[2] VCCME[15] R288 *0_4 +1.5V_SUS
AA35
VCCME[16]
C691 + VCCRTC= 2mA(15mils)
RTC
C694 +VCCRTC A12 L30 +V3.3A_1.5A_HDA_IO R294 *Short_4 +3V_S5
VCCRTC VCCSUSHDA
HDA
220u_3528 1u/10V_4
C750 0.1u/10V_4_X7R VCCSUSHDA= 6mA(15mils)
C748 0.1u/10V_4_X7R IbexPeak-M_R1P0 C471
1u/10V_4
A A
modify 1026

PROJECT : ZYD
3B
IBEX PEAK-M 5/6
5 4 3 2 1
Dr-Bios.com
5 4 3 2 1
U28I
AY7 H49
IBEX PEAK-M (GND) B11
B15
VSS[159]
VSS[160]
VSS[259]
VSS[260] H5
J24
VSS[161] VSS[261]
D B19 VSS[162] VSS[262] K11 D
B23 VSS[163] VSS[263] K43
B31 VSS[164] VSS[264] K47
B35 VSS[165] VSS[265] K7
B39 VSS[166] VSS[266] L14
B43 VSS[167] VSS[267] L18
B47 VSS[168] VSS[268] L2
B7 VSS[169] VSS[269] L22
BG12 VSS[170] VSS[270] L32
BB12 VSS[171] VSS[271] L36
U28H BB16 L40
VSS[172] VSS[272]
AB16 VSS[0] BB20 VSS[173] VSS[273] L52
BB24 VSS[174] VSS[274] M12
AA19 VSS[1] VSS[80] AK30 BB30 VSS[175] VSS[275] M16
AA22 VSS[3] VSS[82] AK32 BB38 VSS[177] VSS[277] N38
AM19 VSS[4] VSS[83] AK34 BB42 VSS[178] VSS[278] M34
AA28 VSS[7] VSS[86] AK43 BC10 VSS[181] VSS[281] M46
AB11 VSS[11] VSS[90] AK8 BC22 VSS[185] VSS[285] N24
AB15 VSS[12] VSS[91] AL2 BC32 VSS[186] VSS[286] P11
AB23 VSS[13] VSS[92] AL52 BC36 VSS[187] VSS[287] AD15
AB30 VSS[14] VSS[93] AM11 BC40 VSS[188] VSS[288] P22
AB31 VSS[15] VSS[94] BB44 BC44 VSS[189] VSS[289] P30
AB32 VSS[16] VSS[95] AD24 BC52 VSS[190] VSS[290] P32
AB39 VSS[17] VSS[96] AM20 BH9 VSS[191] VSS[291] P34
AB43 VSS[18] VSS[97] AM22 BD48 VSS[192] VSS[292] P42
C C
AB8 VSS[21] VSS[100] AM28 BE12 VSS[195] VSS[295] R2
AC2 VSS[22] VSS[101] BA42 BE16 VSS[196] VSS[296] R52
AC52 VSS[23] VSS[102] AM30 BE20 VSS[197] VSS[297] T12
AD11 VSS[24] VSS[103] AM31 BE24 VSS[198] VSS[298] T41
AD31 VSS[29] VSS[108] AM39 BE46 VSS[203] VSS[303] U30
AD32 VSS[30] VSS[109] AM42 BE48 VSS[204] VSS[304] U31
AD34 VSS[31] VSS[110] AU20 BE50 VSS[205] VSS[305] U32
AU22 VSS[32] VSS[111] AM46 BE6 VSS[206] VSS[306] U34
AD42 VSS[33] VSS[112] AV22 BE8 VSS[207] VSS[307] P38
AD46 VSS[34] VSS[113] AM49 BF3 VSS[208] VSS[308] V11
AD49 VSS[35] VSS[114] AM7 BF49 VSS[209] VSS[309] P16
AD7 VSS[36] VSS[115] AA50 BF51 VSS[210] VSS[310] V19
AE2 VSS[37] VSS[116] BB10 BG18 VSS[211] VSS[311] V20
AE4 VSS[38] VSS[117] AN32 BG24 VSS[212] VSS[312] V22
AF12 VSS[39] VSS[118] AN50 BG4 VSS[213] VSS[313] V30
Y13 VSS[40] VSS[119] AN52 BG50 VSS[214] VSS[314] V31
AH49 VSS[41] VSS[120] AP12 BH11 VSS[215] VSS[315] V32
AU4 VSS[42] VSS[121] AP42 BH15 VSS[216] VSS[316] V34
AF35 VSS[43] VSS[122] AP46 BH19 VSS[217] VSS[317] V35
AP13 VSS[44] VSS[123] AP49 BH23 VSS[218] VSS[318] V38
AN34 VSS[45] VSS[124] AP5 BH31 VSS[219] VSS[319] V43
AF45 VSS[46] VSS[125] AP8 BH35 VSS[220] VSS[320] V45
AF46 VSS[47] VSS[126] AR2 BH39 VSS[221] VSS[321] V46
AF49 VSS[48] VSS[127] AR52 BH43 VSS[222] VSS[322] V47
AF5 VSS[49] VSS[128] AT11 BH47 VSS[223] VSS[323] V49
AF8 VSS[50] VSS[129] BA12 BH7 VSS[224] VSS[324] V5
B AG2 AH48 C12 V7 B
VSS[51] VSS[130] VSS[225] VSS[325]
AG52 VSS[52] VSS[131] AT32 C50 VSS[226] VSS[326] V8
AH11 VSS[53] VSS[132] AT36 D51 VSS[227] VSS[327] W2
AH15 VSS[54] VSS[133] AT41 E12 VSS[228] VSS[328] W52
AH16 VSS[55] VSS[134] AT47 E16 VSS[229] VSS[329] Y11
AH24 VSS[56] VSS[135] AT7 E20 VSS[230] VSS[330] Y12
AH32 VSS[57] VSS[136] AV12 E24 VSS[231] VSS[331] Y15
AV18 VSS[58] VSS[137] AV16 E30 VSS[232] VSS[332] Y19
AJ19 VSS[62] VSS[141] AV34 E46 VSS[236] VSS[336] Y31
AJ23 VSS[66] VSS[145] AV49 F49 VSS[240] VSS[340] Y46
AJ26 VSS[67] VSS[146] AV5 F5 VSS[241] VSS[341] P49
AJ28 VSS[68] VSS[147] AV8 G10 VSS[242] VSS[342] Y5
AJ32 VSS[69] VSS[148] AW14 G14 VSS[243] VSS[343] Y6
AJ34 VSS[70] VSS[149] AW18 G18 VSS[244] VSS[344] Y8
AT5 VSS[71] VSS[150] AW2 G2 VSS[245] VSS[345] P24
AJ4 VSS[72] VSS[151] BF9 G22 VSS[246] VSS[346] T43
AK12 VSS[73] VSS[152] AW32 G32 VSS[247] VSS[347] AD51
AM41 VSS[74] VSS[153] AW36 G36 VSS[248] VSS[348] AT8
AN19 VSS[75] VSS[154] AW40 G40 VSS[249] VSS[349] AD47
AK26 VSS[76] VSS[155] AW52 G44 VSS[250] VSS[350] Y47
AK22 VSS[77] VSS[156] AY11 G52 VSS[251] VSS[351] AT12
AK23 VSS[78] VSS[157] AY43 AF39 VSS[252] VSS[352] AM6
AK28 VSS[79] VSS[158] AY47 H16 VSS[253] VSS[353] AT13
H20 VSS[254] VSS[354] AM5
IbexPeak-M_R1P0 H30 AK45
VSS[255] VSS[355]
A H34 VSS[256] VSS[356] AK39 A
H38 VSS[257] VSS[366] AV14
Dr-Bios.com
H42 VSS[258]
IbexPeak-M_R1P0
PROJECT : ZYD
3B
IBEX PEAK-M 6/6
5 4 3 2 1
5 4 3 2 1
+1.5V_SUS
JDIM1B
JDIM1A M_A_DQ[63:0] 5
5 M_A_A[15:0] 75 VDD1 VSS16 44
M_A_A0 98 5 M_A_DQ0 76 48
M_A_A1 A0 DQ0 M_A_DQ1 VDD2 VSS17
97 A1 DQ1 7 81 VDD3 VSS18 49
M_A_A2 96 15 M_A_DQ2 82 54
95 A3 DQ3 17 87 VDD5 VSS20 55
M_A_A4 92 4 M_A_DQ4 88 60
91 A5 DQ5 6 93 VDD7 VSS22 61
M_A_A6 90 16 M_A_DQ6 94 65
M_A_A7 86
A6 DQ6
18 M_A_DQ7
2.48A 99
VDD8 VSS23
66
D 89 A8 DQ8 21 100 VDD10 VSS25 71 D
M_A_A9 85 23 M_A_DQ9 105 72
PC2100 DDR3 SDRAM SO-DIMM

107 A10/AP DQ10 33 106 VDD12 VSS27 127
M_A_A11 84 35 M_A_DQ11 111 128
83 A12/BC# DQ12 22 112 VDD14 VSS29 133
M_A_A13 119 24 M_A_DQ13 117 134
80 A14 DQ14 34 118 VDD16 VSS31 138
M_A_A15 78 36 M_A_DQ15 123 139
A15 DQ15 M_A_DQ16 VDD17 VSS32

DQ16 39 124 VDD18 VSS33 144
109 41 M_A_DQ17 145
5 M_A_BS#0 BA0 DQ17 VSS34
108 51 M_A_DQ18 199 150
5 M_A_BS#1 BA1 DQ18 +3V VDDSPD VSS35
79 53 M_A_DQ19 151
5 M_A_BS#2 BA2 DQ19 VSS36
114 40 M_A_DQ20 77 155
5 M_A_CS#0 S0# DQ20 NC1 VSS37
121 42 M_A_DQ21 122 156
5 M_A_CS#1 S1# DQ21 NC2 VSS38
101 50 M_A_DQ22 125 161
5 M_A_CLK0 CK0 DQ22 NCTEST VSS39
103 52 M_A_DQ23 162
5 M_A_CLK0# CK0# DQ23 VSS40
102 57 M_A_DQ24 198 167
5 M_A_CLK1 CK1 DQ24 4 PM_EXTTS#0 EVENT# VSS41
104 59 M_A_DQ25 30 168
5 M_A_CLK1# CK1# DQ25 15,35 DDR3_DRAMRST# RESET# VSS42
73 67 M_A_DQ26 172
5 M_A_CKE0 CKE0 DQ26 VSS43
74 69 M_A_DQ27 173
5 M_A_CKE1 CKE1 DQ27 VSS44
115 56 M_A_DQ28 M1 +SMDDR_VREF_DQ0 1 178
5 M_A_CAS# CAS# DQ28 VREF_DQ VSS45
110 58 M_A_DQ29 +SMDDR_VREF R129 *Short_6 +SMDDR_VREF_DIMM 126 179
5 M_A_RAS# RAS# DQ29 VREF_CA VSS46
113 68 M_A_DQ30 M3 184
5 M_A_WE# WE# DQ30 VSS47
R206 10K_4 DIMM0_SA0 197 70 M_A_DQ31 R128 *EV@0_6 Modify 1017 185
SA0 DQ31 7,35 VREF_DQ_DIMM0 VSS48
R214 10K_4 DIMM0_SA1 201 129 M_A_DQ32 2 189
CLK_SCLK SA1 DQ32 M_A_DQ33 VSS1 VSS49
202 SCL DQ33 131 35 +SMDDR_VREF_DQ0 3 VSS2 VSS50 190
3,15,28 CLK_SCLK CLK_SDATA 200 141 M_A_DQ34 8 195
(204P)
3,15,28 CLK_SDATA SDA DQ34 M_A_DQ35 VSS3 VSS51
C DQ35 143 9 VSS4 VSS52 196 C
116 130 M_A_DQ36 13
5 M_A_ODT0 ODT0 DQ36 VSS5
120 132 M_A_DQ37 14
5 M_A_ODT1 ODT1 DQ37 VSS6
140 M_A_DQ38 19
5 M_A_DM[7:0] DQ38 VSS7
M_A_DM0 11 142 M_A_DQ39 20
M_A_DM1 DM0 DQ39 M_A_DQ40 VSS8
28 DM1 DQ40 147 25 VSS9
M_A_DM2 46 149 M_A_DQ41 26 203 +0.75V_DDR_VTT
M_A_DM3 63
DM2
DM3
(204P) DQ41
DQ42 157 M_A_DQ42 31
VSS10
VSS11
VTT1
VTT2 204
M_A_DM4 136 159 M_A_DQ43 +1.5V_SUS 32
M_A_DM5 DM4 DQ43 M_A_DQ44 VSS12
153 DM5 DQ44 146 37 VSS13 GND 205
M_A_DM6 170 148 M_A_DQ45 38 206
M_A_DM7 DM6 DQ45 M_A_DQ46 VSS14 GND
187 DM7 DQ46 158 43 VSS15
160 M_A_DQ47 R117
5 M_A_DQS[7:0] DQ47
M_A_DQS0 12 163 M_A_DQ48 *10K_4
M_A_DQS1 DQS0 DQ48 M_A_DQ49
29 DQS1 DQ49 165 DDR3-DIMM0_H=4_STD
M_A_DQS2 47 175 M_A_DQ50
M_A_DQS3 DQS2 DQ50 M_A_DQ51 R123 *Short_6 +SMDDR_VREF_DIMM
64 DQS3 DQ51 177 +SMDDR_VREF
M_A_DQS4 137 164 M_A_DQ52
154 DQS5 DQ53 166
M_A_DQS6 171 174 M_A_DQ54 R118 C248
5 M_A_DQS#[7:0] 188 DQS7 DQ55 176 *10K_4 470p/X7R_4
M_A_DQS#0 10 181 M_A_DQ56
M_A_DQS#1 DQS#0 DQ56 M_A_DQ57
27 DQS#1 DQ57 183
M_A_DQS#2 45 191 M_A_DQ58
62 DQS#3 DQ59 193
M_A_DQS#4 135 180 M_A_DQ60
152 DQS#5 DQ61 182
B M_A_DQS#6 169 192 M_A_DQ62 B
186 DQS#7 DQ63 194
DDR3-DIMM0_H=4_STD
Place these Caps near So-Dimm0.
+1.5V_SUS
+SMDDR_VREF_DIMM +SMDDR_VREF_DQ0
C341 C332 C350 C310 C306
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 .1u/16V_4 .1u/16V_4
C301 + C357 C365 C366 C245 C247 For Arrandale only designs--->Only method M1 should be enabled.
330u/2V_7343
10u/6.3V_6 .1u/16V_4 .1u/16V_4
For Clarksfield only designs--->Both M1 AND M3 methods should be enabled simultaneously
For Common Motherboard designs--->Both M1 AND M3 methods should be enabled simultaneously.
C316 C302 C318 C345 C321 2.2u/6.3V_6 2.2u/6.3V_6
10u/6.3V_6 10u/6.3V_6 .1u/16V_4 .1u/16V_4 .1u/16V_4
M1:PWR SMDRR_VREF
A A
+3V +0.75V_DDR_VTT M1+:voltage divider(Default)
Dr-Bios.com
M3:CPU VREF_DQ_DIMM0
C391 C395 C393 C392 C389 C388 C386
C397
2.2u/6.3V_6
C400
.1u/16V_4
1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6
PROJECT : ZYD
3B
DDRIII SO-DIMM-0
5 4 3 2 1
5 4 3 2 1
+1.5V_SUS
JDIM2A M_B_DQ[63:0] 5 JDIM2B
5 M_B_A[15:0]
M_B_A0 98 5 M_B_DQ0 75 44
M_B_A1 A0 DQ0 M_B_DQ1 VDD1 VSS16
97 A1 DQ1 7 76 VDD2 VSS17 48
M_B_A2 96 15 M_B_DQ2 81 49
95 A3 DQ3 17 82 VDD4 VSS19 54
M_B_A4 92 4 M_B_DQ4 87 55
91 A5 DQ5 6 88 VDD6 VSS21 60
M_B_A6 90 16 M_B_DQ6 93 61
86 A7 DQ7 18 94 VDD8 VSS23 65
M_B_A8 89 21 M_B_DQ8 99 66
D
M_B_A9 85
A8 DQ8
23 M_B_DQ9
2.48A 100
VDD9 VSS24
71
D

107 A10/AP DQ10 33 105 VDD11 VSS26 72
M_B_A11 M_B_DQ11

84 A11 DQ11 35 106 VDD12 VSS27 127
M_B_A12 83 22 M_B_DQ12 111 128
M_B_A13 A12/BC# DQ12 M_B_DQ13 VDD13 VSS28
119 A13 DQ13 24 112 VDD14 VSS29 133
M_B_A14 80 34 M_B_DQ14 117 134
78 A15 DQ15 36 118 VDD16 VSS31 138
M_B_DQ16

DQ16 39 123 VDD17 VSS32 139
109 41 M_B_DQ17 124 144
5 M_B_BS#0 BA0 DQ17 VDD18 VSS33
108 51 M_B_DQ18 145
5 M_B_BS#1 BA1 DQ18 VSS34
79 53 M_B_DQ19 199 150
5 M_B_BS#2 BA2 DQ19 +3V VDDSPD VSS35
114 40 M_B_DQ20 151
5 M_B_CS#0 S0# DQ20 VSS36
121 42 M_B_DQ21 77 155
5 M_B_CS#1 S1# DQ21 NC1 VSS37
101 50 M_B_DQ22 122 156
5 M_B_CLK0 CK0 DQ22 NC2 VSS38
103 52 M_B_DQ23 125 161
5 M_B_CLK0# CK0# DQ23 NCTEST VSS39
102 57 M_B_DQ24 162
5 M_B_CLK1 CK1 DQ24 VSS40
104 59 M_B_DQ25 198 167
5 M_B_CLK1# CK1# DQ25 4 PM_EXTTS#1 EVENT# VSS41
73 67 M_B_DQ26 30 168
5 M_B_CKE0 CKE0 DQ26 14,35 DDR3_DRAMRST# RESET# VSS42
74 69 M_B_DQ27 172
5 M_B_CKE1 CKE1 DQ27 VSS43
115 56 M_B_DQ28 173
5 M_B_CAS# CAS# DQ28 VSS44
110 58 M_B_DQ29 +SMDDR_VREF_DQ1 1 178
5 M_B_RAS# RAS# DQ29 35 +SMDDR_VREF_DQ1 VREF_DQ VSS45
113 68 M_B_DQ30 M1 R114 *Short_6 126 179
5 M_B_WE# WE# DQ30 +SMDDR_VREF_DIMM VREF_CA VSS46
R196 10K_4 DIMM1_SA0 197 70 M_B_DQ31 M3 R122 *EV@0_6 184
SA0 DQ31 7,35 VREF_DQ_DIMM1 VSS47
R199 10K_4 DIMM1_SA1 201 129 M_B_DQ32 185
+3V SA1 DQ32 +SMDDR_VREF_DIMM VSS48
202 131 M_B_DQ33 2 189
3,14,28 CLK_SCLK SCL DQ33 M_B_DQ34 VSS1 VSS49
3,14,28 CLK_SDATA
200 SDA DQ34 141
M_B_DQ35
Modify 1017 3 VSS2 VSS50 190
143 8 195
(204P)
C DQ35 VSS3 VSS51 C
116 130 M_B_DQ36 9 196
5 M_B_ODT0 ODT0 DQ36 VSS4 VSS52
120 132 M_B_DQ37 13
5 M_B_ODT1 ODT1 DQ37 VSS5
140 M_B_DQ38 14
5 M_B_DM[7:0] DQ38 VSS6
M_B_DM0 11 142 M_B_DQ39 19
M_B_DM1 DM0 DQ39 M_B_DQ40 VSS7
28 DM1 DQ40 147 20 VSS8
M_B_DM2 46 149 M_B_DQ41 25
M_B_DM3 63
DM2
DM3
(204P) DQ41
DQ42 157 M_B_DQ42 26
VSS9
VSS10 VTT1 203 +0.75V_DDR_VTT
M_B_DM4 136 159 M_B_DQ43 31 204
M_B_DM5 DM4 DQ43 M_B_DQ44 VSS11 VTT2
153 DM5 DQ44 146 32 VSS12
M_B_DM6 170 148 M_B_DQ45 37 205
M_B_DM7 DM6 DQ45 M_B_DQ46 VSS13 GND
187 DM7 DQ46 158 38 VSS14 GND 206
160 M_B_DQ47 43
5 M_B_DQS[7:0] DQ47 VSS15
M_B_DQS0 12 163 M_B_DQ48
M_B_DQS1 DQS0 DQ48 M_B_DQ49
29 DQS1 DQ49 165
M_B_DQS2 47 175 M_B_DQ50 DDR3-DIMM1_H=8_STD
64 DQS3 DQ51 177
M_B_DQS4 137 164 M_B_DQ52
154 DQS5 DQ53 166
M_B_DQS6 171 174 M_B_DQ54
5 M_B_DQS#[7:0] 188 DQS7 DQ55 176
M_B_DQS#0 10 181 M_B_DQ56
M_B_DQS#1 DQS#0 DQ56 M_B_DQ57
27 DQS#1 DQ57 183
M_B_DQS#2 45 191 M_B_DQ58
62 DQS#3 DQ59 193
M_B_DQS#4 135 180 M_B_DQ60
152 DQS#5 DQ61 182
B M_B_DQS#6 169 192 M_B_DQ62 B
186 DQS#7 DQ63 194
DDR3-DIMM1_H=8_STD
+1.5V_SUS Place these Caps near So-Dimm1.

+SMDDR_VREF_DIMM +SMDDR_VREF_DQ1
C346 C299 C330 C347 C340
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 .1u/16V_4 .1u/16V_4
C351 + C331 C364 C362 C246 C244

330u/2V_7343
10u/6.3V_6 .1u/16V_4 .1u/16V_4
C311 C356 C319 C307 C349 2.2u/6.3V_6 2.2u/6.3V_6

10u/6.3V_6 10u/6.3V_6 .1u/16V_4 .1u/16V_4 .1u/16V_4 For Arrandale only designs--->Only method M1 should be enabled.
For Clarksfield only designs--->Both M1 AND M3 methods should be enabled simultaneously
+3V +0.75V_DDR_VTT For Common Motherboard designs--->Both M1 AND M3 methods should be enabled simultaneously.
A C396 C383 C394 C382 C384 C390 C387 A

C401 C398 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4
Dr-Bios.com
2.2u/6.3V_6 .1u/16V_4 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6

PROJECT : ZYD
3B
DDRIII SO-DIMM-1
5 4 3 2 1
5 4 3 2 1
U18A
AA38 Y33 CPEG_RXP15 C167 EV@0.1u/10V_4_X7R

4 PEG_TXP15 PCIE_RX0P PCIE_TX0P PEG_RXP15 4
Y37 Y32 CPEG_RXN15 C157 EV@0.1u/10V_4_X7R
4 PEG_TXN15 PCIE_RX0N PCIE_TX0N PEG_RXN15 4
D D
Y35 W33 CPEG_RXP14 C154 EV@0.1u/10V_4_X7R

W36 W32 CPEG_RXN14 C139 EV@0.1u/10V_4_X7R
W38 U33 CPEG_RXP13 C144 EV@0.1u/10V_4_X7R

V37 U32 CPEG_RXN13 C128 EV@0.1u/10V_4_X7R
V35 U30 CPEG_RXP12 C123 EV@0.1u/10V_4_X7R

U36 U29 CPEG_RXN12 C127 EV@0.1u/10V_4_X7R
U38 T33 CPEG_RXP11 C112 EV@0.1u/10V_4_X7R

T37 T32 CPEG_RXN11 C106 EV@0.1u/10V_4_X7R
PCI EXPRESS INTERFACE

T35 T30 CPEG_RXP10 C114 EV@0.1u/10V_4_X7R
R36 T29 CPEG_RXN10 C122 EV@0.1u/10V_4_X7R
R38 P33 CPEG_RXP9 C100 EV@0.1u/10V_4_X7R

P37 P32 CPEG_RXN9 C92 EV@0.1u/10V_4_X7R
C C
P35 P30 CPEG_RXP8 C80 EV@0.1u/10V_4_X7R

N36 P29 CPEG_RXN8 C90 EV@0.1u/10V_4_X7R
N38 N33 CPEG_RXP7 C79 EV@0.1u/10V_4_X7R

M37 N32 CPEG_RXN7 C69 EV@0.1u/10V_4_X7R
M35 N30 CPEG_RXP6 C57 EV@0.1u/10V_4_X7R

L36 N29 CPEG_RXN6 C63 EV@0.1u/10V_4_X7R
L38 L33 CPEG_RXP5 C56 EV@0.1u/10V_4_X7R

K37 L32 CPEG_RXN5 C54 EV@0.1u/10V_4_X7R
K35 L30 CPEG_RXP4 C52 EV@0.1u/10V_4_X7R

J36 L29 CPEG_RXN4 C50 EV@0.1u/10V_4_X7R
J38 K33 CPEG_RXP3 C42 EV@0.1u/10V_4_X7R

H37 K32 CPEG_RXN3 C38 EV@0.1u/10V_4_X7R
B B
H35 J33 CPEG_RXP2 C37 EV@0.1u/10V_4_X7R

G36 J32 CPEG_RXN2 C35 EV@0.1u/10V_4_X7R
G38 K30 CPEG_RXP1 C33 EV@0.1u/10V_4_X7R

F37 K29 CPEG_RXN1 C32 EV@0.1u/10V_4_X7R
F35 H33 CPEG_RXP0 C31 EV@0.1u/10V_4_X7R

E37 H32 CPEG_RXN0 C29 EV@0.1u/10V_4_X7R
CLOCK
10 CLK_PCIE_VGA AB35 PCIE_REFCLKP
10 CLK_PCIE_VGA# AA36 PCIE_REFCLKN
For Broadway, Madison and Park
CALIBRATION
PWRGOOD is not required since it is generated internally. R29 EV@1.27K/F_4
AJ21 NC#1 PCIE_CALRP Y30
the PWRGOOD ball must be conneccted to ground AK21
R40 EV@10K_4 NC#2 R27 EV@2K/F_4
A
AH16 PWRGOOD PCIE_CALRN Y29 +1V +1.0V A
GPU_RST#
11 GPU_RST# AA30 PERSTB For M97, Broadway, Madison and Park PCIE_VDDC is 1.0V
EV@Madison/Park_M2
PROJECT : ZYD
3B
Madison/Park M2 PCIE I/F
Dr-Bios.com
5 4 3 2 1
5 4 3 2 1
GPU Power-on sequence U18B U18G
1 => +VGPU_CORE
AU24 LVDS CONTROL AK27
HDMICLK+ 25 EV_LVDS_BRIGHT 24
2 => +VGPU_IO TXCAP_DPA3P
TXCAM_DPA3N
AV23 HDMICLK- 25
VARY_BL
DIGON
AJ27 EV_LVDS_VDDEN 24
3 => +1V MUTI GFX TX0P_DPA2P

AT25
AR24
HDMITX0P 25
R53 *EV@10K_4
TX0M_DPA2N HDMITX0N 25
4 => +1.5V_GPU DPA
TX1P_DPA1P
AU26 HDMITX1P 25 TXCLK_UP_DPF3P
AK35
R57 *EV@10K_4
EV_TXUCLKOUT+ 24
AV25 AL36
5 => +3V_D TX1M_DPA1N HDMITX1N 25 TXCLK_UN_DPF3N EV_TXUCLKOUT- 24
AR8 AT27 HDMITX2P 25 AJ38
D
6 => +1.8V_GPU AU8
DVPCNTL_MVP_0
DVPCNTL_MVP_1
TX2P_DPA0P
TX2M_DPA0N
AR26 HDMITX2N 25
TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N
AK37
EV_TXUOUT0+ 24
EV_TXUOUT0- 24 D
AP8
7 => dGPU_PWROK NC on Park AW8
DVPCNTL_0
DVPCNTL_1 TXCBP_DPB3P
AR30
TXOUT_U1P_DPF1P
AH35 EV_TXUOUT1+ 24
AR3 AT29 AJ36 EV_TXUOUT1- 24
DVPCNTL_2 TXCBM_DPB3N TXOUT_U1N_DPF1N
AR1
DVPCLK
23 RAM_STRAP0 AU1
DVPDATA_0 TX3P_DPB2P
AV31
TXOUT_U2P_DPF0P
AG38 EV_TXUOUT2+ 24 Amos 1014
23 RAM_STRAP1 AU3 AU30 AH37 EV_TXUOUT2- 24
DVPDATA_1 DPB TX3M_DPB2N TXOUT_U2N_DPF0N
23 RAM_STRAP2 AW3
DVPDATA_2
AP6 AR32 AF35
T42 DVPDATA_3 TX4P_DPB1P TXOUT_U3P
AW5 AT31 AG36
DVPDATA_4 TX4M_DPB1N TXOUT_U3N
AU5
DVPDATA_5
AR6 AT33
DVPDATA_6 TX5P_DPB0P LVTMDP
1.8V GPIO AW6
DVPDATA_7 TX5M_DPB0N
AU32
AU6
DVPDATA_8
AT7 AU14 AP34 EV_TXLCLKOUT+ 24
DVPDATA_9 TXCCP_DPC3P TXCLK_LP_DPE3P
AV7 AV13 AR34 EV_TXLCLKOUT- 24
DVPDATA_10 TXCCM_DPC3N TXCLK_LN_DPE3N
AN7
DVPDATA_11
AV9 AT15 AW37 EV_TXLOUT0+ 24
DVPDATA_12 TX0P_DPC2P TXOUT_L0P_DPE2P
AT9 AR14 AU35 EV_TXLOUT0- 24
DVPDATA_13 TX0M_DPC2N TXOUT_L0N_DPE2N
AR10
DVPDATA_14 DPC
AW10 AU16 AR37 EV_TXLOUT1+ 24
AU10 AV15 AU39 EV_TXLOUT1- 24
AP10
DVPDATA_17
AV11 AT17 AP35 EV_TXLOUT2+ 24
AT11 AR16 AR35 EV_TXLOUT2- 24
AR12
NC on Park AW12
DVPDATA_20
DVPDATA_21 TXCDP_DPD3P
AU20
TXOUT_L3P
AN36
AU12 AT19 AP37
+3V_D DVPDATA_22 TXCDM_DPD3N TXOUT_L3N
AP12
DVPDATA_23
AT21
TX3P_DPD2P
AR20
TX3M_DPD2N
DPD
DP Channel D is NC on PARK
AU22
R50 R58 TX4P_DPD1P EV@Madison/Park_M2
AV21
TX4M_DPD1N
EV@10K/F_4
EV@10K/F_4 I2C AT23
TX5P_DPD0P
AR22
TX5M_DPD0N
AK26
SCL
C AJ26 C
SDA
AD39 EV_CRT_RED 24
GENERAL PURPOSE I/O R
AD37
RB
23 GPU_GPIO0 AH20
GPIO_0
23 GPU_GPIO1 AH18 AE36 EV_CRT_GRN 24
GPIO_1 G
23 GPU_GPIO2 AN16 AD35
GPIO_2 GB
23 GPIO3_SMBDAT AH23
GPIO_3_SMBDATA
23 GPIO4_SMBCLK AJ23 AF37 EV_CRT_BLU 24
GPIO_4_SMBCLK B
AH17 AE38
T13 GPIO_5_AC_BATT DAC1 BB
44 IO_VID0 AJ17
GPIO_6 R393 R390 R388
24 EV_LVDS_BLON AK17 AC36 EV_HSYNC 23,24
GPIO_7_BLON HSYNC
23 SOUT_GPIO8 AJ13 AC38 EV_VSYNC 23,24 EV@150/F_4 EV@150/F_4
GPIO_8_ROMSO VSYNC EV@150/F_4
23 SIN_GPIO9 AH15
GPIO_9_ROMSI
23 SCLK_GPIO10 AJ16
+3V_D GPIO_10_ROMSCK R32 EV@499/F_4
23 GPU_GPIO11 AK16 AB34
GPIO_11 RSET
23 GPU_GPIO12 AL16
GPIO_12 AVDD
23 GPU_GPIO13 AM16 AD34
GPIO_13 AVDD +1.8V_GPU
AM14 AE34
R59 T32 GPIO_14_HPD2 AVSSQ
3.3V GPIO 43 VCORE1.2ID0 AM13
GPIO_15_PWRCNTL_0 (1.8V@70mA AVDD)
EV@10K_4 AK14 AC33 VDD1DI 120 ohm/300mA
GPIO_16_SSIN VDD1DI AVDD L42 EV@SBY100505T-121Y-N/0.3A/120ohm_4
23 ALT#_GPIO17 AG30 AC34
GPIO_17_THERMAL_INT VSS1DI
AN14
T36 GPIO_18_HPD3
AM17
GPIO_19_CTF C562 C561 C560 C791
43 VCORE1.2ID1 AL13 AC30
+3V_D GPIO_20_PWRCNTL_1 R2 EV@0.1u/10V_4_X7R EV@10u/6.3V_6*EV@10u/6.3V_6
AJ14 AC31
R66 T16 GPIO_21_BB_EN R2B EV@1u/6.3V_4
23 SCS#_GPIO22 AK13
*EV@10K/F_4 GPIO_22_ROMCSB
AN13 AD30
R101 *EV@10K/F_4 GPIO24_TRSTB GPIO_23_CLKREQB G2
AM23
JTAG_TRSTB G2B
AD31 (1.8V@100mA VDD1DI)
R108 R408 *EV@10K/F_4 T33 AN23 120 ohm/300mA
+3V_D JTAG_TDI
*EV@10K/F_4 27M_CLK AK23 AF30 VDD1DI L5 EV@SBY100505T-121Y-N/0.3A/120ohm_4
3 27M_CLK JTAG_TCK B2
R102 *EV@10K/F_4 AL24 AF31
T46 JTAG_TMS B2B
AM24
JTAG_TDO DAC2 will be NC on future ASIC
+3V_D R407 *EV@10K/F_4 AJ19 C187 C188 C189 C790
10 PEG_CLKREQ# GENERICA
AK19 AC32 EV@0.1u/10V_4_X7R EV@10u/6.3V_6*EV@10u/6.3V_6
GENERICB C EV@1u/6.3V_4
R107
modify 1022_Reserved workaround for A11 Revision AJ20
GENERICC Y
AD32
AK20 AF32
GENERICD COMP
*EV@10K/F_4 AJ24
B GENERICE_HPD4 DAC2 B
AH26
GENERICF T12
GenericF/G is NC on PARK AH24
GENERICG H2SYNC
AD29
AC29 V2SYNC 23
V2SYNC
Amos 1013
25 HDMI_HP_EV AK24
+1.8V_GPU HPD1 VDD1DI
AG31
VDD2DI
AG32
VSS2DI +3V_D
R86 AG33 (3.3V@130mA A2VDD)

A2VDD
EV@499/F_4
AD33 A2VDDQ C165
VREFG A2VDDQ EV@0.1u/10V_4_X7R
AH13
VREFG
AF33
A2VSSQ
R87 C222 +1.8V_GPU
AA29 R34 EV@715/F_4 (1.8V@2mA A2VDDQ)
EV@249/F_4 EV@0.1u/10V_4_X7R R2SET 120 ohm/300mA
+1.8V(75mA) A2VDDQ L41 EV@SBY100505T-121Y-N/0.3A/120ohm_4
120 ohm/300mA
+1.8V_GPU L14 EV@SBY100505T-121Y-N/0.3A/120ohm_4 DPLL_PVDD DDC/AUX AM26 MXM_DDCCK 25
PLL/CLOCK DDC1CLK C559 C552
AN26
C213 C200 C196 DPLL_PVDD AM32
DPLL_PVDD
DDC1DATA MXM_DDCDAT 25
HDMI EV@0.1u/10V_4_X7R
AN32 AM27 EV@1u/6.3V_4
EV@10u/6.3V_6 EV@0.1u/10V_4_X7R R422 *EV@0_4 DPLL_PVSS AUX1P T41
3 CLK_27M_SS AL27
EV@1u/6.3V_4 AUX1N T43
DPLL_VDDC AN31 AM19
C584 EV@27p/50V_4 DPLL_VDDC DDC2CLK T35
AL19
DDC2DATA T22
+1.0V(125mA)
2
120 ohm/300mA XTALI_27M AV33 AN20

L22 EV@SBY100505T-121Y-N/0.3A/120ohm_4 DPLL_VDDC Y3 R421 XTALO_27M XTALIN AUX2P T28
+1V AU34 AM20
EV@1M_4 XTALOUT AUX2N T21
C231 C216 C212 EV@27MHZ AL30
1
DDCCLK_AUX3P T17
AM30
EV@10u/6.3V_6 EV@0.1u/10V_4_X7R C583 EV@27p/50V_4 DDCDATA_AUX3N T44
EV@1u/6.3V_4 AL29
DDCCLK_AUX4P T34
A
23 GPU_D+ AF29
AG29
DPLUS THERMAL DDCDATA_AUX4N
AM29
T39
DDCxx_AUX4x is NC on PARK A
23 GPU_D- DMINUS
+1.8V(5mA) AN21
120 ohm/300mA DDCCLK_AUX5P
AM21
EV_LVDS_DDCCLK
EV_LVDS_DDCDAT
24
24
LVDS
Dr-Bios.com
L6 EV@SBY100505T-121Y-N/0.3A/120ohm_4 TS_VDD T27 DDCDATA_AUX5N
+1.8V_GPU AK32
TS_VDD TS_FDO
AJ32 AJ30
C207 C206 AJ33
TSVDD
TSVSS
DDC6CLK
DDC6DATA
AJ31
EV_CRTDCLK
EV_CRTDDAT
24
24
CRT
EV@10u/6.3V_6 EV@0.1u/10V_4_X7R AK30
NC_DDCCLK_AUX7P T38
NC_DDCDATA_AUX7N
AK29
T23
DDCxx_AUX7x is NC on M9x and PARK
EV@Madison/Park_M2
PROJECT : ZYD
3B
Madison/Park M2 HOST I/F
5 4 3 2 1
5 4 3 2 1
VMA_DQ[63..0] VMB_DQ[63..0]
19 VMA_DQ[63..0] 20 VMB_DQ[63..0]
VMA_DM[7..0] VMB_DM[7..0]
19 VMA_DM[7..0] 20 VMB_DM[7..0]
U18C U18D
VMA_RDQS[7..0] DDR2 DDR2 VMB_RDQS[7..0] DDR2 DDR2
19 VMA_RDQS[7..0] GDDR3/GDDR5 GDDR5/GDDR3 20 VMB_RDQS[7..0] GDDR3/GDDR5 GDDR5/GDDR3
VMA_WDQS[7..0] DDR3 DDR3 VMB_WDQS[7..0] DDR3 DDR3
19 VMA_WDQS[7..0] 20 VMB_WDQS[7..0]
VMA_DQ0 C37 G24 VMA_MA0 VMB_DQ0 C5 P8 VMB_MA0
VMA_DQ1 DQA0_0/DQA_0 MAA0_0/MAA_0 VMA_MA1 VMB_DQ1 DQB0_0/DQB_0 MAB0_0/MAB_0 VMB_MA1
C35 J23 C3 T9
MEMORY INTERFACE A
D
VMA_DQ2 DQA0_1/DQA_1 MAA0_1/MAA_1 VMA_MA2 VMB_MA[13..0] VMB_DQ2 DQB0_1/DQB_1 MAB0_1/MAB_1 VMB_MA2 D
A35 H24 E3 P9
MEMORY INTERFACE B
VMA_MA[13..0] DQA0_2/DQA_2 MAA0_2/MAA_2 20 VMB_MA[13..0] DQB0_2/DQB_2 MAB0_2/MAB_2
VMA_DQ3 E34 J24 VMA_MA3 VMB_DQ3 E1 N7 VMB_MA3
19 VMA_MA[13..0] DQA0_3/DQA_3 MAA0_3/MAA_3 DQB0_3/DQB_3 MAB0_3/MAB_3
VMA_DQ4 G32 H26 VMA_MA4 VMB_DQ4 F1 N8 VMB_MA4
VMA_DQ5 DQA0_4/DQA_4 MAA0_4/MAA_4 VMA_MA5 VMB_BA0 VMB_DQ5 DQB0_4/DQB_4 MAB0_4/MAB_4 VMB_MA5
D33 J26 20 VMB_BA0 F3 N9
VMA_BA0 VMA_DQ6 DQA0_5/DQA_5 MAA0_5/MAA_5 VMA_MA6 VMB_BA1 VMB_DQ6 DQB0_5/DQB_5 MAB0_5/MAB_5 VMB_MA6
19 VMA_BA0 F32 H21 20 VMB_BA1 F5 U9
VMA_BA1 VMA_DQ7 DQA0_6/DQA_6 MAA0_6/MAA_6 VMA_MA7 VMB_BA2 VMB_DQ7 DQB0_6/DQB_6 MAB0_6/MAB_6 VMB_MA7
19 VMA_BA1 E32 G21 20 VMB_BA2 G4 U8
VMA_BA2 VMA_DQ8 DQA0_7/DQA_7 MAA0_7/MAA_7 VMA_MA8 VMB_DQ8 DQB0_7/DQB_7 MAB0_7/MAB_7 VMB_MA8
19 VMA_BA2 D31 H19 H5 Y9
F30 H20 H6 W9
C30 L13 J4 AC8
A30 G16 K6 AC9
F28 J16 K5 AA7
VMA_DQ13 DQA0_12/DQA_12 MAA1_4/MAA_12 VMA_BA2 VMB_DQ13 DQB0_12/DQB_12 MAB1_4/MAB_12 VMB_BA2
C28 H16 L4 AA8
VMA_DQ14 DQA0_13/DQA_13 MAA1_5/MAA_13_BA2 VMA_BA0 VMB_DQ14 DQB0_13/DQB_13 MAB1_5/BA2 VMB_BA0
A28 J17 M6 Y8
VMA_DQ15 DQA0_14/DQA_14 MAA1_6/MAA_14_BA0 VMA_BA1 VMB_DQ15 DQB0_14/DQB_14 MAB1_6/BA0 VMB_BA1
E28 H17 M1 AA9
VMA_DQ16 DQA0_15/DQA_15 MAA1_7/MAA_A15_BA1 Park Madison VMB_DQ16 DQB0_15/DQB_15 MAB1_7/BA1
D27 M3
VMA_DQ17 DQA0_16/DQA_16 VMA_DM0 VMB_DQ17 DQB0_16/DQB_16 VMB_DM0
F26 A32 M5 H3
VMA_DQ18 DQA0_17/DQA_17 WCKA0_0/DQMA_0 VMA_DM1 Memory 64 bit on channel B 128 bit VMB_DQ18 DQB0_17/DQB_17 WCKB0_0/DQMB_0 VMB_DM1
C26 C32 N4 H1
VMA_DQ19 DQA0_18/DQA_18 WCKA0B_0/DQMA_1 VMA_DM2 interface (channel A is NC) VMB_DQ19 DQB0_18/DQB_18 WCKB0B_0/DQMB_1 VMB_DM2
A26 D23 P6 T3
VMA_DQ20 DQA0_19/DQA_19 WCKA0_1/DQMA_2 VMA_DM3 VMB_DQ20 DQB0_19/DQB_19 WCKB0_1/DQMB_2 VMB_DM3
F24 E22 P5 T5
VMA_DQ21 DQA0_20/DQA_20 WCKA0B_1/DQMA_3 VMA_DM4 MEM_CALRP1 and MEM_CALRP[0,2] VMB_DQ21 DQB0_20/DQB_20 WCKB0B_1/DQMB_3 VMB_DM4
C24 C14 R4 AE4
VMA_DQ22 DQA0_21/DQA_21 WCKA1_0/DQMA_4 VMA_DM5 MEM_CALRN1 signals are used. VMB_DQ22 DQB0_21/DQB_21 WCKB1_0/DQMB_4 VMB_DM5
A24 A14 T6 AF5
VMA_DQ23 DQA0_22/DQA_22 WCKA1B_0/DQMA_5 VMA_DM6 Memory are used MEM_CALRP1 and VMB_DQ23 DQB0_22/DQB_22 WCKB1B_0/DQMB_5 VMB_DM6
E24 E10 T1 AK6
VMA_DQ24 DQA0_23/DQA_23 WCKA1_1/DQMA_6 VMA_DM7 Calibration NC_MEM_CALRP[0,2] MEM_CALRN1 VMB_DQ24 DQB0_23/DQB_23 WCKB1_1/DQMB_6 VMB_DM7
C22 D9 U4 AK5
VMA_DQ25 DQA0_24/DQA_24 WCKA1B_1/DQMA_7 signals are not are not connected. VMB_DQ25 DQB0_24/DQB_24 WCKB1B_1/DQMB_7
A22 V6
VMA_DQ26 DQA0_25/DQA_25 GDDR5/DDR2/GDDR3 VMA_RDQS0 connected VMB_DQ26 DQB0_25/DQB_25 GDDR5/DDR2/GDDR3 VMB_RDQS0
F22 C34 V1 F6
VMA_DQ27 DQA0_26/DQA_26 EDCA0_0/QSA_0/RDQSA_0 VMA_RDQS1 VMB_DQ27 DQB0_26/DQB_26 EDCB0_0/QSB_0/RDQSB_0 VMB_RDQS1
D21 D29 V3 K3
A20 D25 Y6 P3
F20 E20 Y1 V5
D19 E16 Y3 AB5
E18 E12 Y5 AH1
C18 J10 AA4 AJ9
A18 D7 AB6 AM5
VMA_DQ34 DQA1_1/DQA_33 EDCA1_3/QSA_7/RDQSA_7 VMB_DQ34 DQB1_1/DQB_33 EDCB1_3/QSB_7/RDQSB_7
F18 AB1
VMA_DQ35 DQA1_2/DQA_34 VMA_WDQS0 VMB_DQ35 DQB1_2/DQB_34 VMB_WDQS0
D17 A34 AB3 G7
VMA_DQ36 DQA1_3/DQA_35 DDBIA0_0/QSA_0B/WDQSA_0 VMA_WDQS1 VMB_DQ36 DQB1_3/DQB_35 DDBIB0_0/QSB_0B/WDQSB_0 VMB_WDQS1
A16 E30 AD6 K1
F16 E26 AD1 P1
D15 C20 AD3 W4
C E14 C16 AD5 AC4 C
F14 C12 AF1 AH3
D13 J11 AF3 AJ8
F12 F8 AF6 AM3
VMA_DQ43 DQA1_10/DQA_42 DDBIA1_3/QSA_7B/WDQSA_7 VMB_DQ43 DQB1_10/DQB_42 DDBIB1_3/QSB_7B/WDQSB_7
A12 AG4
VMA_DQ44 DQA1_11/DQA_43 VMA_ODT0 VMB_DQ44 DQB1_11/DQB_43 VMB_ODT0
D11 J21 VMA_ODT0 19 AH5 T7 VMB_ODT0 20
VMA_DQ45 DQA1_12/DQA_44 ADBIA0/ODTA0 VMA_ODT1 VMB_DQ45 DQB1_12/DQB_44 ADBIB0/ODTB0 VMB_ODT1
F10 G19 VMA_ODT1 19 AH6 W7 VMB_ODT1 20
VMA_DQ46 DQA1_13/DQA_45 ADBIA1/ODTA1 VMB_DQ46 DQB1_13/DQB_45 ADBIB1/ODTB1
A10 AJ4
VMA_DQ47 DQA1_14/DQA_46 VMA_CLK0 VMB_DQ47 DQB1_14/DQB_46 VMB_CLK0
C10 H27 VMA_CLK0 19 AK3 L9 VMB_CLK0 20
VMA_DQ48 DQA1_15/DQA_47 CLKA0 VMA_CLK0# VMB_DQ48 DQB1_15/DQB_47 CLKB0 VMB_CLK0#
G13 G27 VMA_CLK0# 19 AF8 L8 VMB_CLK0# 20
VMA_DQ49 DQA1_16/DQA_48 CLKA0B VMB_DQ49 DQB1_16/DQB_48 CLKB0B
H13 AF9
VMA_DQ50 DQA1_17/DQA_49 VMA_CLK1 VMB_DQ50 DQB1_17/DQB_49 VMB_CLK1
J13 J14 VMA_CLK1 19 AG8 AD8 VMB_CLK1 20
VMA_DQ51 DQA1_18/DQA_50 CLKA1 VMA_CLK1# VMB_DQ51 DQB1_18/DQB_50 CLKB1 VMB_CLK1#
H11 H14 VMA_CLK1# 19 AG7 AD7 VMB_CLK1# 20
VMA_DQ52 DQA1_19/DQA_51 CLKA1B VMB_DQ52 DQB1_19/DQB_51 CLKB1B
G10 AK9
VMA_DQ53 DQA1_20/DQA_52 VMA_RAS0# VMB_DQ53 DQB1_20/DQB_52 VMB_RAS0#
G8 K23 VMA_RAS0# 19 AL7 T10 VMB_RAS0# 20
VMA_DQ54 DQA1_21/DQA_53 RASA0B VMA_RAS1# VMB_DQ54 DQB1_21/DQB_53 RASB0B VMB_RAS1#
K9 K19 VMA_RAS1# 19 AM8 Y10 VMB_RAS1# 20
VMA_DQ55 DQA1_22/DQA_54 RASA1B VMB_DQ55 DQB1_22/DQB_54 RASB1B
K10 AM7
VMA_DQ56 DQA1_23/DQA_55 VMA_CAS0# VMB_DQ56 DQB1_23/DQB_55 VMB_CAS0#
G9 K20 VMA_CAS0# 19 AK1 W10 VMB_CAS0# 20
VMA_DQ57 DQA1_24/DQA_56 CASA0B VMA_CAS1# VMB_DQ57 DQB1_24/DQB_56 CASB0B VMB_CAS1#
A8 K17 VMA_CAS1# 19 AL4 AA10 VMB_CAS1# 20
VMA_DQ58 DQA1_25/DQA_57 CASA1B +1.5V_GPU VMB_DQ58 DQB1_25/DQB_57 CASB1B
C8 AM6
VMA_DQ59 DQA1_26/DQA_58 VMA_CS0# VMB_DQ59 DQB1_26/DQB_58 VMB_CS0#
E8 K24 VMA_CS0# 19 AM1 P10 VMB_CS0# 20
VMA_DQ60 DQA1_27/DQA_59 CSA0B_0 VMB_DQ60 DQB1_27/DQB_59 CSB0B_0
A6 K27 AN4 L10
VMA_DQ61 DQA1_28/DQA_60 CSA0B_1 VMB_DQ61 DQB1_28/DQB_60 CSB0B_1
C6 AP3
VMA_DQ62 DQA1_29/DQA_61 VMA_CS1# VMB_DQ62 DQB1_29/DQB_61 VMB_CS1#
E6 M13 VMA_CS1# 19 AP1 AD10 VMB_CS1# 20
VMA_DQ63 DQA1_30/DQA_62 CSA1B_0 R30 VMB_DQ63 DQB1_30/DQB_62 CSB1B_0
A5 K16 AP5 AC10
DQA1_31/DQA_63 CSA1B_1 EV@40.2/F_4 DQB1_31/DQB_63 CSB1B_1
Used for Park-M2
MVREFDA L18 K21 VMA_CKE0 U10 VMB_CKE0
MVREFDA CKEA0 VMA_CKE0 19 CKEB0 VMB_CKE0 20
R20 EV@243/F_4 MVREFSA L20 J20 VMA_CKE1 MVREFDB Y12 AA11 VMB_CKE1
MVREFSA CKEA1 VMA_CKE1 19 MVREFDB CKEB1 VMB_CKE1 20
MVREFSB AA12
R25 *EV@243/F_4 VMA_WE0# MVREFSB VMB_WE0#
L27 K26 VMA_WE0# 19 N10 VMB_WE0# 20
MEM_CALRN0 WEA0B VMA_WE1# WEB0B VMB_WE1#
N12 L15 VMA_WE1# 19 AB11 VMB_WE1# 20
R42 EV@243/F_4 MEM_CALRN1 WEA1B R28 C119 WEB1B
+1.5V_GPU AG12
MEM_CALRN2 EV@0.1u/10V_4_X7R R409 *EV@10K/F_4
+3V_D
R23 *EV@243/F_4 VMA_MA13 EV@100/F_4 R36 EV@10K/F_4 VMB_MA13 R381 *EV@4.7K_4
GDDR5
M12 H23 AD28 T8
GDDR5
MEM_CALRP1 MAA0_8 TESTEN MAB0_8 +1.5V_GPU
M27 J19 W8
R19 EV@243/F_4 MEM_CALRP0 MAA1_8 MAB1_8
AH12 AK10
R56 EV@243/F_4 MEM_CALRP2 CLKTESTA R95 EV@51/F_4
modify 1022 AL10
CLKTESTB DRAM_RST
AH11 MEM_RST# 19,20
B B
Note by AN_M96_C1 +1.5V_GPU
TP1 AL31 R71 R77 modify 1112
RSVD *0_4 *0_4 R88 C531
Used for Madison-M2
+1.5V_GPU EV@Madison/Park_M2 EV@10K_4 EV@68p/50V_4
EV@Madison/Park_M2 R37
EV@40.2/F_4
R372
EV@40.2/F_4
MVREFDA R31 C155

EV@0.1u/10V_4_X7R
EV@100/F_4
R373 C514
EV@0.1u/10V_4_X7R
EV@100/F_4
+1.5V_GPU
R18
EV@40.2/F_4
MVREFSA
R17 C58
EV@0.1u/10V_4_X7R
A EV@100/F_4 A
5
Dr-Bios.com 4 3 2
Size
Date:
Document Number

PROJECT : ZYD
Madison/Park M2 MEM I/F
1
Sheet 18 of 50
Rev
3B
5 4 3 2 1
VMA_DQ[63..0]
18 VMA_DQ[63..0]
18 VMA_DM[7..0]
VMA_DM[7..0] CHANNEL A: 512MB DDR3 (64M*16*4pcs) Park, M92M Use Channel B Memory Interface Only
VMA_RDQS[7..0] QSA[7..0]
18 VMA_RDQS[7..0]
VMA_WDQS[7..0] QSA#[7..0]
18 VMA_WDQS[7..0]
U13 U1 U14 U2
VREFC_VMA1 M8 E3 VMA_DQ10 VREFC_VMA2 M8 E3 VMA_DQ6 VREFC_VMA3 M8 E3 VMA_DQ54 VREFC_VMA4 M8 E3 VMA_DQ40

VREFD_VMA1 VREFCA DQL0 VMA_DQ11 VREFD_VMA2 VREFCA DQL0 VMA_DQ0 VREFD_VMA3 VREFCA DQL0 VMA_DQ53 VREFD_VMA4 VREFCA DQL0 VMA_DQ44
H1 F7 H1 F7 H1 F7 H1 F7
VREFDQ DQL1 VMA_DQ9 VREFDQ DQL1 VMA_DQ7 VREFDQ DQL1 VMA_DQ55 VREFDQ DQL1 VMA_DQ45
F2 F2 F2 F2
VMA_MA0 DQL2 VMA_DQ12 VMA_MA0 DQL2 VMA_DQ1 VMA_MA0 DQL2 VMA_DQ50 VMA_MA0 DQL2 VMA_DQ42
N3 F8 N3 F8 N3 F8 N3 F8
18
18
18
VMA_MA0
VMA_MA1
VMA_MA2
VMA_MA1
VMA_MA2
VMA_MA3
P7
P3
A0
A1
A2
DQL3
DQL4
DQL5
H3
H8
VMA_DQ13
VMA_DQ15
VMA_DQ8 1
VMA_MA1
VMA_MA2
VMA_MA3
P7
P3
A0
A1
A2
DQL3
DQL4
DQL5
H3
H8
VMA_DQ4
VMA_DQ2
VMA_DQ5
VMA_MA1
VMA_MA2
VMA_MA3
P7
P3
A0
A1
A2
DQL3
DQL4
DQL5
H3
H8
VMA_DQ49
VMA_DQ48
VMA_DQ52 6
VMA_MA1
VMA_MA2
VMA_MA3
P7
P3
A0
A1
A2
DQL3
DQL4
DQL5
H3
H8
VMA_DQ46
VMA_DQ41
VMA_DQ47
5
18 VMA_MA3 N2 G2 N2 G2 N2 G2 N2 G2
D
VMA_MA4 A3 DQL6 VMA_DQ14 VMA_MA4 A3 DQL6 VMA_DQ3 VMA_MA4 A3 DQL6 VMA_DQ51 VMA_MA4 A3 DQL6 VMA_DQ43 D
18 VMA_MA4 P8 H7 P8 H7 P8 H7 P8 H7
VMA_MA5 A4 DQL7 VMA_MA5 A4 DQL7 VMA_MA5 A4 DQL7 VMA_MA5 A4 DQL7
18 VMA_MA5 P2 P2 P2 P2
VMA_MA6 A5 VMA_MA6 A5 VMA_MA6 A5 VMA_MA6 A5
18 VMA_MA6 R8 R8 R8 R8
VMA_MA7 A6 VMA_DQ20 VMA_MA7 A6 VMA_DQ25 VMA_MA7 A6 VMA_DQ63 VMA_MA7 A6 VMA_DQ32
18 VMA_MA7 R2 D7 R2 D7 R2 D7 R2 D7
VMA_MA8 A7 DQU0 VMA_DQ19 VMA_MA8 A7 DQU0 VMA_DQ31 VMA_MA8 A7 DQU0 VMA_DQ56 VMA_MA8 A7 DQU0 VMA_DQ36
18 VMA_MA8 T8 C3 T8 C3 T8 C3 T8 C3
VMA_MA9 A8 DQU1 VMA_DQ23 VMA_MA9 A8 DQU1 VMA_DQ27 VMA_MA9 A8 DQU1 VMA_DQ62 VMA_MA9 A8 DQU1 VMA_DQ33
R3 C8 R3 C8 R3 C8 R3 C8
18
18
18
VMA_MA9
VMA_MA10
VMA_MA11
VMA_MA10
VMA_MA11
VMA_MA12
L7
R7
A9
A10/AP
A11
DQU2
DQU3
DQU4
C2
A7
VMA_DQ18
VMA_DQ22
VMA_DQ16 2
VMA_MA10
VMA_MA11
VMA_MA12
L7
R7
A9
A10/AP
A11
DQU2
DQU3
DQU4
C2
A7
VMA_DQ28
VMA_DQ24
VMA_DQ30
VMA_MA10
VMA_MA11
VMA_MA12
L7
R7
A9
A10/AP
A11
DQU2
DQU3
DQU4
C2
A7
VMA_DQ59
VMA_DQ60
VMA_DQ58 7
VMA_MA10
VMA_MA11
VMA_MA12
L7
R7
A9
A10/AP
A11
DQU2
DQU3
DQU4
C2
A7
VMA_DQ39
VMA_DQ35
VMA_DQ37
4
18 VMA_MA12 N7 A2 N7 A2 N7 A2 N7 A2
VMA_MA13 A12/BC DQU5 VMA_DQ21 VMA_MA13 A12/BC DQU5 VMA_DQ26 VMA_MA13 A12/BC DQU5 VMA_DQ61 VMA_MA13 A12/BC DQU5 VMA_DQ34
18 VMA_MA13 T3 B8 T3 B8 T3 B8 T3 B8
A13 DQU6 VMA_DQ17 A13 DQU6 VMA_DQ29 A13 DQU6 VMA_DQ57 A13 DQU6 VMA_DQ38
T7 A3 T7 A3 T7 A3 T7 A3
A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
M7 M7 M7 M7
A15 +1.5V_GPU A15 +1.5V_GPU A15 +1.5V_GPU A15 +1.5V_GPU
VMA_BA0 M2 B2 VMA_BA0 M2 B2 VMA_BA0 M2 B2 VMA_BA0 M2 B2

18 VMA_BA0 BA0 VDD#B2 BA0 VDD#B2 BA0 VDD#B2 BA0 VDD#B2
VMA_BA1 N8 D9 VMA_BA1 N8 D9 VMA_BA1 N8 D9 VMA_BA1 N8 D9
18 VMA_BA1 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9
VMA_BA2 M3 G7 VMA_BA2 M3 G7 VMA_BA2 M3 G7 VMA_BA2 M3 G7
18 VMA_BA2 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7
K2 K2 K2 K2
VDD#K2 VDD#K2 VDD#K2 VDD#K2
K8 K8 K8 K8
N1 N1 N1 N1
VMA_CLK0 VDD#N1 VMA_CLK0 VDD#N1 VMA_CLK1 VDD#N1 VMA_CLK1 VDD#N1
18 VMA_CLK0 J7 N9 J7 N9 18 VMA_CLK1 J7 N9 J7 N9
VMA_CLK0# CK VDD#N9 VMA_CLK0# CK VDD#N9 VMA_CLK1# CK VDD#N9 VMA_CLK1# CK VDD#N9
18 VMA_CLK0# K7 R1 K7 R1 18 VMA_CLK1# K7 R1 K7 R1
VMA_CKE0 CK VDD#R1 VMA_CKE0 CK VDD#R1 VMA_CKE1 CK VDD#R1 VMA_CKE1 CK VDD#R1
18 VMA_CKE0 K9 R9 K9 R9 18 VMA_CKE1 K9 R9 K9 R9
CKE VDD#R9 +1.5V_GPU CKE VDD#R9 +1.5V_GPU CKE VDD#R9 +1.5V_GPU CKE VDD#R9 +1.5V_GPU
VMA_ODT0 K1 A1 VMA_ODT0 K1 A1 VMA_ODT1 K1 A1 VMA_ODT1 K1 A1

18 VMA_ODT0 ODT VDDQ#A1 ODT VDDQ#A1 18 VMA_ODT1 ODT VDDQ#A1 ODT VDDQ#A1
VMA_CS0# L2 A8 VMA_CS0# L2 A8 VMA_CS1# L2 A8 VMA_CS1# L2 A8
18 VMA_CS0# CS VDDQ#A8 CS VDDQ#A8 18 VMA_CS1# CS VDDQ#A8 CS VDDQ#A8
VMA_RAS0# J3 C1 VMA_RAS0# J3 C1 VMA_RAS1# J3 C1 VMA_RAS1# J3 C1
18 VMA_RAS0# RAS VDDQ#C1 RAS VDDQ#C1 18 VMA_RAS1# RAS VDDQ#C1 RAS VDDQ#C1
VMA_CAS0# K3 C9 VMA_CAS0# K3 C9 VMA_CAS1# K3 C9 VMA_CAS1# K3 C9
18 VMA_CAS0# CAS VDDQ#C9 CAS VDDQ#C9 18 VMA_CAS1# CAS VDDQ#C9 CAS VDDQ#C9
VMA_WE0# L3 D2 VMA_WE0# L3 D2 VMA_WE1# L3 D2 VMA_WE1# L3 D2
18 VMA_WE0# WE VDDQ#D2 WE VDDQ#D2 18 VMA_WE1# WE VDDQ#D2 WE VDDQ#D2
E9 E9 E9 E9
VDDQ#E9 VDDQ#E9 VDDQ#E9 VDDQ#E9
F1 F1 F1 F1
VMA_RDQS1 VDDQ#F1 VMA_RDQS0 VDDQ#F1 VMA_RDQS6 VDDQ#F1 VMA_RDQS5 VDDQ#F1
F3 H2 F3 H2 F3 H2 F3 H2
VMA_RDQS2 DQSL VDDQ#H2 VMA_RDQS3 DQSL VDDQ#H2 VMA_RDQS7 DQSL VDDQ#H2 VMA_RDQS4 DQSL VDDQ#H2
C7 H9 C7 H9 C7 H9 C7 H9
DQSU VDDQ#H9 DQSU VDDQ#H9 DQSU VDDQ#H9 DQSU VDDQ#H9
VMA_DM1 E7 A9 VMA_DM0 E7 A9 VMA_DM6 E7 A9 VMA_DM5 E7 A9

VMA_DM2 DML VSS#A9 VMA_DM3 DML VSS#A9 VMA_DM7 DML VSS#A9 VMA_DM4 DML VSS#A9
C D3 B3 D3 B3 D3 B3 D3 B3 C
DMU VSS#B3 DMU VSS#B3 DMU VSS#B3 DMU VSS#B3
E1 E1 E1 E1
VSS#E1 VSS#E1 VSS#E1 VSS#E1
G8 G8 G8 G8
VMA_WDQS1 VSS#G8 VMA_WDQS0 VSS#G8 VMA_WDQS6 VSS#G8 VMA_WDQS5 VSS#G8
G3 J2 G3 J2 G3 J2 G3 J2
VMA_WDQS2 DQSL VSS#J2 VMA_WDQS3 DQSL VSS#J2 VMA_WDQS7 DQSL VSS#J2 VMA_WDQS4 DQSL VSS#J2
B7 J8 B7 J8 B7 J8 B7 J8
DQSU VSS#J8 DQSU VSS#J8 DQSU VSS#J8 DQSU VSS#J8
M1 M1 M1 M1
VSS#M1 VSS#M1 VSS#M1 VSS#M1
M9 M9 M9 M9
P1 P1 P1 P1
MEM_RST# VSS#P1 MEM_RST# VSS#P1 MEM_RST# VSS#P1 MEM_RST# VSS#P1
T2 P9 T2 P9 T2 P9 T2 P9
18,20 MEM_RST# RESET VSS#P9 RESET VSS#P9 RESET VSS#P9 RESET VSS#P9
T1 T1 T1 T1
VMA_ZQ1 VSS#T1 VMA_ZQ2 VSS#T1 VMA_ZQ3 VSS#T1 VMA_ZQ4 VSS#T1
L8 T9 L8 T9 L8 T9 L8 T9
ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9
B1 B1 B1 B1
VSSQ#B1 VSSQ#B1 VSSQ#B1 VSSQ#B1
B9 B9 B9 B9
R368 VSSQ#B9 R3 VSSQ#B9 R364 VSSQ#B9 R6 VSSQ#B9
D1 D1 D1 D1
VSSQ#D1 VSSQ#D1 VSSQ#D1 VSSQ#D1
EV@240/F_4 D8 EV@240/F_4 D8 EV@240/F_4 D8 EV@240/F_4 D8
E2 E2 E2 E2
VSSQ#E2 VSSQ#E2 VSSQ#E2 VSSQ#E2
J1 E8 J1 E8 J1 E8 J1 E8
NC#J1 VSSQ#E8 NC#J1 VSSQ#E8 NC#J1 VSSQ#E8 NC#J1 VSSQ#E8
L1 F9 L1 F9 L1 F9 L1 F9
NC#L1 VSSQ#F9 NC#L1 VSSQ#F9 NC#L1 VSSQ#F9 NC#L1 VSSQ#F9
J9 G1 J9 G1 J9 G1 J9 G1
NC#J9 VSSQ#G1 NC#J9 VSSQ#G1 NC#J9 VSSQ#G1 NC#J9 VSSQ#G1
L9 G9 L9 G9 L9 G9 L9 G9
NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9
100-BALL 100-BALL 100-BALL 100-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
EV@VRAM _DDR3 EV@VRAM _DDR3 EV@VRAM _DDR3 EV@VRAM _DDR3
TOP Left BOT Left BOT Right TOP Right

Group-A0 VREF Group-A1 VREF
+1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU
B B
R371 R359 R360 R8 R356 R367 R4 R357

EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4
VREFC_VMA1 VREFD_VMA1 VREFC_VMA2 VREFD_VMA2 VREFC_VMA3 VREFD_VMA3 VREFC_VMA4 VREFD_VMA4
R370 C511 R361 C501 R362 C502 R7 C26 R358 C486 R369 C510 R5 C23 R363 C503
EV@0.1u/10V_4_X7R EV@0.1u/10V_4_X7R EV@0.1u/10V_4_X7R EV@0.1u/10V_4_X7R EV@0.1u/10V_4_X7R EV@0.1u/10V_4_X7R EV@0.1u/10V_4_X7R EV@0.1u/10V_4_X7R
Group-A0 decoupling CAP Group-A1 decoupling CAP MEM_A1 CLK

MEM_A0 CLK
+1.5V_GPU
+1.5V_GPU
VMA_CLK1
VMA_CLK0
VMA_CLK1#
VMA_CLK0# C500 C498 C18 C14 C493 C24 C25 C22
C12 C27 C495 C490 C10 C28 C9 C496 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4
EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 R365 R366
R2 R1 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@56.2/F_4
EV@56.2/F_4 EV@56.2/F_4
EV@56.2/F_4 +1.5V_GPU
+1.5V_GPU
C497
C1 C484 C512 C15 C499 C494 C16 C507 C483 EV@0.01u/25V_4
EV@0.01u/25V_4 C11 C8 C5 C491 C21 C492 C7 C6 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4
A EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 A
EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4
Dr-Bios.com
+1.5V_GPU
+1.5V_GPU
C505 C504 C489 C4 C488

C19 C2 C17 C487 C513 EV@10u/6.3V_6 EV@10u/6.3V_6
EV@10u/6.3V_6
EV@10u/6.3V_6
EV@10u/6.3V_6
EV@10u/6.3V_6
EV@10u/6.3V_6
EV@10u/6.3V_6 EV@10u/6.3V_6 EV@10u/6.3V_6 Quanta Computer Inc.
PROJECT : ZYD
3B
MEMORY 1 channel A
5 4 3 2 1
5 4 3 2 1
18 VMB_DQ[63..0]
VMB_DQ[63..0] CHANNEL B: 512MB DDR3 (64M*16*4pcs)
VMB_DM[7..0]
18 VMB_DM[7..0]
VMB_RDQS[7..0] QSA[7..0]
18 VMB_RDQS[7..0]
VMB_WDQS[7..0] QSA#[7..0]
18 VMB_WDQS[7..0]
U3 U17 U21 U4
VREFC_VMB1 M8 E3 VMB_DQ6 VREFC_VMB2 M8 E3 VMB_DQ17 VREFC_VMB3 M8 E3 VMB_DQ36 VREFC_VMB4 M8 E3 VMB_DQ54

VREFD_VMB1 VREFCA DQL0 VMB_DQ3 VREFD_VMB2 VREFCA DQL0 VMB_DQ23 VREFD_VMB3 VREFCA DQL0 VMB_DQ39 VREFD_VMB4 VREFCA DQL0 VMB_DQ51
H1 F7 H1 F7 H1 F7 H1 F7
VREFDQ DQL1 VMB_DQ5 VREFDQ DQL1 VMB_DQ18 VREFDQ DQL1 VMB_DQ33 VREFDQ DQL1 VMB_DQ53
F2 F2 F2 F2
VMB_MA0 DQL2 VMB_DQ1 VMB_MA0 DQL2 VMB_DQ16 VMB_MA0 DQL2 VMB_DQ34 VMB_MA0 DQL2 VMB_DQ50
N3 F8 N3 F8 N3 F8 N3 F8
18
18
18
VMB_MA0
VMB_MA1
VMB_MA2
VMB_MA1
VMB_MA2
VMB_MA3
P7
P3
A0
A1
A2
DQL3
DQL4
DQL5
H3
H8
VMB_DQ7
VMB_DQ0
VMB_DQ4
0 VMB_MA1
VMB_MA2
VMB_MA3
P7
P3
A0
A1
A2
DQL3
DQL4
DQL5
H3
H8
VMB_DQ20
VMB_DQ22
VMB_DQ19
2 VMB_MA1
VMB_MA2
VMB_MA3
P7
P3
A0
A1
A2
DQL3
DQL4
DQL5
H3
H8
VMB_DQ37
VMB_DQ32
VMB_DQ38
4 VMB_MA1
VMB_MA2
VMB_MA3
P7
P3
A0
A1
A2
DQL3
DQL4
DQL5
H3
H8
VMB_DQ52
VMB_DQ48
VMB_DQ55
6
18 VMB_MA3 N2 G2 N2 G2 N2 G2 N2 G2
D
VMB_MA4 A3 DQL6 VMB_DQ2 VMB_MA4 A3 DQL6 VMB_DQ21 VMB_MA4 A3 DQL6 VMB_DQ35 VMB_MA4 A3 DQL6 VMB_DQ49 D
18 VMB_MA4 P8 H7 P8 H7 P8 H7 P8 H7
VMB_MA5 A4 DQL7 VMB_MA5 A4 DQL7 VMB_MA5 A4 DQL7 VMB_MA5 A4 DQL7
18 VMB_MA5 P2 P2 P2 P2
VMB_MA6 A5 VMB_MA6 A5 VMB_MA6 A5 VMB_MA6 A5
18 VMB_MA6 R8 R8 R8 R8
VMB_MA7 A6 VMB_DQ24 VMB_MA7 A6 VMB_DQ15 VMB_MA7 A6 VMB_DQ62 VMB_MA7 A6 VMB_DQ41
18 VMB_MA7 R2 D7 R2 D7 R2 D7 R2 D7
VMB_MA8 A7 DQU0 VMB_DQ31 VMB_MA8 A7 DQU0 VMB_DQ10 VMB_MA8 A7 DQU0 VMB_DQ56 VMB_MA8 A7 DQU0 VMB_DQ46
18 VMB_MA8 T8 C3 T8 C3 T8 C3 T8 C3
VMB_MA9 A8 DQU1 VMB_DQ28 VMB_MA9 A8 DQU1 VMB_DQ14 VMB_MA9 A8 DQU1 VMB_DQ63 VMB_MA9 A8 DQU1 VMB_DQ40
R3 C8 R3 C8 R3 C8 R3 C8
18
18
18
VMB_MA9
VMB_MA10
VMB_MA11
VMB_MA10
VMB_MA11
VMB_MA12
L7
R7
A9
A10/AP
A11
DQU2
DQU3
DQU4
C2
A7
VMB_DQ30
VMB_DQ26
VMB_DQ27
3 VMB_MA10
VMB_MA11
VMB_MA12
L7
R7
A9
A10/AP
A11
DQU2
DQU3
DQU4
C2
A7
VMB_DQ11
VMB_DQ12
VMB_DQ9
1 VMB_MA10
VMB_MA11
VMB_MA12
L7
R7
A9
A10/AP
A11
DQU2
DQU3
DQU4
C2
A7
VMB_DQ58
VMB_DQ61
VMB_DQ57
7 VMB_MA10
VMB_MA11
VMB_MA12
L7
R7
A9
A10/AP
A11
DQU2
DQU3
DQU4
C2
A7
VMB_DQ42
VMB_DQ44
VMB_DQ45
5
18 VMB_MA12 N7 A2 N7 A2 N7 A2 N7 A2
VMB_MA13 A12/BC DQU5 VMB_DQ25 VMB_MA13 A12/BC DQU5 VMB_DQ13 VMB_MA13 A12/BC DQU5 VMB_DQ60 VMB_MA13 A12/BC DQU5 VMB_DQ43
18 VMB_MA13 T3 B8 T3 B8 T3 B8 T3 B8
A13 DQU6 VMB_DQ29 A13 DQU6 VMB_DQ8 A13 DQU6 VMB_DQ59 A13 DQU6 VMB_DQ47
T7 A3 T7 A3 T7 A3 T7 A3
A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
M7 M7 M7 M7
A15 +1.5V_GPU A15 +1.5V_GPU A15 +1.5V_GPU A15 +1.5V_GPU
VMB_BA0 M2 B2 VMB_BA0 M2 B2 VMB_BA0 M2 B2 VMB_BA0 M2 B2

18 VMB_BA0 BA0 VDD#B2 BA0 VDD#B2 BA0 VDD#B2 BA0 VDD#B2
VMB_BA1 N8 D9 VMB_BA1 N8 D9 VMB_BA1 N8 D9 VMB_BA1 N8 D9
18 VMB_BA1 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9
VMB_BA2 M3 G7 VMB_BA2 M3 G7 VMB_BA2 M3 G7 VMB_BA2 M3 G7
18 VMB_BA2 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7
K2 K2 K2 K2
K8 K8 K8 K8
N1 N1 N1 N1
VMB_CLK0 VDD#N1 VMB_CLK0 VDD#N1 VMB_CLK1 VDD#N1 VMB_CLK1 VDD#N1
18 VMB_CLK0 J7 N9 J7 N9 18 VMB_CLK1 J7 N9 J7 N9
VMB_CLK0# CK VDD#N9 VMB_CLK0# CK VDD#N9 VMB_CLK1# CK VDD#N9 VMB_CLK1# CK VDD#N9
18 VMB_CLK0# K7 R1 K7 R1 18 VMB_CLK1# K7 R1 K7 R1
VMB_CKE0 CK VDD#R1 VMB_CKE0 CK VDD#R1 VMB_CKE1 CK VDD#R1 VMB_CKE1 CK VDD#R1
18 VMB_CKE0 K9 R9 K9 R9 18 VMB_CKE1 K9 R9 K9 R9
CKE VDD#R9 +1.5V_GPU CKE VDD#R9 +1.5V_GPU CKE VDD#R9 +1.5V_GPU CKE VDD#R9 +1.5V_GPU
VMB_ODT0 K1 A1 VMB_ODT0 K1 A1 VMB_ODT1 K1 A1 VMB_ODT1 K1 A1

18 VMB_ODT0 ODT VDDQ#A1 ODT VDDQ#A1 18 VMB_ODT1 ODT VDDQ#A1 ODT VDDQ#A1
VMB_CS0# L2 A8 VMB_CS0# L2 A8 VMB_CS1# L2 A8 VMB_CS1# L2 A8
18 VMB_CS0# CS VDDQ#A8 CS VDDQ#A8 18 VMB_CS1# CS VDDQ#A8 CS VDDQ#A8
VMB_RAS0# J3 C1 VMB_RAS0# J3 C1 VMB_RAS1# J3 C1 VMB_RAS1# J3 C1
18 VMB_RAS0# RAS VDDQ#C1 RAS VDDQ#C1 18 VMB_RAS1# RAS VDDQ#C1 RAS VDDQ#C1
VMB_CAS0# K3 C9 VMB_CAS0# K3 C9 VMB_CAS1# K3 C9 VMB_CAS1# K3 C9
18 VMB_CAS0# CAS VDDQ#C9 CAS VDDQ#C9 18 VMB_CAS1# CAS VDDQ#C9 CAS VDDQ#C9
VMB_WE0# L3 D2 VMB_WE0# L3 D2 VMB_WE1# L3 D2 VMB_WE1# L3 D2
18 VMB_WE0# WE VDDQ#D2 WE VDDQ#D2 18 VMB_WE1# WE VDDQ#D2 WE VDDQ#D2
E9 E9 E9 E9
VDDQ#E9 VDDQ#E9 VDDQ#E9 VDDQ#E9
F1 F1 F1 F1
VMB_RDQS0 VDDQ#F1 VMB_RDQS2 VDDQ#F1 VMB_RDQS4 VDDQ#F1 VMB_RDQS6 VDDQ#F1
F3 H2 F3 H2 F3 H2 F3 H2
VMB_RDQS3 DQSL VDDQ#H2 VMB_RDQS1 DQSL VDDQ#H2 VMB_RDQS7 DQSL VDDQ#H2 VMB_RDQS5 DQSL VDDQ#H2
C7 H9 C7 H9 C7 H9 C7 H9
DQSU VDDQ#H9 DQSU VDDQ#H9 DQSU VDDQ#H9 DQSU VDDQ#H9
VMB_DM0 E7 A9 VMB_DM2 E7 A9 VMB_DM4 E7 A9 VMB_DM6 E7 A9

VMB_DM3 DML VSS#A9 VMB_DM1 DML VSS#A9 VMB_DM7 DML VSS#A9 VMB_DM5 DML VSS#A9
C D3 B3 D3 B3 D3 B3 D3 B3 C
DMU VSS#B3 DMU VSS#B3 DMU VSS#B3 DMU VSS#B3
E1 E1 E1 E1
VSS#E1 VSS#E1 VSS#E1 VSS#E1
G8 G8 G8 G8
VMB_WDQS0 VSS#G8 VMB_WDQS2 VSS#G8 VMB_WDQS4 VSS#G8 VMB_WDQS6 VSS#G8
G3 J2 G3 J2 G3 J2 G3 J2
VMB_WDQS3 DQSL VSS#J2 VMB_WDQS1 DQSL VSS#J2 VMB_WDQS7 DQSL VSS#J2 VMB_WDQS5 DQSL VSS#J2
B7 J8 B7 J8 B7 J8 B7 J8
DQSU VSS#J8 DQSU VSS#J8 DQSU VSS#J8 DQSU VSS#J8
M1 M1 M1 M1
M9 M9 M9 M9
P1 P1 P1 P1
MEM_RST# VSS#P1 MEM_RST# VSS#P1 MEM_RST# VSS#P1 MEM_RST# VSS#P1
T2 P9 T2 P9 T2 P9 T2 P9
18,19 MEM_RST# RESET VSS#P9 RESET VSS#P9 RESET VSS#P9 RESET VSS#P9
T1 T1 T1 T1
VMB_ZQ1 VSS#T1 VMB_ZQ2 VSS#T1 VMB_ZQ3 VSS#T1 VMB_ZQ4 VSS#T1
L8 T9 L8 T9 L8 T9 L8 T9
ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9
B1 B1 B1 B1
VSSQ#B1 VSSQ#B1 VSSQ#B1 VSSQ#B1
B9 B9 B9 B9
R24 VSSQ#B9 R380 VSSQ#B9 R394 VSSQ#B9 R51 VSSQ#B9
D1 D1 D1 D1
EV@240/F_4 D8 EV@240/F_4 D8 EV@240/F_4 D8 EV@240/F_4 D8
E2 E2 E2 E2
VSSQ#E2 VSSQ#E2 VSSQ#E2 VSSQ#E2
J1 E8 J1 E8 J1 E8 J1 E8
NC#J1 VSSQ#E8 NC#J1 VSSQ#E8 NC#J1 VSSQ#E8 NC#J1 VSSQ#E8
L1 F9 L1 F9 L1 F9 L1 F9
NC#L1 VSSQ#F9 NC#L1 VSSQ#F9 NC#L1 VSSQ#F9 NC#L1 VSSQ#F9
J9 G1 J9 G1 J9 G1 J9 G1
NC#J9 VSSQ#G1 NC#J9 VSSQ#G1 NC#J9 VSSQ#G1 NC#J9 VSSQ#G1
L9 G9 L9 G9 L9 G9 L9 G9
NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9
100-BALL 100-BALL 100-BALL 100-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
EV@VRAM _DDR3 EV@VRAM _DDR3 EV@VRAM _DDR3 EV@VRAM _DDR3
BOT Down TOP Down TOP Up BOT Up
Group-B0 VREF Group-B1 VREF

+1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU
B B
R374 R11 R387 R376 R399 R403 R41 R55

VREFC_VMB1 VREFD_VMB1 VREFC_VMB2 VREFD_VMB2 VREFC_VMB3 VREFD_VMB3 VREFC_VMB4 VREFD_VMB4
R21 C60 R15 C45 R384 C535 R375 C525 R398 C563 R400 C557 R47 C175 R54 C181
EV@0.1u/10V_4_X7R EV@0.1u/10V_4_X7R EV@0.1u/10V_4_X7R EV@0.1u/10V_4_X7R EV@0.1u/10V_4_X7R EV@0.1u/10V_4_X7R EV@0.1u/10V_4_X7R EV@0.1u/10V_4_X7R
Group-B0 decoupling CAP Group-B1 decoupling CAP MEM_B1 CLK

MEM_B0 CLK
+1.5V_GPU +1.5V_GPU
VMB_CLK1
VMB_CLK0 VMB_CLK1#
C81 C586 C517 C530 C520 C39 C145 C516 C183 C205 C214 C172 C548 C184 C192 C550
VMB_CLK0# EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4
EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 R63 R68
EV@56.2/F_4
R14 R12 EV@56.2/F_4
EV@56.2/F_4 +1.5V_GPU +1.5V_GPU
EV@56.2/F_4
A C193 A
C572 C156 C34 C41 C575 C532 C36 C133 C537 C577 C13 C197 C177 C541 C547 C574 EV@0.01u/25V_4
C523 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4
Dr-Bios.com
EV@0.01u/25V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4
+1.5V_GPU +1.5V_GPU

C65 C30 C536 C237 C524 C236 C159 C544 C3 C543
EV@10u/6.3V_6 EV@10u/6.3V_6 EV@10u/6.3V_6 EV@10u/6.3V_6
EV@10u/6.3V_6 EV@10u/6.3V_6 EV@10u/6.3V_6 EV@10u/6.3V_6 EV@10u/6.3V_6 EV@10u/6.3V_6 PROJECT : ZYD
3B
MEMORY 2 channel B
5 4 3 2 1
5 4 3 2 1
U18F
U18E
For DDR3, MVDDQ = 1.5V (7.5A)
+1.5V_GPU MEM I/O +1.8V_GPU
PCIE (1.8V@400mA PCIE_VDDR) 180 ohm/1.5A AB39 A3
PCIE_VDDR L4 EV@HCB1608KF-181T15/180ohm/1.5A_6 PCIE_VSS#1 GND#1
AC7 AA31 E39 A37
VDDR1#1 PCIE_VDDR#1 PCIE_VSS#2 GND#2
AD11 AA32 F34 AA16
AF7 AA33 F39 AA18
C73 C43 C515 C85 C522 VDDR1#3 PCIE_VDDR#3 C116 C136 C120 C134 C168 C135 C115 C176 PCIE_VSS#4 GND#4
AG10 AA34 G33 AA2
EV@10u/6.3V_6 EV@10u/6.3V_6 VDDR1#4 PCIE_VDDR#4 EV@0.1u/10V_4_X7R EV@1u/6.3V_4 EV@1u/6.3V_4 EV@10u/6.3V_6 PCIE_VSS#5 GND#5
AJ7 V28 G34 AA21
EV@10u/6.3V_6 EV@10u/6.3V_6 EV@10u/6.3V_6 VDDR1#5 PCIE_VDDR#5 EV@0.1u/10V_4_X7R EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 PCIE_VSS#6 GND#6
AK8 W29 H31 AA23
AL9 W30 H34 AA26
G11 Y31 H39 AA28
G14 J31 AA6
VDDR1#9 PCIE_VSS#10 GND#10
G17 J34 AB12
VDDR1#10 +1V PCIE_VSS#11 GND#11
G20 G30 K31 AB15
C146 C84 C48 C117 C113 C49 VDDR1#11 PCIE_VDDC#1 PCIE_VSS#12 GND#12
G23
VDDR1#12 PCIE_VDDC#2
G31 (1.0V@1.1A PCIE_VDDC) K34
PCIE_VSS#13 GND#13
AB17
EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 G26 H29 K39 AB20
EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 VDDR1#13 PCIE_VDDC#3 PCIE_VSS#14 GND#14
G29 H30 L31 AB22
D VDDR1#14 PCIE_VDDC#4 PCIE_VSS#15 GND#15 D
H10 J29 L34 AB24
VDDR1#15 PCIE_VDDC#5 C67 C64 C70 C91 C82 C76 C101 C51 PCIE_VSS#16 GND#16
J7 J30 M34 AB27
VDDR1#16 PCIE_VDDC#6 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@10u/6.3V_6 PCIE_VSS#17 GND#17
J9 L28 M39 AC11
VDDR1#17 PCIE_VDDC#7 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 PCIE_VSS#18 GND#18
K11 M28 N31 AC13
VDDR1#18 PCIE_VDDC#8 PCIE_VSS#19 GND#19
K13 N28 N34 AC16
VDDR1#19 PCIE_VDDC#9 PCIE_VSS#20 GND#20
K8 R28 P31 AC18
C179 C163 C59 C93 C53 C166 VDDR1#20 PCIE_VDDC#10 PCIE_VSS#21 GND#21
L12 T28 P34 AC2
EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 VDDR1#21 PCIE_VDDC#11 PCIE_VSS#22 GND#22
L16 U28 P39 AC21
EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 VDDR1#22 PCIE_VDDC#12 +VGPU_CORE PCIE_VSS#23 GND#23
L21 R34 AC23
VDDR1#23 PCIE_VSS#24 GND#24
L23
VDDR1#24 (30A or more) T31
PCIE_VSS#25 GND#25
AC26
L26 AA15 T34 AC28
VDDR1#25 CORE VDDC#1 PCIE_VSS#26 GND#26
L7 AA17 T39 AC6
VDDR1#26 VDDC#2 PCIE_VSS#27 GND#27
M11 AA20 U31 AD15
VDDR1#27 VDDC#3 C102 C118 C86 C131 C97 C140 C142 C88 C108 C104 PCIE_VSS#28 GND#28
N11 AA22 U34 AD17
C148 C72 C47 C46 C186 VDDR1#28 VDDC#4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 PCIE_VSS#29 GND#29
P7 AA24 V34 AD20
EV@0.1u/10V_4_X7R EV@0.1u/10V_4_X7R VDDR1#29 VDDC#5 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 PCIE_VSS#30 GND#30
R11 AA27 V39 AD22
EV@1u/6.3V_4 EV@0.1u/10V_4_X7R EV@0.1u/10V_4_X7R VDDR1#30 VDDC#6 PCIE_VSS#31 GND#31
U11 AB16 W31 AD24
U7 AB18 W34 AD27
Y11 AB21 Y34 AD9
Y7 AB23 Y39 AE2
AB26 AE6
VDDC#11 GND#36
AB28 AF10
VDDC#12 C130 C141 C149 C111 C98 C71 C109 C89 C105 C96 GND#37
AC17 AF16
VDDC#13 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 GND#38
AC20 AF18
LEVEL VDDC#14 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 GND#39
AC22 AF21
120 ohm/300mA (1.8V@110mA VDD_CT) TRANSLATION VDDC#15
VDDC#16
AC24 GND GND#40
GND#41
AG17 PowerXpress control signal for Madsion and Park only
POWER
L2 EV@SBY100505T-121Y-N/0.3A/120ohm_4 VDDC_CT AF26 AC27 F15 AG2 If not used, can be disconnected.
+1.8V_GPU VDD_CT#1 VDDC#17 GND#100 GND#42
AF27 AD18 F17 AG20 PX_EN = LOW, turn on
VDD_CT#2 VDDC#18 GND#101 GND#43
AG26 AD21 F19 AG22 PX_EN = HIGH, turn off
C171 C169 C160 VDD_CT#3 VDDC#19 GND#102 GND#44
AG27 AD23 F21 AG6 PX_EN is used to turn ON/OFF some
EV@1u/6.3V_4 VDD_CT#4 VDDC#20 GND#103 GND#45
AD26 F23 AG9 regulators for PowerXpress mode. An
EV@10u/6.3V_6 EV@0.1u/10V_4_X7R VDDC#21 C150 C87 C151 C103 C129 C95 C132 C110 C162 C143 GND#104 GND#46
AF17 F25 AH21
I/O VDDC#22 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 GND#105 GND#47 output high Ø3.3Vˇ will turn the regulators
(3.3V@60mA)) VDDC#23
AF20 F27
GND#106 GND#48
AJ10
OFF. An output low Ø0Vˇ will turn the
+3V_D AF23 AF22 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 F29 AJ11
VDDR3#1 VDDC#24 GND#107 GND#49 regulators ON. PX_EN outputs low (0V)
AF24 AG16 F31 AJ2
VDDR3#2 VDDC#25 GND#108 GND#50 by default.
AG23 AG18 F33 AJ28
C242 C170 C161 C164 VDDR3#3 VDDC#26 GND#109 GND#51 If this signal is unused, it can be NC (not
AG24 AG21 F7 AJ6
EV@1u/6.3V_4 EV@1u/6.3V_4 VDDR3#4 VDDC#27 GND#110 GND#52
C AH22 F9 AK11 connected) or connected to ground. C
EV@10u/6.3V_6 EV@1u/6.3V_4 VDDC#28 GND#111 GND#53
AH27 G2 AK31
VDDC#29 C147 C121 C83 C107 C126 C124 GND#112 GND#54 +3V
AF13 AH28 G6 AK7
VDDR4#4 VDDC#30 EV@10u/6.3V_6 EV@10u/6.3V_6 EV@10u/6.3V_6 GND#113 GND#55
AF15 M26 H9 AL11 Modify 1022
120 ohm/300mA VDDR4#5 VDDC#31 EV@10u/6.3V_6 EV@10u/6.3V_6 EV@10u/6.3V_6 GND#114 GND#56
AG13 N24 J2 AL14
L11 VDDR4
EV@SBY100505T-121Y-N/0.3A/120ohm_4 VDDR4#7 VDDC#32 GND#115 GND#57 R69
+1.8V_GPU AG15 N27 J27 AL17
VDDR4#8 VDDC#33 GND#116 GND#58
R18 J6 AL2
VDDC#34 GND#117 GND#59 *EV@10K_4
VDDC#35
R21 BIF_VDDC should be connected to VDDC if BACO feature not used. J8
GND#118 GND#60
AL20
C220 C221 AD12 R23 K14 AL21
EV@0.1u/10V_4_X7R VDDR4#1 VDDC#36 For BACO, refer to the databook GND#119 GND#61
AF11 R26 K7 AL23
EV@1u/6.3V_4 VDDR4#2 VDDC#37 Connect to VDDC in non-PowerXpress designs. GND#120 GND#62
AF12 T17 L11 AL26
VDDR4#3 VDDC#38 PIN different between Broadway and Madison GND#121 GND#63 R67
AG11 T20 L17 AL32
VDDR4#6 VDDC#39 GND#122 GND#64
T22 L2 AL6
VDDC#40 Pin Broadway Madison GND#123 GND#65 *EV@0_4
T24 L22 AL8
VDDC#41 GND#124 GND#66
T27 L24 AM11
VDDC#42 N27 VDDC BIF_VDDC GND#125 GND#67
U16 L6 AM31
T2 VDDC#43 T27 GND#126 GND#68
M20 U18 M17 AM9
T1 NC_VDDRHA VDDC#44 GND#127 GND#69
M21 U21 M22 AN11
NC_VSSRHA VDDC#45 VDDC and VDDCI are assigned to different sets of balls on M97, Madison and GND#128 GND#70
*PAD U23 M24 AN2
*PAD U26 Park. As a result, VDDC and VDDCI will be shorted when a M96 is populated on a N16 AN30
T4 VDDC#47 GND#130 GND#72
V12 V17 compatible design. N18 AN6
T3 NC_VDDRHB VDDC#48 GND#131 GND#73
U12 V20 N2 AN8
NC_VSSRHB VDDC#49 GND#132 GND#74
*PAD V22 N21 AP11
VDDC#50 +VGPU_CORE JP5 +VGPU_IO GND#133 GND#75
*PAD V24 N23 AP7
(For M97, Broadway, Madison and Park SPV10 = 1.0V) VDDC#52
V27 SHORT PAD N26
GND#135 GND#77
AP9
Y16 Modify 1022 2 1 N6 AR5
120 ohm/300mA PLL VDDC#53 GND#136 GND#78
(1.8V@40mA PCIE_PVDD) VDDC#54
Y18 R15
GND#137 GND#79
AW34
L40 EV@SBY100505T-121Y-N/0.3A/120ohm_4 PCIE_PVDD AB37 Y21 VDDCI and VDDC should have seperate regulators with a merge option on PCB R17 B11
+1.8V_GPU PCIE_PVDD VDDC#55 GND#138 GND#80
Y23 For Madison and Park, VDDCI and VDDC can share one common regulator R2 B13
MPV18 VDDC#56 GND#139 GND#81
H7 Y26 R20 B15
C538 C539 C540 MPV18#1 VDDC#57 GND#140 GND#82
H8 Y28 R22 B17
EV@1u/6.3V_4 MPV18#2 VDDC#58 GND#141 GND#83
R24 B19
EV@10u/6.3V_6 EV@0.1u/10V_4_X7R +VGPU_IO GND#142 GND#84
R27 B21
SPV18 GND#143 GND#85
AM10
SPV18 (DDR3 1.12V@4A VDDCI) or more R6
GND#144 GND#86
B23
120 ohm/300mA (1.8V@75mA/Park & 150mA/Madison MPV18) AA13 T11 B25
L1 EV@SBY100505T-121Y-N/0.3A/120ohm_4 SPV10 VDDCI#1 GND#145 GND#87
+1.8V_GPU AN9 AB13 T13 B27
SPV10 VDDCI#2 GND#146 GND#88
AC12 T16 B29
VDDCI#3 C68 C138 C152 C99 C94 C153 C137 C77 C74 C75 GND#147 GND#89
AN10 AC15 T18 B31
B
C40 C44 C61 SPVSS VDDCI#4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1000p/50V_4
EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 GND#148 GND#90 B
AD13 T21 B33
EV@1u/6.3V_4 VDDCI#5 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 GND#149 GND#91
AD16 T23 B7
EV@10u/6.3V_6 EV@0.1u/10V_4_X7R VDDCI#6 GND#150 GND#92
M15 T26 B9
VDDCI#7 GND#151 GND#93
M16 U15 C1
VOLTAGE VDDCI#8 GND#153 GND#94
M18 U17 C39
120 ohm/300mA SENESE VDDCI#9 GND#154 GND#95
(1.8V@75mA SPV18) VDDCI#10
M23 modify 1230_B U2
GND#155 GND#96
E35
+1.8V_GPU L12 EV@SBY100505T-121Y-N/0.3A/120ohm_4 N13 U20 E5
VDDCI#11 GND#156 GND#97
T7 AF28 N15 U22 F11
FB_VDDC VDDCI#12 C66 C125 C78 GND#157 GND#98
N17 U24 F13
C203 C195 VDDCI#13 EV@10u/6.3V_6 GND#158 GND#99
*PAD N20 U27
EV@0.1u/10V_4_X7R VDDCI#14 EV@10u/6.3V_6 EV@10u/6.3V_6 GND#159
T8 AG28 N22 U6
EV@10u/6.3V_6 FB_VDDCI ISOLATED VDDCI#15 GND#160
R12 V11
*PAD CORE I/O VDDCI#16 R13 V16
GND#161
VDDCI#17 GND#163
T14 AH29 R16 V18
120 ohm/300mA FB_GND VDDCI#18 GND#164
(1.0V@120mA SPV10) VDDCI#19
T12 V21
GND#165
+1V L7 EV@SBY100505T-121Y-N/0.3A/120ohm_4 *PAD T15 V23
VDDCI#20 GND#166
V15 V26
VDDCI#21 GND#167
Y13 W2
C204 C194 VDDCI#22 GND#168
W6
EV@0.1u/10V_4_X7R GND#169
Y15
EV@10u/6.3V_6 EV@Madison/Park_M2 GND#170
Y17
GND#171
Y20
VDDC_SENSE/VSS_SENSE and VDDCI_SENSE/VSS_SENSE route as differetial pair GND#172
Y22 A39
GND#173 VSS_MECH#1
Y24 AW1
GND#174 VSS_MECH#2
Y27 AW39
GND#175 VSS_MECH#3
U13
GND#152
V13
GND#162
EV@Madison/Park_M2
+3V
GPU +3V power GPU all PWROK +3V_S5

+3V +3V
R111
A EV@10K_4 A
1
R113 R119
EV@4.7K_4 EV@10K_4 dGPU_PWROK 11,36
3
R112
2 *EV@0_6
EV@AO3413 Q12
2
3
Q9 EV@2N7002E
0.5A
3
R103 *EV@0_4 2 Q8
+1.5V_GPU
EV@PDTC143TT
+3V_D
1
C238 C582 C587 C589 +1.8V_GPU 2

R104 *Short_4
PROJECT : ZYD
Dr-Bios.com
1
6,40,41,42,43,46 MAINON
EV@1u/6.3V_4 EV@1u/6.3V_4
R105 *EV@0_4 EV@10u/6.3V_6 EV@0.1u/10V_4_X7R Q10 Size Document Number Rev
1
11,43 dGPU_VRON
EV@PDTC143TT 3B
Madison/Park M2 MEM I/F
5 4 3 2 1
5 4 3 2 1
+1.8V_GPU +1V
(1.8V@130mA DPA_VDD18) U18H (1.0V@110mA DPA_VDD10) 120 ohm/300mA
120 ohm/300mA DPA_VDD10 L8 EV@SBY100505T-121Y-N/0.3A/120ohm_4
L10 EV@SBY100505T-121Y-N/0.3A/120ohm_4 DPA_VDD18 DP C/D POWER DP A/B POWER
DPA_VDD18 AP20 AN24 DPA_VDD18 C199 C185 C202

C211 C208 C201 DPC_VDD18#1 DPA_VDD18#1 EV@1u/6.3V_4
AP21 DPC_VDD18#2 DPA_VDD18#2 AP24
EV@1u/6.3V_4 EV@10u/6.3V_6 EV@0.1u/10V_4_X7R
EV@10u/6.3V_6 EV@0.1u/10V_4_X7R
D D
DPA_VDD10 AP13 AP31 DPA_VDD10
DPC_VDD10#1 DPA_VDD10#1
AT13 DPC_VDD10#2 DPA_VDD10#2 AP32
AN17 DPC_VSSR#1 DPA_VSSR#1 AN27

AP16 DPC_VSSR#2 DPA_VSSR#2 AP27
AP17 DPC_VSSR#3 DPA_VSSR#3 AP28
AW14 DPC_VSSR#4 DPA_VSSR#4 AW24
AW16 DPC_VSSR#5 DPA_VSSR#5 AW26
DPA_VDD18 AP22 AP25 DPA_VDD18

DPD_VDD18#1 DPB_VDD18#1
AP23 DPD_VDD18#2 DPB_VDD18#2 AP26
DPA_VDD10 AP14 AN33 DPA_VDD10

DPD_VDD10#1 DPB_VDD10#1
AP15 DPD_VDD10#2 DPB_VDD10#2 AP33
C AN19 DPD_VSSR#1 DPB_VSSR#1 AN29 C

AP18 DPD_VSSR#2 DPB_VSSR#2 AP29
AP19 DPD_VSSR#3 DPB_VSSR#3 AP30
AW20 DPD_VSSR#4 DPB_VSSR#4 AW30
AW22 DPD_VSSR#5 DPB_VSSR#5 AW32
R106 EV@150/F_4 DPCD_CALR AW18 AW28 DPAB_CALR R423 EV@150/F_4 +1.8V_GPU

DPCD_CALR DPAB_CALR 120 ohm/300mA
(1.8V@20mA DPA_PVDD)
DPA_PVDD L20 EV@SBY100505T-121Y-N/0.3A/120ohm_4
DP E/F POWER DP PLL POWER
AH34 DPE_VDD18#1 DPA_PVDD AU28
DPE_VDD18 AJ34 AV27 C233 C225 C228
DPE_VDD18#2 DPA_PVSS EV@1u/6.3V_4
EV@10u/6.3V_6 EV@0.1u/10V_4_X7R
+1.8V_GPU
AL33 AV29 DPB_PVDD (1.8V@20mA DPB_PVDD) 120 ohm/300mA
DPE_VDD10 DPE_VDD10#1 DPB_PVDD L19 EV@SBY100505T-121Y-N/0.3A/120ohm_4
AM33 DPE_VDD10#2 DPB_PVSS AR28
+1.8V_GPU (1.8V@400mA DPE/F_VDD18)
180 ohm/1.5A C232 C227 C226
L3 DPE_VDD18
EV@HCB1608KF-181T15/180ohm/1.5A_6 EV@1u/6.3V_4
AN34 AU18 EV@10u/6.3V_6 EV@0.1u/10V_4_X7R +1.8V_GPU
DPE_VSSR#1 DPC_PVDD 120 ohm/300mA
AP39 DPE_VSSR#2 DPC_PVSS AV17
B C158 C173 C174 AR39 DPC_PVDD L15 EV@SBY100505T-121Y-N/0.3A/120ohm_4 B
EV@1u/6.3V_4 DPE_VSSR#3
AU37 DPE_VSSR#4 (1.8V@20mA DPC_PVDD)
EV@0.1u/10V_4_X7R EV@10u/6.3V_6 AW35 DPE_VSSR#5 C235 C224 C230
DPD_PVDD AV19
AR18 EV@1u/6.3V_4
DPD_PVSS EV@10u/6.3V_6 EV@0.1u/10V_4_X7R +1.8V_GPU
AF34 120 ohm/300mA
DPE_VDD18 DPF_VDD18#1 DPD_PVDD L21 EV@SBY100505T-121Y-N/0.3A/120ohm_4
AG34 DPF_VDD18#2
+1V (1.0V@400mA DPE/F_VDD10) AM37
180 ohm/1.5A DPE_PVDD
DPE_PVSS AN38 (1.8V@20mA DPD_PVDD)
L9 EV@HCB1608KF-181T15/180ohm/1.5A_6DPE_VDD10 C234 C223 C229
AK33 EV@1u/6.3V_4
DPE_VDD10 DPF_VDD10#1 EV@10u/6.3V_6 EV@0.1u/10V_4_X7R
AK34 DPF_VDD10#2
C215 C210 C198 AL38
EV@1u/6.3V_4 NC_DPF_PVDD
NC_DPF_PVSS AM35
EV@0.1u/10V_4_X7R EV@10u/6.3V_6
AF39 DPF_VSSR#1
AH39 +1.8V_GPU
DPF_VSSR#2 120 ohm/300mA
AK39 DPF_VSSR#3 (1.8V@40mA DPE/F_PVDD)
AL34 DPE_PVDD L44 EV@SBY100505T-121Y-N/0.3A/120ohm_4
DPF_VSSR#4
AM34 DPF_VSSR#5
C566 C571 C570
EV@1u/6.3V_4
A R62 EV@150/F_4 DPEF_CALR AM39 EV@10u/6.3V_6 EV@0.1u/10V_4_X7R A
DPEF_CALR
EV@Madison/Park_M2
PROJECT : ZYD
3B
Madison/Park M2 DPPW_GND
Dr-Bios.com
5 4 3 2 1
5 4 3 2 1
PIN STRAPS CONFIGURATION STRAPS

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
Memory Aperture size THEY MUST NOT CONFLICT DURING RESET
+3V_D
STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS DEFAULT REMARK

17 GPU_GPIO0
R49 *EV@10K/F_4 GPIO[13:11] Size
R46 *EV@10K/F_4 TX_PWRS_ENB GPIO0 0 = 50% TX OUTPUT SWING 0
17 GPU_GPIO1
1 = FULL TX OUTPUT SWING
D 000 128MB D
TX_DEEMPH_EN GPIO1 PCIE TRANSMITTER DE-EMPHASIS ENABLED 0
001 256MB 0 = TX DE-EMPHASIS DISABLED
R45 *EV@10K/F_4 1 = TX DE-EMPHASIS ENABLED
17 GPIO3_SMBDAT
ENABLE EXTERNAL BIOS ROM
R44 *EV@10K/F_4 010 64MB BIOS_ROM_EN GPIO_22_ROMCSB 0 = DISABLE 0
17 GPIO4_SMBCLK
1 = ENABLE
SCS#_GPIO22 R433 *EV@10K/F_4 011 32MB ROMIDCFG(2:0) GPIO[13:11] SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT
000 See Memory Aperture size
R72 *EV@10K/F_4
17 GPU_GPIO13
BIF_GEN2_EN_A GPIO2 0 = PCIE DEVICE AS 2.5GT/S CAPABLE 0
R60 *EV@10K/F_4 1 = PCIE DEVICE AS 5GT/S CAPABLE
17 GPU_GPIO12
17 GPU_GPIO11
R70 *EV@10K/F_4 Audio Table GPIO_8_ROMSO GPIO8
H2SYNC H2SYNC Reserved Only 0
EXT_HSYNC EXT_VSYNC GPIO_21_BB_EN GPIO21
17 GPU_GPIO2
R73 *EV@10K/F_4 Discription
AUD[1:0]
AUD[1] HSYNC 00: NO AUDIO FUNCTION.
R38 EV@10K/F_4 0 0 No Audio 01: AUDIO FOR DISPLAYPORT AND HDMI IF
17,24 EV_HSYNC
AUD[0] VSYNC ADAPTER IS DETECTED. 11 See Audio table
R39 EV@10K/F_4
17,24 EV_VSYNC
0 1 Any one by dectec 10: AUDIO FOR DISPLAYPORT ONLY.
11: AUDIO FOR BOTH DISPLAYPORT AND HDMI.

SIN_GPIO9 R424 *EV@10K/F_4
1 0 DP only
R35 *EV@10K/F_4 GPIO_9_ROMSI GPIO9 0 = VGA controller capacity enable 0
17 V2SYNC
C
1 1 Both DP & HDMI C
VIP_DEVICE_STRAP_ENA V2SYNC 0 = DRIVER would ignore the value sample on VHAD_0 during RESET. 0
DDR3 Memory Aperture size

EEPROM
U23 DDR3 VRAM size
SIN_GPIO9 5 2 SOUT_GPIO8
17 SIN_GPIO9 D Q SOUT_GPIO8 17
RAM_STRAP2 RAM_STRAP1 RAM_STRAP0
17 SCLK_GPIO10 6
C Vendor Vendor P/N STN B/S P/N Size
SCS#_GPIO22
DVPDATA_2 DVPDATA_1 DVPDATA_0
17 SCS#_GPIO22 1 S
7
+3V_D HOLD 512MB 1 1 0
R429 *EV@10K_4 3 W
Hynix H5TQ1G63BFR-12C AKD5LZGTW04
8 4
R425 VCC VSS (64M*16) 1GB 1 0 0
*EV@10K_4C585 *EV@M25P10-AVMN6P
*EV@0.1u/10V_4
2GB 1 0 1
B B
EEPROM is required on all GDDR5 designs

512MB 0 1 0
Thermal Sensor K4W1G1646E-HC12 AKD5LGGT506
NS none 1GB
+3V_D Samsung (64M*16) 0 0 0
WINDBOND AL83L771K02
GMT AL000780003 K4W2G1646B-HC12 AKD5MGGT500 2GB 0 0 1
R84
2
EV@10K_4
AMD 23EY2387MA-12 AKD5LGGT700
36 MXM_SMCLK12 3 1
+3V_D
0 1 0
Q7
EV@2N7002E +1.8V_GPU
+3V_D
+3V_D R435 *EV@10K/F_4

17 RAM_STRAP2
R85 R61
EV@10K_4 R430 EV@10K/F_4
R83 EV@10K_4 C219 EV@0.1u/10V_4_X7R
2
EV@10K_4
U5
36 MXM_SMDATA12 3 1 R434 *EV@10K/F_4
17 RAM_STRAP1
GPU_SMCLK 8 1
A SCLK VCC GPU_D+ 17 R436 A
Q6 EV@10K/F_4
EV@2N7002E GPU_SMDATA 7 SDA DXP 2 C209 RAM_STRAP2 SET DDR3 Vendor
RAM_STRAP[1:0] SET SIZE.
Dr-Bios.com
6 3 EV@2200p/50V_4 R431 *EV@10K/F_4
17 ALT#_GPIO17 ALERT# DXN
GPU_D- 17 R426
T31 4 5 EV@10K/F_4
OVERT# GND 17 RAM_STRAP0
*PAD
EV@G780-1P81U(MSOP)
$''5(66$+ PROJECT : ZYD
3B
Strip/Thermal
5 4 3 2 1
5 4 3 2 1
CRT(CRT) C650 0.22u/10V_4

1A/30V 1 2
D17
F1
CRTVDD5
16
+5V 2 1 2 1
CN13
SMD1206P100TF CRT
RSX101M-30
6
VGA_RED_SYS L48 BLM18BA750SN1D/300mA/47ohm_6 CRT_R1 1 11 CRT_11 T49
7
VGA_GRN_SYS L47 BLM18BA750SN1D/300mA/47ohm_6 CRT_G1 2 12 DDCDAT_1
8
INT_CRT_RED R470 IV@0_4 VGA_RED_SYS VGA_BLU_SYS L46 BLM18BA750SN1D/300mA/47ohm_6 CRT_B1 3 13 CRTHSYNC
8 INT_CRT_RED
INT_CRT_GRN R467 IV@0_4 VGA_GRN_SYS 9
8 INT_CRT_GRN
INT_CRT_BLU R464 IV@0_4 VGA_BLU_SYS 4 14 CRTVSYNC
8 INT_CRT_BLU
INT_VSYNC R137 IV@0_4 VSYNC R469 R466 R463 C668 C661 C659 C658 C660 C667 10
8 INT_VSYNC
INT_HSYNC R139 IV@0_4 HSYNC 5 15 DDCCLK_1
D 8 INT_HSYNC D
INT_CRT_DDCDAT R459 IV@0_4 CRTDDAT 150/F_4 150/F_4 150/F_4 10p/50V_4 10p/50V_4 10p/50V_4 10p/50V_4 10p/50V_4 10p/50V_4
VIN 8 INT_CRT_DDCDAT
INT_CRT_DDCCLK R460 IV@0_4 CRTDCLK
8 INT_CRT_DDCCLK
17
7/17 modify
C792 C787 C788

*10u/25V_1206 *10u/25V_1206 *10u/25V_1206
R468 EV@0_4 VGA_RED_SYS
17 EV_CRT_RED +3V
R465 EV@0_4 VGA_GRN_SYS
17 EV_CRT_GRN
R462 EV@0_4 VGA_BLU_SYS C361 R136 *short_4 CRTVSYNC
17 EV_CRT_BLU
R456 EV@0_4 VSYNC R138 *short_4 CRTHSYNC
17,23 EV_VSYNC
R457 EV@0_4 HSYNC 0.1u/10V_4 U6
17,23 EV_HSYNC +3V
R458 EV@0_4 CRTDDAT CRTVDD5 1 16 CRT_VSYNC1
17 EV_CRTDDAT VCC_SYNC SYNC_OUT2
0221 add for CRT issue R461 EV@0_4 CRTDCLK 14 CRT_HSYNC1
17 EV_CRTDCLK SYNC_OUT1 8/31 modify
7
C363 0.22u/25V_6 CRT_BYP VCC_DDC
8
BYP VSYNC C355 *0.1u/10V_4 CRTVDD5
15
SYNC_IN2 HSYNC R142 R141 CRTVDD5
+3V 2 13
VCC_VIDEO SYNC_IN1 2.7K_4 2.7K_4 C314 *10p/50V_4 CRTVSYNC
C360
CRT_R1 3 10 CRTDCLK R143 R140 C339 *10p/50V_4 CRTHSYNC
0.1u/10V_4 CRT_G1 VIDEO_1 DDC_IN1 CRTDDAT 2.7K_4 2.7K_4
4 11
CRT_B1 VIDEO_2 DDC_IN2 C308 10p/50V_4 DDCCLK_1
5
VIDEO_3 DDCCLK_1
9
DDC_OUT1 DDCDAT_1 C344 10p/50V_4 DDCDAT_1
6 12
GND DDC_OUT2
CM2009-02QR
+3V
LVDS(LDS) LCD Power(LDS)
C +3V C
+3V VIN
R78 R80
modify 1223_B
U20
2.2K_4 2.2K_4 C217 C218 C62 C178 C569
1u/6.3V_4 6 1 LCDVCC_R R404 *Short_8 LCDVCC
0.1u/10V_4 1000p/50V_4 4.7u/25V_8 1000p/50V_4 IN OUT
R93 EV@0_4 LCD_EDIDDATA 4 2
17 EV_LVDS_DDCDAT IN GND C555 C554 C553 C556
R79 IV@0_4 LVDS_VDDEN 3 5
8 INT_LVDS_EDIDDATA ON/OFF GND 1u/6.3V_4 *0.1u/10V_4 0.01u/16V_4 22u/6.3V_8
R94 EV@0_4 LCD_EDIDCLK
17 EV_LVDS_DDCCLK
AAT4280-4
R81 IV@0_4 R33
8 INT_LVDS_EDIDCLK
100K_4
R405 *EV@0_4 LVDS_BRIGHT +3V VIN

17 EV_LVDS_BRIGHT
CN3
R395 IV@SBY100505T-121Y-N/300mA/120ohm_4
G_5
8 INT_LVDS_BRIGHT
0.8A 40
r402 EV@SBY100505T-121Y-N/300mA/120ohm_4
36 CONTRAST 39
C565 *0.1u/10V_4 LCDVCC 38
37
Hall Sensor(HSR)
modify 1230_B 36
35 R355 100K_4
34 +3VPCU
Modify 1021 LCD_EDIDDATA
LCD_EDIDCLK 33
RN15 EV@0_4P2R TXLCLKOUT- C699 *22P/50V_4 LVDS_BRIGHT 32
17 EV_TXLCLKOUT- 3 4
TXLCLKOUT+ BL_ON 31 G_4
17 EV_TXLCLKOUT+ 1 2
RN11 EV@0_4P2R TXLOUT0- 30
17 EV_TXLOUT0- 3 4 30 MIC2_INTL1
TXLOUT0+ 29 LID591#
17 EV_TXLOUT0+ 1 2 30 MIC_GND 1 2
RN16 EV@0_4P2R TXLOUT1- 28
17 EV_TXLOUT1- 3 4
TXLOUT1+ TXUOUT2+ 27 MR1
17 EV_TXLOUT1+ 1 2
RN12 EV@0_4P2R TXLOUT2- TXUOUT2- 26 C482
17 EV_TXLOUT2- 3 4 Modify 1102
B
TXLOUT2+ 25 PT3661-BB
B
17 EV_TXLOUT2+ 1 2
3
TXUOUT1+ 24 0.1u/10V_4
RN1 EV@0_4P2R LVDS_VDDEN TXUOUT1- 23
17 EV_LVDS_VDDEN 3 4
LVDS_BLON 22
17 EV_LVDS_BLON 1 2
RN17 EV@0_4P2R TXUCLKOUT- TXUOUT0+ 21 G_2
17 EV_TXUCLKOUT- 3 4
TXUCLKOUT+ TXUOUT0- 20
17 EV_TXUCLKOUT+ 1 2
RN13 EV@0_4P2R TXUOUT0- 19
17 EV_TXUOUT0- 3 4
TXUOUT0+ TXUCLKOUT+ 18
17 EV_TXUOUT0+ 1 2
RN18 EV@0_4P2R TXUOUT1- TXUCLKOUT- 17
17 EV_TXUOUT1- 3 4
TXUOUT1+ 16
17 EV_TXUOUT1+ 1 2
RN14 EV@0_4P2R TXUOUT2- TXLOUT2+ 15
17 EV_TXUOUT2- 3 4
TXUOUT2+ TXLOUT2- 14 Modify 1022
17 EV_TXUOUT2+ 1 2
13
TXLOUT1+ 12
TXLOUT1- 11
10 G_1
INT_TXLCLKOUT+ RN7 IV@0_4P2R TXLCLKOUT+ TXLOUT0+ 9
8 INT_TXLCLKOUT+ 3 4
INT_TXLCLKOUT- TXLCLKOUT- TXLOUT0- 8
1 2
8 INT_TXLCLKOUT-
8 INT_TXLOUT0+
INT_TXLOUT0+ RN3 3 4 IV@0_4P2R TXLOUT0+ 7
6
Backlight Control(LDS)
INT_TXLOUT0- 1 2 TXLOUT0- TXLCLKOUT+
8 INT_TXLOUT0- 5
INT_TXLOUT1+ RN8 3 4 IV@0_4P2R TXLOUT1+ TXLCLKOUT-
8 INT_TXLOUT1+ 4
INT_TXLOUT1- 1 2 TXLOUT1-
8 INT_TXLOUT1- 3 +3V
INT_TXLOUT2+ RN4 3 4 IV@0_4P2R TXLOUT2+ USBP8+_R
8 INT_TXLOUT2+ 2
INT_TXLOUT2- 1 2 TXLOUT2- USBP8-_R
8 INT_TXLOUT2- 1
G_0
GS12401-1011-40P-R-NH
INT_LVDS_DIGON RN2 1 2 IV@0_4P2R LVDS_VDDEN R82
8 INT_LVDS_DIGON
INT_LVDS_BLON 3 4 LVDS_BLON 10K_4
8 INT_LVDS_BLON
INT_TXUCLKOUT+ RN9 3 4 IV@0_4P2R TXUCLKOUT+
8 INT_TXUCLKOUT+
INT_TXUCLKOUT- 1 2 TXUCLKOUT- BL_ON D10 2 1 BAS316 LID591# LID591# 36
8 INT_TXUCLKOUT-
INT_TXUOUT0+ RN5 3 4 IV@0_4P2R TXUOUT0+ R16
8 INT_TXUOUT0+
INT_TXUOUT0- 1 2 TXUOUT0-
8 INT_TXUOUT0-
INT_TXUOUT1+ RN10 3 4 IV@0_4P2R TXUOUT1+ 10K_4
8 INT_TXUOUT1+
3
8 INT_TXUOUT1-
INT_TXUOUT2+ RN6 3 4 IV@0_4P2R TXUOUT2+
8 INT_TXUOUT2+
3
8 INT_TXUOUT2-
A BL# 2 A
2 EC_FPBACK# 36
3
Q1
Dr-Bios.com
2N7002K Q3
CAMERA Module(CCD) DTC144EUA
1
LVDS_BLON 2
R90 *Short_4
Q2
L13 2N7002K
4 3 USBP8+_R R43
10 USBP8+
1
4 3 USBP8-_R
1 2
10 USBP8- 1 2
*DLW21HN900SQ2L/330mA/90ohm
100K_4 Quanta Computer Inc.
R89 *Short_4 PROJECT : ZYD
3B
CRT/LVDS
Amos 0325 Date: Tuesday, April 06, 2010 Sheet 24 of 50
5 4 3 2 1
5 4 3 2 1
HDMI-detect
IV@ HDMI LEVEL SHIFTER
+3V +3V
R639 *0_4
9 HDMI_HPD_PCH#
R626 R600
+3V 10K_4 EV@10K_4
HDMI_MB_HP
MB_HDMI_DDCDATA HDMI_HPD_EC# HDMI_HP_EV 17
36 HDMI_HPD_EC#
MB_HDMI_DDCCLK
3
C764 C771 C768 C765 C763 +3V R317 IV@4.7K_4 HDMI_HPD_EC# +5V
IV@2.2u/6.3V_6 IV@.1u/10V_4 IV@.1u/10V_4 IV@.1u/10V_4 IV@.1u/10V_4 DDCBUF_EN OE# control for power saving
CFG HP_EV 2
D D
+3V +3V R633
3
Active Buffer *10K_4
close to pin2/11/15/21/26/33/40/46 Q34
+3V EV@ME2N7002D
1
HDMI_MB_HP
36
35
34
33
32
31
30
29
28
27
26
25
U32 2
CCT2
CCT1
OE#
HPD_SINK
SDA_SINK
GND
VCC
SCL_SINK
DDC_EN
GND
GND
VCC
C777 C776 Q33
ME2N7002D
from PCH
1
*IV@.1u/10V_4 *IV@.1u/10V_4 37 24
GND GND MB_HDMITX0N
8 INT_HDMITX0N 38 23
IN_D1- OUT_D1- MB_HDMITX0P
8 INT_HDMITX0P 39 22
IN_D1+ OUT_D1+
+3V 40 21 +3V
VCC VCC MB_HDMITX2N
IN_D2- OUT_D2- MB_HDMITX2P
42 19
8 INT_HDMITX2P
43
IN_D2+
GND
OUT_D2+
GND
18
MB_HDMITX1P
I2C
8 INT_HDMITX1P 44 17
IN_D3- OUT_D3- MB_HDMITX1N
IN_D3+ OUT_D3+
+3V 46 15 +3V
VCC VCC MB_HDMICLK+
8 INT_HDMICLK+ 47 14
IN_D4- OUT_D4- MB_HDMICLK-
8 INT_HDMICLK- 48 13
IN_D4+ OUT_D4+ D24 2 1RB501V-40
HPDEN
49
HPD_S
SDA_S
SCL_S
GND +5V
REXT
TRIM
GND
GND
GND
VCC
VCC
NC
1
2
3
4
5
6
7
8
9
10
11
12
IV@SN75DP139 R603 +5V R621
+3V EV@1.5K/F_4 1.5K/F_4 Near HDMI connector
2
R611 *IV@4.7K_4 PC0 Q45 EV@BSN20
R619 *IV@4.7K_4 +3V +3V
LS_REXT
PC0 1 3
17 MXM_DDCCK
R617 *IV@4.7K_4 PC1 PC1
C C
R616 *IV@4.7K_4 DDCBUF_EN from PCH
R608 *IV@4.7K_4 R605 IV@3.9K/F_4 MB_HDMI_DDCCLK R629 IV@0_4 R631 *short_6 HDMI_DDCCLK_MB
R601 *IV@4.7K_4 CFG Control by pin4 HPDEN_R

R414 *IV@4.7K_4 +5V D25 2 1RB501V-40 C766
8 INT_HDMI_HPD
*.1u/10V_4
+5V
R622 IV@0_4 HDMI_DDCDATA_SW R623 R607
8 SDVO_CTRLDAT
EV@1.5K/F_4 1.5K/F_4
2
R609 IV@0_4 HDMI_DDCCLK_SW Q46 EV@BSN20
8 SDVO_CTRLCLK
17 MXM_DDCDAT 1 3
R615 IV@2.2K_4
+3V R628 IV@2.2K_4 MB_HDMI_DDCDATA R630 IV@0_4 R632 *short_6 HDMI_DDCDATA_MB
C774
*.1u/10V_4
B B
External Graphic HDMI source ESD Protect EMI HDMI connector

U35 *RClamp0524P MB_HDMITX2P
MB_HDMITX0N 1 10 MB_HDMITX0N CN19
C772 EV@0.1u/10V_4_X7R MB_HDMITX0N MB_HDMITX0P 1 10 MB_HDMITX0P R627 *100/F_4
17 HDMITX0N 2 9 20
C762 EV@0.1u/10V_4_X7R MB_HDMITX0P 2 9 MB_HDMITX2P SHELL1
17 HDMITX0P 3 1 22
MB_HDMITX2N GND_3/8 MB_HDMITX2N MB_HDMITX2N D2+SHELL3
4 7 2
C770 EV@0.1u/10V_4_X7R MB_HDMITX2N MB_HDMITX2P 4 7 MB_HDMITX2P MB_HDMITX2N D2 Shield
17 HDMITX2N 5 6 3
C767 EV@0.1u/10V_4_X7R MB_HDMITX2P 5 6 MB_HDMITX1P MB_HDMITX1P D2-
17 HDMITX2P 4
U34 *RClamp0524P D1+
5
C769 EV@0.1u/10V_4_X7R MB_HDMITX1P MB_HDMITX1P MB_HDMITX1P R606 *100/F_4 MB_HDMITX1N D1 Shield
17 HDMITX1P 1 10 6
C761 EV@0.1u/10V_4_X7R MB_HDMITX1N MB_HDMITX1N 1 10 MB_HDMITX1N MB_HDMITX0P D1-
17 HDMITX1N 2 9 7
2 9 MB_HDMITX1N D0+
3 8
C773 EV@0.1u/10V_4_X7R MB_HDMICLK+ MB_HDMICLK+ GND_3/8 MB_HDMICLK+ MB_HDMITX0N D0 Shield
17 HDMICLK+ 4 7 9
C775 EV@0.1u/10V_4_X7R MB_HDMICLK- MB_HDMICLK- 4 7 MB_HDMICLK- MB_HDMITX0P MB_HDMICLK+ D0-
17 HDMICLK- 5 6 10
5 6 CK+
11
U33 *RClamp0524P R618 *100/F_4 MB_HDMICLK- CK Shield
12
R625 R620 R610 R598 R599 R624 R613 R602 HDMI_DDCCLK_MB HDMI_DDCCLK_MB +5V CK-
1 10 13
EV@499/F_4 EV@499/F_4 EV@499/F_4 EV@499/F_4 HDMI_DDCDATA_MB 1 10 HDMI_DDCDATA_MB MB_HDMITX0N CE Remote
2 9 14
EV@499/F_4 EV@499/F_4 EV@499/F_4 EV@499/F_4 2 9 F2 HDMI_DDCCLK_MB NC
3 15
GND_3/8 MB_HDMICLK+ SMD1206P100TF HDMI_DDCDATA_MB DDC CLK
4 7 16
HDMI_MB_HP 4 7 HDMI_MB_HP D23 SSM22LLPT DDC DATA
5 6 2 1 17
3
5 6 R612 *100/F_4 GND

18
HDMI_MB_HP R162 *Short_4HP_DET +5V
19 23
Q35 MB_HDMICLK- HP DET
SHELL4
21
SHELL2
+5V 2
R604 QJ1119C-NK01-8F
R614 EV@2N7002E 100K_4

EV@100K_4
1
A A
5
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Date:
Document Number

PROJECT : ZYD
HDMI (SN75DP139)
1
Sheet 25 of 50
Rev
3B
5 4 3 2 1
Giga-LAN AR8151
+3V_S5 +3V_LAN
R178 *Short_6 +3V_LAN

D C368 C367 C370 C371 C369 D
10u/6.3V_8 10u/6.3V_8 1u/6.3V_4 0.1u/10V_4 *1000p/50V_4 U7
1 22 AVDDH C353 0.1u/10V_4

VDD33 AVDDH
2 PERSTn CLKREQn/LED2 23
4,10,11,28,31,36 PLTRST#
3 24 DVDDL C358 0.1u/10V_4
8,28 PCIE_WAKE# WAKEn DVDDL
4 25 SMCLK_8151 R170 *0_4
10 CLK_PCIE_LAN_REQ# CLKREQn SMCLK SMB_CLK_ME0 10
C670 0.1u/10V_4 +VDDCT 5 VDDCT
AR8151
5X5mm SMDATA 26 SMDATA_8151 R163 *0_4
SMB_DATA_ME0 10
C671 1u/6.3V_4 AVDDL 6 40-Pin QFN 27
AVDDL_REG TESTMODE
C669 0.1u/10V_4 XTLO 7 28 AVDDH
XTLO TEST_RST
XTLI 8 29 PCIE_RXN1_LAN_R 0.1u/10V_4_X7R C379
XTLI TX_N PCIE_RX1- 10
C665 1u/6.3V_4 AVDDH 9 30 PCIE_RXP1_LAN_R 0.1u/10V_4_X7R C380
AVDDH_REG TX_P PCIE_RX1+ 10
C666 0.1u/10V_4 R147 2.37K/F_4 RBIAS 10 31 AVDDL C375 0.1u/10V_4
RBIAS AVDDL
C C
27 LAN_TRD0P 11 TRXP0 REFCLK_N 32
CLK_PCIE_LOM# 10
27 LAN_TRD0N 12 TRXN0 REFCLK_P 33

CLK_PCIE_LOM 10
C664 0.1u/10V_4 AVDDL 13 34 AVDDL C373 0.1u/10V_4
NC/AVDDL AVDDL
27 LAN_TRD1P 14 TRXP1 RX_P 35 PCIE_TX1+ 10
27 LAN_TRD1N 15 TRXN1 RX_N 36 PCIE_TX1- 10

C663 0.1u/10V_4 AVDDH 16 37 DVDDL C374 1u/6.3V_4
NC/AVDDH DVDDL_REG
C359 33p/50V_4 XTLO 17 38 LAN_ACTLED C376 0.1u/10V_4
27 LAN_TRD2P NC/TRXP2 LED0 LAN_ACTLED 27
1
18 39 LAN_LINKLED#
27 LAN_TRD2N NC/TRXN2 LED1 LAN_LINKLED# 27
1.2H Y1
25MHz C662 0.1u/10V_4 AVDDL 19 40 LX L24 4.7uH/1A_2X2 +VDDCT
NC/AVDDL LX
2
C354 33p/50V_4 XTLI 20 41 C377 C378 C381

27 LAN_TRD3P NC/TRXP3 GND
21 10u/6.3V_8 0.1u/10V_4 *1000p/50V_4
27 LAN_TRD3N NC/TRXN3
AR8151
B B
LAN_TRD0P
LAN_TRD1P
LAN_TRD2P
LAN_TRD3P
LAN_TRD0N
LAN_TRD1N
LAN_TRD2N
LAN_TRD3N
R155
R154
R153
R152
R151
R150
R149
R148
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
LAN_N1
LAN_N2
LAN_N3
LAN_N4
C338 C337 C336 C335

A A
0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4

PROJECT : ZYD
3B
GLAN BCM57780
Dr-Bios.com
5 4 3 2 1
1 2 3 4 5 6 7 8
L23 +VDDCT
PBY160808T-181Y-N/2A/180ohm_6
C278 C255 C259 C267
A C285 1U/10V_4 A
0.1u/10V_4_X7R 0.1u/10V_4_X7R 0.1u/10V_4_X7R 0.1u/10V_4_X7R
CN11
Close to Transformer pin 1,4,7,10 TRANSFORMER R439 220_8 LAN_ACT_LED_PWR
9 YELLOW_N
26 LAN_ACTLED 10 YELLOW_P
R437 5.1K_4 14
X-TX0P GND2
1 0+ GND1 13
U25 X-TX0N 2
X-TX1P 0-
1 TCT1 MCT1 24 3 1+
LAN_TRD0P 2 23 X-TX0P X-TX2P 4
26 LAN_TRD0P TD1+ MX1+ 2+
LAN_TRD0N 3 22 X-TX0N X-TX2N 5
26 LAN_TRD0N TD1- MX1- 2-
X-TX1N 6
X-TX3P 1-
4 TCT2 MCT2 21 7 3+
LAN_TRD1P 5 20 X-TX1P X-TX3N 8 Modify 1028
26 LAN_TRD1P TD2+ MX2+ 3-
LAN_TRD1N 6 19 X-TX1N
26 LAN_TRD1N TD2- MX2-
26 LAN_LINKLED#
7 18 LAN_LINKLED# 11
LAN_TRD2P TCT3 MCT3 X-TX2P R454 220_8 LAN_LNK_LED_PWR GREEN_N
26 LAN_TRD2P 8 TD3+ MX3+ 17 +3V_LAN 12 GREEN_P
26 LAN_TRD2N TD3- MX3- RJ45
B 10 TCT4 MCT4 15 B
LAN_TRD3P 11 14 X-TX3P
26 LAN_TRD3P TD4+ MX4+
26 LAN_TRD3N TD4- MX4-
LFE9276A-R
LAN_ACT_LED_PWR
R130 R131 R132 R133
75/F_8 75/F_8 75/F_8 75/F_8 LAN_LINKLED#
Delta9276A-R DBBL5MLAN01
Delta9276C-R DB0ZR1LAN00 C243 C633
*0.1u//50V_8 *0.1u//50V_8
C252
1500p/3KV_18
C C
D D
1 2
Dr-Bios.com 3 4 5 6
Size
Date:
Document Number
7
PROJECT : ZYD
LAN Transformer and RJ45
Tuesday, April 06, 2010 Sheet 27 of
8
50
Rev
3B
1 2 3 4 5 6 7 8
MINI-CARD WLAN(MPC)
+1.5V_Mini2_VDD +3V_Mini2_VDD
modify 1223_B
+3.3V: 1000mA +3V_Mini2_VDD H=5.6mm modify 1026
+3.3Vaux:330mA +3V_Mini2_VDD +1.5V +1.5V_Mini2_VDD
CN8 LTS_AAA-PCI-046-K01
+1.5V:500mA R634 R410 *Short_8
51 52
R455 *0_4 CL_RST1#_WLAN Reserved +3.3V
10 CL_RST1# 49 50 *10K_4
Reserved GND
1
R452 *0_4 CL_DATA1_WLAN 47 48 C573
10 CL_DATA1 Reserved +1.5V
R451 *0_4 CL_CLK1_WLAN 45 46 C529 C546
10 CL_CLK1 Reserved LED_WPAN#
43 44 *0.1u/10V_4 *0.47u/10V_6 *10u/6.3V_8
2
Reserved LED_WLAN# RFLED2# R401 *Short_4 RF_LED#
41 42
Reserved LED_WWAN#
39 40
Reserved GND
37 38 USBP10+ 10
Reserved USB_D+
A 35 36 USBP10- 10 A
GND USB_D-
33 34
10 PCIE_TX2+ PETp0 GND CLK_SDATA
31 32
10 PCIE_TX2- PETn0 SMB_DATA CLK_SCLK
29
GND SMB_CLK
30 Modify 1102
27
GND +1.5V
28 Modify 1102
10 PCIE_RX2+ 25 26
PERp0 GND +3V +3V_Mini2_VDD
10 PCIE_RX2- 23 24
PERn0 +3.3Vaux
21 22 PLTRST# 4,10,11,26,31,36
GND PERST# RF_EN R26 *Short_8
19 20
UIM_C4 W_DISABLE#
17 UIM_C8 GND 18
C528
15 16 C521 C579 C564 C542
GND UIM_VPP 10u/6.3V_8 0.1u/10V_4 0.1u/10V_4 *4.7U/6.3V_6
10 CLK_PCH_SRC1 13 REFCLK+ UIM_RST 14
11 12 0.1u/10V_4
10 CLK_PCH_SRC1# REFCLK- UIM_CLK
9 10
GND UIM_DATA
10 CLKREQ_3G# 7 CLKREQ# UIM_PWR 8
5 Reserved +1.5V 6
3 4
GND
GND
PCIE_WAKE#_R Reserved GND
1 2
WAKE# +3.3V
+WL_VDD
53
54
2
Q27
*DTC144EUA
3 1 PCIE_WAKE#_R
8,26 PCIE_WAKE#
B B
MINI-CARD (MNC)Reserve for BA70
Check LED signal. (active high or low)

modify 0106_B H=7.0mm modify 1223_B
modify 1223_B LTS_AAA-PCI-049-K01 +3V +WL_VDD
CN10
51 Reserved +3.3V 52 +WL_VDD
49 50 R448 *Short_8 +WL_VDD
R453 *Short_4 Reserved GND
10 PCI_RST# 47 48 +1.5V
R450 *Short_4 Reserved +1.5V
10 CLK_LPC_DEBUG 45 46
Reserved LED_WPAN# RFLED# R447 *Short_4 C623 C634 C620 C591 C618
43 44 RF_LED# 32,36
Reserved LED_WLAN# 10u/10V_8 0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4
+WL_VDD 41 42
Reserved LED_WWAN# *4.7U/6.3V_6
39 40
Reserved GND
37 Reserved USB_D+ 38 USBP13+ 10
35 GND USB_D- 36 USBP13- 10
10 PCIE_TX6+ 33 34
PETp0 GND
10 PCIE_TX6- 31 32
PETn0 SMB_DATA CLK_SDATA 3,14,15
29
GND SMB_CLK
30
CLK_SCLK 3,14,15
Modify 1102
27 28 +1.5V
GND +1.5V
10 PCIE_RX6+ 25 26
PERp0 GND
10 PCIE_RX6- 23 24 +WL_VDD
PERn0 +3.3Vaux PLTRST#
21 GND PERST# 22
19 20 +1.5V
UIM_C4 W_DISABLE# RF_EN 36
17 UIM_C8 GND 18
15 16 A_LFRAME#_R R386 *Short_4

GND UIM_VPP LPC_LFRAME# 9,36
13 14 A_LAD3_R R382 *Short_4
10 CLK_PCH_SRC2 REFCLK+ UIM_RST LPC_LAD3 9,36
C 11 12 A_LAD2_R R379 *Short_4 C
10 CLK_PCH_SRC2# REFCLK- UIM_CLK LPC_LAD2 9,36
9 10 A_LAD1_R R378 *Short_4
GND UIM_DATA LPC_LAD1 9,36
7 8 A_LAD0_R R377 *Short_4 C622 C632 C598
10 PCIE_CLK_REQ2# CLKREQ# UIM_PWR LPC_LAD0 9,36
5 6 +1.5V 1000p/50V_4 0.1u/10V_4 10u/6.3V_8
Reserved +1.5V
3 4
GND
GND
PCIE_WAKE#_R Reserved GND

1 WAKE# +3.3V 2 +WL_VDD
modify 1223_B
53
54
D D
Dr-Bios.com
PROJECT : ZYD
3B
MINI PCI-E card/TV
1 2 3 4 5 6 7 8
1 2 3 4
EE RETURN-PATH CAPACITORS
MAIN SATA HDD
+5V C757 *.01u/25V_4 VIN
CN16 VIN
23 C590 *.01u/25V_4
GND23
A A
1 C20 0.1u/25V_4_X5R
GND1 SATA_TXP0_C C733 .01u/25V_4 +5V
RXP 2 SATA_TXP0 9
3 SATA_TXN0_C C730 .01u/25V_4 SATA_TXN0 9 C506 0.1u/25V_4_X5R
RXN
GND2 4
5 SATA_RXN0 C722 .01u/25V_4 +3V C674 *.01u/25V_4 VIN C752 *.1u/10V_4 C621 0.1u/25V_4_X5R
TXN SATA_RXN0_C 9
6 SATA_RXP0 C716 .01u/25V_4
TXP SATA_RXP0_C 9
7 C751 *.1u/10V_4 C619 0.1u/25V_4_X5R
GND3
+5V_S5 C474 *.1u/10V_4 C677 *.1u/10V_4 C485 0.1u/25V_4_X5R

3.3V 8
9 C475 *.01u/25V_4 C609 *.1u/10V_4 C509 0.1u/25V_4_X5R
3.3V
3.3V 10
11 C754 *.1u/10V_4 C641 0.1u/25V_4_X5R
GND
GND 12
13 +5V C649 *.01u/25V_4 +3V C608 *.1u/10V_4 C508 0.1u/25V_4_X5R
GND +5V_HDD
5V 14
15 C679 *.1u/10V_4 C642 0.1u/25V_4_X5R
5V C448 *.1u/10V_4
5V 16 +3V
17 C753 *.1u/10V_4 C55 0.1u/25V_4_X5R
GND
RSVD 18
B GND 19 modify 1223_B B
12V 20
12V 21
12V 22
R506 *Short_8 +5V_HDD
+5V
GND24 24
C682 C683 C687 C686 C685 C684
MAIN_SATA +
100u/6.3V_3528 10u/10V_8 *.1u/16V_4 *.1u/16V_4 .01u/25V_4 .01u/25V_4
ODD (SATA)
CN12
GND14 14
C C
GND 1
2 SATA_TXP1_C C283 .01u/25V_4 SATA_TXP1 9
A+ SATA_TXN1_C C280 .01u/25V_4
A- 3 SATA_TXN1 9
GND 4
5 SATA_RXN1 C269 .01u/25V_4
B- SATA_RXN1_C 9
6 SATA_RXP1 C265 .01u/25V_4
B+ SATA_RXP1_C 9
GND 7
+5V_ODD +5V
8 SATA_DPR449 1K_4
DP R446 *Short_8
5V 9
5V 10
C615 C614 C613 C616 C617 C610
+
MD 11
GND 12
13 .01u/25V_4 .01u/25V_4 *.1u/16V_4 *.1u/16V_4 10u/10V_8 100u/6.3V_3528
GND
GND15 15
C16654-122A4-L_Serial_ATA
D sata-127382fr013s219zr-13p-r D
DFHS13FR006 Quanta Computer Inc.

PROJECT : ZYD
3B
SATA-HDD/ODD/USB-ESATA
Dr-Bios.com
1 2 3 4
5 4 3 2 1
Codec(ADO) Headphone
(CX20672-11Z for QFN) 1 CN18 7

HPL R314 39/F_4 HPL_1 L38 SBK160808T-121Y-N_6 HPL_SYS 2
(ADO) FILT_1.65V AVDD_3.3 AVDD_3.3 pin is output of 6
HPR R298 39/F_4 HPR_1 L37 SBK160808T-121Y-N_6 HPR_SYS 3
C710 C712
internal LDO. Do NOT connect LINEOUT_JD# 4
0.1U/10V/X5R_4 C447 C453 to external supply. 8
1U/10V/X5R_6 10U/10V/X5R_8 modify 1230_B 5
D 0.1U/10V/X5R_4 C467 C472 JA6331-0230T3B-8H D
R305 R311 2200p/50V_6 2200p/50V_6
*20K_4 *20K_4
ADOGND
L58 TI321611U480_1206 +3AVDD ADOGND
+3V
Determines the signaling voltage that C743 C738 C727
is being used on the host system 10U/10V/X5R_8 0.1U/10V/X5R_4
0.1U/10V/X5R_4
ADOGND
+3V R277 *Short_6 Modify 1020
+5V_ADO
C461 C462 +5V_ADO
0.1U/10V/X5R_4 C723 C724
1U/10V/X5R_6 0.1U/10V/X5R_4 D21
10U/10V/X5R_8 1
Layout Note: Path from +5V to LPWR_5.0 and
+3.3V_AUX LINEOUT_JD#
L34 *TI321611U480_1206 R333
RPWR_5.0 must be very low resistance ( <0.01 ohms). 3
+3V_S5
0.1/F_1206 2
Place bypass caps very close to device.
+3V L52 TI321611U480_1206
*DA204U
C706 C711 R37 only needed if supply to VAUX_3.3 is
0.1U/10V/X5R_4 CLASSD_5V
10U/10V/X5R_8
removed during system re-start.
FILT_1.8V
C739
INT. MIC
Note: C713 C719 0.1U/10V/X5R_4 C740 C741 C744 C747
R539 0.1U/10V/X5R_4 0.1U/10V/X5R_4 10U/10V/X5R_8
To support Wake-on-Jack, the CODEC VAUX_3.3 pins 10U/10V/X5R_8 0.1U/10V/X5R_4 10U/10V/X5R_8
10K_4
must be powered by a Standby supply.
MIC2_R C703 2.2U/6.3V/X5R_6
18
26
29
27
28
12
15
17
3
2
7
C746 U29
*22P/50V_4 MIC2_L C702 2.2U/6.3V/X5R_6 MIC2_INTL1
FILT_1.8
VAUX_3.3
VDD_IO
DVDD_3.3
AVDD_HP
FILT_1.65
AVDD_3.3
AVDD_5V
LPWR_5.0
RPWR_5.0
CLASSDREF
MIC2_INTL1 24
Use as needed for EMI.
R536 5.11K/F_4 +3.3V_AUX
MIC2-VREFO MIC_GND 24
C728 9 R534 4.7K_4
9 PCH_AZ_CODEC_RST# RESET# R533 39.2K/F_4 LINEOUT_JD#
*22P/50V_4 10u/6.3V_6
R529
C R546 *Short_4 5 36 SENSE_A R535 10K_4 1% MIC_JD# C704 *Short_4 C
9 PCH_AZ_CODEC_BITCLK BIT_CLK SENSE_A
9 PCH_AZ_CODEC_SYNC 8
PCH_AZ_CODEC_SDIN0_R SYNC
9 PCH_AZ_CODEC_SDIN0 6
R551 33_4 SDATA_IN
9 PCH_AZ_CODEC_SDOUT 4
SDATA_OUT
ADOGND
C725
*22P/50V_4 35 MIC2_R ADOGND
PORTB_R MIC2_L
34
PORTB_L MIC2-VREFO
33
C742 B_BIAS
R561 33_4 SPKR_R1 0.1U/10V/X5R_4 SPKR_R2 10 32 MIC1_VREFO
9 SPKR PC_BEEP C_BIAS MIC1_R1
31
PORTC_R MIC1_L1
39 30
SPDIF PORTC_L
SPKR_R1 EAPD# 38 CX20672-11Z
MUTE# GPIO0/EAPD#
37
GPIO1/SPK_MUTE# EXT. MIC
25
NC_DR
24
NC_DL
C745 23 HPR
*1000P/16V/X7R_4 PORTA_R HPL
40 22
DMIC_CLK PORTA_L D12 MIC1_VREFO_R
1
DMIC_1/2 AVEE BAS316
21
AVEE MIC1_VREFO
20
FLY_N
19
FLY_P C737 1U/10V/X5R_6 D13 MIC1_VREFO_L
EP_GND
RIGHT+
C735 C736 BAS316

RIGHT-
LEFT+
LEFT-
0.1U/10V/X5R_4
10U/10V/X5R_8 R269 R247
2.2K_4 2.2K_4 BLACK

11
13
14
16
41
1 CN17 7
MIC1_L1 C440 2.2U/6.3V/X5R_6 MIC1_L2 R270 100_6 MIC1_L3 L35 MIC1_L 2
SBK160808T-121Y-N/400mA/120ohm_6 6
MIC1_R1C433 2.2U/6.3V/X5R_6 MIC1_R2 R248 100_6 MIC1_R3 L33 MIC1_R 3
ADOGND SBK160808T-121Y-N/400mA/120ohm_6 4
MIC_JD# 8
5
modify 1230_B C426 C460 JA6331-0230T3B-8H 10/5 modify
R_SPK+
B B
560P/50V_6 560P/50V_6 Normal OPEN Jack
R_SPK-
Max. 100mVrms input for Mic-IN
L_SPK-
L_SPK+ ADOGND
Modify 1020 Modify 1020

+5V_ADO
D11
1
MIC_JD#
3
*DA204U
Power (ADO) Mute(ADO) Add it for EMI_C test

Internal Speaker(AMP)
Demodulation Filter L65 Place close to Codec R635 *Short_4

R636 *Short_4
+3V R637 *Short_4
Modify 1019 R638 *Short_6
DIGITAL ANALOG
R640 *Short_6
L31 MLB-201209-0030P-N1-RU CN7
+5V +5V_ADO R526 R_SPK- R344 *Short_6 R_SPK-_1
9/29 apply for ESD improve R_SPK+ R343 *Short_6 R_SPK+_1 1
U11 10K_4 R347 *Short_6 L_SPK- R342 *Short_6 L_SPK-_1 25
R252 *Short_6 L_SPK+ R341 *Short_6 L_SPK+_1 36
3 4
IN OUT MUTE# BAS316 D19 PCH_AZ_CODEC_RST# R306 *Short_6 4
A 2 R243 *Short_6 C479 C478 C477 C476 A

GND R224 *Short_6 SPEAKER-CON
1 5 R238 *29.4K/F_4 *BAS316 D20 EAPD# R223 *Short_6 *100P/50V_6 *100P/50V_6 *100P/50V_6 *100P/50V_6
Dr-Bios.com
SHDN SET R345 *0_6
*G923-330T1UF R346 *Short_6
R241 + C415 C425 BAS316 D18 R517 *0_6
AMP_MUTE# 36
*10K/F_4 R286 *Short_6
10u/10V_3216 0.1u/10V_4
C411 C416 R518 *Short_6
+ R242 *0_4 R589 *0_6
R590 *Short_6
0.1u/10V_4 10u/10V_3216 R568 *0_6
R519 *Short_6 9/21 modify
C690 *1000p/50V_4
C444 *Short_4
PROJECT : ZYD
Modify 1020 Size Document Number Rev
Vset =1.25V CX20672-11Z 3B
C730, C787 close U37 pin3 and L65 ADOGND
Vout =Vset[1+AR(1,2)/AR(2,GND)] Date: Tuesday, April 06, 2010 Sheet 30 of 50
5 4 3 2 1
A B C D E
Cardreader CONN(MMC)
+5V_S5 +3V
C672 C372
*0.1u/10V_4 *0.1u/10V_4
4 4
CN5
+3V 20 20
19 19
+5V_S5 18 18
17 17
16 16
15 15
14 14
10 USB_OC1_5# 13 13
4,10,11,26,28,36 PLTRST# 12 12
33,36 USBON# 11 11
10 10
USBP11-_R 9
USBP11+_R 9
to USB board USB connector 8 8
7 7
to USB board card reader USBP12-_R 6
USBP12+_R 6
5 5
3 4 4 3
USBP3-_R 3
USBP3+_R 3
to USB board USB connector 2 2
1 1
USB_CONN
R338 *Short_4
L39
2 1 USBP3+_R Modify 1028
10 USBP3+ 2 1
3 4 USBP3-_R
10 USBP3- 3 4
*RFCMF1632100M3T/200mA/90ohm
R340 *Short_4
R641 *Short_4
L59
2 1 USBP12+_R
10 USBP12+ 2 1
3 4 USBP12-_R
10 USBP12- 3 4
2 R642 *Short_4 2
R643 *Short_4
L60
2 1 USBP11+_R
10 USBP11+ 2 1
3 4 USBP11-_R
10 USBP11- 3 4
R644 *Short_4
Amos 03/25
1 1
A
Dr-Bios.com B C D
Size
Date:
Document Number

PROJECT : ZYD
CardReader &USB/B
Sheet
E
31 of 50
Rev
3B
5 4 3 2 1
LED(UIF)
POWER BOARD CONN(UIF)
+3V_S5
D D
POWER Amber
LED1
SUSLED# R349 3.6K_4 SUSLED#_R 4 2
36 SUSLED#
PWRLED# R350 2.37K_4 PWRLED#_R 3 1
36 PWRLED#
LED_A/B
Modify 1028
Blue
R352 *1M_4 +3VPCU
modify 0322_ramp R354 *1M_4

+3VPCU
+3V
Battery Amber
CN1
12 LED2
11 14 R351 3.3K/F_4 BATLED1#_R 4 2
36 BATLED1#
10 13
9 R353 3.3K/F_4 BATLED0#_R 3 1
C 36 BATLED0# C
D1 BAS316 NBSWON#_R 8
36 NBSWON#
modify 1230_B 7
Modify 1028 LED_A/B
6
36 RF_LED_EN#
SATA_LED#_R
5
4
Blue
28,36 RF_LED# 3
2
+3V 1
POWER/B
R9
5
10K/F_4 1
4 SATA_LED#_R
9 SATA_ACT# 2
U15
3
*TC7SH08FU
R10 *Short_4
B B
modify 1223_B
A A

PROJECT : ZYD
Dr-Bios.com
3B
POWER/MMB/LAUNCH/LED
5 4 3 2 1
5 4 3 2 1
BLUETOOTH CONNECTOR(BTM)
modify 1223_B
D D
CN6
+3V_S5 1 3 BT_POWER
5
Q24 4
+ C481 10 USBP4+ 3
C480
10 USBP4-
2
AO3413 1000p/50V_4 BT_LED 2 7
2.2u/6.3V_6 T69 1 6
36 BT_POWERON#
BT_CONN
C473
*.01u/16V_4
Modify 1022
C C
modify 0224_C
USBX1(USB)
+5V_S5
C399 U10
1u/10V_4 2 8 USBPWR1
IN1 OUT3
3 IN2 OUT2 7
6 C678 C676
OUT1 +
31,36 USBON# 4 EN#
1 1000p/50V_4
GND
OC# 5
330u/6.3V_6X5.7
B G547F2P81U B
10 USB_OC0#
CN15
1 1 8 8
USBP1-_R 2 7
USBP1+_R 2 7
3 3 6 6
4 4 5 5
USB_MB_Turbo
1
RV2 RV1
R195 *Short_4
*EGA-0402 *EGA-0402
2
L28
2 1 USBP1-_R
10 USBP1- 2 1
3 4 USBP1+_R
10 USBP1+ 3 4
A R197 *Short_4 A
Amos 03/25 Quanta Computer Inc.

PROJECT : ZYD
3B
USB/ BT
Dr-Bios.com
5 4 3 2 1
5 4 3 2 1
K/B CN2 CPU FAN(THM)

MY0 1
36 MY0
7 8 MX2 MY1 2
36 MY1
5 6 MX3 MY2 3
36 MY2
3 4 MX4 MY3 4
36 MY3
1 2 MX5 MY4 5
36 MY4 +5V +5V
CP6 *100p/50Vx4 MY5 6 +3V +3V +3V
36 MY5
7 8 MX6 MY6 7
36 MY6
5 6 MX7 MY7 8
D 36 MY7 D
3 4 MY17 MY8 9
36 MY8
1 2 MY16 MY9 10 R97 R96 R98 R99
36 MY9
CP5 *100p/50Vx4 MY10 11
36 MY10
7 8 MY3 MY11 12 10K_4 10K_4 10K_4 10K_4
36 MY11
5 6 MY2 MY12 13
36 MY12
3 4 MY1 MY13 14 R100
36 MY13
1 2 MY0 MY14 15 FAN_PWM_E
36 MY14
CP1 *100p/50Vx4 MY15 16 *10K_4 CN9
36 MY15 36 FANSIG
7 8 MY7 MY16 17
36 MY16 1
2
5 6 MY6 MY17 18
36 MY17 2
3
3 4 MY5 MX7 19
36 MX7 3
1 2 MY4 MX6 20 2 Q5 1 3 FAN_PWM_CN
36 MX6 10,11,36 SML1ALERT# 4
CP2 *100p/50Vx4 MX5 21 MMBT3904
36 MX5
7 8 MY11 MX4 22 Q4 30mil FAN
36 MX4
1
5 6 MY10 MX3 23 MMBT3904
36 MX3
3 4 MY9 MX2 24 27
36 MX2 36 CPUFAN#
1 2 MY8 MX1 25 28
36 MX1
CP3 *100p/50Vx4 MX0 26
36 MX0
7 8 MY15
5 6 MY14 KB
3 4 MY13 +3VPCU
1 2 MY12
CP4 *100p/50Vx4
C
C518 *100p/50V_4 MX1
MX0
RP1 10K_10P8R TOUCHPAD & Switch CONN.(TPD) C
C519 *100p/50V_4 10 1 MX3
MX4 9 2 MX2
MX5 8 3 MX1
MX6 7 4 MX0 modify 1223_B
MX7 6 5 +5V +5V
L18 *Short_8 +TPVDD
C239
HOLE18 HOLE10 HOLE20 HOLE1 HOLE31 HOLE30 HOLE28 HOLE23 HOLE13
*HG-C315D110P2 *HG-C315D110P2 *HG-C315D110P2 *HG-C315D110P2 *HG-C315D110P2 *HG-C315D110P2 *h-c236d146p2 *h-c236d146p2 *h-c197d122p2 R91 R92 0.1u/10V_4_X7R
7 6 7 6 7 6 7 6 7 6 7 6 10K_4 10K_4 CN4
8 5 8 5 8 5 8 5 8 5 8 5 1
9 4 9 4 9 4 9 4 9 4 9 4 2
L16 *Short_6 TPDATA_R 3
36 TPDATA
L17 *Short_6 TPCLK_R 4
36 TPCLK
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
5
6
C240 C241 RIGHT# 7
HOLE7 HOLE33 HOLE32 HOLE3 HOLE26 HOLE8 HOLE5 8
*HG-C315D110P2 *hg-c236d118p2 *HG-C315D110P2 *HG-C315D110P2 HOLE34 HOLE35 *h-c236d118p2 *h-c197d122p2 *h-c197d122p2 *.01u/25V_4 9
7 6 7 6 7 6 7 6 *h-re75x47d75x47n
*h-re75x47d75x47n *.01u/25V_4 10 13
8 5 8 5 8 5 8 5 11 14
B 9 4 9 4 9 4 9 4 LEFT# 12 B
Aces 88501-120N
1
2
3
1
2
3
1
2
3
1
2
3
1
1
HOLE25 HOLE24 HOLE14 HOLE19 HOLE2 HOLE22 HOLE21 HOLE16 HOLE17

*HG-C315D110P2 *HG-C315D110P2 *HG-C315D110P2 *HG-C315D110P2 *HG-C315D110P2*h-c236d142p2 *h-c236d142p2 *h-c236d142p2 *h-c236d142p2 SW3 SW2
7 6 7 6 7 6 7 6 7 6 RIGHT# 3 2 LEFT# 3 2
1
8 5 8 5 8 5 8 5 8 5 1 4 1 4
9 4 9 4 9 4 9 4 9 4 RV3 RV4
SWITCH_1.5 SWITCH_1.5
*EGA-0402 *EGA-0402
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
2
PAD13 PAD10 PAD11 PAD12
*h-r394x315pt
*PAD-C157 *PAD-C157 *PAD-C157
1
A PAD1 PAD5 PAD4 PAD3 PAD6 PAD2 PAD7 PAD8 PAD9 A

*PAD-C157 *PAD-C157 *PAD-C157 *PAD-C157 *PAD-C157 *PAD-C157 *PAD-C157 *PAD-C157 *PAD-C157
HOLE27 HOLE29 HOLE9 HOLE4 HOLE11 HOLE15 HOLE12
*h-c236d142p2 *h-c177d79p2 *H-TC276BC190D142P2 *H-C236D110P2 *h-ts228bc197d51p2 *h-c197d87p2 *H-C236D110P2
1
PROJECT : ZYD
1
1
3B
KB/FAN/TP+FP
Dr-Bios.com
5 4 3 2 1
1 2 3 4 5 6 7 8
+0.75V_DDR_VTT +1.5V_CPUVDDQ
PR96 PR95
A A
*22_8 *220_8
3
SM_DRAMRST# signal (to system memory) to be driven high
2 MAINON_DIS_G 2
CKE signals (to system memory) to be driven low 46 MAINON_DIS_G
VREFDQ and VREFCA voltage (on system memory) needs to be maintained PQ17 PQ18
1.5-V power rail to system memory to be maintained. *DMN601K-7 *DMN601K-7
All other DDR3 memory interface signals are don’t care during S3 state for
1
memory self refresh.
SM_DRAMPWROK (to processor) is driven low during S3 as Processor VDDQ (1.5 V)
is turned off with this implementation.
appears no need stuff if PQ12 don't stuff
C300 *.1u_4
and why PQ86 is 220ohm
C295 *.1u_4
+1.5V_SUS +1.5V_CPUVDDQ
C293 *.1u_4
C292 *.1u_4
B B
+3V_S5
+3V_S5 +1.5V_SUS
R110
R192
5
*10K/F_4 U9 *1K_4
R198 2 R190
DDR3_DRAMRST# 14,15
*10K/F_4 4 PM_DRAM_PWRGD 4,8
3
3
1 Q11
Q17 *1.5K/F_4
+1.5V_CPUVDDQ *2N7002E *TC7SH08FU
3
2 R191 11 RST_GATE# 2 R109

*750/F_4 *Short_4
3
*BSS138
2 Q18
1
1
*PDTC143TT
PWRGD_1.5VCPU 42 4 CPU_DDR3_DRAMRST#
1
C C
+1.5V_SUS +1.5V_SUS
+1.5V_SUS
R120 R116
*EV@1K/F_4 *EV@1K/F_4
PQ12
1
2
5
6
R135 R134
+SMDDR_VREF_DQ0 14 +SMDDR_VREF_DQ1 15
*AO6402A *Short_1206 *Short_1206
3
38,42,46 MAIND 3
Q14 Q13
R121 R115
RST_GATE# 2 *EV@1K/F_4 RST_GATE# 2 *EV@1K/F_4
4
+1.5V_CPUVDDQ
*EV@A03402 *EV@A03402
6A/maximum
1
Modify 1017
7,14 VREF_DQ_DIMM0 7,15 VREF_DQ_DIMM1
D D
These isolation FETs are not required for ARD-only
Dr-Bios.com
designs. Only CFD and common motherboard designs need to implement this circuit to
meet the DDR3 VREF specification during S3.
PROJECT : ZYD
3B
S3 power saving
1 2 3 4 5 6 7 8
5 4 3 2 1
EC(KBC) L45 PBY160808T-250Y-N/3A/25ohm_6 +A3VPCU

+3V
I/O ADDRESS SETTING(KBC)
C567 C568
30mil
0.1u/10V_4_X7R 10u/6.3V_6
+3VPCU E775AGND
R48 2.2_6 D15 C526 C527
1 2 +3VPCU_EC 0.03A(30mils)
BAS316 4.7U/6.3V_6 0.1u/10V_4_X7R
C558 C551 C190 C191 C549 C533
115
102
19
46
76
88
4
4.7U/6.3V_6 0.1u/10V_4_X7R
*.1u/16V_4 0.1u/10V_4_X7R
*.1u/16V_4 0.1u/10V_4_X7R U19
AVCC
VDD
VCC1
VCC2
VCC3
VCC4
VCC5
E775AGND C580 10u/6.3V_8 ICMNT SHBM=0: Enable shared memory with host BIOS
D D
C576 0.01u/16V_4
9,28 LPC_LFRAME# 3 97 TEMP_MBAT 37
LFRAME GPIO90/AD0 WL_SW
9,28 LPC_LAD0 126 98 T29
LAD0 GPIO91/AD1 SHBM_R R420 10K_4
9,28 LPC_LAD1 127
LAD1 GPIO92/AD2
99 SML1ALERT# 10,11,34 SHBM
9,28 LPC_LAD2 128
LAD2 A/D GPIO93/AD3
100 ICMNT 37
9,28 LPC_LAD3 1 108
CLK_PCI_775 CLK_PCI_775 LAD3 GPIO05
10 CLK_PCI_775 2
LCLK GPIO04
96 1/13 Comfirm by vendor mail :
Disabled ('1') if using FWH device on LPC.
8 CLKRUN# 8
GPIO11/CLKRUN Power_Save Enabled ('0') if using SPI flash for both system BIOS and EC firmware
R385 GPIO94/DA0
101 T25 modify 1019
11 SIO_A20GATE 121 105
GPIO85/GA20 GPI95/DA1
*22_4
D/A GPI96/DA2
106
11 SIO_RCIN# 122 107
KBRST/GPIO86 GPI97
11 SIO_EXT_SCI#
D16 BAS316 29
ECSCI/GPIO54 LPC SM BUS PU(KBC) +3VPCU
64 ACIN 37
C534 EC_FPBACK# GPIO01/TB2
24 EC_FPBACK# 6 95 NBSWON# 32
GPIO24/LDRQ GPIO03 MBCLK R64 10K_4
*10p/50V_4 93 LID591# 24
NOCIR# GPIO06/IOX_DOUT MBDATA R65 10K_4
T10 124 94 SUSB# 8
GPIO10/LPCPD GPIO07 +3V_D
119 MXM_SMCLK12 23
PLTRST# GPIO23/SCL3 ACPRN
4,10,11,26,28,31 PLTRST# 7 109 T20
LREST GPIO30/CIRTX2 MXM_SMCLK12 R391 2.2K_4
120 MXM_SMDATA12 23
USBON# GPIO31/SDA3 MXM_SMDATA12 R389 2.2K_4
31,33 USBON# 123 65 BATLED0# 32
GPIO67/PWUREQ GPIO32/D_PWM
66 BATLED1# 32
IRQ_SERIRQ GPIO33/H_PWM +3V
9 IRQ_SERIRQ 125 15 VRON 39
SERIRQ GPIO36
16 SUSLED# 32
GPIO40/F_PWM AC_OFF ODD_EJ R419 *10K_4
11 SIO_EXT_SMI# 9 17 T74
GPIO65/SMI GPIO42/TCK 2ND_MBCLK R76 10K_4
GPIO GPIO43/TMS
20
3G_SW
AMP_MUTE# 30
2ND_MBDATA R75 10K_4
21 T9
MX0 GPIO44/TDI
34 MX0 54 22 CPUFAN# 34
MX1 KBSIN0 GPIO45/E_PWM GPIO46 ODD_POWER R383 *10K_4
34 MX1
MX2
55
KBSIN1 GPIO46/CIRRXM/TRST
23 T5 modify 1014
34 MX2 56 24 VIN_ON 37
MX3 KBSIN2 GPO47/SCL4
C 34 MX3 57 25 D/C# 37 C
MX4 KBSIN3 GPIO50/TDO
34 MX4 58 26 S5_ON 38,47
MX5 KBSIN4 GPIO51 HDMI_HPD_EC# +3VPCU
59 27
34
34
MX5
MX6
MX6
MX7
60
KBSIN5
KBSIN6
GPIO52/CIRTX2/RDY
GPIO53/SDA4
28 ODD_POWER T72
HDMI_HPD_EC# 25
ACER ID(KBC) 8/11 modify
34 MX7 61 91 DNBSWON# 8
KBSIN7 GPIO81 U16
110 T18
MY0 GPO82/TEST MXM_SMCLK12
34 MY0 53 112 RF_LED_EN# 32 6 1
MY1 KBSOUT0/JENK GPO84/TRIST GPIO41 MXM_SMDATA12 SCL A0
34 MY1
MY2
52
KBSOUT1/TCK GPIO41
80 T45 modify 1014 5
SDA A1
2
34 MY2 51 3
MY3 KBSOUT2/TMS A2
34 MY3
MY4
50
KBSOUT3/TDI ODDLED
modify 1230_B
34 MY4
MY5
49
KBSOUT4/JEN0 KB GPIO56/TA1
31 T75 7
WP VCC
8
34 MY5 48 117 SUSON 38,42 4
MY6 KBSOUT5/TDO GPIO20/TA2/IOX_DIN GND C180
34 MY6 47 63 FANSIG 34
MY7 KBSOUT6/RDY GPIO14/TB1 *24C02
34 MY7 43
MY8 KBSOUT7 *0.1u/10V_4
34 MY8
MY9
42
KBSOUT8 TIMER GPIO15/A_PWM
32
NUMLED#
CONTRAST 24
34 MY9 41 118 T11
MY10 KBSOUT9/SDP_VIS GPIO21/B_PWM
34 MY10 40 62 PWRLED# 32
MY11 KBSOUT10/P80_CLK GPIO13/C_PWM CAPSLED#
34 MY11 39 81 T19
MY12 KBSOUT11/P80_DAT GPIO66/G_PWM
34 MY12 38
MY13 KBSOUT12/GPIO64
37 modify 1019
34
34
MY13
MY14
MY14
MY15
36
KBSOUT13/GPIO63
KBSOUT14/GPIO62 GPIO77/SPI_DI
84 ODD_EJ
SHBM_R
T83 SPI FLASH(KBC) +3VPCU
34 MY15
MY16
35
KBSOUT15/GPIO61/XOR_OUT SPI GPO76/SPI_DO/SHBM
83
R647 *0_4 U24
34 MY16 34 82 RF_LED# 28,32
MY17 GPIO60/KBSOUT16 GPIO75/SPI_SCK SPI_SDI_uR R432 22_4 SPI_SDI_uR_R
34 MY17 33 2 8
GPIO57/KBSOUT17 SO VDD
75 RSMRST#_uR R415 *Short_4 R427 *100K_4 SPI_SDO_uR 5 7 C182
GPIO72/IRRX1/SIN2 ICH_RSMRST# 8 SI HOLD
MBCLK 70 73
37 MBCLK GPIO17/SCL1 GPIO70/IRRX2_IRSL0 SUSC# 8 7/24 modify
MBDATA 69 74 PWROK_EC_uR R74 *Short_4 SPI_SCK_uR 6 3 0.1u/10V_4
37 MBDATA GPIO22/SDA1 GPIO71/IRTX/SOUT2 PWROK_EC 8 SCK WP
10 2ND_MBCLK 2ND_MBCLK 67 SMB IR 113
GPIO73/SCL2 GPIO87/CIRRXM/SIN_CR RF_EN 28
10 2ND_MBDATA 2ND_MBDATA 68 14 CIRR_X2 T71 +3VPCU R441 10K_4 SPI_CS0#_uR 1 4
GPIO74/SDA2 GPIO34/CIRRXL HWPG CE VSS
GPIO16/CIRTX
114
P_SAVE_LED#
modify 1223_B W25Q16BVSSIG
111 T24
TPCLK GPO83/SOUT_CR/XORTR
34 TPCLK 72
TPDATA GPIO37/PSCLK1 At 11/24 add
34 TPDATA 71
GPIO35/PSDAT1
1/13 Comfirm by vendor mail :
B PCH_ACIN 10 86 SPI_SDI_uR If the Southbridge enables 'Long Wait Abort' by Winbond W25X16AVSSIG AKE38ZP0N01 B
8 PCH_ACIN GPIO26/PSCLK2 F_SDI
11 PS/2 87 SPI_SDO_uR_R R417 22_4 SPI_SDO_uR MXIC MX25L1605AM2C-15G AKE37FP0Z13
33 BT_POWERON# GPIO27PSDAT2 F_SDO default, the flash device should be 50MHz (or faster)
12 FIU 90 SPI_CS0#_uR EON EN25F16-100HIP AKE38ZA0Q00
21,40,41,42,43,46 MAINON GPIO25/PSCLK3 F_CS0
T73 MAINOND 13 92 SPI_SCK_uR_R R416 22_4 SPI_SCK_uR AMIC A25L016 AKE38ZN0800
GPIO12/PSDAT3 F_SCK
8 ICH_SUSCLK R413 *Short_4 E775_32KX1 77 30 ECDB_CLOCK T70
GPIO00/32KCLKIN GPIO55/CLKOUT/IOX_DIN +3V
VCC_POR
85 VCC_POR# R418 47K/F_4 +3VPCU HWPG(KBC)
VCORF
AGND
GND1
GND2
GND3
GND4
GND5
GND6
R412 *20M_6 E775_32KX2 79 104 VREF_uR R397 *Short_4 +A3VPCU R392

GPIO02 VREF
R428 NPCE781 10K_4

5
18
45
78
89
116
103
VCORF_uR 44
D4 BAS316 HWPG
Y2 *33K/F_4 SM BUS ARRANGEMENT TABLE 40 HWPG_VTT
1 4 D9 BAS316
46 HWPG_1.8V
SM Bus 1 Battery R396
L43 PBY160808T-250Y-N/3A/25ohm_6 D7 BAS316 *Short_4
41 HWPG_1.05V
C581 *32.768KHz C588 C545 SM Bus 2 PCH D8 BAS316
42 HWPG_1.5V
*15p/50V_4 *15p/50V_4
MPWROK 4
1u/6.3V_4 D6 BAS316
38 SYS_HWPG
E775AGND E775AGND SM Bus 3 VGA Thermal
D5 IV@BAS316
45 HWPG_GFX
SM Bus 4 11,21 dGPU_PWROK D3 EV@BAS316
modify 1014
POWER-ON Switch(KBC) INTERNAL KEYBOARD STRIP SET(KBC)

A A
+3VPCU
J4 *SHORT_ PAD
NBSWON# 2 1 MY0 R52 10K_4
Dr-Bios.com
2
D2
*VPORT_6

1
PROJECT : ZYD
3B
Modify 1028
WPCE781 & FLASH
5 4 3 2 1
5 4 3 2 1
VA PD7 PR151
PC128 PL5 SBR1045SP5-13 PQ37 0.01/F_7520 VIN_SRC PQ34
POWER_JACK 2200p/50V_6 UPB201212T-800Y-N/5A/80ohm_8 1 FDD6685 FDD6685
4 VDC 3 VA1 3 4 1 2 3 4 BAT-V
3 2
2
1
1
1
PC34 PC33 PC138 PR158 PC242 PC240 PC29 PC31 PC232 PC233 PR27
PJ2 PC131 PC132 PL6 0.1u/50V_6 0.1u/50V_6 PD8 0.1u/50V_6 220K/F_6 0.1u/50V_6 *10u/25V_1206 0.1u/50V_6 2200p/50V_6 10u/25V_1206 *10u/25V_120633K_6
0.1u/50V_6
0.1u/50V_6 UPB201212T-800Y-N/5A/80ohm_8 SMAJ20A VIN_SRC
modify 1223_B PC241
2
D PC244 PC245 PC246 1000p/50V_6 CSIP_1 D
10u/25V_1206 10u/25V_1206 1 6 PR28
22u/25V_1210 modify 1231_B 10K_6
PD1 PR144 2 5
SW1010CPT 220K/F_6
3 4
3
PQ30
IMD2AT108
36 D/C# 2
PQ4
DMN601K-7
1
VIN_SRC VIN_SRC
CSIP_1 PC17
1u/16V_6
PR29 PR26
10/F_6 10/F_6
PC234 PC235
PR142 PC120 10u/25V_1206 10u/25V_1206
PC21 4.7_6 PC116 10u/25V_1206
0.1u/50V_6 1u/16V_6
PC239
PC121 1000p/50V_6
CSIP CSIN 0.1u/50V_6
PD5 PC122 modify 1231_B
33
32
31
30
28
27
26
21
C C
1
+3VPCU PC16 +3VPCU *RB500V-40 2200p/50V_6
5
6
7
8
PU2 0.1u/50V_6
CSSP
VDDP
NC
GND
GND
GND
GND
CSSN
VCC
CM1293A-04SO
1 6 MBDATA PR24 PC13
CH1 CH4 2.7_6 0.1u/50V_8 88731_DH 4
2 5 +3VPCU PR23 MBDATA 11 25
VN VP 100K/F_6 VDDSMB BOOT PQ29
TEMP_MBAT 3 4 MBCLK AO4468 0.01_3720
CH2 CH3 MBCLK 9 SDA UGATE 24 PR138
PL1
6.8uH
3
2
1
10 23 88731_LX 1 2 BAT-V
36 ACIN SCL PHASE
5
6
7
8
13 ACOK LGATE 20
PR132
PC9 88731_DL 4 *4.7_6 PC113
PR10 0.1u/50V_6 19 0.01u/50V_6
PR11 49.9/F_6 PGND
*Short_6 DCIN 22 DCIN PU3 PR4 PQ25 PC108
PR33 ISL88731A 10/F_6 AO4710 *680p/50V_6 PC114
82.5K/F_6 18 CSOP CSOP_1 2200p/50V_6
3
2
1
CSOP PC111 PC110
2 ACIN
PC112 10u/25V_1206 10u/25V_1206
0.1u/50V_6 PC7
2 1 PR32 3 0.1u/50V_6
VREF
B
22K/F_6
CSON 17 CSON BAT-V
B
PC109 4 PR1 10/F_6 CSOP_1 VIN_SRC VIN

100p/50V_6 ICOMP PR15 PQ36
NC 16
BAT-V AOL1413
5 *Short_4 1
UPB201212T-800Y-N/5A/80ohm_8 NC 2010/02/02 2 5
PJ1 PL3 15 BAT-V 3
MBAT+ BAT-V VBF
10 1 6 VCOMP
29 PR17
2 GND 100_4 PC243
GND
4
3
ICM
PL2 PR39
NC
NC
4 UPB201212T-800Y-N/5A/80ohm_8 1U/25V_6 150K_6
5 PD6 7
14
12
6 RB500V-40
7 PR30
9 8 TEMP_MBAT 2.21K/F_6 2010/02/02 change footprint 12/31 change 150K and 1uF and 39K
TEMP_MBAT 36
Batt_Conn PR18
PC3 PC4 *0_6 PR38
47p/50V_6 47p/50V_6 ICMNT 36 39K_6
PC25
+3VPCU
0.01u/50V_6
3
PR22
Modify 1017 100K/F_6
2
PR13 PR14 PC26

100_4 100_4 *1u/16V_6 PC28 2
36 VIN_ON
PC27 *0.01u/50V_6
1
MBCLK 36 0.01u/50V_6 PQ3

DMN601K-7
A A
1
MBDATA 36 un-mount 11/16
PC19
3300p/50V_4

1
PR25 PC14
*100K/F_6 *0.01u/50V_6
PROJECT : ZYD
2

3B
CHARGER (ISL88731)
Dr-Bios.com
5 4 3 2 1
5 4 3 2 1
MAIND
MAIND 35,42,46
PR226 VL
4,47 SYS_SHDN#
*Short_4
VIN_SRC
1
VIN_SRC
D D
PR225 VIN_SRC
39.2K/F_4 VL
1
PC218 PC214
2
+ 0.1u/50V_6 *10u/25V_1206 PD4 PC191
2
3V5V_EN UDZS5.6BTE-17 4.7u/10V_8
*Short_4
2
PC91 PC237 PR223 PR102 PC238
1
PC217 *10u/25V_1206 1000p/50V_6 PR244 PR245 1000p/50V_6
2200p/50V_6 *Short_4 *Short_4 *Short_4
1
change P/N 11/16 modify 1231_B
PC207 modify 1231_B PR97 PC81 PR101 PC95 PC100 PC236
100K/F_4 PC190 1u/16V_6 *0_4 0.1u/50V_6 *10u/25V_1206
100u/25V_6.3*5.8
5V_EN
3V_EN
100u/25V_6.3X5.8 0.1u/50V_6 PC102
5
6
7
8
PC189 2200p/50V_4
OCP:10A
2
0.01u/16V_4 PC83 OCP : 8A
0.1u/50V_6
1
REF +3VPCU
L(ripple current) 4
3V_DH PQ69
=(19-5)*5/(2.2u*0.4M*19)
8
7
6
5
OCP: 10A PR99 *0_6 AO4468
~4.18A PR98
+5VPCU 200K/F_4
8
7
6
5
4
3
2
1
Iocp=10-(4.18/2)=7.91A 4 5V_DH
PL17
LDOREFIN
LDO
VIN
NC
ONLDO
VCC
TON
REF
3
2
1
Vth=7.91A*14.2mOhm=112.322mV 2.2uH_14A
R(Ilim)=(112.322mV*10)/5uA PQ68 +3VPCU
AO4468 PR113 3V_LX
~220K
5
6
7
8
1
+5VPCU 9 32 REFIN2 191K/F_6
PL15 BYP REFIN2 PR126
10 31 1 2
1
2
3
2.2uH_14A OUT1 ILIM2
C 11 FB1 OUT2 30 *2.2_6 C
+5VPCU 5V_LX 1 2 12 PU12 29 SKIP 4
PR114 220K/F_6 DDPWRGD_R 13 ILIM1 RT8206B SKIP# DDPWRGD_R +
28
2
PGOOD1 PGOOD2
1
8
7
6
5
5V_EN 14 27 3V_EN PR228
PR103 PR127 EN1 EN2 *Short_6
15 DH1 DH2 26
*0_4 *2.2_6 16 25 PC97 PC221
PC220 5V_DL LX1 LX2 *2200p/50V_6 330u/6.3V_6X5.7
4 37 PAD
+ 36
2
3
2
1
PAD
PGND
PVCC
PC94 PQ70
BST1
BST2
GND
PAD
PAD
PAD
DL1
DL2
0.1u/50V_6 PC204 PC205 AO4710 PD12
NC
330u/6.3V_6X5.7 PC98 0.1u/50V_6 0.1u/50V_6 SX34 1 2
PR110 *2200p/50V_6 PQ71 PR255 PR230 *0_4
35
34
33
17
18
19
20
21
22
23
24
*Short_4 AO4710 PR256 1/F_6
1
2
3
1/F_6 1 2
PD13 1 2 3V_DL *Short_4
SX34 PR238 PC222
0.1u/50V_6
PC96 PR263 VL PR224 SKIP PR112 *0_6 REF
*10u/25V_1206 *0_6 PR109
PC209 *0_6
PR46 EV@0_6 2 0.1u/50V_6 PC211 *Short_6 PR242
PD10 1u/16V_6
CHN217UPT 3
OCP:8A *Short_6
1 +3VPCU
+5VPCU 1 3 +5V_GPU
L(ripple current)
PQ64 0.75A PR262
PR236 *EV@AO3413 PC212 2 =(19-3.3)*3.3/(2.2u*0.5M*19)
2
0.1u/50V_6 PD11 ~2.48A

+5V *EV@10K_4 CHN217UPT 3 *Short_6 PR234
B B
PC210 Iocp=8-(2.48/2)=6.67A 100K/F_4
1 0.1u/50V_6
Vth=6.67A*15mOhm=94.714mV
PR264
PR237 R(Ilim)=(94.714mV*10)/5uA PR235
3
+15V_ALWP DDPWRGD_R
*EV@10K_4
+15V ~191K SYS_HWPG 36
*Short_4
dGPU_5V_EN 2 22_8 PC213
0.1u/50V_6
3
PQ67
*EV@DMN601K-7 +5VPCU +3VPCU
1
11 dGPU_PWR_EN# 2
PQ62
*EV@DMN601K-7
5
6
7
8
5
6
7
8
1
VIN_SRC +1.5V_SUS +SMDDR_VREF +15V

MAIND 4 MAIND 4
VIN_SRC +3V_S5 +5V_S5 +15V +5VPCU +3VPCU
+3VPCU
PR72 PR84 PR85 PR75 PQ23 PQ21
1M_6 22_8 22_8 *3G@1M_6 AO4496 AO4496
PR257 PR229 PR240 PR221 +3V
3
1
2
5
6
1M_6 22_8 22_8 1M_6
3
2
1
3
2
1
5
6
7
8
SUSD 3
S5D 2 L36 2.17A 3.11A
3
A S5D 4 3 EV@0_8 A
3
+5V +3V
4
3
PQ22 2 2A 7/28 BOM option for 3G or WL

36,42 SUSON
3
Dr-Bios.com
AO3404 2 PC57
+3VSUS
1
2 2 2 PQ20
36,47 S5_ON
2 PR79 *2.2n/50V_4 *3G@AO6402A
+3V_S5
1
2 2 PC188 PQ16 1M_6

3
2
1
PR252 PQ24 0.23A DTC144EU PQ13 PQ14 PQ15

1
PQ61 1M_6 DMN601K-7 DMN601K-7

1
DTC144EU AO4496 *3G@DMN601K-7

PROJECT : ZYD
1
PQ65 PQ66 PQ63 2.2n/50V_4

1
DMN601K-7 DMN601K-7 DMN601K-7 Size Document Number Rev

+5V_S5 7/9 add +3VSUS for 3G option 3B
SYSTEM 5V/3V (RT8206)
2.85A Date: Tuesday, April 06, 2010 Sheet 38 of 50
5 4 3 2 1
5 4 3 2 1
[PWM]
VR_PWRGD_CK505# 3 VIN
VIN
DELAY_VR_PWRGOOD 4,8
1
1
+
PC155 PC53 PC54 PC156 PC154
2200p/50V_6 0.1u/50V_6 *10u/25V_1206 *10u/25V_1206 15u/25V_6X4.5
2
PQ49
5
AOL1448
change P/N 11/16
62882_DH1 4
D D
1
2
3
+VCC_CORE
VIN +3V
PL10 0.36uH
62882_LX1 1 2
PR74 PQ51 PQ53
4
5
5
*Short_6 AOL1718 AOL1718 PR71
+ PC56
PR216 PR214 *2.2/F_6
+5V_S5 1.91K/F_4 1.91K/F_4 4 4 330u/2V_7343
PC63
1
2
3
1
2
3
PR73 0.22u/25V_6 5/12 Change pr144 from 10K to 1.91K PC55
10_6 *1000p/50V_6 PR189 PR190
PR92
*Short_4 *Short_4
16
17
40
1
PU10
*Short_8
VDD
VIN
CLK_EN#
PGOOD
PC62
1u/6.3V_4
41
+1.1V_VTT PAD
UGATE1 20
7/16 modify PR66 10K/F_4
BOOT1 19 1 2
PR212
*499/F_4 PSI# PR213 10K/F_4 2 PR203 VSUM+ PR195 3.65K/F_4
6 H_PSI# PSI# 2.2_6 PC165
PR91 147K/F_6 3 0.22u/25V_6
RBIAS VSUM- PR196 1/F_4
21
PHASE1
4 H_PROCHOT# 4 VR_TT#
23 62882_DL1A
PR191 PR90 LGATE1a PR67 10K/F_4
C Close to Phase 1 Inductor *470K_4 NTC *4.02K/F_4 C
5 VIN
PC70 NTC VIN
*0.01u/16V_4 24 62882_DL1B
LGATE1b
1
1 2
1
22 +
VSSP1 PC183 PC76 PC75 PC182 PC184
11 62882_ISEN1 2200p/50V_6 0.1u/50V_6 *10u/25V_1206 *10u/25V_1206 100u/25V_6.3*5.8
2
H_VID0 ISEN1
6 H_VID0 31
VID0
1
H_VID1 32
6 H_VID1 VID1 PC166 PQ58
5
H_VID2 33 0.22u/10V_4 AOL1448
6 H_VID2
2
VID2 VSUM-
H_VID3 34
6 H_VID3 VID3 62882_DH2 4
PR209 *Short_4
H_VID4 35 25
6 H_VID4 VID4 VCCP +5V_S5
ISL62882
1
2
3
H_VID5 36 PC170 1u/6.3V_4
6 H_VID5 VID5 +VCC_CORE
1 2
H_VID6 37
6 H_VID6 VID6 PC69 1u/6.3V_4 PL11 0.36uH
VR_ON 38 1 2 62882_LX2 1 2
36 VRON VR_ON PQ57 PQ55
5
DPRSLPVR 39 29 AOL1718 AOL1718
6 H_DPRSLPVR
4
DPRSLPVR UGATE2
2
PR217 30 1 2 PR93
PR218 499/F_4 BOOT2 62882_DL2 4 + PC71
4
100K/F_4 PR215 *2.2/F_6
2.2_6 PC173 330u/2V_7343
1
1
2
3
1
2
3
8 0.22u/25V_6 PR187 PR188
FB *Short_4
28 *Short_4
PHASE2
PR87 PC168 26
*10K/F_4 22p/50V_4 LGATE2 PC73
9 27 *1000p/50V_6
FB2 VSSP2
B B
PR82 10 62882_ISEN2
412K/F_4 PC64 ISEN2
2 1
1
150p/50V_4 7 PC167
COMP 0.22u/10V_4
2
VSUM-
PC169
10p/50V_4 PR88 6
8.06K/F_4 VW
18 I_MON 6
IMON
PR64 10K/F_4
1
PR202 PC160
PC67 9.76K/F_4 0.033u/16V_4
1000p/50V_4 VSUM+ PR193 3.65K/F_4
2
ISUM+
ISUM-
VSEN
VSSSENSE
RTN
PR80 VSUM- PR194 1/F_4

12
13
14
15
2.8K/F_4 PR65 10K/F_4

2010/02/02 change footprint
PC158 PC159
PR78 PC58 0.22u/10V_6 0.068u/25V_6
562/F_4 390p/50V_4 VSUM+
1
+VCC_CORE 1 2 PR200 PR68

PR76 *27.4_4 82.5/F_4 2.61K/F_4
2
PR69 PC60
*Short_4 PC162 PR198
330p/50V_4 11K/F_4
6 VCCSENSE
Parallel PC164 PC163 PR197
2700p/50V_4
2
A 330p/50V_4 0.01u/16V_4 10K _6_NTC Panasonic A

6 VSSSENSE
PC61 PR192
*Short_4 *Short_4
ERT-J1VR103J
1
PR70 1 2 1000p/50V_4
Dr-Bios.com
PR77 *27.4_4
VSUM-
5/12 Change pr34 rom 1K to 1.24K
PR199
1.24K/F_4 PC157
0.1u/10V_4 Close to Phase 1 Inductor
PC161 PR201 Load Line setting to 2mV/A
*1000p/50V_4 *100/F_4
PROJECT : ZYD
3B
CPU Core ( ISL62882)
5 4 3 2 1
5 4 3 2 1
[PWM]
VIN
+5V_S5
PR52 PD3
10_6 RB500V-40
5
D PR59 D
2.2/F_6
1
PR168
1M/F_6 PC46 4 1.05V/15A
PR177 4.7u/6.3V_6 OCP: 18A
2
*Short_6 PC51 PC49 PC44
1
2
3
*Short_6 PU8 PQ48 2200p/50V_4 0.1u/50V_6 *10u/25V_1206
UP6111AQDD AOL1448 PC43
PR170
PC150 *10u/25V_1206
15 13 0.1u/50V_6
21,36,41,42,43,46 MAINON EN/DEM BOOT
+3V 16 12 UGATE-VTT
PC41 TON UGATE PL8
*0.1u/50V_6 1 11 PHASE-VTT
VOUT PHASE 1.5uH +1.1V_VTT
2 10 PR178 3.92K/F_6
VDD OC
5
PR53
*10K/F_6 3 9 PC151
FB VDDP + +
4 8 1u/16V_6 LGATE-VTT 4 PR175
36 HWPG_VTT PGOOD LGATE *4.7_6
6 7 PQ44 PC42
1
2
3
C GND PGND AOL1718 330u/2V_7343 C
5 NC TPAD 17
PC145
14 *680p/50V_6
NC
1
PC48 PC142
330u/2V_7343 0.1u/50V_6
PC38 PC39 PC143
2
1u/16V_6 *1000p/50V_6 10u/10V_8
*Short_6
VOUT=(1+R1/R2)*0.75
PR55
PR165 PC141
R1 4.02K/F_6 *33p/50V_6
VTT_FB
B
Modify 1108 B
PR166
R2 10K/F_6
Aurbundale (1.05V) R1 = 4.02K (CS24023F928)

AO1718 Rdson=3~4.3mOhm
TON=3.85p*RTON*Vout/(Vin-0.5) Clarksfield(1.1V) R1 = 4.75K (CS24753F919)
L(ripple current)
Frequency=Vout/(Vin*TON) =(19-1.05)*1.05/(1u*272k*19)
~3.64A
TON=3.85p*1M*1/(Vin-0.5) 4.3m*18=RILIM*20uA
RILIM=3.87K --- 3.92K
Frequency=1/(0.0036767)=272K
A A

PROJECT : ZYD
3B
+VTT (UP6111A)
5 4 3 2 1
Dr-Bios.com
5 4 3 2 1
VIN
VIN
+5V_S5
Amos 03/25
2
PR129 PD14
D D
10/F_6 RB500V-40
5
6
7
8
PR275
1
2.2/F_6
1
PR269 PC231 4
1M_6 4.7u/6.3V_6 PQ72
2
PR270 AO4468 PC103 PC225 PC226 PC247
*Short_6 PU13 *Short_6 2200p/50V_4 0.1u/50V_6 4.7u/25V_8 4.7u/25V_8
UP6111AQDD
PR128
PC227
15 13 0.1u/50V_6
OCP: 10A
,36,40,42,43,46 MAINON
3
2
1
EN/DEM BOOT PL16
+3V 16 12 UGATE-1.05V 2.2uH_8A
1.05V/8A
PC223 TON UGATE
*0.1u/50V_6 1 11 PHASE-1.05V
VOUT PHASE +1.05V
PR274 2 10 PR130 7.15K/F_6 8/24 modify
VDD OC
5
6
7
8
*10K/F_6
3 9 PC230
FB VDDP 1u/16V_6
C C
4 8 LGATE-1.05V 4 PR131
36 HWPG_1.05V PGOOD LGATE +
*4.7_6
6 7
Rds*OCP=RILIM*20uA
GND PGND
5 NC TPAD 17
PQ73 PC107
14 AO4710 *680p/50V_6
3
2
1
NC
1
PC105
*10u/10V_8
PC106 PC224 PC104
2
1u/16V_6 *1000p/50V_6 0.1u/50V_6

PC228
560u/2.5V_6X5.7
B B
PR271 PC229
R1 4.02K/F_6 *33p/50V_6
1.05V_FB
VOUT=(1+R1/R2)*0.75
*Short_6
PR272
10K/F_6
R2 PR273
TON=3.85p*RTON*Vout/(Vin-0.5)
AO4710 Rdson=11.7~14.2mOhm
Frequency=Vout/(Vin*TON) L(ripple current)
A =(19-1.05)*1.05/(1u*272k*19) A
TON=3.85p*1M*1/(Vin-0.5) ~3.646A Quanta Computer Inc.
Frequency=1/(0.0036767)=272K 14.2m*10=RILIM*20uA PROJECT : ZYD
RILIM=7.1K--- 7.15K 3B
VCCP 1.05V(UP6111A)
5 4 3 2 1
Dr-Bios.com
5 4 3 2 1
[PWM]
36
D D
PC178
10u/10V_8
*Short_6
PC177
PR219
0.1u/50V_6
+0.75V_DDR_VTT
VIN
VIN
8207_DH
PC172 PC174
2A 10u/10V_8 10u/10V_8 8207_LX
PC179
5
8207_DL 100u/25V_6.3*5.8
PC176 PC72
25
24
23
22
21
20
19
1
2
3
PQ54 2200p/50V_6 *10u/25V_1206
AOL1448 PL12 12A
LL
DRVL
VTT
VBST
GND
VLDOIN
DRVH
2.2uH_14A
+1.5V_SUS +1.5V_SUS
1 18
VTTGND PGND
2 VTTSNS CS_GND 17
+ +
5
3 RT8207A 16
GND PU11 CS +5V_S5 PR94
PR89 4 *4.7_6
C +1.5V_SUS 4 5.62K/F_6 C
MODE V5IN 15
PR211 PQ56
1
2
3
5.1/F_6 AOL1718
+SMDDR_VREF 5 VTTREF V5FILT 14
1
PC66 PC74
0.003A
VDDQSNS
VDDQSET
PC68 +5V_S5 6 13 1u/6.3V_4 PC171 *680p/50V_6 PC175 PC181 PC180
2
0.033u/50V_6 COMP PGOOD 1u/6.3V_4 560u/2.5V_6x5.7 *560u/2.5V_6x5.7 10u/10V_8
2
NC
NC
PR210 100K/F_6
S3
S5
+3VPCU
change P/N 11/16
FOR DDR III
7
10
11
12
HWPG_1.5V 36
AO1412 Rdson=3.8~4.6mOhm
PR207 (For RT8207A 400KHZ )
620K/F_4
VIN OCP=12.21+0.5A
PR205 *Short_6
S5_1.8V
L(ripple current)
SUSON 36,38
PR206
S3_1.8V
*Short_6 =(19-1.5)*1.5/(2.2u*400k*19)
MAINON 21,36,40,41,43,46
PR81 *0/F_6
PWRGD_1.5VCPU 35 Add it for S3 leakage circuit ~1.57A
PR204
PR83 *Short_6 *0/F_6 +5V_S5 7/23 modify
4.6m*12=RILIM*10uA
RILIM=5.62K
PC59 PR208
(10u*PR35)/Rdson+Delta_I/2=Iocp
*33p/50V_6 10.2K/F_4
Vout = (PR150/PR149) X 0.75 + 0.75
B B
PR86 +1.5V_SUS
10K/F_4 PC65
*0.033u/50V_6
change P/N 11/16
3
MAIND 2
35,38,46 MAIND
+1.5V_SUS
PQ52
AO3404
1
change PQ50 to AO4492
VIN +15V
PR62
+1.5V
5
6
7
8
EV@1M/F_6 PR60
EV@1M/F_6
4 2.03A
3
3.94A
3
PQ50
A PR61 EV@AO4492 A
2 EV@1M/F_6 2
46 PG_1.5V_EN PC45
Dr-Bios.com
3
2
1
PQ10 *EV@2.2n/50V_4
1
PQ11 EV@DMN601K-7
1
PR63 EV@DTC144EUA
1
*EV@100K_4 add PC248 PC249

+1.5V_GPU
2
PC248 PC249
330u_3528 330u_3528 PROJECT : ZYD
PC249 close C507 Size Document Number Rev
3B
DDR III 1.5V(TPS51116)
5 4 3 2 1
1 2 3 4 5
+5V_GPU VIN
VIN
2
PR139 PC126 PC24 PC125 29A
+3V *EV@0_4 EV@4.7u/25V_8
*EV@4.7u/25V_8 OCP=35A
EV@4.7u/25V_8
1
PR21 PC22
5
EV@200K/F_4 EV@0.1u/50V_6 +VGPU_CORE
PC6 EV@1u/10V_6 2 7 8792TON
VDD TON PQ35
A A
PR5 5 8792DH 4 EV@AOL1448
EV@100K_4 PC2 EV@1u/10V_6 8792VCC DH PC23
13 VCC EV@2200p/50V_4
1
2
3
6 8792BST
PG_GPUIO_EN14 BST PR20 PC11
44 PG_GPUIO_EN PGOOD EV@1_6 EV@0.22u/25V_6 PL7
PR135 *EV@0_4 8792EN 1 PU1 EV@0.36uH
21,36,40,41,42,46 MAINON EN 8792LX +VGPU_CORE
4
*EV@0_4 EV@MAX8792ETD+TLX
PR222 PC1 8792SKIP# 12
11,21 dGPU_VRON SKIP# 8792DL
DL 3
5
+3V_D EV@0.1u/10V_4 PR12 *EV@0_4
8792REFIN 10 PR31
PR134 REFIN EV@1_8
FB 8
EV@0_4 PR133 4 4 + + +
REF-2V
EV@100K_4 8792REF 11 9 8792ILIM PC35
1
2
3
1
2
3
REF ILIM *EV@470u/2V
*Short_6 PC18
EP
EV@1000p/50V_4
PR2
15
PR140 PR141
EV@44.2K/F_4 EV@51K/F_4
PC15
*EV@4700P/25V_4 PQ33 PQ32 PC136 PC137 PC32
EV@AOL1718 EV@AOL1718 EV@0.1u/50V_6 EV@470u/2V EV@470u/2V
Place near GND pin15
PR137 PC10
3
B EV@470K/F_4 EV@1000P/50V_4 B
PR19
VID1 EV@100K_4
2 PQ27
17 VCORE1.2ID0 EV@2N7002E Frequency(PR220=200K) 300K
PR136
EV@100K_4
1
PR143
EV@49.9K/F_4
2*PR128/(PR128+PR14)/20=(IL-deltaI/2)*Rdson
PC115
EV@0.01u/16V_4
PR6
3
EV@220K/F_4
VID2
2 PQ2
17 VCORE1.2ID1 EV@2N7002E
PR7
EV@100K_4
1
C C
PC5
EV@0.01u/16V_4
VIN_SRC +VGPU_CORE
PR9 PR3
Madison VID Table EV@1M_6 EV@22_8
PR140 = 44.2K
VID1 VID2 PR143 = 49.9K
3
VCORE1.2ID0 VCORE1.2ID1 +VCC_GFX_CORE PR137 = 470K
PR6= 220K
3
LOW (0) LOW (0) 1.05V
2
HIGH (1) LOW (0) 1.0V 8792EN 2
PR8 PQ1
LOW (0) HIGH (1) 0.95V PQ26 EV@1M_6 EV@ME2N7002D
1
HIGH (1) HIGH (1) 0.90V EV@DTC144EU
PARK XT VID Table

PR140= 39.2K CS33922FB15
VID1 VID2 PR143 = 49.9K
D VCORE1.2ID0 VCORE1.2ID1 +VCC_GFX_CORE PR137 = 332K CS43322FB15 D
PR6 = 130K CS41302FB00
LOW (0) LOW (0) 1.12V
Dr-Bios.com
HIGH (1) LOW (0) 1.05V
LOW (0) HIGH (1) 0.95V
HIGH (1) HIGH (1) 0.90V Quanta Computer Inc.
PROJECT : ZYD
3B
GPU CORE(MAX8792)
1 2 3 4 5
5 4 3 2 1
*Short_6
[PWM] PC124
PR146
+5V_GPU
EV@10u/10V_8
62872_PVCC2
2
VIN
PR145
EV@2.2_6
D D
VIN
1
62872_DL
20
1
5
6
7
8
PC20 PC118
PC123 EV@0.1u/50V_6 100u/25V_6.3*5.8
LGATE
PVCC2
EV@10u/10V_8
PR34 4
EV@0_6 2 19
PGND VCC
82872_AGND PC117
82872_AGND 3 GND BOOT 18 1 2 EV@2.2n/50V_4 4.5A
PC12
PR148 *Short_4 PR147 PC127 EV@0.1u/50V_6 +VGPU_IO
3
2
1
4 17 EV@2.2_6 EV@0.22u/25V_6 62872_DH PQ31
43 PG_GPUIO_EN EN UGATE EV@AO4468
DCR(max)=20mohm
C IO_VID1_R 5 16 62872_LX +VGPU_IO C
VID1 PHASE
PR155 *EV@0_4 PU7 PL4
IO_VID0_R 6 EV@ISL62872 15 EV@2.2uH_8A
17 IO_VID0 VID0 NC
5
6
7
8
+
62872_SREF 7 14 62872_OCSET
SREF OCSET PR16 PR40
4 *EV@4.7_6 PR35
PR43 8 13 *Short_4 *Short_4
SET0 VO
1
EV@16.5K/F_6
9 12 62872_FB
2
SET1 FB
PGOOD
PC30 PC8
EV@47n/16V_6 *EV@680p/50V_6
SET2
3
2
1
PQ28 PC130 PC135 PC134
EV@AO4710 EV@560u/2.5V_6X5.7 EV@10u/10V_8 EV@0.1u/50V_6
10
11
82872_AGND PR42
EV@15K/F_6 PC133
B B
EV@2700p/50V_4
2 1 PR36
EV@17.4K/F_6
PR45 2 1 VDDCI VID
PR154 PG_1V_EN EV@100/F_6
EV@14K/F_6 PC129
EV@0.1u/25V_4 VID1 VID0 VDDC
2 1 2 1 1 1 0.92V
+3VPCU
PR41 PR156 PR44 PR153 1 0 0.97V
EV@287K/F_6 EV@28K/F_6 EV@24K/F_6 EV@17.4K/F_6
82872_AGND 2 1 0 1 1.07V
PR152 PR37 0 0 1.12V

*EV@10K/F_4 *EV@10K/F_4
+3V
IO_VID0_R IO_VID1_R
A A
PR150
EV@10K/F_4
PR149 PR157
EV@10K/F_6
EV@10K/F_4
PROJECT : ZYD
PG_1V_EN Size Document Number Rev
46 PG_1V_EN
3B
+VGPU_IO(ISL62872)
5 4 3 2 1
Dr-Bios.com
A B C D E F G H
Int_VGA [PWM]
6 GFX_VID0
6 GFX_VID1 +1.1V_VTT +1.1V_VTT

6 GFX_VID2
6 GFX_VID3
1 PR119 PR118 PR233 PR117 PR111 PR105 PR100 1

6 GFX_VID4
*IV@0_6 *IV@0_6 *IV@0_6 *IV@0_6 *IV@0_6 *IV@0_6 *IV@0_6
6 GFX_VID5
6 GFX_VID6
GFX_VID6 GFX_VID5 GFX_VID4 GFX_VID3 GFX_VID2 GFX_VID1 GFX_VID0
PC202
*IV@0.01u/25V_4
62881_GND 2 1
PR243 *Short_4
6 GFX_ON
PR249 *Short_4
6 GFX_DPRSLPVR
PR239 short VIN VIN
62881_GND
62881DPRSLPVR
62881_GND
62881VR_ON
1
GFX_VID6
GFX_VID5
GFX_VID4
GFX_VID3
GFX_VID2
PC77 PC78 PC186
*IV@10u/25V_1206 IV@100u/25V_6.3*5.8 PC187
2
+3V IV@0.1u/50V_6 IV@2.2n/50V_4
29
28
27
26
25
24
23
22
5
PR258
VID6
VID5
VID4
VID3
VID2
GND
DPRSLPVR
VR_ON
GFX_VID1
GFX_VID0
*Short_4 IV@1.91K/F_4
PR120 1
CLK_EN#
2 4 2
62881PGOOD 2 21 +5V_S5
36 HWPG_GFX PGOOD VID1
1
2
3
PQ60
PR247 IV@47K/F_4 62881RBIAS 3 20 IV@AOL1448
62881_GND RBIAS VID0
PR248
*IV@150K/F_4 PC79
PR259 IV@8.06K/F_4 62881VW 4 19 1 2
62881_GND VW VCCP
PU5
PC88 IV@4.7u/6.3V_6
22A
IV@ISL62881HRZ-T 18 62881LGATE
IV@1000p/50V_4 62881COMP 5 LGATE PL13 +VGFX_AXG
COMP IV@0.56uH
PR261 PC206 17
IV@820K/F_4 IV@22p/50V_4 VSSP
62881FB 6
FB
16 62881PHASE
PC208 PHASE
DCR=1.6~1.8mOhm
IV@100p/50V_4 PR121
Load Line=7mV/A
5
IV@8.87K/F_4 15 62881UGATE
62881VSEN UGATE PR107 + + 1.6m*0.6168=0.986m
7
VSEN PR220 IV@3.65K/F_4 0.986m/.49K=396p
ISUM+
BOOT
ISUM-
IMON *IV@4.7_6
4 4
VDD
RTN
392p*2*8.87K=7.03m
VIN
PR260 PC89
PR116 PR227 OCP
1
2
3
1
2
3
PQ59 PQ19 IV@2.61K/F_4 IV@10K _6_NTC
20u/2*2.49K=24.9m
8
10
11
12
13
14
IV@17.8K/F_4 IV@150p/25V_4 PC86 PR104 PC80 IV@AOL1718 IV@AOL1718
PC90 IV@330p/50V_4 62881BOOT 1 2 PC185 24.9m/0.6168=40.3m
62881VDD
62881ISUM+
62881ISUM-
62881VIN
IV@330p/50V_4 IV@1_6 *IV@680p/50V_6 PC201 PC192 PC193 40.3m/1.6m=25.2A

62881RTN IV@0.22u/25V_6 PR108 IV@560u/2.5V_6X5.7 IV@560u/2.5V_6X5.7 IV@10u/6.3V_8
GFX_IMON
GFX_IMON 6
PC87 IV@11K/F_4
2
62881_GND PR106
IV@1000p/50V_4 *IV@19.1K/F_4 PC82
*IV@0.022u/25V_4
1
PC196 PC85
3 VSS_AXG_SENSE IV@0.15u/10V_4 IV@0.1u/10V_4 3
62881_GND
PR231 *Short_4 VIN
PC199 62881_GND
PC195 *IV@0.1u/10V_4
IV@0.22u/25V_6
62881_GND
+5V_S5
PR232 PC197
*IV@180p/50V_4
PR246
PC198 IV@10_6 IV@2.49K/F_4
IV@1u/6.3V_4
PR241
*IV@100/F_4
62881_GND
PR115 PC84
2 1
IV@82.5/F_4 IV@0.01u/25V_4
Parallel
*Short_4 PR251 IV@10/F_4
PR250
VSS_AXG_SENSE 6
4 4
*Short_4 PR254 IV@10/F_4

PR253
Dr-Bios.com
VCC_AXG_SENSE 6

PROJECT : ZYD
3B
1.Level 1 Environment-related Substances Should NEVER be Used. +VGFX_AXG (ISL62881)
2.Purchase ink, paint, wire rods, and Molding resins only from the business Partners that Sony approves as Green Partners. Date: Tuesday, April 06, 2010 Sheet 45 of 50
A B C D E F G H
5 4 3 2 1
+3VPCU 1.76A
+1.8V
PC101
PC99 0.1u/25V_4
10u/10V_8
PU6 HPA00835RTER
16 10 DCR(max)=10mohm
VIN PH
1 11 PL14
*Short_4 VIN PH 1.0uH/11A_7X7X3
D D
PR267 2 VIN PH 12
PR265 *Short_6
MAINON 15 13
EN BOOT
54418-1.8_VFB 6 14 PC215 0.1u/50V_6 PR125
VSNS PWRGD 51.1/F_4
PC219 7 3
COMP GND
1000p/50V_4
8
RT/CLK GND
4 R1
PAD
PAD
PAD
PAD
PAD
PAD
HWPG_1.8V 36
9 5 PR268
PR122 PR266 SS AGND PR123
*100K/F_4
15K/F_4 182K/F_4 +3VSUS 100K/F_4 PC203 PC200 PC194
22
21
20
19
18
17
0.1u/25V_4 10u/10V_8 10u/10V_8
PC93
*100P/50V_4 PC216
0.01u/25V_4 54418-1.8_VFB
PC92
1200p/50V_4 V0=0.8*(R1+R2)/R2
R2 PR124
78.7K/F_4
+3VPCU
C C
2A
+1V
PC153
PC152 EV@0.1u/25V_4
EV@10u/10V_8
PU9 EV@HPA00835RTER
16 DCR(max)=10mohm
VIN PH 10
1 11 PL9
*Short_4 VIN PH EV@1.0uH/11A_7X7X3
PR174 2 VIN PH 12
15 13 PR172 EV@0_6
44 PG_1V_EN EN BOOT
54418-1_VFB 6 14 PC149
VSNS PWRGD EV@0.1u/50V_6 PR186
PC147 7 3 EV@51.1/F_4
COMP GND
EV@1000p/50V_4
8
RT/CLK GND
4 R1
PAD
PAD
PAD
PAD
PAD
PAD
PG_1.5V_EN 42
9 5 PR173
PR184 PR183 SS AGND PR185
EV@100K/F_4
EV@8.06K/F_4 EV@182K/F_4 +3VSUS EV@20K/F_4
22
21
20
19
18
17
PC148 PC146 PC144

PC50 EV@0.1u/25V_4
EV@10u/10V_8
EV@10u/10V_8
B PC47 B
*EV@100P/50V_4
EV@0.01u/25V_4 54418-1_VFB
PC52
EV@1200p/50V_4 PR182 +1.8V
EV@78.7K/F_4R2
V0=0.8*(R1+R2)/R2 VIN_SRC +15V
PR58 PR54
EV@1M/F_6 EV@1M/F_6
1
2
5
6
2010/02/02 3 PQ7
EV@AO6402A
3
*Short_4
4
PR56
+1.5V_GPU 2 2 +1.8V_GPU
PR57 PQ9 PC37
+3V +5V +1.1V_VTT +1.5V +1.05V EV@1M/F_6 EV@DMN601K-7 *EV@2.2n/50V_4
VIN_SRC +15V PQ8 1.41A
1
EV@DTC143TT
1
PC40
Add it for S3 leakage circuit PR159 PR164 PR169 PR181 PR180 EV@1u/10V_4
PR176 22_8 22_8 22_8 22_8 22_8
35 MAINON_DIS_G 1M/F_6 PR167
1M/F_6
MAIND
A MAIND 35,38,42 A
3
3
Dr-Bios.com
PR171
2 1M/F_6 2
21,36,40,41,42,43 MAINON PC140
2 2 2 2 2
PQ40 *2.2n/50V_4 7/7 modify
1
PQ47 PQ45 DMN601K-7

1
PR179 DTC144EUA PQ38 PQ43 PQ46 DMN601K-7

1
*100K_4 PQ42
1
DMN601K-7
DMN601K-7
DMN601K-7 DMN601K-7
PROJECT : ZYD
2

3B
Discharge/1.8V)
5 4 3 2 1
1 2 3 4 5
VIN_SRC
A A
PD2
SW1010CPT
PR49
1M_6
1
PQ5
AO3409
TH_ON 2
3
Thermal protection
3
S5_ON 2
36,38 S5_ON
PQ41
1
B
VL VL DTC144EUA B
SYS_SHDN# 4,38
PR163 PR161
? 1K_4 200K/F_4 PR48
200K_6
PC36
0.1u/50V_6
3
8
PR47
based on thermister SPEC 10K _6_NTC 2.469V 3 +
1K--->82~83 NTC
1 2
2 - PQ39
PU4A DMN601K-7
4
LM393 PC139
1
0.1u/50V_6
PR160
C 200K/F_4 C
+3VPCU
3
VL
S5_ON 2
PR162
PQ6 100K/F_6
DMN601K-7
PR51
1
10K/F_6
PD9
5
+ NC_TEMP
7 T84
4.95V 6
-
PU4B RB500V-40
LM393
For EC control thermal protection (output 3.3V)
PR50
1M/F_6
D D

PROJECT : ZYD
3B
Thermal Protection
Dr-Bios.com
1 2 3 4 5
5 4 3 2 1
ISL62882
VCC_CORE CPU
PU10 U26
AO4496 RTC U28(PCH) USBX3 PU10(VDD) PU8(VDD) PU13(VDD) PU11(VDD) PU5(VDD)

PQ24 +5V_S5
D D
AO4496 U28(PCH) CN13(CRT) CN12(ODD) CN16(HDD) U29(ADO) CN4(TP) CN9(FAN)
+5VPCU +5V
PQ23
AO3413/0ohm PU1 PU7

RT8206B
PU12 PQ64/PR46 +5V_GPU
RTC MR1 LED2 U19(EC) U24(BIOS)

+3VPCU
AC System
Charger VIN_SRC AO1413 VIN AO3404
ISL88731A U28(PCH) U7(LAN) LED1 CN6(BT) U29(ADO)
PQ36 +3VPCU PQ22 +3V_S5
DC
PU3
AO4496
U27(CLK) U30(ME) U28(PCH) DIMM(SPD) U6(CRT) CN3(LDS) CN8(MPC) CN10(MNC) U29(ADO) CN5(MMC) CN1(LED)
PQ21 +3V
C AO3413 C
+3V_D
Q9
HPA00835 U26(CPU) U28(PCH)

PU6 +1.8V
AO6402 +1.8V_GPU
PQ7
HPA00835
+1V U18(VGA)
PU9
UP6111A
+1.05V U27(CLK) U28(PCH)
PU13
B B
UP6111A
+1.1V_VTT U26(CPU) U28(PCH)
PU8
JDIM1 JDIM2
+0.75V_DDR_VTT
JDIM1 JDIM2
RT8207A +SMDDR_VREF
PU11
AO4496
+1.5V_GPU
PQ50
+1.5V_SUS AO3404 U27(CLK) CN8(MPC) CN10(MNC)

PQ52 +1.5V
JDIM1 JDIM2 U26(CPU)
ISL62881 U26(CPU)
A PU8 +VGFX_AXG A
MAX8792 +VGPU_CORE
PU1
ISL62872 Quanta Computer Inc.

+VGPU_IO PROJECT : ZYD
PU7 Size Document Number Rev
3B
POWER MANAGEMENT
5 4 3 2 1
Dr-Bios.com
5 4 3 2 1
MODEL
ZYD
Model REV CHANGE LIST FROM To
X 1A
20091028 Page 30, Move the resisters and common chokes from M/B to daughter board
1A 20091028 Page 30, Move the R1027 and R1059 to daughter board and change to 0402 (place closer).
X 1A
ZYD MB 20091028 Page 30, Move USB Power switch to daughter board
X 1A
X 1A
20091028 Page 30, Change card reader&USB board CONN P/N to DFFC20FR255
X 1A
20091028 Page 26, Delete R203 and R171 to leave RJ45 chasiss contact to GND directly
X 1A
20091028 Page 31, Add net name susled#_R, Pwrled#_R,BATLED0#_R, BATLED1#_R,RFLED#_R,RFLED2#_R
X 1A
20091028 Page 35, Add SW1 for debug purpose
X 1A
20091028 Page 33, update Hole footprints
D
X 1A D
20091029 Page 41, Change PR199, PR200 P/N from CS00003J951 to CS00003F916 X 1A
X 1A
20091102 Page 24, 29, Add Mic_GND for internal analog MIC
X 1A
20091102 Page 27, Delete C204, C208, C558, R411, R385, R373, RP3, Q27, Q26. and change C578 from 0.47u to 4.7u
X 1A
20091102 Page 10, Stuff R1001, R1002, R503
X 1A
20091103 Page 33, Delete Hole4, Hole5, Hole8, Hole18 X 1A
X 1A
20091104 Page 33, update power schematic
X 1A
20091104 Page 30, swap L38,L39,L58 USB nets for layout request.
X 1A
20091108 Page 45, delete net name MAINON_G X 1A
20091108 Page 39, Change PR151 P/N from CS24703F908 to CS24023F928 for support Arrandale only X 1A
20091108 Page 33, Delete Hole36 X 1A
X 1A
20091110 Page 31, Move Wi-Fi LED to PB
X 1A
20091111 Page 39, Delete Pl8 and Change PL9 footprint and value(1.5uH footprint:CHOKE-ETQP4LR36WFC-NB4) X 1A
20091111 Page 41, Stuff +1.5V_GPU power source for EV@ only X 1A
20091111 Page 37, reserve PR275 for GPU power X 1A
X 1A
20091112 Page 18, Follow ATI suggestion to modify R419 from 680ohm to 51 ohm.
X 1A
20091112 Page 27, Remove LPC from Mini PCIE port CN24
X 1A
20091112 Page 37,45, unstuff +3V_SUS components
X 1A
20091113 Page 27, Two Wi-Fi LED share one net RF_LED# X 1A
20091113 Page 31, Delete Q21,Q23, R347 X 1A
20091113 Page 29, Reserve three more resistors R373, R368, R385 for ESD solution X 1A
C
X 1A C
20091116 Page 34, unstuff PR95, PR96, PQ17, PQ15 X 1A
20091116 Page 24, Change C650 from 0.22u/6.3V_4 to 0.22u/10V_4 X 1A
20091116 Page 32, Change C399 from 1U/6.3V_4 to 1u/10V_4 X 1A
20091116 Page 7, unstuff R159 X 1A
20091116 Page 11, stuff R592 for DIS and stuff R595 for UMA X 1A
20091116 Page 11, Reserve pull low for unused pin dGPU_VRON_R X 1A
20091116 Page 8, Delete R414 X 1A
20091116 Page 25, Delete R162 X 1A
20091116 Page 36~45, PC14 un-mount; PC207 change P/N; PC154 change P/N and value.; PC155 un-mount; PC180 change P/N; PC119 change P/N; PC118 change P/N X 1A
1A 2A
20091119 Page 36, Modify Bat CONN P/N and footprint
2A 1A 2A
20091119 Page 29, Modify Speaker CN7 P/N from DFHD04MR779 to DFHD04MR057
1A 2A
20091120 Page 8`13, Modify PCH P/N from AJ0QMGS0T05 to AJSLGZS0T07
1A 2A
20091124 Page 27, Short Pin42 and Pin44 of CN8 and CN10 to support Intel WiMAX/WiFi combo module 1A 2A
1A 2A
20091128 Page 37, stuff L36 for discrete sku
1A 2A
20091128 Page 9, change U30(ME ROM) P/N from AKE391P0N00 to AKE38ZP0N01
1A 2A
20091202 Page 3, reserve 1U for CLK GEN +1.5V power 1A 2A
1A 2A
20091203 Page 27, Stuff Q26 and Q28; unstuff R401 and R447; and add LPC bus to CN24 for debug purpose
1A 2A
20091209 Page 42, add VID table for Park XT 1A 2A
20091209 Page 3, change R257 from 0ohm to 33ohm 1A 2A
20091209 Page 3,17,18 follow AMD suggestion to stuff R257, R101, R407,R409 amd remove R36 to fix AMD pre-production silicon bug 1A 2A
1A 2A
20091214 Page 9, change R317 to a JP and stuff R322
B
1A 2A B
20091214 Page 32, change CN6 from DFHD05MRD98 to DFWF05MR027
1A 2A
20091221 Page 29, change R533 from CS03923F916 to CS33922FB15 1A 2A
1A 2A
20091223 Page 10, change R202, R203, R540, R566, R547 to short pad
1A 2A
20091223 Page 36, change DC jack P/N to DFHS04FR741
1A 2A
20091223 Page 32, change CN6 P/N to DFWF05MR012 1A 2A
1A 2A
20091225 Page 50, change CN19 P/N to DFHD19MR083
1A 2A
20091230 Page 12, Add C786 for CRT flicker issue 1A 2A
20091230 Page 27, change transformer footprint to TRF-10-1-24P-SMT 1A 2A
20091230 Page 17, change VGPU_CORE VID control pin 1A 2A
20091230 Page 28, Exchange P/N for cn8 and cn10 1A 2A
20091230 Page 28, Move controller link from CN10 to CN8 1A 2A
2A 3A
3A 20100129 Page 32, remove power LED MOS Q25 2A 3A
20100130 Page 18, Remove AMD option 2 workaround for Madison and Park; and change R36 from 1K to 10K 2A 3A
20100130 Page 28, Change Mini card footprint to MIPCI-800055FB052GX-52P-LDV-NB4 2A 3A
2A 3A
20100201 Page 32, restore power LED MOS Q25
2A 3A
20100201 Page 25, Change Q33,Q34 to ESD protection part
2A 3A
20100222 Page 24, Reserve C787 and C788 for CRT flicker issue 2A 3A
20100222 Page 36, Remove SW1 2A 3A
20100222 Page 12, Add C789 for VCCADAC 2A 3A
20100222 Page 17, Reserve 10U*2 caps for +1.8V_GPU 2A 3A
20100222 Page 30, Add short Pad R635,R636,R637,R638,R640 for EMI 2A 3A
A A
20100222 Page 24, unstuff L13 and stuff R89 and R90 2A 3A
Size
Date:
Document Number
PROJECT : ZYD
Change list2
5
Sheet 49 of 50
Rev
3B
DOC NO.
4
PROJECT MODEL :
PART NUMBER:
Dr-Bios.comZYD
3
APPROVED BY:
DRAWING BY:
2
DATE:
REVISON:
1
2010/3/25
3B
5 4 3 2 1
MODEL
ZYD
Model REV CHANGE LIST FROM To
3A 3B
3B 20100322 Page 32, delete Q25 3A 3B
ZYD MB 20100322 Page 44,45 modify PU5,PU7 footprint 3A 3B
20100324 Page 44,45 change PC184,PC179,PC207,PC125,PC236,PC118,PC186 P/N to CC71004MZ04 3A 3B
20100324 Page 43 change PC126, PC24, PC125 to CH5474KEA06(4.7uF 25V 0805) 3A 3B
20100324 Page 30 change R298,R314 to 39ohm 3A 3B
3A 3B
3A 3B
20100325 reserved EMI chock lacation for USB 1/3/11/12/8 3A 3B
D
20100325 Page 41 change PC226 to 0805 4.7uF/25V,and add PC247 ,BOM stuff. 3A 3B D
20100325 Page 30 change R223,R347,C444,R252, R590 and R306 to short pad. 3A 3B

3A 3B
3A 3B
C C
B B
A A
Size
Date:
Document Number
PROJECT : ZYD
Change list2
Wednesday, April 07, 2010
5
Sheet 50 of 50
Rev
3B
DOC NO.
4
PROJECT MODEL :
PART NUMBER: Dr-Bios.com

ZYD
3
APPROVED BY:
DRAWING BY:
2
DATE:
REVISON:
2010/3/25
3B
1

Acer TravelMate 7740 7740Z 1 Quanta ZYD - Rev3B

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Acer TravelMate 7740 7740Z 1 Quanta ZYD - Rev3B

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5 4 3 2 1

AU6437-GBL USB-3/11/12 PCIE-1 AR8151

BATTERY RTC P27

USB Port X2 X'TAL

Power Touch Pad

GPU PWR CTRL Option 1 (Default/ VDDR3 before VDDC)

GPU PWR CTRL Option 2 (VDDR3 after VDDR1)

Power States Thermal Follow Chart

+VCCRTC +3V~+3.3V RTC POWER ALWAYS ALWAYS NTC

+15V +15V CHARGE PUMP POWER ALWAYS ALWAYS

+3V_S5 +3.3V LAN/BT/PCH S5_ON S0-S5

+3V +3.3V CLK GEN/PCH/GPU/LVDS/Mini card/Codec/card MAINON

+1.5V_SUS +1.5V CPU/SODIMM CORE POWER SUSON S0-S3 SML1ALERT#

+1.8V +1.8V CPU/PCH/Braidwood POWER MAINON S0 SM-Bus

+1.1V_VTT +1.05V or +1.1V CPU VTT POWER MAINON S0 EC

+VCC_CORE variation CPU CORE POWER VRON S0

LCDVCC +3.3V LCD POWER LVDS_VDDEN S0

+VGPU_CORE +0.9V~+1.1V GPU CORE POWER +3V_D Discrete enable

+VGPU_IO +0.9V~+1.1V GPU I/O POWER PG_GPUIO_EN Discrete enable

+1V +1V DP/PEG POWER PG_1V_EN Discrete enable

+1.5V_GPU +1.5V VRAM CORE POWER PG_1.5V_EN Discrete enable

+1.8V_GPU +1.8V GPU_CRE/LVDS/PLL POWER +1.5V_GPU Discrete enable

Quanta Computer Inc.

AUBURNDALE/CLARKSFIELD PROCESSOR (DMI,PEG,FDI) AUBURNDALE/CLARKSFIELD PROCESSOR (CLK,MISC,JTAG)

Processor Compensation Signals

JTAG & BPM

Processor pull-up JTAG MAPPING

XDP_TMS R177 *51_4 *Short_4

Scan Chain STUFF -> R469, R491, R507

R175 (Default) NO STUFF -> R489, R490

Quanta Computer Inc.

AUBURNDALE/CLARKSFIELD PROCESSOR (DDR3) U26D

15 M_B_DQ[63:0] SB_CK[0] W8 M_B_CLK0 15

DDR SYSTEM MEMORY - B

M_A_DQ35 AK7 F8 M_A_DQS#1 M_B_DQ40 AK3 AR5 M_B_DQS#6

Channel A DQ[15,32,48,54], DM[5] Channel B DQ[16,18,36,42,56,57,60,61,62]

Tuesday, April 06, 2010 Sheet

CPU Core Power U26F

VTT Rail Values are AUBURNDALE/CLARKSFIELD PROCESSOR (GRAPHICS POWER)

1.1V RAIL POWER

C309 330u/2V_7343 AC32 +1.1V_VTT R490 EV@0_4 AJ16 Y1

CPU CORE SUPPLY

PEG & DMI

VCC62 VTT1_52 VTT1_68

VCC88 VCC_SENSE VCCSENSE 39

AUBURNDALE/CLARKSFIELD PROCESSOR (GND) AUBURNDALE/CLARKSFIELD PROCESSOR( RESERVED, CFG)

AT20 VSS1 VSS81 AE34 RSVD32 AJ13

AL20 VSS40 VSS120 W6 E21 VSS198 AJ29 CFG[15] RSVD_TP_59 E15

IBEX PEAK-M (DMI,FDI,GPIO)

Digital Display Interface

36 ICH_RSMRST# C16 H7 SUSC# 36 BC46

PM_RI# F14 F6 PM_SLP_LAN# TP39

PCH Pull-high/low +3V_S5

PM_RI# R321 10K_4

RTC Circuitry C758

RTC_N03 AH8 SATA_TXP1 29

+3VPCU R523 *10K_4 SPI_CS1# AY3 T3

SPI_MOSI TPM Functionality 1 = Enabled

SPKR Reboot option at power-up 0 = Default Mode (Internal weak Pull-down)

0 = Flash Descriptor Security will be overridden J3 *SHORT_ PAD1

GNT3#/ Top-Block 0 = Top Block Swap Mode

IntelR Anti-Theft Technology

NV_CLE DMI Termination DMI termination voltage. Weak

XDP_TMS R177 51_4 Short_4