System C

JOÃO LEONARDO FRAGOSO

System C
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System C 1.0 - HDL

System C 2.0 - HW/SW Codesign

João Leonardo Fragoso

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 System C – Concepts (1)
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Be able to model systems in an abstract

manner, but still be able to model concurrency
and interaction. Not dictate either a software
or hardware implementation

Be able to leverage existing, high level design
libraries, most of which are written in C.

João Leonardo Fragoso

System C – Concepts (2)

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Support synthesis into logic or embedded processor

code

Enjoy wide industrial support, which will insure
model portability

Support ease of modeling.

João Leonardo Fragoso

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 Why not simply C++ (1)
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Concurrency : Hardware systems are inherently

concurrent, i.e. they operate in parallel

Notion of time : Time sequenced operations

Hardware style communication : Signals,
protocols, etc.

João Leonardo Fragoso

Why not simply C++ (2)

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Reactivity : Hardware is inherently reactive

Hardware data types : Bit type, multi-valued logic
type, signed and unsigned integer types and fixed-
point types.

João Leonardo Fragoso

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 System C (library C++)
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Processes (for concurrency)

Clocks (for time)

Hardware data types (bit vectors, 4-valued
logic, fixed-point types, arbitrary precision
integers)

Waiting and watching (for reactivity)

Modules, ports, signals

João Leonardo Fragoso

System C
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History:

Version 1.0
 Circa 2000
 Basic Definition of the Language
 Interconnect Model: VHDL signal semantics
 Most Suitable for RTL modeling

Version 2.0
 Circa 2002
 Interconnect Model: channel
 Suitable for System Level Modeling for
Hardware/Software Co-Design
João Leonardo Fragoso

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 System C
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João Leonardo Fragoso

System C
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tools:
 EVE: Zebu- Hardware assisted co-modelling product
 Forte: Synthesizer, ECS, Gigascale - high level synthesis, library
and full system verification environement
 Future Design Automation: High Level Behavioral Synthesis
 IKOS - Vstation co-modelling
 Innoveda/summit - Visual Elite System Level Design - definition
and verification
 LisaTEK - Embedded Processor Tool Suite
 Mentor Graphics- Seamless C-bridge

João Leonardo Fragoso

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 System C
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tools:
 Synopsys: Cocentric serie - fied point designer, system C compiler,
Co-simulator, Synthesis of HW.
 Tension: Converts Verilog to SystemC
 TNI-Valiosys: simulation backplane and VHDL2SC
 TOPS-SLD: TS-SLD - integrate into LSI design flow
 Verisity: Specman - supports SystemC
 Veritools: SuperC - Accelerated Co-simulation
 Xilinx: FPGA system C flow

João Leonardo Fragoso

System C
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Summary of tools:
3 Commercial SystemC simulators
 4 Co-simulators
 4 Links to Emulation
 6 Synthesis tool
 4 HDL to SystemC converter
 2 SystemC extended libraries
 3 Analysis, display, verification and checkers
 6 System Level Modelling and Design Tools

João Leonardo Fragoso

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 System C
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Types:

Includes all normal C++ data types:
bool,char,int,short,long,unsigned, float, double, and long
double and associated operators.

SystemC defines additional data types of the form sc_xx,
where xx denotes a specific type.

User defined types supported

João Leonardo Fragoso

System C types (1)

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System C class and class templates:

sc_bit 2 value single bit (0,1)

sc_logic 4 value single bit (0,1,X,Z)

sc_int<n> 1 to 64 bit signed integer

sc_uint<n> 1 to 64 bit unsigned integer

sc_bigint arbitrary sized signed integer

sc_biguint arbitrary sized unsigned integer

João Leonardo Fragoso

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 System C types (2)
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sc_bv arbitrary sized 2 value vector

sc_lv arbitrary sized 4 value vector

sc_fixed templated signed fixed point

sc_ufixed templated unsigned fixed point

sc_fix untemplated signed fixed point

João Leonardo Fragoso

Signals and Variables

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Signals (sc_signal<n>) and Variables

Signals and ports have the same semantics as in VHDL

Initialization
 Staticvariables can be initialized in the constructor
 signals initialized only by assignment statements

João Leonardo Fragoso

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 System C
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Modules and Ports

Modules (sc_module)
 Fundamental structural entity
 include ports, constructors, data members and function
members
 Contain processes
 Contain other modules(creating hierarchy)

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System C
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Ports(sc_in<>,sc_out<>,sc_inout<>)
 Modules have ports
 Portshave types
 A process can be made sensitive to ports/signals
sc_in<porttype>//input port of type porttype
sc_out<porttype>//output port of type porttype
sc_inout<porttype>//inout port of type porttype
sc_in<sc_logic> a[32];
 Port read/write operations
 Read and write using read() and write() method

João Leonardo Fragoso

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 System C
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Arrays

supported but no direct assignment (like
C)

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System C
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Structural Models and Test Benches

Structural models are primarily created by instantiation into
the test bench, thus models are usually flat.

Test bench is sc_main

Execution of parts of sc_main is part concurrent, not totally

sequential as in normal C++

João Leonardo Fragoso

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 System C
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Clocks

Defined and started in two ways
 sc_clock clock(“my clock”, 20, SC_NS); sc_start(200,SC_NS);
 sc_initialize();
for (int i = 0; i <= 200; i++){
clock = 1;
sc_cycle(10,SC_NS);
clock = 0;
sc_cycle(10,SC_NS); }

João Leonardo Fragoso

System C
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Reactivity

Waiting (wait(), wait_until(...) )

Watching (watching(...))

Watching for an event while doing something else

(local or global)

João Leonardo Fragoso

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 System C
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Processes

Three process types

SystemC processes do not automatically loop

type 1: method
 activated by signals in a "sensitivity list" and then runs to
completion
 inactive until signals in sensitivity list are reactivated

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System C
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// dff.h
#include "systemc.h"
SC_MODULE(dff) {
sc_in<bool> din;
sc_in<bool> clock;
sc_out<bool> dout;
void doit();
SC_CTOR(dff) { // constructor
SC_METHOD(doit);
sensitive_pos << clock; // sensitivity list
}
};
// dff.cc
#include "systemc.h"
#include "dff.h"
void dff::doit() {
dout = din;

}
João Leonardo Fragoso

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 System C
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Type 2: Thread processes

 activated by signals in a "sensitivity list" and then runs to
completion or till suspended by a wait.
 if suspended by a wait, will resume when wait is satisfied,
otherwise when signals in the sensitivity list are reactivated

João Leonardo Fragoso

System C
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#include "systemc.h"
SC_MODULE(traff) {
// input ports
sc_in<bool> roadsensor;
sc_in<bool> clock;
// output ports
Traff.h sc_out<bool> NSred;
sc_out<bool> NSyellow;
sc_out<bool> NSgreen;
sc_out<bool> EWred;
sc_out<bool> EWyellow;
sc_out<bool> EWgreen;
void control_lights();
int i;
SC_CTOR(traff) { // constructor
SC_THREAD(control_lights); // Thread
Process
sensitive_pos << clock;

João Leonardo Fragoso

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 Traff.cc
System C
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#include "systemc.h"
#include "traff.h"
void traff::control_lights() {
NSred = false;
NSyellow = false;
NSgreen = true;
EWred = true;
EWyellow = false;
EWgreen = false;
while (true) {
while (roadsensor.delayed() == false)
wait();
NSgreen = false; // road sensor triggered
NSyellow = true; // set NS to yellow
NSred = false;
for (i=0; i<5; i++)

João Leonardo Fragoso wait();

System C
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NSgreen = false; // yellow interval over

Traff.cc
NSyellow = false; // set NS to red
NSred = true; // set EW to green
EWgreen = true;
EWyellow = false;
EWred = false;
for (i= 0; i<50; i++)
wait();
NSgreen = false; // times up for EW green
NSyellow = false; // set EW to yellow
NSred = true;
EWgreen = false;
EWyellow = true;
EWred = false;
for (i=0; i<5; i++) // times up for EW yellow

João Leonardo Fragoso wait();

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NSgreen = true; // set EW to red

NSyellow = false; // set NS to green Traff.cc
NSred = false;
EWgreen = false;
EWyellow = false;
EWred = true;
for (i=0; i<50; i++) // wait one more long
wait(); // interval before allowing
// a sensor input again
}
}

João Leonardo Fragoso

System C
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Type 3 - Clocked Thread

Same as threaded processes, except process is always
activated by the system clock

The SystemC 2.0 scheduler will execute all thread
processes and all method processes during the
initialization phase of the simulation. (as in VHDL)

you can use the dont_initialize() function

João Leonardo Fragoso

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 System C
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Time: 64 bits integer

time resolution: default 1 ps

commands: sc_set_time_resolution(10,SC_PS)
sc_set_default_time_unit(1,SC_PS)
sc_clk clk(„clk1“,10)

João Leonardo Fragoso

System C
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Example - counter (declaration):

// counter.h
#include "systemc.h"
SC_MODULE(counter) {
sc_in<bool> clock;
sc_in<bool> load;
sc_in<bool> clear;
sc_in<sc_int<8> > din;
sc_out<sc_int<8> > dout;
int countval;
void onetwothree ();
SC_CTOR(counter) {
SC_METHOD(onetwothree);
sensitive_pos (clock);
countval = 0;
}

};

João Leonardo Fragoso

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 System C
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Example - counter (behaviour):

// counter.cc
#include "counter.h"
void counter::onetwothree () {
if (clear == ’1’) {
countval = 0;
} else if (load == ’1’) {
countval = din.read(); // use read when a type
// conversion is happening
// from an input port
} else {
countval++;
}
dout = countval;
}

João Leonardo Fragoso

System C
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Example

João Leonardo Fragoso

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 System C
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Example

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