FPGA EB 02020 1 0 MachXO3D Development Board

MachXO3D Development Board
Evaluation Board User Guide
FPGA-EB-02020-1.0
May 2020
Disclaimers
Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its
products for any particular purpose. All information herein is provided AS IS and with all faults, and all risk associated with such information is entirely
with Buyer. Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have been
subject to limited testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the
same. No Lattice products should be used in conjunction with mission- or safety-critical or any other application in which the failure of Lattice’s
product could create a situation where personal injury, death, severe property or environmental damage may occur. The information provided in this
document is proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any
products at any time without notice.
© 2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
2 FPGA-EB-02020-1.0
Contents
Acronyms in This Document ................................................................................................................................................. 6
1. Introduction .................................................................................................................................................................. 7
1.1. MachXO3D Development Board ......................................................................................................................... 7
1.2. Features .............................................................................................................................................................. 8
1.3. MachXO3D Device ............................................................................................................................................... 9
1.4. L-ASC10 Device .................................................................................................................................................... 9
2. Applying Power to the Board ...................................................................................................................................... 10
3. JTAG/I2C Programming ............................................................................................................................................... 12
3.1. JTAG Download Interface .................................................................................................................................. 12
3.2. I2C Download Interface ..................................................................................................................................... 13
3.3. Alternate JTAG Download Interface .................................................................................................................. 13
3.4. JTAG to MSPI Pass-through Interface ............................................................................................................... 14
3.5. Other JTAG Configuration Pins .......................................................................................................................... 14
4. MachXO3D Clock Sources ........................................................................................................................................... 15
5. Headers and Test Connections ................................................................................................................................... 16
5.1. Versa Headers ................................................................................................................................................... 16
5.2. Arduino Board GPIO Headers ............................................................................................................................ 18
5.3. FX12 Headers (DNI) ........................................................................................................................................... 19
5.4. Aardvark Header (DNI) ...................................................................................................................................... 21
5.5. Raspberry Pi Board GPIO Header ...................................................................................................................... 21
5.6. Dedicated I3C Test Points ................................................................................................................................. 23
5.7. Dedicated Slew Rate Test Circuits ..................................................................................................................... 23
6. I2C and SPI Buses......................................................................................................................................................... 24
6.1. I2C Topology ...................................................................................................................................................... 24
6.2. SPI Topology ...................................................................................................................................................... 25
6.2.1. SPI Configuration .......................................................................................................................................... 25
6.2.2. SPI Flash Access ............................................................................................................................................ 26
7. LEDs and Switches ...................................................................................................................................................... 27
7.1. Four-Position DIP Switch ................................................................................................................................... 27
7.2. General Purpose Push Buttons ......................................................................................................................... 28
7.3. General Purpose LEDs ....................................................................................................................................... 28
7.4. LVDS Outputs Pins ............................................................................................................................................. 29
7.5. General Purpose DDR Outputs .......................................................................................................................... 30
7.6. Seven-Segment Display ..................................................................................................................................... 30
8. ASC Connections ......................................................................................................................................................... 31
8.1. ASC Interface ..................................................................................................................................................... 31
8.2. ASC Voltage Monitor ......................................................................................................................................... 31
8.3. ASC Current Monitor ......................................................................................................................................... 32
8.4. ASC Temperature Monitor ................................................................................................................................ 33
8.5. ASC LEDs ............................................................................................................................................................ 34
8.6. ASC HVOUT and Trim Pins ................................................................................................................................. 34
9. Software Requirements .............................................................................................................................................. 35
10. Storage and Handling ............................................................................................................................................. 35
11. Ordering Information .............................................................................................................................................. 35
12. Errata ...................................................................................................................................................................... 35
Technical Support Assistance .............................................................................................................................................. 36
Appendix A. MachXO3D-9400 Development Board Schematics ........................................................................................ 37
Appendix B. MachXO3D-9400 Development Board Bill of Materials ................................................................................. 47
Appendix C. Predefined Preference File Listing .................................................................................................................. 54
Appendix D. User Defined Preference File Listing .............................................................................................................. 55
References .......................................................................................................................................................................... 60
Revision History................................................................................................................................................................... 61
FPGA-EB-02020-1.0 3
Figures
Figure 1.1. Top View of MachXO3D Development Board ..................................................................................................... 7
Figure 1.2. Bottom View of MachXO3D Development Board............................................................................................... 8
Figure 2.1. Board Power Supply.......................................................................................................................................... 10
Figure 3.1. JTAG/I2C Programming Architecture ................................................................................................................ 12
Figure 3.2. JTAG Programming Mode ................................................................................................................................. 12
Figure 3.3. I2C Programming Mode .................................................................................................................................... 13
Figure 4.1. Optional Clock Circuit Design ............................................................................................................................ 15
Figure 5.1. Aardvark SS Pin Connections ............................................................................................................................ 21
Figure 5.2. Slew Rate Test Circuits ...................................................................................................................................... 23
Figure 6.1. I2C Topology ...................................................................................................................................................... 24
Figure 6.2. I2C MUX Circuits ................................................................................................................................................ 25
Figure 7.1. Four-Position DIP Switch Circuits ...................................................................................................................... 27
Figure 7.2. Four-Position DIP Switch Photograph ............................................................................................................... 27
Figure 7.3. Push Button SW5 Circuit Design ....................................................................................................................... 28
Figure 7.4. Board LEDs ........................................................................................................................................................ 29
Figure 7.5. Seven-Segment Display and its Symbol ............................................................................................................ 30
Figure 8.1. Trimmer Circuit Design for VMON7 .................................................................................................................. 32
Figure 8.2. Trimmer Wiper Description .............................................................................................................................. 32
Figure 8.3. VCC Core Current Monitoring Circuit................................................................................................................ 33
Figure 8.4. PNP Temperature Sensor Circuit ...................................................................................................................... 33
Figure 8.5. NPN Temperature Sensor Circuit ...................................................................................................................... 33
Figure 8.6. ASC LEDs ........................................................................................................................................................... 34
Figure 12.1. Top view of Raspberry Pi Connector............................................................................................................... 35
Figure A.1. Title Page .......................................................................................................................................................... 37
Figure A.2. Block Diagram ................................................................................................................................................... 38
Figure A.3. USB to JTAG I/F ................................................................................................................................................. 39
Figure A.4. VERSA Connector (BANK0) ............................................................................................................................... 40
Figure A.5. Arduino Header (BANK1) .................................................................................................................................. 41
Figure A.6. CrossLink Header (BANK2) ................................................................................................................................ 42
Figure A.7. Raspberry Pi Header and Others (BANK3, BANK4, and BANK5) ....................................................................... 43
Figure A.8. Analog Sense and Control ................................................................................................................................ 44
Figure A.9. Power Decoupling and LEDs ............................................................................................................................. 45
Figure A.10. Power Regulators ........................................................................................................................................... 46
4 FPGA-EB-02020-1.0
Tables
Table 2.1. 5 V Sources and Connections ............................................................................................................................. 10
Table 2.2. MachXO3D Power Rail Options.......................................................................................................................... 11
Table 2.3. ASC Power Connections ..................................................................................................................................... 11
Table 3.1. JTAG Connections .............................................................................................................................................. 13
Table 3.2. Other JTAG Signals ............................................................................................................................................. 14
Table 4.1. Input Clock Options ............................................................................................................................................ 15
Table 5.1. Versa J8 Header Pin Connections....................................................................................................................... 16
Table 5.2. Versa J9 Header Pin Connections ....................................................................................................................... 17
Table 5.3. Arduino J2 Pin Connections ............................................................................................................................... 18
Table 5.7. FX12 U4 Header Pin Connections ...................................................................................................................... 19
Table 5.8. FX12 U5 Header Pin Connections ...................................................................................................................... 20
Table 5.9. Aardvark J7 Header Pin Connections ................................................................................................................. 21
Table 5.10. Raspberry Pi J6 Header Pin Connections ......................................................................................................... 22
Table 5.11. I3C Test Points.................................................................................................................................................. 23
Table 5.12. Slew Rate Test Conditions ................................................................................................................................ 23
Table 6.1. I2C MUX Function ............................................................................................................................................... 24
Table 6.2. I2C Global Bus Connections ................................................................................................................................ 25
Table 6.3. MachXO3D SPI Connections .............................................................................................................................. 26
Table 6.4. MachXO3D SPI Configuration Options ............................................................................................................... 26
Table 7.1. Four-Position DIP Switch Signals ........................................................................................................................ 27
Table 7.2. Push Button Switch Signals ................................................................................................................................ 28
Table 7.3. LED Signals ......................................................................................................................................................... 28
Table 7.4. LVDS Test Points................................................................................................................................................. 29
Table 7.5. GDDR Test Points ............................................................................................................................................... 30
Table 7.6. Seven-Segment Display Connections ................................................................................................................. 30
Table 8.1. ASC to MachXO3D Connections ......................................................................................................................... 31
Table 8.2. ASC VMON Connections .................................................................................................................................... 31
Table 8.3. ASC IMON Connections ...................................................................................................................................... 32
Table 8.4. ASC TMON Connections ..................................................................................................................................... 33
Table 8.5. GPIO LED Connections ....................................................................................................................................... 34
Table 8.6. ASC HVOUT and Trim Connections .................................................................................................................... 34
Table 11.1 Ordering Information ........................................................................................................................................ 35
FPGA-EB-02020-1.0 5
Acronyms in This Document

A list of acronyms used in this document.
Acronym Definition
ASC Analog Sense and Control
CMOS Complementary Metal-Oxide Semiconductor
GDDR Graphics Double Data Rate
FTDI Future Technology Devices International
GPIO General Purpose Input/Output
I2C Inter-Integrated Circuit
I3C The MIPI I3C Sensor Interface, is an evolution of I2C
LDO Low Dropout
LVDS Low-Voltage Differential Signaling
SPI Serial Peripheral Interface
6 FPGA-EB-02020-1.0
1. Introduction
The Lattice Semiconductor MachXO3D™ Development Board allows designers to investigate and experiment with the
features of the MachXO3D device. The features of the MachXO3D Development Board can assist engineers with the
rapid prototyping and testing of their specific designs.
The MachXO3D Development Board is part of the MachXO3D Development Kit, which includes the following:
 MachXO3D Development Board pre-loaded with the demo design
 Mini USB cable
 Quick Start Guide
This document is intended to be referenced in conjunction with MachXO3D demo user guides. See the References
section.
The contents of this user guide include top-level functional descriptions of the various portions of the development
board, descriptions of the onboard headers, diodes and switches, and a complete set of schematics.
1.1. MachXO3D Development Board

Along with the MachXO3D-9400HC device, the MachXO3D Development Board also includes features to expand the
usability of the MachXO3D-9400HC with Arduino, Raspberry, FX12, Versa, and Aardvark headers.
Figure 1.1 shows the top view of the MachXO3D Development Board.
Figure 1.2 shows the bottom view of this board.
Segment Displayer (D20) SMA Header (J10) Versa Headers (J8, J9)
Trimmer 10K
(POT1)
L-ASC10
Device (U7)
JTAG Header
(J1)
Push Buttons
(SW2~SW5)
User LEDs
(D1~D8)
DIP Switch FX12 Header MachXO3D FX12 Header SPI Flash Aardvark Header
(SW1) (U4) Device (U3) (U5) (U6) (J7)
Figure 1.1. Top View of MachXO3D Development Board
FPGA-EB-02020-1.0 7
Mini-USB Header (J11)
Arduino Headers FTDI Device Raspberry Pi

(J2, J3, J4, J5) (U1) Header (J6)
Figure 1.2. Bottom View of MachXO3D Development Board
1.2. Features
 LCMXO3D-9400HC demonstration
 General Purpose Input/Output (GPIO) interface with Arduino and Raspberry Pi boards
 USB-B connection for device programming and Inter-Integrated Circuit (I2C) utility
 Onboard Boot Flash – 128 Mbit Serial Peripheral Interface (SPI) Flash with Quad read feature for user’s application
 7-Segment Blue LED, 4-position DIP Switches, 4 push buttons, and 16 red LEDs for demo purposes
 Lattice Diamond® programming support
 Multiple reference clock sources
 Two Hirose FX12-40 header positions (DNI)
 Aardvark header (DNI)
Note: DNI stands for “Do NOT Install” parts and DI stands for “Do Install” parts for assembly.
Caution: The MachXO3D Development Board contains ESD-sensitive components. ESD safe
practices should be followed while handling and using the development board.
8 FPGA-EB-02020-1.0
1.3. MachXO3D Device

The MachXO3D Development Board features the MachXO3D-9400HC in a 484-ball caBGA package. This device offers a
variety of features and programmability that enhances Secure Control PLD functionality with hardware Root-of-Trust
and Dual Boot capabilities. Its immutable Embedded Security Block offers cryptographic functions such as ECDSA256,
SHA256, HMAC, ECIES, ECDH, AES-128/256, PUF, Public/Private Key Generation, and True Random Number Generator.
Along with the Embedded Security Block, numerous system functions are included such as two PLLs and 432 kbits of
embedded RAM plus hardened implementations of I2C and SPI. Flexible, high performance I/O support numerous
single-ended and differential standards including LVDS. For more information on the capabilities of MachXO3D, see
MachXO3D Family Data Sheet (FPGA-DS-02026).
1.4. L-ASC10 Device

The L-ASC10 (also referred to as ASC, or Analog Sense and Control) is a Hardware Management (Power, Thermal, and
Control Plane Management) Expander designed to be used with Platform Manager 2 or MachXO2™/MachXO3 FPGAs to
implement the Hardware Management Control function in a circuit board. The L-ASC10 is included on this board for
future expansion. This design flow is not supported in Diamond 3.11 SP2 or earlier. Check the Lattice website –
www.latticesemi.com – for the latest news and support information for the MachXO3D + L-ASC10.
The L-ASC10 enables seamless scaling of power supply voltage and current monitoring, temperature monitoring,
sequence and margin control channels. ASC includes dedicated interfaces supporting the exchange of monitor signal
status and output control signals with centralized hardware management controllers. For more information on the
capabilities of ASC device, see L-ASC10 In-System Programmable Hardware Management Expander Data Sheet
(FPGA-DS-02038).
FPGA-EB-02020-1.0 9
2. Applying Power to the Board

The MachXO3D Development Board is ready to power on with onboard Low Dropout (LDO) generators powered by an
external 5 V power, as shown in Figure 2.1. The 5 V power can come from a USB connection (J11) and routed to
multiple onboard headers listed in Table 2.1. Note that the 5 V power path to headers should be manually connected
using a short resistor or jumper before power is applied to the mated board as outlined in Table 2.1.
Table 2.1. 5 V Sources and Connections
Header (Reference) 5 V Power Pins 5 V Power Path (Assembly)
USB header (J11) 1 L3 (DI)
FX12 header 1 (U4) 23, 38 R153 (DNI)
FX12 header 2 (U5) 23, 38 R155 (DNI)
Aardvark header (J7) 4, 6 R78 (DNI), R79 (DNI)
Arduino header (J4) 5 JP6 (DNI)
Raspberry Pi header (J6) 2, 4 JP7 (DNI)
Versa header (J8) 21 R30 (DNI)
Warning: Avoid power conflict when the 5 V power path is enabled from the MachXO3D
Development Board to the mated board. Do Not apply 5V power from both boards
when the path in the table is configured shorted.
Conversely, 5 V power can be supplied from onboard headers if J11 is not connected to a USB cable. The power from
the headers can be used to drive LDOs and other mated boards.
Aside from the 3.3 V LDO (U8) default power source for MachXO3D device (U3), the board provides additional LDO
footprint (U9) for lower power applications. SOT-223 footprint compatible LDOs from 1.2 V to 3.3 V can also be
considered. Currently TLV1117LV12DCY is used to provide 1.2 V for optional VCCIOs. VCCIO1 for Bank 1, and VCCIO3
for Bank 3 can likewise be supplied from mated boards for better GPIO voltage alignment.
Figure 2.1. Board Power Supply
10 FPGA-EB-02020-1.0
Table 2.2. MachXO3D Power Rail Options

MachXO3D Power (U3) 3.3 V Option (Assembly) 1.2V~3.3 V Option (Assembly) Mated Board Option (Assembly)
VCC Core R123 (DI) R127 (DNI)* NA
VCCIO0 R124 (DI) R128 (DNI) NA
VCCIO1 R125 (DI) R129 (DNI) R151 (DNI) for Arduino header
VCCIO3 R132 (DI) R137 (DNI) R158 (DNI) for Raspberry Pi header
*Note: R127 is applicable only in 2.5 V~3.3 V (U9) range for LCMXO3D-9400HC device.
Warning: Only one option should be enabled for each MachXO3D device power rail.
The ASC device (U7) acquires power from the 3.3 V LDO only. A jumper (JP1) needs to be installed to provide the power
and this can also be used as test point to measure current drawn by the ASC.
Table 2.3. ASC Power Connections
ASC Power ASC Power Pins ASC Power Isolation (Assembly)
3.3 V VCC 8, 33 of U7 JP1 (DI)
FPGA-EB-02020-1.0 11
3. JTAG/I2C Programming
The JTAG/I2C programming architecture of the MachXO3D Development Board is shown in Figure 3.1.
Figure 3.1. JTAG/I2C Programming Architecture
3.1. JTAG Download Interface

The MachXO3D Development Board has a built-in download controller for programming the MachXO3D device. It uses
an FT2232H Future Technology Devices International (FTDI) part to convert USB to JTAG. To use the built-in download
cable, connect the USB cable from J11 to your PC (with Diamond programming software installed). A mini USB to USB-A
cable is included in the MarchXO3D Development Kit. The USB hub on the PC detects the cable of the USB function on
Port 0, making the built-in cable available for use with the Diamond programming software. Using JTAG Programming
for the Access mode is shown in Figure 3.2.
Figure 3.2. JTAG Programming Mode
12 FPGA-EB-02020-1.0
3.2. I2C Download Interface

The USB hub on the PC can also detect the addition of the USB function on Port 1. Select the port FTUSB-1 on the
programmer interface and enable the I2C MUX path from FTDI to the I2C bus. This is done by setting the J10 jumper
(D57 red LED is lighted). The I2C interface programming can be also used to configure the MachXO3D device as shown
in Figure 3.3, however, make sure that the I2C port is not disabled by the current working pattern.
Figure 3.3. I2C Programming Mode
3.3. Alternate JTAG Download Interface

J1 is an 8-pin standalone JTAG header that is used with an external Lattice download cable (available separately) when
the FTDI part is disabled from the JTAG chain after setting JP9. A USB download cable can be attached to the board
using J1 to interface with the MachXO3D device. For details on the connection between the USB download cable and
J1, refer to Programming Cable User Guide (FPGA-UG-02042).
J1 can also be used as test point when USB to JTAG is working. Additionally, you can enable the JTAG access path
through the Raspberry Pi header (J6) for customer applications. This is done by connecting the J6 header to the J1
header through some onboard resistors. The JTAG connections between J1 and J6 are listed in Table 3.1.
Table 3.1. JTAG Connections
MachXO3D Ball J1 to J6 Isolation
J1 Pin Number JTAG Signal Name J6 Pin Number Raspberry Pi GPIO
Location for JTAG (Assembly)
1 VCCIO0 — — — —
2 TDO E8 10 R90 (DNI) IO15
3 TDI E9 11 R93 (DNI) IO17
4 — — — — —
5 — — — — —
6 TMS C10 12 R91 (DNI) IO18
7 GND — — — —
8 TCK D10 8 R95 (DNI) IO14
FPGA-EB-02020-1.0 13
3.4. JTAG to MSPI Pass-through Interface

The download controller can also access the JTAG to MSPI pass-through circuit that allows the slave SPI Flash to be
erased, programmed, and read with Diamond Programmer.
3.5. Other JTAG Configuration Pins

The MachXO3D Development Board provides test points for other JTAG configuration pins as shown in Table 3.2.
Table 3.2. Other JTAG Signals
Signal Name MachXO3D Ball Location Test Point
JTAGENB E14 TP6
PROGRAMN E15 Pin 1 of JP5
INITN F16 TP7
DONE E17 TP8
2
For more information on MachXO3D JTAG/ I C programming, refer to MachXO3D Programming and Configuration
Usage Guide (FPGA-TN-02069).
14 FPGA-EB-02020-1.0
4. MachXO3D Clock Sources

The MachXO3D Development Board has four options for the MachXO3D clock sources:
 12 MHz from U1 (FTDI)
 8 MHz from U7 (ASC)
 User defined frequency by installing an oscillator in the X2 (DNI) footprint
 Off-board clock source from J10 (DNI)
The 8 MHz clock from U7 is the default clock source when building a Platform Manager design. Note that JP1 should be
installed to power the ASC device.
The 12 MHz clock from the FT2232H FTDI device is another clock source. Its use requires JP11 to be installed to connect
the 12 MHz clock signal to the MachXO3D device I/O. JP9 should not be installed to enable U1.
Table 4.1. Input Clock Options
Clock Signal MachXO3D Clock
Comments
Frequency Name Ball Location Source
8 MHz ASC_CLK L1 U7 JP1 installed, test point TP14.
12 MHz 12MHz B10 U1 JP11 installed, JP9 removed.
User defined OSC_IN D22 X2 (DNI) JP4 removed and OSC_EN signal (MachXO3D ball L20) Logic 1.
X2 not installed, or OSC_EN signal (MachXO3D ball L20) Logic 0,
User defined OSC_IN D22 J10 (DNI)
or JP4 installed.
Additional information on using optional clock sources:
 The board provides an optional clock input for the MachXO3D from either the Oscillator (X2) or the SMA header
(J10), as shown in Figure 4.1. Neither of them is populated.
 X2 should be installed by the end user, and it should be a 2.5 mm × 2.0 mm 4-SMD package. This is compatible
with the ASDMB serial of the Ultra Miniature Pure Silicon™ Clock Oscillator from Abracon LLC. JP4 can be used to
disable X2 output by pulling down OSC_EN, which can also be controlled by the L20 pin of MachXO3D.
 J10 should be installed by the end user. A Complementary Metal-Oxide Semiconductor (CMOS) compatible clock
can then be connected to an SMA cable.
Figure 4.1. Optional Clock Circuit Design
FPGA-EB-02020-1.0 15
5. Headers and Test Connections

This section describes the MachXO3D Development Board headers and test connections.
5.1. Versa Headers

The board provides two headers – J8 and J9 for expansion purpose.
Table 5.1. Versa J8 Header Pin Connections
J8 Pin Number Signal Name MachXO3D Ball Location
1 GND —
2 NC —
3 EXPCON_2V5* —
4 EXPCON_IO29 E12
5 EXPCON_IO30 D14
6 EXPCON_IO31 C15
7 EXPCON_IO32 C17
8 EXPCON_IO33 D15
9 EXPCON_IO34 C18
10 EXPCON_IO35 D16
11 EXPCON_IO36 C19
12 EXPCON_IO37 D17
13 EXPCON_IO38 D18
14 EXPCON_IO39 C20
15 EXPCON_IO40 E16
16 EXPCON_IO41 E13
17 EXPCON_IO42 F13
18 EXPCON_IO43 F15
19 EXPCON_IO44 G15
20 EXPCON_IO45 G12
21 5VIN* —
22 GND —
23 EXPCON_2V5* —
24 GND —
25 VCCIO0 —
26 GND —
27 VCCIO0 —
28 GND —
29 EXPCON_OSC* —
30 GND —
31 EXPCON_CLKIN A10
32 GND —
33 EXPCON_CLKOUT A21
34 GND —
35 EXPCON_3V3** —
36 GND —
37 EXPCON_3V3** —
38 GND —
39 EXPCON_3V3** —
40 GND —
16 FPGA-EB-02020-1.0
Notes:
* Signal is optionally connected to power source through resistor DNI.
** Signal is optionally connected to power source through resistor DI.
Table 5.2. Versa J9 Header Pin Connections
1 HPE_RESOUT# G9
2 GND —
3 EXPCON_IO0 F8
4 EXPCON_IO1 G8
5 EXPCON_IO2 F9
6 EXPCON_IO3 F7
7 EXPCON_IO4 E7
8 EXPCON_IO5 E6
9 EXPCON_IO6 D5
10 EXPCON_IO7 C3
11 EXPCON_IO8 D6
12 EXPCON_IO9 C4
13 EXPCON_IO10 F10
14 EXPCON_IO11 C5
15 EXPCON_IO12 C6
16 EXPCON_IO13 B12
17 EXPCON_IO14 D7
18 EXPCON_IO15 A12
19 GND —
20 EXPCON_3V3** —
21 EXPCON_IO16 D8
22 GND —
23 EXPCON_IO17 C8
24 GND —
25 EXPCON_IO18 D9
26 GND —
27 EXPCON_IO19 E10
28 EXPCON_IO20 C9
29 EXPCON_IO21 G11
30 GND —
31 EXPCON_IO22 E11
32 EXPCON_IO23 D11
33 EXPCON_IO24 F11
34 GND —
35 EXPCON_IO25 D12
36 EXPCON_IO26 F12
37 EXPCON_IO27 D13
38 CARDSEL#* —
39 EXPCON_IO28 C14
40 GND —
Notes:
** Signal is optionally connected to power source through resistor DI.
FPGA-EB-02020-1.0 17
5.2. Arduino Board GPIO Headers

The board provides four headers, J2, J3, J4, and J5, for Arduino Zero board adaption.
Table 5.3. Arduino J2 Pin Connections
Arduino ZERO MachXO3D
J2 Pin Number Signal Name Comments
Board Signal Ball Location
1 AR_IO8 ~8 U21 —
2 AR_IO9 ~9 U22 —
Optional connection to SS through R67 for SPI access,
3 AR_SS_IO10 ~10 W20
DNI by default.
AR_MOSI_IO1 Optional connection to SISPI through R82 for SPI
4 ~11 V18
1 access, DNI by default.
AR_MISO_IO1 Optional connection to SPISO through R77 for SPI
5 ~12 G16
2 access, DNI by default.
Optional connection to MCLK through R76 for SPI
6 AR_SCK_IO13 ~13 F17
access, DNI by default.
7 GND GND — —
AR_AREF connection to AREF through R43, DNI by
8 AR_AREF AREF U17
default.
Optional connection to SDA0 through R44, DNI by
9 AR_SDA SDA U19
default.
Optional connection to SCL0 through R45, DNI by
10 AR_SCL SCL U18
default.

J3 Pin Number Signal Name Arduino ZERO Board Signal MachXO3D Ball Location
1 AR_IO0 RX <- 0 G19
2 AR_IO1 TX -> 1 G20
3 AR_IO2 2 G21
4 AR_IO3 ~3 H20
5 AR_IO4 ~4 G18
6 AR_IO5 ~5 L21
7 AR_IO6 ~6 W22
8 AR_IO7 7 V22
9 AR_SDA SDA U19
10 AR_SCL SCL U18

Arduino ZERO MachXO3D Ball
Board Signal Location
1 AR_IO14 ATN T17 —
2 NC IOREF — —
Pin U20 should be set high by default. Avoid
3 AR_RESET RESET U20 Arduino ZERO board in Reset status when
connected.
4 +3.3V_AR 3.3 V — 3.3 V power supply from Arduino ZERO board.
5 AR_5V 5V — Jump to 5 V main power through JP6.
6 GND GND — —
7 GND GND — —
8 +12V VIN — 12 V power supply from Arduino ZERO board.
18 FPGA-EB-02020-1.0
Note: If JP6 is installed, 5 V power can be supplied from either the Arduino board or the MachXO3D Development Board. With JP6
removed, both boards need their own 5 V power
Arduino ZERO MachXO3D Ball
Board Signal Location
1 AR_AD0 A0 P19 Used as GPIO in digital mode.
5 AR_AD4 A4 K22 Used as GPIO in digital mode.
6 AR_AD5 A5 G17 Used as GPIO in digital mode.
5.3. FX12 Headers (DNI)

The board provides two headers, U4 and U5, to connect to FX12 compatible boards or cables. Each header has eight
pairs of Low-Voltage Differential Signaling (LVDS) signals for high-speed data receiver.
Table 5.7. FX12 U4 Header Pin Connections
U4 Pin Number Signal Name MachXO3D Ball Location
1 CH0_DCK_P AA10
2 CH0_DCK_N AB10
3 GND —
4 CH0_DATA0_P AA4
5 CH0_DATA0_N AB4
6 GND —
7 CH0_DATA2_P AA5
8 CH0_DATA2_N AB5
9 GND —
10 FX_SN* —
11 FX_SCLK* —
12 PWR_12V** —
13 SDA2 AB13
14 SCL2 AA13
15 GND —
16 CH2_DATA0_P AA6
17 CH2_DATA0_N AB6
18 GND —
19 CH2_DCK_P AA7
20 CH2_DCK_N AB7
21 PWR_12V** —
22 RESETN AB3
23 PWR_5-0V* —
24 CH0_DATA1_P AA2
25 CH0_DATA1_N AB2
26 PWR_3-3V* —
27 CH0_DATA3_P AA8
28 CH0_DATA3_N AB8
29 PWR_1-8V* —
30 FX_MOSI* —
FPGA-EB-02020-1.0 19

31 FX_MISO* —
32 PWR_1-8V* —
33 GND —
34 GND —
35 PWR_3-3V* —
36 CH2_DATA1_P AA9
37 CH2_DATA1_N AB9
38 PWR_5-0V* —
39 SDA1 AA11
40 SCL1 AB11
Notes:
** 12 V power needs external supply from pin 8 of J4.
Table 5.8. FX12 U5 Header Pin Connections
1 CH1_DCK_P AB12
2 CH1_DCK_N AA12
3 GND —
4 CH1_DATA0_P AB16
5 CH1_DATA0_N AA16
6 GND -
7 CH1_DATA2_P AB17
8 CH1_DATA2_N AA17
9 GND —
10 FX_SN* —
11 FX_SCLK* —
12 PWR_12V** —
13 SDA2 AB13
14 SCL2 AA13
15 GND —
16 CH3_DATA0_P AB18
17 CH3_DATA0_N AA18
18 GND —
19 CH3_DCK_P AB19
20 CH3_DCK_N AA19
21 PWR_12V** —
22 RESETN AB3
23 PWR_5-0V* —
24 CH1_DATA1_P AB14
25 CH1_DATA1_N AA14
26 PWR_3-3V* —
27 CH1_DATA3_P AB15
28 CH1_DATA3_N AA15
29 PWR_1-8V —
30 FX_MOSI* —
31 FX_MISO* —
32 PWR_1-8V* —
33 GND —
20 FPGA-EB-02020-1.0

34 GND —
35 PWR_3-3V* —
36 CH3_DATA1_P AB20
37 CH3_DATA1_N AA20
38 PWR_5-0V* —
39 SDA1 AA11
40 SCL1 AB11
Notes:
** 12 V power needs external supply from pin 8 of J4.
5.4. Aardvark Header (DNI)

The Aardvark I2C /SPI Host Adapter is a fast and powerful I2C bus and SPI bus host adapter through USB. It allows you to
interface a Windows, Linux, or Mac OS X PC through USB to a downstream embedded system environment and
transfer serial messages using the I2C and SPI protocols.
The MachXO3D Development Board provides an Aardvark compatible header for customer applications. The I 2C bus is
capable of connecting to a global I2C bus on the board, if JP10 is NOT set.
Table 5.9. Aardvark J7 Header Pin Connections
1 J7_SCL To I2C analog switch U10
2 — GND
3 J7_SDA To I2C analog switch U11
4 +5V_I2C To VBUS_5V through R78, DNI
5 SPISO To MachXO3D U9
6 +5V_SPI To VBUS_5V through R79, DNI
7 MCLK To MachXO3D T9
8 SISPI To MachXO3D AA21
9 SS Multiple options, as shown in Figure 5.1.
10 — —
Caution: VCCIO2 should be 3.3 V when connected to Aardvark I2C/SPI Host Adapter.
Pin 9 of the Aardvark header is an SS signal that can be optionally connected to multiple devices or connectors. By
default, Pin 9 can access Slave SPI in the MachXO3D device as the Master SPI through R160. It can access FX12 header,
Raspberry Pi header and on-board SPI Flash by enabling R161. It can also access the Arduino header by enabling R67.
Figure 5.1. Aardvark SS Pin Connections
5.5. Raspberry Pi Board GPIO Header

The MachXO3D Development Board provides a 40-pin receptacle that is compatible with the GPIO header of Raspberry
Pi 2/3 serial models.
FPGA-EB-02020-1.0 21
Table 5.10. Raspberry Pi J6 Header Pin Connections

1 3.3V_RASP* —
2 RASP_5V** —
3 RASP_IO02 U2
4 RASP_5V** —
5 RASP_IO03 V1
6 GND —
7 RASP_IO04 T6
8 RASP_IO14 P4
9 GND —
10 RASP_IO15 N5
11 RASP_IO17 N6
12 RASP_IO18 N7
13 RASP_IO27 P5
14 GND —
15 RASP_IO22 P6
16 RASP_IO23 R3
17 3.3V_RASP* —
18 RASP_IO24 R4
19 RASP_IO10 R6
20 GND —
21 RASP_IO09 R7
22 RASP_IO25 R5
23 RASP_IO11 T3
24 RASP_IO08 T4
25 GND —
26 RASP_IO07 T5
27 RASP_ID_SD V5
28 RASP_ID_SC T7
29 RASP_IO05 U3
30 GND —
31 RASP_IO06 U4
32 RASP_IO12 V4
33 RASP_IO13 U5
34 GND —
35 RASP_IO19 W3
36 RASP_IO16 W4
37 RASP_IO26 P7
38 RASP_IO20 Y2
39 GND —
40 RASP_IO21 Y3
Notes:
* 3.3 V power is supplied from Raspberry Pi board.
** 5 V power can come from either the Raspberry Pi board or the MachXO3D Development Board when jumper JP7 is installed.
When jumper JP7 is not installed, both boards need their own 5 V power.
22 FPGA-EB-02020-1.0
5.6. Dedicated I3C Test Points

The MachXO3D device features four pairs of I/O with I3C dynamic pull up capability in Bank 3. The MachXO3D
Development Board routes out two pairs of unoccupied I/O to test points for customer applications.
Table 5.11. I3C Test Points
Test Points Signal Name MachXO3D Ball Location
TP3 I3C_AA1 AA1
TP4 I3C_Y1 Y1
TP5 I3C_U1 U1
TP9 I3C_T2 T2
5.7. Dedicated Slew Rate Test Circuits

MachXO3D device features two sets of test circuits to simulate the trace conditions for different board sizes, providing
variable traces with 4-inch, 8-inch and 16-inch length for customer flexibility. Figure 5.2 shows one of the test circuits.
The test conditions for different trace length are summarized in Table 5.12.
Figure 5.2
Figure 5.2. Slew Rate Test Circuits
Table 5.12. Slew Rate Test Conditions

Enable 4- inch Trace Enable 8-inch Trace Enable 16-inch Trace
IO
MachXO3D Ball Location Test Load Path Test Load Path Load Path
Bank Test Point
Point Cap Config Point Cap Config Cap Config
R279(DI) R279(DNI) R279(DNI)
R280(DNI) R280(DI) R280(DI)
M22 1 TP105 C116 TP107 C118 TP109 C120
R290(DNI) R290(DI) R290(DNI)
R281(DNI) R281(DNI) R281(DI)
R282(DI) R282(DNI) R282(DNI)
R283(DNI) R283(DI) R283(DI)
B21 0 TP106 C117 TP108 C119 TP110 C121
R291(DNI) R291(DI) R291(DNI)
R284(DNI) R284(DNI) R284(DI)
FPGA-EB-02020-1.0 23
6. I2C and SPI Buses

This section describes the MachXO3D Development Board I2C and SPI topology.
6.1. I2C Topology

The MachXO3D Development Board has a flexible I2C bus to support all optional connectors and devices on the board.
The global I2C bus has the signal names SDA0 and SCL0, and they are routed close to the devices and headers as shown
in Figure 6.1.
FTDI (UI) Aardvark Header (J7)
I2C MUX (U10/U11)

R87
R70
R71
R85
ASC MachXO3D
Raspberry Pi MachXO3D FX12 Headers
(U7) Bank2
Header (J6) Bank3 (U4/U5)
R96
R81
R84
R83
R97
R98
R45
R37
R35
R44
Versa Header MachXO3D MachXO3D Arduino
Bank0 MachXO3D Header (J2)
(J9) Bank1
Bank4
Figure 6.1. I2C Topology
The board provides two options for accessing the global I2C bus from external cables. One is from the mini USB cable
(J11) through FTDI (U1). The other is from the Aardvark header (J7) for an Aardvark cable. Two analog MUXes, as
shown in Figure 6.2, are used to select between the USB and Aardvark cables. Both MUXes are controlled by the signal
USB_I2C_EN.
Table 6.1. I2C MUX Function
Global I2C Controller USB_I2C_EN Logic Level FSA4157 MUX Function SCL0 Test Point SDA0 Test Point
J7_SCL <> SCL0 J7_SDA <>
Aardvark Header (J7) 0 (JP10 removed) Pin1 of J7 Pin3 of J7
SDA0
FTDI_SCL <> SCL0 FTDI_SDA
USB FTDI (U1) 1 (JP10 installed) TP1 TP2
<> SDA0
When the jumper JP10 is removed, the USB_I2C_EN signal is low and the Aardvark header J7 is connected to the global
I2C bus. When the jumper JP10 is installed, the USB_I2C_EN signal is high and the USB connector J11 is connected to
the global I2C bus through the FTDI device.
24 FPGA-EB-02020-1.0
Figure 6.2. I2C MUX Circuits
To support a wide variety of I2C applications, each header or device is connected to a dedicated MachXO3D GPIO bank
with a direct local I2C bus. Each local I2C bus can optionally connect to the global I2C bus through resistors. The local I2C
connections are summarized in Table 6.2.
Table 6.2. I2C Global Bus Connections
MachXO3D Component MachXO3D Logical Signal Name
Header Pin Resistor
Bank (Reference) Ball (Global I2C Signal)
18 A12 EXPCON_IO15 (SDA0) R37 (DI)*
0 Versa header (J9)
16 B12 EXPCON_IO13 (SCL0) R35 (DI)*
9 U19 AR_SDA (SDA0) R44 (DNI)
1 Arduino header (J2)
10 U18 AR_SCL (SCL0) R45 (DNI)
39 AA11 SDA1 (SDA0) R81 (DNI)
FX12 headers 40 AB11 SCL1 (SCL0) R83 (DNI)
2
(U4/U5) 13 AB13 SDA2 (SDA0) R71 (DNI)
14 AA13 SCL2 (SCL0) R70 (DNI)
3 U2 RASP_IO02 (SDA0) R84 (DNI)
Raspberry Pi 5 V1 RASP_IO03 (SCL0) R96 (DNI)
3
header (J6) 27 V5 RASP_ID_SD (SDA0) R87 (DNI)
28 T7 RASP_ID_SC (SCL0) R85 (DNI)
14 K2 I2C_SDA0 (SDA0) R97 (DI)*
4 ASC device (U7)
15 K1 I2C_SCL0 (SDA0) R98 (DI)*
*Note: The resistor needs to be installed to support programming of the ASC device. Versa header J9 pins 16 and 18 need to be
high-Z to support programming of the ASC device. Balls B12 and A12 should be used in Platform Manager design. Balls K1 and K2
provide a connection for a user-instantiated I2C port as part of a separate system to communicate with the ASC device.
6.2. SPI Topology

6.2.1. SPI Configuration
One of the major functions of SPI connections on the board is to support MachXO3D configuration from SPI ports. The
MachXO3D Development Board can support both Master SPI (MSPI) and Slave SPI (SSPI) modes for MachXO3D
configuration.
FPGA-EB-02020-1.0 25
Table 6.3. MachXO3D SPI Connections

Signal Name MachXO3D Ball Location MSPI Mode Direction SSPI Mode Direction
MCLK T9 Output Input
SN AB21 Input Input
SISPI AA21 Output Input
SPISO U9 Input Output
CSSPIN AA3 Output Not used
The MachXO3D device can be configured from different ports on the board as listed in Table 6.4. By default, the
MachXO3D device can boot up from SPI Flash with Master SPI mode.
Table 6.4. MachXO3D SPI Configuration Options
Master CS (Pin Number of Slave CS (Pin Number of
Master SPI Device (Reference) Slave SPI Device (Reference)
Reference Part) Reference Part)
MachXO3D (U3) CSSPIN (AA3) SPI Flash (U6) CS# (1)
MachXO3D (U3) CSSPIN (AA3) FX12 (U4, U5) FX_SN (10)
Aardvark (J7) SS (9) MachXO3D (U3) SN (AB21)
Arduino (J2) AR_SS_IO10 (3) MachXO3D (U3) SN (AB21)
Raspberry Pi (J6) Rasp_IO08 (24) MachXO3D (U3) SN (AB21)
For detailed information on Master SPI and Slave SPI mode configuration, refer to MachXO3D Programming and
Configuration Usage Guide (FPGA-TN-02069).
6.2.2. SPI Flash Access

Onboard SPI Flash memory can be used to store the MachXO3D configuration data in either External or Dual Boot
mode. It can also store customer data in certain applications. The MachXO3D device includes the JTAG to MSPI
pass-through circuit that allows the slave SPI Flash to be erased, programmed, and read with Diamond Programmer.
For detailed information on JTAG to MSPI pass-through for slave SPI Flash access, refer to MachXO3D Programming and
Configuration Usage Guide (FPGA-TN-02069).
26 FPGA-EB-02020-1.0
7. LEDs and Switches

LEDs and switches of the MachXO3D Development Board that can be used in demo and customer designs are described
in this section.
7.1. Four-Position DIP Switch

Four MachXO3D pins are connected to the four switches of SW1, as shown in the circuit design in Figure 7.1. The CTS
side actuated DIP switches are connected to logic level 0 when in the ON position, as shown in Figure 7.2.
VCCIO5
R39 R40 R41 R42
4.7K 4.7K 4.7K 4.7K SW1

DIP_SW1 1 8
DIP_SW2 2 1 8 7
DIP_SW3 3 2 7 6
DIP_SW4 4 3 6 5
4 5
SW-DIP4
Figure 7.1. Four-Position DIP Switch Circuits
Figure 7.2. Four-Position DIP Switch Photograph
One side of each switch is connected to GPIOs within the VCCIO5 bank and pulled up through 4.7 kΩ resistors. The
other side is grounded. The designated pins are connected, as shown in Table 7.1.
Table 7.1. Four-Position DIP Switch Signals
MachXO3D Ball SW1 DIP Switch Logic Level at ON
Signal Name 4.7 kΩ Pull up Resistor
Location Position Position
DIP_SW1 H5 1 R39 0
DIP_SW2 J5 2 R40 0
DIP_SW3 J4 3 R41 0
DIP_SW4 J3 4 R42 0
FPGA-EB-02020-1.0 27
7.2. General Purpose Push Buttons

The MachXO3D Development Board provides four push button switches, SW2, SW3, SW4, and SW5, for demos and
user applications. Pressing these buttons drives a logic level 0 to the corresponding I/O pins.
Table 7.2. Push Button Switch Signals
Signal Name MachXO3D Ball Location Push Button Reference Logic Level at Button Pressed
PB1 D3 SW2 0
PB2 D4 SW3 0
PB3 F6 SW4 0
PB4 G7 SW5 0
SW2, SW3, and SW4 are designed for general-purpose applications. SW5 is designed with additional jumper JP5, as
shown in Figure 7.3. SW5 can be used as PROGRAMN push button when JP5 is set to trigger the configuration process
without power cycle. For detailed information on PROGRAMN, refer to MachXO3D Programming and Configuration
Usage Guide (FPGA-TN-02069).
VCCIO5
R150
4.7K
SW5
PB4 2 JP5 1
PROGRAMN [4]
JUMPER
PB4 C100
0.1uF
Figure 7.3. Push Button SW5 Circuit Design
7.3. General Purpose LEDs

The MachXO3D Development Board provides eight red LEDs that are connected to I/O within Bank 5. The LEDs are
lighted when the output is driven LOW. Table 7.3 lists the red LEDs and their associated pins.
Table 7.3. LED Signals
Red LEDs Signal Name MachXO3D Ball Location Logic Level to Light
D1 XLED0 G1 0
D2 XLED1 H2 0
D3 XLED2 J2 0
D4 XLED3 F4 0
D5 XLED4 H1 0
D6 XLED5 J1 0
D7 XLED6 G3 0
Note: The LEDs are not lined up in sequence, as shown in Figure 7.4.
28 FPGA-EB-02020-1.0
Figure 7.4. Board LEDs
7.4. LVDS Outputs Pins

The MachXO3D Development Board provides nine pairs of unused LVDS outputs pins that are connected to J14 for
possible customer applications. The LVDS test points are detailed in Table 7.4.
Table 7.4. LVDS Test Points
Signal Name MachXO3D Ball Location Test Pin of J14 Comments
LVDS_OUT0_P B1 1
LVDS output pair 0
LVDS_OUT0_N A2 2
LVDS_OUT1_P B2 3
LVDS output pair 1
LVDS_OUT1_N A3 4
LVDS_OUT2_P B3 5
LVDS output pair 2
LVDS_OUT2_N A4 6
LVDS_OUT3_P B4 7
LVDS output pair 3
LVDS_OUT3_N A5 8
LVDS_OUT4_P B5 9
LVDS output pair 4
LVDS_OUT4_N A6 10
LVDS_OUT5_P B6 11
LVDS output pair 5
LVDS_OUT5_N A7 12
LVDS_OUT6_P B8 13
LVDS output pair 6
LVDS_OUT6_N A8 14
LVDS_OUT7_P B9 15
LVDS output pair 7
LVDS_OUT7_N A9 16
LVDS_OUT8_P B11 17
LVDS output pair 8
LVDS_OUT8_N A11 18
GND — 19 For test convenience
For test convenience through
VCCIO0 — 20
R285 (DNI)
FPGA-EB-02020-1.0 29
7.5. General Purpose DDR Outputs

Graphics Double Data Rate (GDDR) signals are wired to the test pads for signal validation.
Table 7.5. GDDR Test Points
Signal Name MachXO3D Ball Location Test Point
GDDR_DQ0 R22 TP93
GDDR_DQ1 R21 TP94
GDDR_DQ2 T22 TP95
GDDR_DQ3 T21 TP96
GDDR_DQ4 Y22 TP97
GDDR_DQ5 W21 TP98
GDDR_DQ6 AA22 TP99
GDDR_DQ7 Y21 TP100
GDDR_DQS N22 TP101
GDDR_DQSN P21 TP102
7.6. Seven-Segment Display

The MachXO3D Development Board features a blue Seven-Segment Display of D20, as shown in Figure 7.5, controlled
by I/O within Bank 5. Each segment LED is lighted blue when the output is driven LOW. Table 7.6 lists the connections
between display LED segments and their associated driver pins.
Figure 7.5. Seven-Segment Display and its Symbol
Table 7.6. Seven-Segment Display Connections

Signal Name D20 Pin Number MachXO3D Ball Location Logic Level to Light
SEG_A 7 G2 0
SEG_B 6 D1 0
SEG_C 4 C1 0
SEG_D 2 D2 0
SEG_E 1 E2 0
SEG_F 9 E3 0
SEG_G 10 E1 0
SEG_DP 5 F1 0
30 FPGA-EB-02020-1.0
8. ASC Connections
8.1. ASC Interface

Important: The MachXO3D + ASC design flow is NOT supported by Diamond 3.11 SP2 or earlier version. Check the
Lattice website (www.latticesemi.com) for the latest news on MachXO3D + ASC design support. The ASC device is
included on this board in anticipation of future support. The information provided below throughout this ASC section is
for reference only.
The MachXO3D Development Board includes a dedicated ASC Interface (ASC-I/F) between the onboard ASC device and
the MachXO3D Bank 4.
Table 8.1. ASC to MachXO3D Connections
MachXO3D Ball ASC Breakout
ASC Connections ASC Pins Description
Location Test Point
I2C_SDA0 K2 14 I2C data programming (user control) TP2
I2C_SCL0 K1 15 I2C clock programming (user control) TP1
ASC_ CLK L1 7 8 MHz clock output from ASC TP14
ASC_RESETb L3 43 ASC device reset (Active Low) TP13
ASC_WRCLK M1 6 ASC-I/F clock signal to ASC TP12
ASC_RDAT N1 5 ASC-I/F data signal from ASC TP11
ASC_WDAT P1 4 ASC-I/F data signal to ASC TP10
I2C Configuration Write Control signal when
Share with TP44
WP[1:0] = 10 in ASC WRITEPROTECT_USERTAG
I2C_WRITE_PROTECT N2 44 for ASC_LED1 if
Register; pull high to enable overwriting by I2C
R99 is installed.
instructions.
8.2. ASC Voltage Monitor

ASC Voltage Monitors (VMONs) are connected to various power sources on the board, as listed in Table 8.2.
Table 8.2. ASC VMON Connections
Power Name ASC Signal Name ASC Pin Number ASC Breakout Test Point
+2.5V** ASC_VMON1 26 TP15
GND* ASC_GS_VMON1 25 TP16
VCC1_8FT** ASC_VMON2 28 TP17
+3.3V_RASP** ASC_VMON3 30 TP18
+3.3V_AR** ASC_VMON4 32 TP21
VBUS_5V** ASC_VMON5 34 TP23
— ASC_VMON6 35 TP24
POT*** ASC_VMON7 36 TP25
— ASC_VMON8 37 TP26
+3.3V_ASC** ASC_VMON9 38 TP27
Notes:
* Connection to GND is through 100 Ω (R109 – R112) so that the test point is not overdriven.
** Connection to the supply is through 270 Ω (R104 – R108, R182) so that the test point is not overdriven.
*** Connection to POT is through 1 kΩ (R277) so that the test point is not overdriven.
FPGA-EB-02020-1.0 31
A 10 kΩ Trimmer Potentiometers (POT1) is used to provide voltage variation from 0 V - 3.3 V to ASC VMON7, as shown
in Figure 8.1.
Figure 8.1. Trimmer Circuit Design for VMON7
Rotate the Trimmer clockwise to decrease the voltage, as shown in Figure 8.2, and to increase the voltage to VMON7,
rotate the POT counter-clockwise.
2 Wiper
Decreasing
CCW 1 3 CW Wiper
Clockwise Voltage
Figure 8.2. Trimmer Wiper Description
The Trimmer wiper can optionally be connected to a GPIO of MachXO3D Bank 0, providing the capability to evaluate
the sysI/O features including LVCMOS25R33, LVCMOS18R33, LVCMOS15R33, LVCMOS12R33, LVCOMS10R33, and
LVCMOS18R25 when VCCIO0=3.3V, as well as VCMOS15R25, LVCMOS12R25 and LVCMOS10R25 when VCCIO0=2.5V.
For the Trimmer wiper voltage settings in detail to supply VREF, see MachXO3D Family Data Sheet (FPGA-DS-02026).
8.3. ASC Current Monitor

One of the ASC Current Monitors (IMONs) is connected to monitor the MachXO3D core current using resistor R181 as a
shunt. The IMON uses the differential voltage across R181 to monitor the current. The ASC has two IMONs: one is used
for lower voltage (–0.3 V to 5.9 V) current monitoring (pins 19 and 20), and the other HIMON (pins 17 and 18) is used
for higher voltage (4.5 V to 13.2 V) current monitoring. Pin 18 is a shared input pin used for both HIMON and HVMON.
Table 8.3. ASC IMON Connections
Power Name ASC Signal Name ASC Pin Number ASC Breakout Test Point Comments
ASC_IMONP 19 TP30 R181 (0.020 Ω) is placed
VCC_CORE between P/N node for
ASC_IMONN 20 TP31 current measurement
ASC_HIMONP 17 TP28 HV IMON positive input
User Connected Dual Function: HV IMON
ASC_HVMON 18 TP29 negative input and
VMON10 input
32 FPGA-EB-02020-1.0
The VCC_CORE current measurement is designed according to Figure 8.3.
[8] ASC_IMONN
[8] ASC_IMONP
VCC_CORE
R269 R270
+3.3V 0 0
R123 1
0.020
+1.2V R181
R127 1 VCC_CORE_P
DNI
Figure 8.3. VCC Core Current Monitoring Circuit
8.4. ASC Temperature Monitor

The ASC has two external Temperature Monitors (TMONs) that both are connected to on-board temperature sensors,
as listed in Table 8.4. One TMON is connected to a PNP transistor, as shown in Figure 8.4. The other TMON is
connected to an NPN transistor, as shown in Figure 8.5. Note that the noise suppression capacitors (C33 and C34)
shown on the schematic are close to the transistors. However, they are physically close to the L-ASC10 (U7).
Table 8.4. ASC TMON Connections
Temperature Sensor (Reference) ASC Signal Name ASC Pin Number ASC Breakout Test Point Comments
TEMP_SENSE1P 21 TP32
Temperature Sensor 1 (Q1) PNP Type
TEMP_SENSE1N 22 TP33
TEMP_SENSE2P 23 TP34
Temperature Sensor 2 (Q2) NPN Type
TEMP_SENSE2N 24 TP35
Figure 8.4. PNP Temperature Sensor Circuit
Figure 8.5. NPN Temperature Sensor Circuit
FPGA-EB-02020-1.0 33
8.5. ASC LEDs

As shown in Figure 8.6, there are nine red LEDs to support ASC applications. They are connected to the ASC GPIOs as
listed in Table 8.5. The LEDs illuminate when the GPIO is driven low.
Figure 8.6. ASC LEDs
Table 8.5. GPIO LED Connections

Signal Name ASC Pin Number LED Breakout Test Point Logic Level to Light
ASC_LED1 44 D9 TP44 0
ASC_LED10 13 D17 TP52 0
Caution: The MachXO3D Development Board contains ESD-sensitive components. ESD safe
practices should be followed while handling and using the development board.
Note: The LEDs are lined up in sequence, as shown in Figure 8.6.
8.6. ASC HVOUT and Trim Pins

The ASC has four high-voltage charge-pump outputs (HVOUTs) and four Trim-DAC outputs (TRIMs), which are brought
out to test pins for user convenience, as listed in Table 8.6. The HVOUTs are designed to drive the gates of MOSFETs to
enable circuits and loads. The TRIMs are designed to drive the trim inputs of DC-DC converters to adjust the output
voltage.
Table 8.6. ASC HVOUT and Trim Connections
Signal Name ASC Pin Number Breakout Test Point
ASC_HVOUT1 2 TP40
ASC_HVOUT2 3 TP41
ASC_HVOUT3 9 TP42
ASC_HVOUT4 10 TP43
ASC_TRIM1 39 TP36
ASC_TRIM2 40 TP37
ASC_TRIM3 41 TP38
ASC_TRIM4 42 TP39
34 FPGA-EB-02020-1.0
9. Software Requirements
The following software are required to develop designs for the MachXO3D Development Board:
 Diamond 3.11 (or later version)
 Diamond Programmer 3.11 (or later version)
 LatticeMico System Development Tools (Optional)
Note: L-ASC device is not supported in Diamond 3.11 SP2 or earlier. Check www.latticesemi.com for the latest news on
MachXO3D + ASC support.
10. Storage and Handling

Static electricity can shorten the life span of electronic components. Observe these tips to prevent damage that can
occur from electrostatic discharge:
 Use antistatic precautions such as operating on an antistatic mat and wearing an antistatic wristband.
 Store the MachXO3D Development Board in the provided packaging.
 Touch a metal USB housing to equalize voltage potential between you and the board.
11. Ordering Information

Table 11.1 Ordering Information
Description Ordering Part Number China RoHS Environment-Friendly Use Period (EFUP)
MachXO3D Development Board LCMXO3D-9400HC-D-EVN
12. Errata
There is one known issue on the MachXO3D Development Board.
Silk ink for the Raspberry Pi J6 Header (1, 2, 39, 40) should be swapped. Figure 12.1 shows the correct order.
2 40
1 39
Figure 12.1. Top view of Raspberry Pi Connector
FPGA-EB-02020-1.0 35
Technical Support Assistance

Submit a technical support case through www.latticesemi.com/techsupport.
36 FPGA-EB-02020-1.0
Appendix A. MachXO3D-9400 Development Board Schematics

5 4 3 2 1
D
MachXO3D-Dev-Brd D
Rev - A
01 - Title page
C
02 - Block diagram C
03 - USB to JTAG I/F

04 - Versa connector (BANK0)
05 - Arduino Header (BANK1)
06 - CrossLink Header (BANK2)
B B
07 - Raspberry Pi (BANK3&4&5)
08 - Analog Sense and Control
09 - POWER DECOUPLING AND LED'S
10 - POWER REGULATORS
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
A A
Phone (503) 268-8001 -or- (800) LATTICE
Title
Title page
Size Project Schematic Rev 1.0
A MachXO3D-Dev-Brd Board Rev A
Date: Friday, May 10, 2019 Sheet 1 o f 10
5 4 3 2 1
Figure A.1. Title Page
FPGA-EB-02020-1.0 37
MachXO3D-9400 Development Board
5 4 3 2 1
D D
C C
B B
A A
Phone (503) 268-8001 -or- (800) LATTICE
Title
Block diagram
B MachXO3D-Dev-Brd Board Rev A
5 4 3 2 1
Figure A.2. Block Diagram
38 FPGA-EB-02020-1.0
5 4 3 2 1
+3.3V
L1 VCCIO0
2 1 FT_VPLL
600ohm 500mA
1
+3.3V C1 C2
4.7uF R1 R2 R3
+3.3V 0.1uF
2
C10 C11 C12 C13 C14
D L2 J1 4.7K 4.7K 4.7K D
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 2 1 FT_VPHY 1
600ohm 500mA 1 2 TDO
2
1
C3 C4 VCC1_8FT +3.3V 3 TDI
4.7uF 3 4
0.1uF 4 5
5
2
6 TMS
6 7
7 8 TCK
8
Header 1x8
VCC1_8FT +3.3V DNI R8
2 1 FT_RSTb U1 2.2K
12
37
64
20
31
42
56
4
9
JP9 FT2232HL
JUMPER
VPLL
VCORE
VCORE
VCORE
VPHY
VCCIO
VCCIO
VCCIO
VCCIO
16 ADBUS0 0 R4 TCK [4,7]
50 ADBUS0 17 ADBUS1 0 R5
VREGIN ADBUS1 TDI [4,7]
18 ADBUS2 0 R6 TDO [4,7]
49 ADBUS2 19 ADBUS3 0 R7
VREGOUT ADBUS3 TMS [4,7]
21
ADBUS4 22
7 ADBUS5 23
C [10] DM DM ADBUS6 +3.3V C
[10] DP 8 24
+3.3V DP ADBUS7
C5 C6 26 ACBUS0 0 DNI R278 USB_I2C_EN I2C_EN_LED_DR
R9 2.2K FT_RSTb 14 ACBUS0 27
+3.3V 10uF 0.1uF RESET# ACBUS1 28 R263 R264
R11 R12 R13 ACBUS2 29 4.7k
ACBUS3 470
R10 12K FT_REF 6 30
REF ACBUS4 32
ACBUS5 33
U2 10K 10K 10K ACBUS6 34 FOR FUTURE RS232 FUNCTION D57
8 1 FT_EECS 63 ACBUS7 Red
7 VCC CS 2 FT_EECLK 62 EECS 38 BDBUS0 0 DNI R14
NU CLK FT_EEDATA EECLK BDBUS0 RS232_Rx_TTL [4]
6 3 61 39 BDBUS1 0 DNI R15
ORG DI EEDATA BDBUS1 RS232_Tx_TTL [4]
5 4 40 BDBUS2 0 DNI R16 RTSn [4]
C7 VSS DO 12K R19 BDBUS2 41 BDBUS3 0 DNI R17
FT_OSCI BDBUS3 CTSn [4]
93LC56C-I/SN 2 43 BDBUS4 0 DNI R18 DTRn [4] Q3
0.1uF OSCI BDBUS4 44 BDBUS5 0 DNI R20 MMBT3904
BDBUS5 DSRn [4]
45 BDBUS6 0 DNI R21
X1 BDBUS6 DCDn [4]
46 BDBUS7 0 DNI R22
FT_OSCO BDBUS7 RI [4]
1 3 3
1 3 OSCO 48
2 4 BCBUS0 52 0 R23 FTDI_SCL 1 TP1
C8 G1 G2 C9 BCBUS1 53 0 R24
13 BCBUS2 54 0 R25 FTDI_SDA 1 TP2
B 18pF 7M-12.000MAAJ 18pF B
TEST BCBUS3 55
BCBUS4 57
BCBUS5 58
FTDI High-Speed USB BCBUS6 59
BCBUS7
[4] 12MHZ
2 1 FT2232H PWREN#
60
JP11
JUMPER
36
SUSPEND#
AGND
[4,5,6,7] SCL0 SCL0 150 R36 [4,5,6,7] SDA0 SDA0 150 R38
GND
GND
GND
GND
GND
GND
GND
GND
+3.3V
+3.3V
10
11
15
25
35
47
51
1
5
+3.3V
C104
C103 10nF
10nF
R262
1k U10 U11
5 5
JP10 VCC VCC
2 1 4 3 J7_SCL 4 3 J7_SDA
A_IN B0_NC J7_SCL [6] A_IN B0_NC J7_SDA [6]
JUMPER FTDI_SCL FTDI_SDA
A 1 1 A
B1_NO B1_NO
USB_I2C_EN 6 6
S_CTRL S_CTRL Email: techsupport@Latticesemi.com
2 2
GND GND Phone (503) 268-8001 -or- (800) LATTICE
R202 Title
10k FSA4157_Analog_Sw FSA4157_Analog_Sw USB to JTAG I/F
B MachXO3D-Dev-Brd
B1 connected to A when S_CTRL is high Board Rev A
5 4 3 2 1
Figure A.3. USB to JTAG I/F
FPGA-EB-02020-1.0 39
5 4 3 2 1
VERSA Connectors
VCCIO0 Pin 2 removed for coding
of expansion board
J8 J9
1 2 HPE_RESOUT# 1 2
R146 DNI EXPCON_2V5 3 4 EXPCON_IO29 EXPCON_IO0 3 4 EXPCON_IO1
0 EXPCON_IO30 5 6 EXPCON_IO31 EXPCON_IO2 5 6 EXPCON_IO3
D EXPCON_IO32 7 8 EXPCON_IO33 EXPCON_IO4 7 8 EXPCON_IO5 D
VBUS_5V EXPCON_IO34 9 10 EXPCON_IO35 EXPCON_IO6 9 10 EXPCON_IO7
EXPCON_IO36 11 12 EXPCON_IO37 EXPCON_IO8 11 12 EXPCON_IO9
EXPCON_IO38 13 14 EXPCON_IO39 EXPCON_IO10 13 14 EXPCON_IO11
EXPCON_IO40 15 16 EXPCON_IO41 EXPCON_IO12 15 16 EXPCON_IO13 VCCIO0
EXPCON_IO42 17 18 EXPCON_IO43 EXPCON_IO14 17 18 EXPCON_IO15 +3.3V
EXPCON_IO44 19 20 EXPCON_IO45 19 20 EXPCON_3V3
R30 DNI 5VIN 21 22 EXPCON_IO16 21 22
0 EXPCON_2V5 23 24 EXPCON_IO17 23 24
25 26 EXPCON_IO18 25 26 R287
VCCIO0 EXPCON_IO19 EXPCON_IO20
27 28 27 28 49.9
EXPCON_OSC 29 30 EXPCON_IO21 29 30 R147
R31 EXPCON_CLKIN 31 32 EXPCON_IO22 31 32 EXPCON_IO23 0
EXPCON_CLKOUT 33 34 EXPCON_IO24 33 34
35 36 EXPCON_IO25 35 36 EXPCON_IO26 DNI
0 37 38 EXPCON_IO27 37 38 CARDSEL#
EXPCON_3V3 EXPCON_IO28
1
39 40 39 40
D58
HDR40 HDR40 Red
R159 DNI EXPCON_OSC

[5] OSC_IN VCCIO0
0
2
R275 DNI EXPCON_IO20
C [7,8] ASC_RESETb C
0
LED_A19 R288 LED_24mA
R33 R34 0
U3C 2K 2K
D12 EXPCON_IO25 LED_B20 R289 DNI
LVDS_OUT0_P B1 PT27A E12 EXPCON_IO29 0
LVDS_OUT0_N A2 PT9A_L_GPLLT PT27B B12 EXPCON_IO13 49.9 R35 SCL0
EXPCON_IO5 PT9B_L_GPLLC PT27C_SCL/PCLKT0_0 EXPCON_IO15 SCL0 [3,5,6,7] VCCIO0
E6 A12 49.9 R37 SDA0 SDA0 [3,5,6,7]
EXPCON_IO3 F7 PT9C PT27D_SDA/PCLKC0_0 G12 EXPCON_IO45
LVDS_OUT1_P B2 PT9D PT28A F12 EXPCON_IO26 C15 C16
LVDS_OUT1_N A3 PT10A PT28B E13 EXPCON_IO41
EXPCON_IO7 C3 PT10B PT28C F13 EXPCON_IO42 150pF 150pF
EXPCON_IO9 C4 PT10C PT28D A13
LVDS_OUT2_P B3 PT10D BANK 0 PT29A B13
RS232_Rx_TTL [3] DNI DNI
R266 R267 R268
LVDS_OUT2_N PT11A PT29B RS232_Tx_TTL [3]
A4 C13 CARDSEL#
EXPCON_IO0 F8 PT11B PT29C D13 EXPCON_IO27
EXPCON_IO1 G8 PT11C PT29D A14 U3D
LVDS_OUT3_P PT11D PT30A RTSn [3]
B4 B14 E8 TDO TDO [3,7] 10K 10K 10K
LVDS_OUT3_N PT12A PT30B EXPCON_IO28 CTSn [3] PT15C_TDO
A5 C14 E9 TDI TDI [3,7]
EXPCON_IO6 D5 PT12B PT30C D14 EXPCON_IO30 PT15D_TDI D10 TCK TP6
EXPCON_IO11 PT12C PT30D PT22C_TCK TCK [3,7]
C5 G14 C10 TMS TMS [3,7]
LVDS_OUT4_P B5 PT12D PT31A F14 PT22D_TMS E14 JTAGENB TP7
LVDS_OUT4_N A6 PT13A PT31B PT31C_JTAGENB E15 PROGRAMN TP8
EXPCON_IO8 D6 PT13B A15 PT31D_PROGRAMN F16 INITN
B DCDn [3] B
EXPCON_IO4 E7 PT13C PT38A B15 PT44C_INITN E17
LVDS_OUT5_P B6 PT13D PT38B C15 EXPCON_IO31 RI [3] BANK 0 PT44D_DONE
DONE
LVDS_OUT5_N A7 PT14A PT38C D15 EXPCON_IO33 R265

EXPCON_IO12 PT14B PT38D PROGRAMN [7]
C6 A16 DTRn [3]
EXPCON_IO14 D7 PT14C PT39A B17 XO3D_9400HC_484CABGA
EXPCON_IO17 PT14D PT39B EXPCON_IO32 DSRn [3]
C8 C17
EXPCON_IO16 D8 PT15A PT39C D16 EXPCON_IO35 10K
LVDS_OUT6_P B8 PT15B PT39D A17
LVDS_OUT6_N A8 PT20A PT40A B18 Bank0_T1
EXPCON_IO20 PT20B PT40B EXPCON_IO40 Bank0_T1 [5]
C9 E16
EXPCON_IO18 D9 PT20C PT40C D17 EXPCON_IO37
PT20D PT40D A18 VREF_BANK0
PT41A VREF_BANK0 [8]
B19
LVDS_OUT7_P B9 PT41B C18 EXPCON_IO34 LVDS OUTPUT layout equal lenth
LVDS_OUT7_N A9 PT21A PT41C D18 EXPCON_IO38 (Swap P and N of LVDS OUT 6/7 for easy layout)
EXPCON_IO2 F9 PT21B PT41D
J14
HPE_RESOUT# G9 PT21C A19 LED_A19 LVDS_OUT0_P 1 2 LVDS_OUT0_N
EXPCON_IO10 F10 PT21D PT42A B20 LED_B20 LVDS_OUT1_P 3 1 2 4 LVDS_OUT1_N
EXPCON_IO19 E10 PT22A PT42B F15 EXPCON_IO43 LVDS_OUT2_P 5 3 4 6 LVDS_OUT2_N
B10 PT22B PT42C G15 EXPCON_IO44 LVDS_OUT3_P 7 5 6 8 LVDS_OUT3_N
[3] 12MHZ EXPCON_CLKIN PT23A_PCLKT0_1 PT42D LVDS_OUT4_P 7 8 LVDS_OUT4_N
A10 9 10
EXPCON_IO21 G11 PT23B_PCLKC0_1 A20 LVDS_OUT5_P 11 9 10 12 LVDS_OUT5_N
EXPCON_IO24 F11 PT23C PT43A_R_GPLLT B21 Bank0_T1 LVDS_OUT6_N 13 11 12 14 LVDS_OUT6_P
A PT23D PT43B_R_GPLLC C19 EXPCON_IO36 LVDS_OUT7_N 15 13 14 16 LVDS_OUT7_P VCCIO0 A
LVDS_OUT8_P B11 PT43C C20 EXPCON_IO39 LVDS_OUT8_P 17 15 16 18 LVDS_OUT8_N
PT24A PT43D 17 18 Lattice Semiconductor Applications
LVDS_OUT8_N A11 19 20 R285 DNI
EXPCON_IO22 PT24B EXPCON_CLKOUT 19 20 Email: techsupport@Latticesemi.com
E11 A21 0
EXPCON_IO23 D11 PT24C PT44A_R_GPLLT B22 Header 2X10 Phone (503) 268-8001 -or- (800) LATTICE
PT24D PT44B_R_GPLLC Title
DNI Versa connector (BANK0)
XO3D_9400HC_484CABGA HS LVDS OUT TEST POINTS Size Project Schematic Rev 1.0
5 4 3 2 1
Figure A.4. VERSA Connector (BANK0)
40 FPGA-EB-02020-1.0
5 4 3 2 1
ARDUINO Connector
U3G
D C21 M22 Bank1_T0 D
C22 PR2A_R_GPLLT_FB PR17A_PCLKT1_0 M21
AR_SCK_IO13 F17 PR2B_R_GPLLC_FB PR17B_PCLKC1_0 M20 J3 J5
[6] AR_SCK_IO13 AR_MISO_IO12 PR2C PR17C AR_IO0 AR_AD5
[6] AR_MISO_IO12 G16 M19 1 6
OSC_IN D22 PR2D PR17D M16 AR_IO1 2 IO0/RXD AR_AD4 5 AD5/SCL
D21 PR3A_R_GPLLT_IN PR18A N16 AR_IO2 3 IO1/TXD AR_AD3 4 AD4/SDA
D19 PR3B_R_GPLLC_IN PR18B N17 AR_IO3 4 IO2 AR_AD2 3 AD3
D20 PR3C PR18C N18 AR_IO4 5 IO3/PWM AR_AD1 2 AD2
E22 PR3D PR18D N22 GDDR_DQS AR_IO5 6 IO4 AR_AD0 1 AD1
E21 PR4A PR19A P21 GDDR_DQSN AR_IO6 7 IO5/PWM AD0
E19 PR4B PR19B N20 AR_IO7 8 IO6/PWM Header 1x6
E20 PR4C PR19C N19 IO7
F22 PR4D BANK 1 PR19D R22 GDDR_DQ0 Header 1x8
G22 PR5A PR20A R21 GDDR_DQ1
F18 PR5B PR20B P22 +3.3V_AR VBUS_5V +12V
F19 PR5C PR20C P20
AR_IO2 G21 PR5D PR20D T22 GDDR_DQ2 J4
AR_IO1 G20 PR6A PR21A T21 GDDR_DQ3 8
AR_IO0 G19 PR6B PR21B P19 AR_AD0 J2 7 VIN
AR_IO4 G18 PR6C PR21C P18 AR_AD1 AR_IO8 1 JP6 JUMPER 6 GND2
H22 PR6D PR21D P17 AR_AD2 AR_IO9 2 IO8 2 1 AR_5V 5 GND1
H21 PR7A PR24A P16 AR_AD3 AR_SS_IO10 3 IO9/PWM 4 5V0
AR_AD5 G17 PR7B PR24B U22 AR_IO9 AR_MOSI_IO11 4 SS/PWM AR_RESET 3 3V3
AR_IO3 H20 PR7C PR24C U21 AR_IO8 AR_MISO_IO12 5 MOSI/PWM 2 RESET
C
H19 PR7D PR24D V22 AR_IO7 AR_SCK_IO13 6 MISO AR_IO14 1 IOREF C
H18 PR10A PR25A W22 AR_IO6 7 SCK N/A

H17 PR10B PR25B R20 AR_AREF 0 DNI R43 8 GND Header 1x8
H16 PR10C PR25C R19 AR_SDA 9 AREF
J16 PR10D PR25D AR_SCL 10 AD4/SDA
J17 PR11A R18 AD5/SCL
J18 PR11B PR26A R17 Header 1x10
J19 PR11C PR26B R16
J21 PR11D PR26C T20
J22 PR12A PR26D T19
J20 PR12B PR27A T18
K20 PR12C PR27B T17 AR_IO14
K19 PR12D PR27C U20 AR_RESET 4 inch trace Bank1_T0 R279 0 TP105
K18 PR13A PR27D Y22 GDDR_DQ4 R280 DNI
K17 PR13B PR28A W21 GDDR_DQ5 4 inch trace R290 DNI TP107 C116
K16 PR13C PR28B U19 AR_SDA 0 DNI R44 R281 DNI 10pF
PR13D PR28C AR_SCL SDA0 [3,4,6,7]
L17 U18 0 DNI R45 SCL0 [3,4,6,7]
8 inch trace TP109 C118
L16 PR14A PR28D AA22 GDDR_DQ6 10pF
L19 PR14B PR29A Y21 GDDR_DQ7 C120
OSC_EN L20 PR14C PR29B U17 AR_AREF TP111 TP112 TP113
PR14D PR29C 10pF
AR_AD4 K22 V19
AR_IO5 L21 PR16A PR29D V18 AR_MOSI_IO11 Bank0_T1
PR16B PR30A AR_SS_IO10 AR_MOSI_IO11 [6] [4] Bank0_T1
L22 W20 AR_SS_IO10 [6]
M17 PR16C PR30B W19 GDDR_DQ0
B TP93 B
PR16D PR30C Y20 4 inch trace Bank0_T1 R282 0
PR30D GDDR_DQ1 TP106
TP94 R283 DNI
4 inch trace R291 DNI TP108 C117
XO3D_9400HC_484CABGA GDDR_DQ2 R284 DNI 10pF
TP95
8 inch trace TP110 C119
GDDR_DQ3 10pF
TP96
C121
GDDR_DQ4 10pF TP116 TP114 TP115
TP97
VCCIO1 GDDR_DQ5
TP98
R145 10K JP4
OSC_EN 2 1 GDDR_DQ6
TP99
JUMPER GDDR_DQ7
TP100
X2
4 1 GDDR_DQS
VDD Standby OSC_IN TP101
2 3 OSC_IN [4]
C97 GND OUT GDDR_DQSN
TP102
1
50ohm trace
0.1uF ASDMB-XX.XXXMHz Bank1_T0
TP103
DNI R144
2.5 x 2.0 mm 4-SMD 0 Bank0_T1
TP104
1 2
A EXT_CLK A
PLACE X2 CLOSE TO U3
J10 Lattice Semiconductor Applications
SMA DNI TEST PADs close to U3
Phone (503) 268-8001 -or- (800) LATTICE
5
Title
Arduino Header (BANK1)
5 4 3 2 1
Figure A.5. Arduino Header (BANK1)
FPGA-EB-02020-1.0 41
5 4 3 2 1
CrossLink Headers
VBUS_5V +3.3V VCC1_8FT VBUS_5V +3.3V VCC1_8FT
+12V
D NOTE : PLACE ALL THE TERMINATION D
R153 R152 R154 +12V R155 R156 R157 LVDS RX TERMINATION RESISTORS RESISTORS ON TOP SIDE AND CLOSE
U4 0 0 0 U5 0 0 0 TO THE U3
DNI DNI DNI DNI DNI DNI
CH0_DCK_P 1 21 CH1_DCK_P 1 21 CH0_DCK_P CH0_DATA3_P CH1_DATA2_P CH2_DATA1_P
CH0_DCK_N 2 CH0_DCK_P PWR_12-0V 22 RESETN CH1_DCK_N 2 CH1_DCK_P PWR_12V 22 RESETN
3 CH0_DCK_N RESETN 23 PWR_5-0V_L 3 CH1_DCK_N RESETN 23 PWR_5-0V_R R49 R50 R51 R52
GND PWR_5-0V GND PWR_5-0V
100 100 100 100
CH0_DATA0_P 4 24 CH0_DATA1_P CH1_DATA0_P 4 24 CH1_DATA1_P
CH0_DATA0_N 5 CH0_DATA0_P CH0_DATA1_P 25 CH0_DATA1_N CH1_DATA0_N 5 CH1_DATA0_P CH1_DATA1_P 25 CH1_DATA1_N CH0_DCK_N CH0_DATA3_N CH1_DATA2_N CH2_DATA1_N
6 CH0_DATA0_N CH0_DATA1_N 26 PWR_3-3V_L 6 CH1_DATA0_N CH1_DATA1_N 26 PWR_3-3V_R
GND PWR_3-3V GND PWR_3-3V DNI DNI DNI DNI
CH0_DATA2_P 7 27 CH0_DATA3_P CH1_DATA2_P 7 27 CH1_DATA3_P CH0_DATA0_P CH1_DCK_P CH1_DATA3_P CH3_DCK_P
RX Connector2
CH0_DATA2_N 8 CH0_DATA2_P CH0_DATA3_P 28 CH0_DATA3_N CH1_DATA2_N 8 CH1_DATA2_P CH1_DATA3_P 28 CH1_DATA3_N
RX Connector1
9 CH0_DATA2_N CH0_DATA3_N 29 PWR_1-8V_L 9 CH1_DATA2_N CH1_DATA3_N 29 PWR_1-8V_R R53 R54 R55 R56
GND PWR_1-8V GND PWR_1-8V
100 100 100 100
FX_SN 10 30 FX_MOSI FX_SN 10 30 FX_MOSI
FX_SCLK 11 SN MOSI 31 FX_MISO FX_SCLK 11 SN MOSI 31 FX_MISO CH0_DATA0_N CH1_DCK_N CH1_DATA3_N CH3_DCK_N
SCLK MISO SCLK MISO
+12V 12 32 +12V 12 32 DNI DNI DNI DNI
SDA2 13 PWR_12V PWR_1-8V 33 SDA2 13 PWR_12_0V PWR_1-8V 33 CH0_DATA1_P CH1_DATA0_P CH2_DCK_P CH3_DATA0_P
SCL2 14 SDA1 GND 34 SCL2 14 SDA1 GND 34
SCL1 GND SCL1 GND R57 R58 R59 R60
15 35 15 35 100 100 100 100
CH2_DATA0_P 16 GND PWR_3-3V 36 CH2_DATA1_P CH3_DATA0_P 16 GND PWR_3-3V 36 CH3_DATA1_P
CH2_DATA0_N 17 CH2_DATA0_P CH2_DATA1_P 37 CH2_DATA1_N CH3_DATA0_N 17 CH3_DATA0_P CH3_DATA1_P 37 CH3_DATA1_N CH0_DATA1_N CH1_DATA0_N CH2_DCK_N CH3_DATA0_N
CH2_DATA0_N CH2_DATA1_N CH3_DATA0_N CH3_DATA1_N
18 38 18 38 DNI DNI DNI DNI
CH2_DCK_P 19 GND PWR_5-0V 39 SDA1 CH3_DCK_P 19 GND PWR_5-0V 39 SDA1 CH0_DATA2_P CH1_DATA1_P CH2_DATA0_P CH3_DATA1_P
CH2_DCK_N 20 CH2_DCK_P SDA 40 SCL1 CH3_DCK_N 20 CH3_DCK_P SDA 40 SCL1
CH2_DCK_N SCL CH3_DCK_N SCL R61 R62 R63 R64
43 45 43 45 100 100 100 100
44 Shield3 Shield5 46 44 Shield3 Shield5 46
Shield4 Shield6 Shield4 Shield6 CH0_DATA2_N CH1_DATA1_N CH2_DATA0_N CH3_DATA1_N
41 42 41 42 +12V VBUS_5V +3.3V VCC1_8FT
Shield1 Shield2 +12V VBUS_5V +3.3V VCC1_8FT Shield1 Shield2 DNI DNI DNI DNI
C Hirose - FX12 - 40 Pos Hirose - FX12 - 40 Pos C20 C21 C22 C23 Note : C
C24 C25 C26 C27 1) Match length within pair as well as other pairs with +/- 5% tolerence
DNI DNI 2)Differential impedance should be 100 Ohms and 50 Ohms as a single ended signals
0.1uF 0.1uF 0.1uF 0.1uF 3)All the power rails should be capable of carrying 1A current
0.1uF 0.1uF 0.1uF 0.1uF
FX_SCLK 0 DNI R271 MCLK

Note : Speed of the bus, < 2.5ps skew for pairs and
FX_MOSI 0 DNI R272 SISPI across the bus, traces should be 100 Ohms
Trace match LVDSI* pins between P and N channels as
FX_MISO well as individual pairs.
0 DNI R273 SPISO
FX_SN 0 DNI R274 CSSPIN
VCCIO2
SPI FLASH
U3B
CH0_DATA1_P AA2
CH0_DATA1_N AB2 PB5A R68 C28
V6 PB5B R65 R66 R69
U6 PB5C 100nF
CSSPIN AA3 PB5D AB12 CH1_DCK_P 10V
RESETN AB3 PB7A_CSSPIN PB29A_PCLKT2_1 AA12 CH1_DCK_N DNI U6
PB7B PB29B_PCLKC2_1
8
Y4 V13 R48 DNI 10K 10K 10K
W5 PB7C PB29C U13
VCC
CH0_DATA0_P AA4 PB7D PB29D AB13 SDA2 0 DNI R71 SISPI 0 R72 SDI 5 2 SDO 0 R73 SPISO
CH0_DATA0_N PB8A PB30A SDA0 [3,4,5,6,7] [7] SISPI SDI SDO SPISO [7]
AB4 AA13
U7 PB8B BANK 2 PB30B Y13
SCL2 0 DNI R70
SCL0 [3,4,5,6,7]
MCLK 0 R74 SCK 6
B PB8C PB30C [7] MCLK SCK B
T8 W13 NOTE : 0 OHM RESISTOR SHUOULD BE PLACED
CH0_DATA2_P AA5 PB8D PB30D T13 NEAR U3 WP# 3 SPI FLASH
CH0_DATA2_N AB5 PB10A PB32A T14 WP
Y5 PB10B PB32B U14 2 JP8 1 1 7
[7] CSSPIN CSSPIN CS#
GND
Y6 PB10C PB32C V14 CS HOLD
CH2_DATA0_P AA6 PB10D PB32D AB14 CH1_DATA1_P JUMPER
CH2_DATA0_N AB6 PB11A PB33A AA14 CH1_DATA1_N
PB11B PB33B
4
W6 Y14 MT25QL128ABA1ESE
V7 PB11C PB33C W14
CH2_DCK_P AA7 PB11D PB33D AB15 CH1_DATA3_P
CH2_DCK_N AB7 PB13A PB35A AA15 CH1_DATA3_N
V8 PB13B PB35B Y15
U8 PB13C PB35C W15
0 DNI R76 MCLK T9 PB13D PB35D AB16 CH1_DATA0_P
[5] AR_SCK_IO13 PB16A_MCLK/CCLK PB38A CH1_DATA0_N
[5] AR_MISO_IO12 0 DNI R77 SPISO U9 AA16 HOLD#
WP# V9 PB16B_SO/SPISO PB38B V15
HOLD# W8 PB16C PB38C U15
CH0_DATA3_P AA8 PB16D PB38D AB17 CH1_DATA2_P
Y8 PB18B PB40B Y17
W9 PB18C PB40C V16
CH2_DATA1_P AA9 PB18D PB40D AB18 CH3_DATA0_P
T10 PB19B PB41B Y18 VCCIO2 AARDVARK
U10 PB19C PB41C W17 Connector VBUS_5V
V10 PB19D PB41D AB19 CH3_DCK_P
W10 PB21A PB43A AA19 CH3_DCK_N J7
Y9 PB21B PB43B T15 R80 J7_SCL 1 2
Y10 PB21C PB43C U16 [3] J7_SCL J7_SDA 3 1 2 4 +5V_I2C 0 DNI R78
PB21D PB43D CH3_DATA1_P [3] J7_SDA 3 4 +5V_SPI
AB20 SPISO 5 6 0 DNI R79
CH0_DCK_P AA10 PB44A AA20 CH3_DATA1_N MCLK 7 5 6 8 SISPI
CH0_DCK_N AB10 PB22A_PCLKT2_0 PB44B Y19 10K SS 9 7 8 10
T11 PB22B_PCLKC2_0 PB44C W18 9 10
U11 PB22C PB44D AB21 SN HEADER 5X2
0 DNI R81 SDA1 AA11 PB22D PB46A_SN AA21 SISPI 0 R82
[3,4,5,6,7] SDA0 PB24A PB46B_SI/SISPI AR_MOSI_IO11 [5]
0 DNI R83 SCL1 AB11 V17
[3,4,5,6,7] SCL0 PB24B PB46C
V11 T16 DNI
Y11 PB24C PB46D
A A
NOTE : 0 OHM RESISTOR SHUOULD BE PLACED Y12 PB24D
NEAR U3 T12 PB27A
U12 PB27B AARDVARK
V12 PB27C
PB27D
XO3D_9400HC_484CABGA CSSPIN R161 DNI 0 SS Lattice Semiconductor Applications

SN R160 0 Phone (503) 268-8001 -or- (800) LATTICE
[7] SN
Title
AR_SS_IO10 R67
CrossLink Header (BANK2)
[5] AR_SS_IO10 DNI 0
C MachXO3D-Dev-Brd Board Rev A
5 4 3 2 1
Figure A.6. CrossLink Header (BANK2)
42 FPGA-EB-02020-1.0
5 4 3 2 1
7-SEGMENT
VCCIO5 D20
5 R190 22 SEG_DP Character Signal Map
VCCIO5
DP
10 R189 22 SEG_G
U3A U3 pin D18 pin Segment
G
D PB1 D3 G2 SEG_A 9 R188 22 SEG_F D
PB2 D4 PL2A PL7A_PCLKT5_0 G1 XLED0 8
E4 5
F
PB3 F6 PL2B PL7B_PCLKC5_0 H4 XLED0 [9] R39 R40 R41 R42 1 R187 22 SEG_E DP
PB4 G7 PL2C PL7C H3
F5 10
E
E4 PL2D PL7D H2 XLED1 2 R186 22 SEG_D G
F5 PL3A_L_GPLLT_FB PL10A H1 XLED4 XLED1 [9] 3
G6 9 F
D
G6 PL3B_L_GPLLC_FB PL10B J7 XLED4 [9] 4.7K 4.7K 4.7K 4.7K 4 R185 22 SEG_C
H7 PL3C PL10C J6 SW1
H7 1 E
C
SEG_C C1 PL3D PL10D H5 DIP_SW1 1 8 6 R184 22 SEG_B
SEG_D D2 PL4A_L_GPLLT_IN PL11A J5 DIP_SW2 2 1 8 7
C1 2 D
B
G5 PL4B_L_GPLLC_IN PL11B J4 DIP_SW3 3 2 7 6 7 R183 22 SEG_A
H6 PL4C PL11C J3 DIP_SW4 4 3 6 5
D2 4 C
A
SEG_B D1 PL4D PL11D J2 4 5
SEG_E E2 PL5A BANK 5 PL12A J1
XLED2
XLED5 XLED2 [9]
SEG_F E3 PL5B PL12B K7 XLED5 [9] SW-DIP4 G5 6 B
XLED3 F4 PL5C PL12C K6
[9] XLED3 SEG_G E1 PL5D PL12D H6 7 A
SEG_DP F1 PL6A
XLED6 G3 PL6B
[9] XLED6 XLED7 G4 PL6C
[9] XLED7 PL6D
0 DNI R86
RASP_IO04
RASP_IO07
T6
T5 PL26D PL30D
T7
V5
RASP_ID_SC
RASP_ID_SD
0
0
DNI R85
DNI R87
SCL0 [3,4,5,6,7] 7-SEGMENT DISPLAY
[6] CSSPIN RASP_IO08 PL26C PL30C RASP_IO16 SDA0 [3,4,5,6,7]
[6] SN 0 DNI R88 T4 W4
C
0 DNI R89 RASP_IO11 T3 PL26B PL30B Y3 RASP_IO21 C
[6] MCLK RASP_IO09 PL26A PL30A RASP_IO20
[6] SPISO 0 DNI R92 R7 Y2
0 DNI R94 RASP_IO10 R6 PL25D PL29D W3 RASP_IO19
[6] SISPI I3C_U1 PL25C PL29C I3C_AA1
U1 AA1
I3C_T2 T2 PL25B PL29B Y1 I3C_Y1
RASP_IO26 P7 PL25A BANK 3 PL29A U5 RASP_IO13 VBUS_5V
RASP_IO25 R5 PL24D PL28D V4 RASP_IO12
RASP_IO24 PL24C PL28C +3.3V_RASP JP7
R4 W2 J6 2 1
RASP_IO23 R3 PL24B PL28B W1 1 2 RASP_5V
RASP_IO22 PL24A PL28A RASP_IO06 RASP_IO02 1 2 JUMPER
P6 U4 3 4
RASP_IO27 P5 PL21D PL27D U3 RASP_IO05 C30 RASP_IO03 5 3 4 6
T1 PL21C PL27C V1 RASP_IO03 0 DNI R96 RASP_IO04 7 5 6 8 RASP_IO14 C29
PL21B PL27B_PCLKC3_0 RASP_IO02 SCL0 [3,4,5,6,7] 7 8 RASP_IO15
R2 U2 0 DNI R84 SDA0 [3,4,5,6,7] 0.1uF 9 10
0 DNI R91 RASP_IO18 N7 PL21A PL27A_PCLKT3_0 RASP_IO17 11 9 10 12 RASP_IO18 0.1uF
[3,4] TMS RASP_IO17 PL20D RASP_IO27 11 12
[3,4] TDI 0 DNI R93 N6 13 14
0 DNI R90 RASP_IO15 N5 PL20C RASP_IO22 15 13 14 16 RASP_IO23
[3,4] TDO RASP_IO14 PL20B 15 16 RASP_IO24
[3,4] TCK 0 DNI R95 P4 17 18
PL20A RASP_IO10 19 17 18 20
L7 M1 ASC_WRCLK RASP_IO09 21 19 20 22 RASP_IO25
K5 PL13A PL17A N1 ASC_RDAT ASC_WRCLK [8] RASP_IO11 23 21 22 24 RASP_IO08
K4 PL13B PL17B M6 ASC_RDAT [8] 25 23 24 26 RASP_IO07
K3 PL13C PL17C M5 RASP_ID_SD 27 25 26 28 RASP_ID_SC
I2C_SDA0 K2 PL13D BANK 4 PL17D N2 I2C_WRITE_PROTECT RASP_IO05 29 27 28 30
[8] I2C_SDA0 I2C_SCL0 K1 PL14A PL18A P1 ASC_WDAT I2C_WRITE_PROTECT [8] RASP_IO06 31 29 30 32 RASP_IO12
B B
[8] I2C_SCL0 L6 PL14B PL18B N3 ASC_WDAT [8] RASP_IO13 33 31 32 34
L5 PL14C PL18C N4 RASP_IO19 35 33 34 36 RASP_IO16
ASC_CLK L1 PL14D PL18D P2 RASP_IO26 37 35 36 38 RASP_IO20
[8] ASC_CLK PL16A_PCLKT4_0 PL19A I2C_SDA0 37 38 RASP_IO21
M2 R1 [3,4,5,6,7] SDA0 0 R97 39 40
ASC_RESETb L3 PL16B_PCLKC4_0 PL19B P3 39 40
[4,8] ASC_RESETb PL16C PL19C I2C_SCL0
L4 M7 [3,4,5,6,7] SCL0 0 R98
PL16D PL19D
Receptacle 20X2
XO3D_9400HC_484CABGA
I3C_AA1 1 TP3
Raspberry PI Connector
NOTE : PLACE SWITCH ON THE TOP SIDE
I3C_Y1 1 TP4
VCCIO5 VCCIO5 VCCIO5 VCCIO5
I3C_U1 1 TP5
R148 I3C_T2 1 TP9

R46 R149 R150
4.7K
4.7K 4.7K 4.7K
TP89 TP90 TP91
SW2 SW3 SW4 SW5
A A
JP5
PB1 PB2 PB3 PB4 2 1 PROGRAMN [4] Lattice Semiconductor Applications
JUMPER Email: techsupport@Latticesemi.com
PB1 C17 PB2 C98 PB3 C99 PB4 C100
Phone (503) 268-8001 -or- (800) LATTICE
0.1uF 0.1uF 0.1uF 0.1uF Title
Raspberry Pi (BANK3&4&5)
5 4 3 2 1
Figure A.7. Raspberry Pi Header and Others (BANK3, BANK4, and BANK5)
FPGA-EB-02020-1.0 43
5 4 3 2 1
Analog Sense and Control ASC1 TEST POINTS
R99 0
ASC_LED1 ASC_WDAT
+3.3V [7] I2C_WRITE_PROTECT ASC_RDAT TP10
ASC_WRCLK TP11
+3.3V_ASC ASC_RESETb TP12
ASC_CLK TP13
JP1 TP14
D +3.3V_ASC 2 1 D
+3.3V_ASC ASC_VMON1
JUMPER ASC_GS_VMON1 TP15
ASC_VMON2 TP16
R100 22
33
ASC_SDA ASC_GS_VMON2 TP17
8
U7 TP19
[7] I2C_SDA0 ASC_VMON3
C31 C32 R102 TP18
VCC
VCC
100nF 100nF 10k ASC_GS_VMON3
ASC_VMON4 TP20
R101 22 14 TP21
ASC_SCL 15 SDA ASC_GS_VMON4
[7] I2C_SCL0 I2C_ADDR SCL ASC_VMON5 TP22
16 TP23
I2C_ADDR 2 ASC_HVOUT1 ASC_VMON6
ASC_WDAT HVOUT1 ASC_HVOUT2 ASC_VMON7 TP24
[7] ASC_WDAT 4 3 TP25
R103 ASC_RDAT 5 WDAT HVOUT2 9 ASC_HVOUT3 ASC_VMON8
[7] ASC_RDAT ASC_WRCLK RDAT HVOUT3 ASC_HVOUT4 ASC_VMON9 TP26
0 [7] ASC_WRCLK 6 10 TP27
ASC_CLK 7 WRCLK HVOUT4
[7] ASC_CLK ASCCLK ASC_LED1 ASC_HIMON
I2C LSB bits set to 000 44 TP28
GPIO1 45 ASC_LED2 ASC_HVMON
ASC_VMON1 GPIO2 ASC_LED3 ASC_IMONP TP29
+1.2V R104 270 26 46 TP30
ASC_GS_VMON1 25 VMON1 GPIO3 47 ASC_LED4 ASC_IMONN
ASC_VMON2 VMON1GS GPIO4 ASC_LED5 TP31
VCC1_8FT R105 270 28 48
ASC_GS_VMON2 VMON2 GPIO5 ASC_LED6 TEMP_SENSE1P
NOTE : PCB trace as a ASC_VMON3
27
VMON2GS GPIO6
1
TEMP_SENSE1N TP32
R106 270 30
signal line not power +3.3V_RASP ASC_GS_VMON3 29 VMON3 11 ASC_LED8 TEMP_SENSE2P TP33
ASC_LED[1:6] [9] TP34
plane. +3.3V_AR R107 270 ASC_VMON4 32 VMON3GS GPIO8 12 ASC_LED9 TEMP_SENSE2N
TP35
C ASC_GS_VMON4 31 VMON4 GPIO9 13 ASC_LED10 C
R182 270 ASC_VMON5 34 VMON4GS GPIO10 ASC_TRIM1

VBUS_5V ASC_VMON6 VMON5 ASC_LED[8:10] [9] ASC_TRIM2 TP36
35 TP37
ASC_VMON7 36 VMON6 39 ASC_TRIM1 ASC_TRIM3
ASC_VMON8 VMON7 TRIM1 ASC_TRIM2 ASC_TRIM4 TP38
37 40 TP39
ASC_VMON9 38 VMON8 TRIM2 41 ASC_TRIM3
ASC_HIMON 17 VMON9 TRIM3 42 ASC_TRIM4 ASC_HVOUT1
ASC_HVMON HIMONP TRIM4 ASC_HVOUT2 TP40
18 TP41
19 HIMONN_HVMON ASC_HVOUT3
[10] ASC_IMONP IMON1P ASC_HVOUT4 TP42
MMBT3906 C33 [10] ASC_IMONN 20 TP43
Temperature Sensor 1 Q1 150pF TEMP_SENSE1P 21 IMON1N 43 ASC_RESETb
TEMP_SENSE1N TMON1P RESETb ASC_RESETb [4,7] ASC_LED1
22 TP44
TEMP_SENSE2P 23 TMON1N ASC_LED2
NOTE: Place Q1 under TEMP_SENSE2N TMON2P ASC_LED3 TP45
24
U8 on another side TMON2N ASC_LED4 TP46
TP47
of PCB. Q2 ASC_LED5
TP48
MMBT3904 C34
GND
150pF ASC_LED6
ASC_LED8 TP49
Temperature Sensor 2
+3.3V_ASC ASC_LED9 TP50
TP51
49
ASC10-SG48 ASC_LED10
TP52
R277
B 1k B
1
POT1 POT1_WIPER ASC_VMON7
2
3314G-1-103E VMON7
3
VREF_BANK0
Through Hole Prototype Area R286
0
DNI
VREF_BANK0 [4]
VBUS_5V
+3.3V_ASC
+3.3V_ASC AG21 AF21 AE21 AD21 AC21 AB21 AA21 R108 270
ASC_VMON9
AG11 AF11 AE11 AD11 AC11 AB11 AA11

AG12 AF12 AE12 AD12 AC12 R109 100
AB12 AA12 ASC_GS_VMON1
AG15 AF15 AE15 AD15 AC15 R110 100
AB15 AA15 ASC_GS_VMON2
A R111 100 A
ASC_GS_VMON3
R112 100
DNI ASC_GS_VMON4 Phone (503) 268-8001 -or- (800) LATTICE
Title
Analog Sense and Control
5 4 3 2 1
Figure A.8. Analog Sense and Control
44 FPGA-EB-02020-1.0
5 4 3 2 1
VCC_CORE
U3E U3F
K10 A1
K11 VCC1
VCC2
GND1
GND2
A22 +3.3V LEDs
K12 B7
K13 VCC3 GND3 B16
L11 VCC4 GND4 C2
L12 VCC5 GND5 C11
M11 VCC6 GND6 E5
M12 VCC7 GND7 E18
D N10 VCC8 GND8 F2 R113 R114 R115 R116 R117 R118 R119 R120 D
N11 VCC9 GND9 F21
VCC10 GND10 1K 1K 1K 1K 1K 1K 1K 1K
N12 H8
N13 VCC11 GND11 H10
VCCIO5 VCC12 VCCIO1 GND12 H13
GND13 H15
F3 F20 GND14 J9
VCCIO5_1 VCCIO1_1 GND15
1
J8 J15 J10
VCCIO4 K8 VCCIO5_2 VCCIO1_2 K15 GND16 J11 D8 D7 D6 D5 D4 D3 D2 D1
VCCIO5_3 VCCIO1_3 L15 GND17 J12
VCCIO1_4 GND18 Red Red Red Red Red Red Red Red
L8 M15 J13
M8 VCCIO4_1 VCCIO1_5 M18 GND19 J14
M3 VCCIO4_2 VCCIO1_6 N15 GND20 K9
VCCIO4_3 VCCIO1_7 GND21
2
P15 K14
VCCIO3 VCCIO1_8 V20 GND22 K21
VCCIO1_9 GND23 L2 LAYOUT LEDs IN A SINGLE ROW
N8 GND24 L9
P8 VCCIO3_1 GND25 L10
VCCIO2 VCCIO3_2 VCCIO0 GND26 [7] XLED7
V3 L13 [7] XLED6
VCCIO3_3 GND27 L14
GND28 [7] XLED5
R9 C7 L18 [7] XLED4
R10 VCCIO2_1 VCCIO0_1 C12 GND29 M4
VCCIO2_2 VCCIO0_2 GND30 [7] XLED3
R11 C16 M9 [7] XLED2
R12 VCCIO2_3 VCCIO0_3 G10 GND31 M10
C VCCIO2_4 VCCIO0_4 GND32 [7] XLED1 C
R13 G13 M13 [7] XLED0
R14 VCCIO2_5 VCCIO0_5 H9 GND33 M14
W7 VCCIO2_6 VCCIO0_6 H11 GND34 N9
VCCIO2_9 VCCIO0_9 GND37 P9
GND38 P10
Note : LEDs above are controlled by XO3L I/O Bank 5.
GND39
GND40
P11 When VCCIO5 is set to a voltage less than 3.3V, observe
P12
XO3D_9400HC_484CABGA GND41 P13 all I/O overdrive requirements. Refer to Lattice TN1280
GND42
VCCIO0 GND43
P14
R8
"MachXO3L sysIO Usage Guide" for more information.
GND44 R15
GND45 V2
GND46 V21 +3.3V
GND47 W12
C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C106 GND48 Y7
GND49 Y16
10uF 0.1uF 0.01uF 0.01uF 0.01uF 0.1uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF GND50 AB1 R165 R167 R169 R171 R173 R175 R177 R179 R121
GND51 AB22 2.2k 2.2k 2.2k 2.2k 2.2k 2.2k 2.2k 2.2k 2.2k
GND52
R166 R168 R170 R172 R174 R176 R178 R180 R122
XO3D_9400HC_484CABGA 2.2k 2.2k 2.2k 2.2k 2.2k 2.2k 2.2k 2.2k 2.2k
B
VCCIO1 B
D9 D10 D11 D12 D13 D14 D15 D16 D17
Red Red Red Red Red Red Red Red Red
C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C107
ASC_LED1 ASC_LED2 ASC_LED3 ASC_LED4 ASC_LED5 ASC_LED6 ASC_LED8 ASC_LED9 ASC_LED10
10uF 0.1uF 0.01uF 0.01uF 0.01uF 0.1uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF
[8] ASC_LED[1:6]
VCCIO2 VCCIO3 [8] ASC_LED[8:10]
C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 C108 C78 C79 C80 C81 C109
10uF 0.1uF 0.01uF 0.01uF 0.01uF 0.1uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 10uF 0.1uF 0.01uF 0.01uF 0.01uF
A VCC_CORE VCCIO4 VCCIO5 A

Phone (503) 268-8001 -or- (800) LATTICE
C65 C66 C67 C68 C69 C70 C71 C72 C73 C74 C75 C76 C77 C105 C82 C83 C84 C85 C110 C113 C111 C114 C112 C115 Title
POWER DECOUPLING AND LED'S
10uF 0.1uF 0.01uF 0.01uF 0.01uF 0.1uF 0.01uF 0.01uF 0.01uF 0.01uF 0.1uF 0.01uF 0.01uF 0.01uF 10uF 0.1uF 0.01uF 0.01uF 0.01uF 10uF 0.1uF 0.01uF 0.01uF 0.01uF
5 4 3 2 1
Figure A.9. Power Decoupling and LEDs
FPGA-EB-02020-1.0 45
5 4 3 2 1
+3.3V VCCIO1
NOTE : Boot from external SPI Flash (U6)
VBUS_5V
requires VCCIO2 set to 3.3V. Use caution
when setting VCCIO2 to any other voltage.
+3.3V VCCIO0 +3.3V VCCIO2
R125 1
C86 [8] ASC_IMONN
1
R124 1 R126 1
0.1uF L3 +1.2V
[8] ASC_IMONP
D 600ohm 500mA VCC_CORE D
+1.2V R129 1 +1.2V R269 R270
+3.3V 0 0
2
DNI
J11 USB_MINI_B DI R128 1 +3.3V_AR R130 1 R123 1
1 VBUS
VCC R163 0 0.020
DNI DNI
2 D- R151 1 +1.2V R181
D- DM [3]
3 D+ DP [3]
D+ DNI
R162 0 R127 1 VCC_CORE_P
4 VBUS_5V TP54 TP55 TP56
NC 5
GND VCCIO0 VCCIO1 VCCIO2 DNI
D19
1
6 SHLD C101
CASE 7 0.01uF 1 6
CASE 8 GND VBUS
CASE 9 R164 100K DM 2 5 DM TP53
CASE NC2 D+
10 DP 3 4 DP VCC_CORE
MH1 NC3 D-
1
11
MH2 +3.3V VCCIO3 +3.3V VCCIO4 +3.3V VCCIO5
ESDR0502N-UDFN6
C C
R132 1 R133 1 R134 1 +3.3V
+3.3V
VBUS_5V
+1.2V +1.2V +1.2V
U8 R136 0 L4 C91 C92 C93 C94
R135 3 2 3.3V_OUT 2 1
IN OUT 4 600ohm 500mA R137 1 R138 1 R139 1 10uF 1uF 0.1uF 0.01uF
TAB
1
1K
D18 C88 C89 C90 DNI
GND DNI DNI
Blue
10uF 22uF 0.1uF +3.3V_RASP
1 NCP1117
TP58 TP59 TP60
2
R158 1
VCCIO4 VCCIO5 +3.3V
1
DNI
TP57
3.3V_IN
VCCIO3
B B
1
TP62 TP81 TP82 TP83 TP84 TP85
J12 J13
GND GND
1
1 1
TP61
+1.2V
1
spread across board, easy access
+1.2V
MH1 MH2 MH3 MH4

U9 R140 0 L5 ThruHole ThruHole ThruHole ThruHole
3 2 1.2V_OUT 1.2V_IN 2 1
Input Output 600ohm 500mA
C96
4 C95
GND
A 10uF Tab R141 A

22uF Lattice Semiconductor Applications
100 MH5 MH6 MH7 MH8
1
TLV1117LV12DCY ThruHole ThruHole ThruHole ThruHole

Phone (503) 268-8001 -or- (800) LATTICE
Title
POWER REGULATORS
5 4 3 2 1
Figure A.10. Power Regulators
46 FPGA-EB-02020-1.0
Appendix B. MachXO3D-9400 Development Board Bill of

Materials
PCB
Item Reference Qty Part Part Number Manufacturer Description Assembly
Footprint
1 AG11,AF11,AE11, 49 T POINT R TP — — — DNI
AD11,AC11,AB11,
AA11,AG12,AF12,
AE12,AD12,AC12,
AB12,AA12,AG13,
AF13,AE13,AD13,
AC13,AB13,AA13,
AG14,AF14,AE14,
AD14,AC14,AB14,
AA14,AG15,AF15,
AE15,AD15,AC15,
AB15,AA15,AG20,
AF20,AE20,AD20,
AC20,AB20,AA20,
AG21,AF21,AE21,
AD21,AC21,AB21,
AA21
2 C1,C3 2 4.7uF C0603 CL10A475KA8NQNC Samsung CAP CER —
4.7UF 6.3V
10% X5R
0603
3 C2,C4,C6,C7,C10,C 28 0.1uF C0402 C1005X5R1E104K05 TDK CAP CER —
11,C12,C13,C14,C 0BC 0.1UF 25V
17,C20,C21,C22,C 10% X5R
23,C24,C25,C26,C 0402
27,C28,C29,C30,C
86,C90,C93,C97,C
98,C99,C100
4 C5,C35,C45,C55,C 11 10uF C0603 LMK107BBJ106MAL Taiyo Yuden CAP CER —
65,C78,C82,C88,C T 10UF 10V
91,C96,C113 20% X5R
0603
5 C8,C9 2 18pF C0402 C0402C180K3GAC7 KEMET CAP CER —
867 18PF 25V
10% NP0
0402
6 C15,C16 2 150pF C0402 — — CAP CER DNI
0.1UF 16V
10% X7R
0402
7 C31,C32 2 100nF C0603 CL10B104KA8NNNC Samsung — —
8 C33,C34 2 150pF C0603 CL10B151KB8NNNC Samsung — —
9 C36,C40,C46,C50, 12 0.1uF C0201 C0603X5R1E104K03 TDK CAP CER —

C56,C60,C66,C70, 0BB 0.1UF 25V
C75,C79,C83,C111 10% X5R
0201
© 2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02020-1.0 47
PCB
Footprint
10 C37,C38,C39,C41, 43 0.01uF C0201 GRM033R61E103KA Murata CAP CER —
C42,C43,C44,C47, 12D 10000PF
C48,C49,C51,C52, 16V 10%
C53,C54,C57,C58, X7R 0201
C59,C61,C62,C63,
C64,C67,C68,C69,
C71,C72,C73,C74,
C76,C77,C80,C81,
C84,C85,C105,
C106,C107,C108,
C109,C110,C112,
C114,C115
11 C89,C95 2 22uF cc0805 C2012X5R1C226K12 TDK CAP CER —
5AC 22UF 16V
10% X5R
0805
12 C92 1 1uF C0402 CGB2A3X5R0J105K0 TDK CAP CER —
33BB 1UF 6.3V
10% X5R
0402
13 C94,C101 2 0.01uF C0402 CL05B103KA5NNNC Samsung CAP CER —
10000PF
16V 5% X7R
0402
14 C103,C104 2 10nF C0603 CL10A103KB8NNNC Samsung - —
15 C116,C117,C118,C 6 10pF C0402 - - CAP CER

119,C120,C121 10PF 25V
10% NP0
0402
16 D1,D2,D3,D4,D5, 19 Red led_0603 LTST-C190KRKT LITE-On INC LED RED —
D6,D7,D8,D9,D10, CLEAR 0603
D11,D12,D13,D14, SMD
D15,D16,D17,D57,
D58
17 D18 1 Blue led_0603 LTST-C190TBKT LITE-On INC LED 468NM —
BLUE CLEAR
0603 SMD
18 D19 1 ESDR0502 UDFN6_040 ESDR0502NMUTBG ON semi TVS DIODE —
N-UDFN6 5.5VWM
6UDFN
19 D20 1 XZFBBA05 LED10-057- XZFBBA05A SunLED DISPLAY —
A 394- LED 0.2"
XZFBBA05A BLUE CA
SMD
20 J1 1 Header hdr_amp_87 22284081 Molex CONN DNI
1x8 220_8_1x8_ HEADER
100 8POS .100
VERT TIN
21 J2 1 Header CONF1X10- — — CONN —
1x10 254P_2612X HEADER
240X850H_T 10POS .100
H VERT TIN
48 FPGA-EB-02020-1.0
PCB
Footprint
22 J3,J4 2 Header CONF1X8- — — CONN —
240X850H_T 8POS .100
H VERT TIN
23 J5 1 Header CONF1X6- — — CONN —
240X850H_T 6POS .100
H VERT TIN
24 J6 1 Receptacl HDR254- PPTC202LFBN-RC Sullins CONN —
e 20X2 2X20_socket HEADER
FEM 40POS
.1" DL TIN
25 J7 1 HEADER HDR254- 30310-6002HB 3M CONN DNI
5X2 2X5_SHROU HEADER
DED 2.54MM
10POS
GOLD
26 J8,J9 2 HDR40 HDR-20x2 — — CON M —
20x2 THT
RM2.54
27 J10 1 SMA bnc5-100- 5-1814832-1 TE CONN SMA DNI
280t Connectivity JACK STR 50
OHM PCB
28 J11 1 USB_MINI usb2-0-rec- UX60-MB-5ST Hirose CONN —

_B 240-0001-9 RECEPT
MINI
USB2.0
5POS
29 J12, J13 2 GND TUR_TH 1573-2 Keystone TERMINAL —
Electronics TURRET
DBL .082"L
30 J14 1 HEADER HDR254- — — CONN DNI

10X2 2X10 HEADER
20POS
.100" STR
31 JP1,JP4,JP5,JP6, 9 JUMPER Header_1x2 — — CONN —
JP7,JP8,JP9,JP10, HEADER
JP11 2POS .100
VERT TIN
32 L1,L2,L3,L4,L5 5 600ohm fb0603 BLM18AG601SN1D Murata FERRITE —
500mA CHIP 600
OHM
500MA
0603
33 POT1 1 3314G-1- sot23- 3314G-1-103E Bourns Inc. TRIMMER —
103E 3314G-1 10K OHM
0.25W SMD
34 Q1 1 MMBT390 MMBT3906 MMBT3906 ON TRANS PNP —
6 Semiconducto 40V 0.2A
r SOT-23
35 Q2,Q3 2 MMBT390 MMBT3904 MMBT3904 ON TRANS NPN —
4 Semiconducto 40V 0.2A
r SOT-23
FPGA-EB-02020-1.0 49
PCB
Footprint
36 R1,R2,R3,R39,R40, 12 4.7k R0603 RC0603FR-074K7L Yageo RES 4.70K —
R41,R42,R46, OHM
R148,R149, 1/10W 1%
R150,R263 0603 SMD
37 R4,R5,R6,R7,R23,R 23 0 R0603 RC0603FR-070RL Yageo RES 0.0 —
24,R25,R31,R72,R OHM
73,R74,R97,R98,R 1/10W
99,R103,R136,R14 JUMP 0603
0,R160,R269,R270 SMD
,R279,R282,R288
38 R8,R9,R121,R122, 20 2.2k R0603 RC0603FR-072K2L Yageo — —
R165,R166,R167,
R168,R169,R170,
R171,R172,R173,
R174,R175,R176,
R177,R178,R179,
R180
39 R10,R19 2 12K R0603 RC0603FR-0712KL Yageo RES 12K —
OHM
1/10W 1%
0603 SMD
40 R11,R12,R13, 14 10K R0603 RC0603FR-0710KL Yageo RES 10K —
R65,R66,R69,R80, OHM
R102,R145,R202,R 1/10W 5%
265,R266,R267,R2 0603
68
41 R14,R15,R16,R17, 60 0 R0603 — — RES 0.0 DNI
R18,R20,R21,R22, OHM
R30,R43,R44,R45, 1/10W
R67,R70,R71,R76, JUMP 0603
R77,R78,R79,R81, SMD
R82,R83,R84,R85,
R86,R87,R88,R89,
R90,R91,R92,R93,
R94,R95,R96,R146
,R147,R152,R153,
R154,R155,R156,R
157,R159,R161,R2
71,R272,R273,R27
4,R275,R278,R280
,R281,R283,R284,
R285,R286,R289,R
290,R291
42 R33,R34 2 2K R0603 RC0603FR-072KL Yageo RES 2.0K —
OHM
1/10W 5%
0603 SMD
43 R35,R37,R287 3 49.9 R0603 RC0603FR-0749R9L Yageo RES 49.9 —
OHM
1/10W 1%
0603 SMD
44 R36,R38 2 150 R0603 RC0603FR-07151RL Yageo RES 150 —
OHM
1/10W 5%
0603 SMD
50 FPGA-EB-02020-1.0
PCB
Footprint
45 R49,R50,R51,R52, 16 100 R0402 — — RES SMD DNI
R53,R54,R55,R56, 100 OHM
R57,R58,R59,R60, 1% 1/16W
R61,R62,R63,R64 0402
46 R48, R68 1 1K R0603 — — — DNI
47 R100,R101,R183,R 10 22 R0603 RC0603FR-0722RL Yageo — —

184,R185,R186,R1
87,R188,R189,R19
0
48 R104,R105,R106, 6 270 R0603 RC0603FR-07270RL Yageo — —
R107,R108,R182
49 R109,R110,R111, 5 100 R0603 RC0603FR-07100RL Yageo — —

R112,R141
50 R113,R114, 11 1k R0603 RC0603FR-071KL Yageo RES 1K —

R115,R116,R117, OHM
R118,R119,R120, 1/10W 1%
R135,R262,R277 0603 SMD
51 R123,R124,R125, 7 1 R0603 RC0603FR-071RL Yageo RES 1.0 —
R126,R132,R133, OHM .25W
R134 5% 0603
SMD
52 R127,R128,R129, 9 1 R0603 RC0603FR-071RL Yageo RES 1.0 DNI
R130,R137,R138, OHM .25W
R139,R151,R158 5% 0603
SMD
53 R144,R162,R163 3 0 R0402 RC0402FR-070RL Yageo — —
54 R164 1 100K R0603 RC0603FR-07100KL Yageo — —
55 R181 1 0.02 SM_R_ RL1206FR-070R02L Yageo — —

1206
56 R264 1 470 R0603 RC0603FR-07470RL Yageo — —
57 SW1 1 SW-DIP4 sw_sp_st_ 195-4MST CTS SWITCH —

cts_195- PIANO DIP
4mst SPST 50MA
24V
58 SW2,SW3,SW4,S 4 Push sw_sp_st_ TL1015AF160QG E-Switch SWITCH —
W5 Button eswitch_ TACTILE
tl1015 SPST-NO
0.05A 12V
FPGA-EB-02020-1.0 51
PCB
Footprint
59 TP1,TP2,TP3,TP4,T 70 T POINT R TP - - Square test DNI
P5,TP6,TP7,TP8,TP point, 40mil
9,TP10,TP11,TP12, inner
TP13,TP14,TP15,T diameter,
P16,TP17,TP18,TP 63mil outer
19,TP20,TP21,TP2 diameter
2,TP23,TP24,TP25,
TP26,TP27,TP28,T
P29,TP30,TP31,TP
32,TP33,TP34,TP3
5,TP36,TP37,TP38,
TP39,TP40,TP41,T
P42,TP43,TP44,TP
45,TP46,TP47,TP4
8,TP49,TP50,TP51,
TP52,TP53,TP54,T
P55,TP56,TP57,TP
58,TP59,TP60,TP6
1,TP62,TP81,TP82,
TP83,TP84,TP85,T
P89,TP90,TP91
60 TP93,TP94,TP95,T 24 T POINT R TPC32
P96,TP97,TP98,TP
99,TP100,TP101,T
P102,TP103,TP10
4,TP105,TP106,TP
107,TP108,TP109,
TP110,TP111,TP11
2,TP113,TP114,TP
115,TP116
61 U1 1 FT2232HL tqfp64_ FT2232HL-TRAY FTDI IC USB HS —
0p5_12p2x1 DUAL
2p2_h1p6 UART/FIFO
64-LQFP
62 U2 1 93LC56C- so8_50_ 93LC56C-I/SN Microchip IC EEPROM —
I/SN 244 2KBIT
3MHZ
8SOIC
63 U3 1 XO3D_94 BGA484-080 XO3D_9400HC_484 Lattice XO3D- —
00HC_484 CABGA HC9400
CABGA device
64 U4,U5 2 Hirose - Hirose-FX12 FX12B-40P-0.4SV Hirose CONN PLUG DNI
FX12 - 40 40POS
Pos 0.4MM
SMD
SHIELD
65 U6 1 MT25QL1 sop8-50-208 MT25QL128ABA1ES Micron IC FLASH —
28ABA1ES E-0SIT 128MBIT
E 133MHZ
8SOW
66 U7 1 ASC10- TQFN_48 L-ASC10-1SG48I Lattice ASC Device —
SG48
67 U8 1 NCP1117 sot223_4p NCP1117ST33T3G ON semi IC REG LDO —

3.3V 1A
SOT223
52 FPGA-EB-02020-1.0
PCB
Footprint
68 U9 1 TLV1117L sot223_4p TLV1117LV12DCY TI IC REG LDO —
V12DCY 1.2V 1A
SOT223-3
69 U10,U11 2 FSA4157_ SOP-6-26 FSA4157P6X Fairchild IC SWITCH —
Analog_ SPDT SC70-
Sw 6
70 X1 1 7M- xtal_4p_ 7M-12.000MAAJ-T TXC CRYSTAL —
12.000MA 7m 12MHZ
AJ 18PF SMD
71 X2 1 ASDMB- x4-2520 ASDMB serial Abracon LLC OSC MEMS DNI
XX.XXXM CMOS SMD
Hz
FPGA-EB-02020-1.0 53
Appendix C. Predefined Preference File Listing

// These names are generated by the Platform Designer tool in Diamond software
// and can be copied into the preference file or entered into the Spreadsheet
// view.
// ASC0 Connections
LOCATE COMP "ASC0_RSTN" SITE "L3" ;
LOCATE COMP "ASC0_CLK" SITE "L1" ;
LOCATE COMP "rdat_0" SITE "N1" ;
LOCATE COMP "wdat_0" SITE "P1" ;
LOCATE COMP "wrclk_0" SITE "M1" ;
54 FPGA-EB-02020-1.0
Appendix D. User Defined Preference File Listing

// These names follow the MachXO3D Development Board schematic but,
// they may be defined by the user. Thus, they can be copied into the
// preference file and edited to match a different naming convention if
// needed or used to fill in the Spreadsheet view.
// XO3D LED Connections

// Note: The following order matches the LED locations on the board
// from top to bottom
LOCATE COMP "XLED3" SITE "F4" ;
LOCATE COMP "XLED7" SITE "G4" ;
LOCATE COMP "XLED1" SITE "H2" ;
LOCATE COMP "XLED4" SITE "H1" ;
LOCATE COMP "XLED2" SITE "J2" ;
LOCATE COMP "XLED5" SITE "J1" ;
// XO3D High Current LED

LOCATE COMP "LED_A19" SITE "A19" ;
LOCATE COMP "LED_B20" SITE "B20" ;
// XO3D DIP Switch Connections

LOCATE COMP "DIP_SW1" SITE "H5" ;
LOCATE COMP "DIP_SW2" SITE "J5" ;
// XO3D SEG LED Connections

LOCATE COMP "SEG_DP" SITE "F1" ;
LOCATE COMP "SEG_G" SITE "E1" ;
LOCATE COMP "SEG_F" SITE "E3" ;
LOCATE COMP "SEG_E" SITE "E2" ;
LOCATE COMP "SEG_D" SITE "D2" ;
LOCATE COMP "SEG_C" SITE "C1" ;
LOCATE COMP "SEG_B" SITE "D1" ;
LOCATE COMP "SEG_A" SITE "G2" ;
// XO3D Push Button Switch Connections

LOCATE COMP "PB1" SITE "D3" ;
LOCATE COMP "PB2" SITE "D4" ;
LOCATE COMP "PB3" SITE "F6" ;
LOCATE COMP "PB4" SITE "G7" ;
// XO3D I3C Connections

LOCATE COMP "I3C_SDA0" SITE "AA1" ;
LOCATE COMP "I3C_SCL0" SITE "Y1" ;
LOCATE COMP "I3C_SDA1" SITE "U1" ;
LOCATE COMP "I3C_SCL1" SITE "T2" ;
// XO3D SPI Flash Connections

LOCATE COMP "CSSPIN" SITE "AA3" ;
LOCATE COMP "MCLK" SITE "T9" ;
LOCATE COMP "SISPI" SITE "AA21" ;
LOCATE COMP "SPISO" SITE "U9" ;
LOCATE COMP "WP#" SITE "V9" ;
LOCATE COMP "HOLD#" SITE "W8" ;
FPGA-EB-02020-1.0 55
// XO3D Slew Rate Test Points

LOCATE COMP "Bank0_T1" SITE "B21" ;
LOCATE COMP "Bank1_T0" SITE "M22" ;
// XO3D ARDUINO Connections

LOCATE COMP "AR_AD0" SITE "P19" ;
LOCATE COMP "AR_AD4" SITE "K22" ;
LOCATE COMP "AR_AD5" SITE "G17" ;
LOCATE COMP "AR_IO0" SITE "G19" ;
LOCATE COMP "AR_IO3" SITE "H20" ;
LOCATE COMP "AR_IO5" SITE "L21" ;
LOCATE COMP "AR_IO6" SITE "W22" ;
LOCATE COMP "AR_IO7" SITE "V22" ;
LOCATE COMP "AR_IO8" SITE "U21" ;
LOCATE COMP "AR_IO9" SITE "U22" ;
LOCATE COMP "AR_SS_IO10" SITE "W20" ;
LOCATE COMP "AR_MOSI_IO11" SITE "V18" ;
LOCATE COMP "AR_MISO_IO12" SITE "G16" ;
LOCATE COMP "AR_SCK_IO13" SITE "F17" ;
LOCATE COMP "AR_IO14" SITE "T17" ;
LOCATE COMP "AR_AREF" SITE "U17" ;
LOCATE COMP "AR_SDA" SITE "U19" ;
LOCATE COMP "AR_SCL" SITE "U18" ;
LOCATE COMP "AR_RESET" SITE "U20" ;
// XO3D Raspberry Pi Connections

LOCATE COMP "RASP_IO02" SITE "U2" ;
LOCATE COMP "RASP_IO03" SITE "V1" ;
LOCATE COMP "RASP_IO04" SITE "T6" ;
LOCATE COMP "RASP_IO09" SITE "R7" ;
LOCATE COMP "RASP_IO12" SITE "V4" ;
LOCATE COMP "RASP_IO14" SITE "P4" ;
LOCATE COMP "RASP_IO15" SITE "N5" ;
LOCATE COMP "RASP_IO16" SITE "W4" ;
LOCATE COMP "RASP_IO19" SITE "W3" ;
LOCATE COMP "RASP_IO20" SITE "Y2" ;
LOCATE COMP "RASP_IO21" SITE "Y3" ;
LOCATE COMP "RASP_IO22" SITE "P6" ;
LOCATE COMP "RASP_ID_SD" SITE "V5" ;
LOCATE COMP "RASP_ID_SC" SITE "T7" ;
56 FPGA-EB-02020-1.0
// XO3D Clock Connections

LOCATE COMP "12MHZ" SITE "B10" ;
LOCATE COMP "OSC_IN" SITE "D22" ;
LOCATE COMP "OSC_EN" SITE "L20" ;
// XO3D VERSA Connections

LOCATE COMP "EXPCON_IO0" SITE "F8" ;
LOCATE COMP "EXPCON_IO1" SITE "G8" ;
LOCATE COMP "EXPCON_IO4" SITE "E7" ;
LOCATE COMP "EXPCON_IO6" SITE "D5" ;
LOCATE COMP "EXPCON_IO7" SITE "C3" ;
LOCATE COMP "EXPCON_IO13" SITE "B2" ;
LOCATE COMP "EXPCON_IO15" SITE "A12" ;
LOCATE COMP "EXPCON_OSC" SITE "D22" ;
LOCATE COMP "EXPCON_CLKIN" SITE "A10" ;
LOCATE COMP "EXPCON_CLKOUT" SITE "A21" ;
LOCATE COMP "CARDSEL#" SITE "C13" ;
LOCATE COMP "HPE_RESOUT#" SITE "G9" ;
FPGA-EB-02020-1.0 57
// XO3D LVDS Test Connections

LOCATE COMP "LVDS_OUT0_P" SITE "B1" ;
LOCATE COMP "LVDS_OUT0_N" SITE "A2" ;
// XO3D GDDR Test Connections

LOCATE COMP "GDDR_DQ0" SITE "R22" ;
LOCATE COMP "GDDR_DQ1" SITE "R21" ;
LOCATE COMP "GDDR_DQ2" SITE "T22" ;
LOCATE COMP "GDDR_DQ3" SITE "T21" ;
LOCATE COMP "GDDR_DQ4" SITE "Y22" ;
LOCATE COMP "GDDR_DQ5" SITE "W21" ;
LOCATE COMP "GDDR_DQ6" SITE "AA22" ;
LOCATE COMP "GDDR_DQ7" SITE "Y21" ;
LOCATE COMP "GDDR_DQS" SITE "N22" ;
LOCATE COMP "GDDR_DQSN" SITE "P21" ;
// XO3D CrossLink Connections

LOCATE COMP "CH0_DCK_P" SITE "AA10" ;
LOCATE COMP "CH0_DCK_N" SITE "AB10" ;
LOCATE COMP "CH0_DATA0_P" SITE "AA4" ;
LOCATE COMP "CH0_DATA0_N" SITE "AB4" ;
LOCATE COMP "CH1_DCK_P" SITE "AB12" ;
LOCATE COMP "CH1_DCK_N" SITE "AA12" ;
LOCATE COMP "CH1_DATA0_P" SITE "AB16" ;
LOCATE COMP "CH1_DATA0_N" SITE "AA16" ;
LOCATE COMP "CH2_DCK_P" SITE "AA7" ;
LOCATE COMP "CH2_DCK_N" SITE "AB7" ;
58 FPGA-EB-02020-1.0
// XO3D CrossLink Connections Continued

LOCATE COMP "CH3_DCK_P" SITE "AB19" ;
LOCATE COMP "CH3_DCK_N" SITE "AA19" ;
LOCATE COMP "SDA1" SITE "AA11" ;
LOCATE COMP "SCL1" SITE "AB11" ;
LOCATE COMP "SDA2" SITE "AB13" ;
LOCATE COMP "SCL2" SITE "AA13" ;
LOCATE COMP "FX_SN" SITE "AA3" ;
LOCATE COMP "FX_SCLK" SITE "T9" ;
LOCATE COMP "FX_MOSI" SITE "AA21" ;
LOCATE COMP "FX_MISO" SITE "U9" ;
LOCATE COMP "RESETN" SITE "AB3" ;
FPGA-EB-02020-1.0 59
References
For more information, refer to the following documents:
 L-ASC10 In-System Programmable Hardware Management Expander Data Sheet (FPGA-DS-02038)
 MachXO3D Programming and Configuration Usage Guide (FPGA-TN-02069)
 Programming Cable User Guide (FPGA-UG-02042)
 MachXO3D Slew Rate Control Demo User Guide (FPGA-UG-02067)
 MachXO3D Dual Boot Demo User Guide (FPGA-UG-02068)
 MachXO3D Hitless I/O and Hitless EBR Demo User Guide (FPGA-UG-02069)
60 FPGA-EB-02020-1.0
Revision History
Revision 1.0, May 2020
Section Change Summary
All Initial release.
FPGA-EB-02020-1.0 61
www.latticesemi.com

FPGA EB 02020 1 0 MachXO3D Development Board

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

FPGA EB 02020 1 0 MachXO3D Development Board

Uploaded by

Copyright:

Available Formats

MachXO3D Development Board

Evaluation Board User Guide

Acronyms in This Document

1.1. MachXO3D Development Board

Figure 1.1. Top View of MachXO3D Development Board

Mini-USB Header (J11)

Arduino Headers FTDI Device Raspberry Pi

Figure 1.2. Bottom View of MachXO3D Development Board

1.3. MachXO3D Device

1.4. L-ASC10 Device

2. Applying Power to the Board

Figure 2.1. Board Power Supply

Table 2.2. MachXO3D Power Rail Options

Figure 3.1. JTAG/I2C Programming Architecture

3.1. JTAG Download Interface

Figure 3.2. JTAG Programming Mode

3.2. I2C Download Interface

Figure 3.3. I2C Programming Mode

3.3. Alternate JTAG Download Interface

3.4. JTAG to MSPI Pass-through Interface

3.5. Other JTAG Configuration Pins

4. MachXO3D Clock Sources

Figure 4.1. Optional Clock Circuit Design

5. Headers and Test Connections

5.1. Versa Headers

5.2. Arduino Board GPIO Headers

Table 5.4. Arduino J3 Pin Connections

Table 5.5. Arduino J4 Pin Connections

5.3. FX12 Headers (DNI)

U4 Pin Number Signal Name MachXO3D Ball Location

U5 Pin Number Signal Name MachXO3D Ball Location

5.4. Aardvark Header (DNI)

Figure 5.1. Aardvark SS Pin Connections

5.5. Raspberry Pi Board GPIO Header

Table 5.10. Raspberry Pi J6 Header Pin Connections

5.6. Dedicated I3C Test Points

5.7. Dedicated Slew Rate Test Circuits

Figure 5.2. Slew Rate Test Circuits

Table 5.12. Slew Rate Test Conditions

6. I2C and SPI Buses

6.1. I2C Topology

FTDI (UI) Aardvark Header (J7)

I2C MUX (U10/U11)

Figure 6.1. I2C Topology

Figure 6.2. I2C MUX Circuits

6.2. SPI Topology

Table 6.3. MachXO3D SPI Connections

6.2.2. SPI Flash Access

7. LEDs and Switches

7.1. Four-Position DIP Switch

R39 R40 R41 R42

4.7K 4.7K 4.7K 4.7K SW1

Figure 7.1. Four-Position DIP Switch Circuits

Figure 7.2. Four-Position DIP Switch Photograph

7.2. General Purpose Push Buttons

Figure 7.3. Push Button SW5 Circuit Design

7.3. General Purpose LEDs

Figure 7.4. Board LEDs

7.4. LVDS Outputs Pins

7.5. General Purpose DDR Outputs

7.6. Seven-Segment Display

Figure 7.5. Seven-Segment Display and its Symbol

Table 7.6. Seven-Segment Display Connections