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Acer 4262 WWW - Lqv77.com-Ilovepdf-Compressed
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1 1
Compal Confidential
2 2
3
2005-11-08 3
REV: 0.3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 1 of 59
A B C D E
A B C D E
Compal Confidential
Thermal Sensor Clock Generator
Model Name : HBL50 Fan Control
page 47
Yonah
F75383M ICS9LPRS325
page 4 page 14
File Name : LA-2921 uPGA-478 Package
page 4,5
1 1
PSB
H_A#(3..31) 533/667MHz H_D#(0..63)
DVI-D Conn. LCD Conn. CRT & TV-out
page 25 page 23 page 24
nVidia G73M/(72M)/72MV
with 64/128/256MB VRAM DMI New Card LAN(GbE) MINI CARD x2 USB conn x4 Bluetooth
BCM5789
page 15,16,17,18,19,20,21,22 Socket page 37 page 34 page 36 page 37 Conn page 42
PCI Express USB port 3, 7 USB port 0, 2 USB port5
PCI BUS USB port 1
2
3.3V 33 MHz Intel ICH7-M 3.3V 48MHz 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 2 of 59
A B C D E
A B C D E
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
B+ AC or battery power rail for power circuit. N/A N/A N/A
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+CPU_CORE Core voltage for CPU ON OFF OFF
+0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.05VS 1.05V switched power rail ON OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF
+1.8V 1.8V power rail for DDR ON ON OFF Board ID / SKU ID Table for AD channel
+1.8VS 1.8V switched power rail ON OFF OFF Vcc 3.3V +/- 5%
+2.5VS 2.5V switched power rail ON OFF OFF Ra/Rc/Re 100K +/- 5%
+3VALW 3.3V always on power rail ON ON ON* Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+3VS 3.3V switched power rail ON OFF OFF 0 0 0 V 0 V 0 V
+5VALW 5V always on power rail ON ON ON* 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+5VS 5V switched power rail ON OFF OFF 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+VSB VSB always on power rail ON ON ON* 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+RTCVCC RTC power ON ON ON 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
5 100K +/- 5% 1.453 V 1.650 V 1.759 V
6 200K +/- 5% 1.935 V 2.200 V 2.341 V
7 NC 2.500 V 3.300 V 3.300 V
2 2
External PCI Devices Board ID PCB Revision BTO Item BOM Structure
Device IDSEL# REQ#/GNT# Interrupts
0 0.1 VGA PM@ + VGA@
CardBus(SD) AD20 2 PIRQA/PIRQB
1 UMA GM@
13 94 AD16 0 PIRQE
2 UMA's DVI 7307@
LAN(10/100) AD17 3 PIRQF
3 LAN(10/100) 4401@
Mini-PCI(WLAN/TV-Tuner) AD18 1 PIRQG/PORQH
4 LAN(GIGA) 5789@
5 MINI CARD1 MINI1@
6 MINI CARD2 MINI2@
7 SATA-to-IDE 3811@
PATA PATA@
SKU ID Table GRAPEVINE GRA@
EC SM Bus1 address EC SM Bus2 address G72MV Only G72@
3
Device Address Device Address
SKU ID SKU G73 Only G73@ 3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 3 of 59
A B C D E
5 4 3 2 1
JP18A H_D#[0..63]
H_D#[0..63] 6
H_A#[3..31] H_A#3 J4 E22 H_D#0
6 H_A#[3..31]
H_A#4
H_A#5
L4
A3#
A4#
YONAH D0#
D1# F24 H_D#1
H_D#2 +3VS
M3 A5# D2# E26
H_A#6 K5 H22 H_D#3 C624
H_A#7 A6# D3# H_D#4 0.1U_0402_16V4Z
M1 A7# D4# F23
D H_A#8 H_D#5 D
N2 A8# D5# G25 1 2
H_A#9 J1 E25 H_D#6
H_A#10 A9# D6# H_D#7
N3 A10# D7# E23
H_A#11 P5 K24 H_D#8
H_A#12 A11# D8# H_D#9
P2 A12# D9# G24
H_A#13 L1 J24 H_D#10 1 U37
H_A#14 A13# D10# H_D#11 C625
P4 A14# D11# J23 1 VDD SCLK 8 EC_SMB_CK2 40
H_A#15 P1 H26 H_D#12
H_A#16 A15# D12# H_D#13 2200P_0402_50V7K THERMDA
R1 A16# D13# F26 2 D+ SDATA 7 EC_SMB_DA2 40
H_A#17 H_D#14 2
Y2 A17# D14# K22
H_A#18 U5 H25 H_D#15 THERMDC 3 6
H_A#19 A18# D15# H_D#16 D- ALERT#
R3 A19# D16# N22
H_A#20 W6 K25 H_D#17 4 5
H_A#21 A20# D17# H_D#18 THERM# GND
U4 A21# D18# P26
H_A#22 Y5 R23 H_D#19
H_A#23 A22# D19# H_D#20 ADM1032ARMZ-2REEL_MSOP8
U2 A23# D20# L25
H_A#24 R4 L22 H_D#21
H_A#25 A24# D21# H_D#22 F75383M_MSOP8
T5 A25# ADDR GROUP DATA GROUP D22# L23
H_A#26 T3 M23 H_D#23
H_A#27 A26# D23# H_D#24
W3 A27# D24# P25
H_A#28 W5 P22 H_D#25
H_A#29 A28# D25# H_D#26
Y4 A29# D26# P23
H_A#30 W2 T24 H_D#27
H_A#31 A30# D27# H_D#28
Y1 A31# D28# R24
L26 H_D#29
H_REQ#[0..4] H_REQ#0 D29# H_D#30
6 H_REQ#[0..4] K3 REQ0# D30# T25
H_REQ#1 H2 N24 H_D#31
H_REQ#2 REQ1# D31# H_D#32
K2 REQ2# D32# AA23
H_REQ#3 J3 AB24 H_D#33
H_REQ#4 REQ3# D33# H_D#34 +1.05VS
L5 REQ4# D34# V24
V26 H_D#35
D35# H_D#36
6 H_ADSTB#0 L2 ADSTB0# D36# W25
C H_D#37 C
6 H_ADSTB#1 V4 ADSTB1# D37# U23
U25 H_D#38
D38# H_D#39 ITP_TDI R15 56_0402_5%
D39# U22 2 1
AB25 H_D#40
D40# H_D#41 ITP_TDO R17 56_0402_5%
D41# W22 2 1
Y23 H_D#42
D42# H_D#43 ITP_TMS R16 56_0402_5%
14 CLK_CPU_BCLK A22 BCLK0 D43# AA26 2 1
A21 HOST CLK Y26 H_D#44
14 CLK_CPU_BCLK# BCLK1 D44#
Y22 H_D#45 H_PROCHOT# R500 2 1 75_0402_5%
D45# H_D#46
D46# AC26
AA24 H_D#47 ITP_BPM#5 R18 2 1 56_0402_5%
D47# H_D#48
6 H_ADS# H1 ADS# D48# AC22
E2 AC23 H_D#49 H_IERR# R501 2 1 56_0402_5%
6 H_BNR# BNR# D49#
G5 AB22 H_D#50
6 H_BPRI# BPRI# D50# H_D#51
6 H_BR0# F1 BR0# D51# AA21
H5 AB21 H_D#52
6 H_DEFER# DEFER# D52# H_D#53
6 H_DRDY# F21 DRDY# D53# AC25
G6 AD20 H_D#54
6 H_HIT# HIT# D54#
E4 CONTROL AE22 H_D#55
6 H_HITM# HITM# D55#
H_IERR# D20 AF23 H_D#56
IERR# D56# H_D#57
6 H_LOCK# H4 LOCK# D57# AD24
H_RESET# B1 AE21 H_D#58
6 H_RESET# RESET# D58# H_D#59
D59# AD21
AE25 H_D#60
H_RS#[0..2] H_RS#0 D60# H_D#61
6 H_RS#[0..2] F3 RS0# D61# AF25
H_RS#1 F4 AF22 H_D#62
H_RS#2 RS1# D62# H_D#63 ITP_TRST# R19 56_0402_5%
G3 RS2# D63# AF26 2 1
6 H_TRDY# G2 TRDY# ITP_TCK R20 2 1 56_0402_5%
DINV0# J26 H_DINV#0 6
M26 TEST1 R513 2 1 @ 1K_0402_5%
DINV1# H_DINV#1 6
PAD ITP_BPM#0 AD4 V23
B T5 BPM0# DINV2# H_DINV#2 6 B
PAD ITP_BPM#1 AD3 AC20 TEST2 R512 2 1 51_0402_5%
T3 BPM1# DINV3# H_DINV#3 6
PAD ITP_BPM#2 AD1
T1 BPM2#
PAD ITP_BPM#3 AC4
T4 BPM3#
DSTBN0# H23 H_DSTBN#0 6
ITP_DBRRESET# C20 M24
28 ITP_DBRESET# DBR# DSTBN1# H_DSTBN#1 6
6 H_DBSY# E1 DBSY# DSTBN2# W24 H_DSTBN#2 6
27 H_DPSLP# B5 DPSLP# DSTBN3# AD23 H_DSTBN#3 6
27,56 H_DPRSTP# E5 DPRSTP# DSTBP0# G22 H_DSTBP#0 6
6 H_DPWR# D24 DPWR# DSTBP1# N25 H_DSTBP#1 6
PAD ITP_BPM#4 AC2 MISC Y25
T2 PRDY# DSTBP2# H_DSTBP#2 6
ITP_BPM#5 AC1 AE24
PREQ# DSTBP3# H_DSTBP#3 6
H_PROCHOT# D21
PROCHOT#
H_PW RGOOD D6
27 H_PWRGOOD PWRGOOD
H_CPUSLP# D7
6 H_CPUSLP# SLP#
ITP_TCK AC5
ITP_TDI TCK
AA6 TDI A20M# A6 H_A20M# 27
ITP_TDO AB3 A5
TDO FERR# H_FERR# 27
TEST1 C26 C4
TEST1 IGNNE# H_IGNNE# 27
TEST2 D25 B3
TEST2 INIT# H_INIT# 27
ITP_TMS AB5 C6
TMS LINT0 H_INTR 27
ITP_TRST# AB6 B4
TRST# LINT1 H_NMI 27
LEGACY CPU
THERMAL
THERMDA A24 D5
THERMDC THERMDA DIODE STPCLK# H_STPCLK# 27
A25 THERMDC SMI# A3 H_SMI# 27
6,27 H_THERMTRIP# C7 THERMTRIP#
FOX_PZ47903-2741-42_YONAH
A A
Layout Note:
THERMDA & THERMDC Trace / Space = 10 / 10 mil
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Yonah (1/2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 4 of 59
5 4 3 2 1
5 4 3 2 1
Layout Note:
Route VCCSENSE and VSSSENSE traces at 27.4Ohms
with 50 mil spacing.
Place PU and PD wihin 1 inch of CPU.
+CPU_CORE
+CPU_CORE JP18B +CPU_CORE JP18C
56 VCCSENSE
R499 1 100_0402_1% VCCSENSE
3 x 330uF(9mOhm/3)
2 AF7 VCCSENSE VSS AB26 AE18 VCC VSS K1
R498 1 2 100_0402_1% VSSSENSE AE7 AA25 1 1 1 AE17 J2
D VSSSENSE VSS VCC VSS D
56 VSSSENSE VSS AD25 AB15 VCC VSS M2
+ C614 + C609 + C621
20mils VSS AE26 AA15 VCC VSS N1
+1.5VS B26 AB23 @ AD15 T1
VCCA VSS 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9 VCC VSS
VSS AC24 AC15 VCC VSS R2
2 2 2
1 1 +1.05VS K6 VCCP VSS AF24 AF15 VCC VSS V2
C628 C626 J6 AE23 AE15 W1
VCCP VSS VCC VSS
M6 VCCP VSS AA22 South Side Secondary AB14 VCC VSS A26
10U_0805_10V4Z 0.01U_0402_16V7K N6 AD22 AA13 D26
2 2
T6
VCCP
VCCP
YONAH VSS
VSS AC21 AD14
VCC
VCC
VSS
VSS C25
R6 VCCP VSS AF21 AC13 VCC VSS F25
K21 AB19 +CPU_CORE AF14 B24
VCCP VSS VCC VSS
J21 VCCP VSS AA19 3 x 330uF(9mOhm/3) AE13 VCC VSS A23
Layout Note: M21 VCCP VSS AD19 AB12 VCC VSS D23
N21 AC19 AA12 E24
Place C14 near Pin B26 T21
VCCP
VCCP
VSS
VSS AF19
1
+ C620 + C608
1
+ C619
1
AD12
VCC
VCC
YONAH VSS
VSS B21
R21 VCCP VSS AE19 AC12 VCC VSS C22
V21 AB16 @ AF12 F22
VCCP VSS VCC VSS
56 CPU_VID4 AE3 VID4 VSS AB11 AE10 VCC POWER, GROUND VSS F16
R511 56 CPU_VID5 AF2 AA11 AE9 E16
1K_0402_1% VID5 VSS 2 2 2 2 2 2 2 2 VCC VSS
56 CPU_VID6 AE2 VID6 VSS AD11 AB7 VCC VSS B13
AC11 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M AA7 A14
C VSS (Place these capacitors on South side,Secondary Layer) VCC VSS C
AF11 AD7 D13
2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Yonah (2/2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 5 of 59
5 4 3 2 1
5 4 3 2 1
945GM(A-3)(QK56)[QS]: SA0000059D0(ABO!)
945PM(A-3)(QK58)[QS]: SA00000KD70(ABO!)
DMI
H_D#10 K7 D9 H_A#13 DMI_ITX_MRX_P3 AG39 G16 CFG9
HD10# HA13# 28 DMI_ITX_MRX_P3 DMIRXP3 CFG9 CFG9 10
H_D#11 J8 J14 H_A#14 E16 CFG10 PAD
HD11# HA14# CFG10 T12
H_D#12 H4 H13 H_A#15 D15 CFG11
HD12# HA15# CFG11 CFG11 10
H_D#13 J3 J15 H_A#16 DMI_MTX_IRX_N0 AE37 G15 CFG12
HD13# HA16# 28 DMI_MTX_IRX_N0 DMITXN0 CFG12 CFG12 10
H_D#14 K11 F14 H_A#17 DMI_MTX_IRX_N1 AF41 K15 CFG13
HD14# HA17# 28 DMI_MTX_IRX_N1 DMITXN1 CFG13 CFG13 10
CFG
H_D#15 G4 D12 H_A#18 DMI_MTX_IRX_N2 AG37 C15 CFG14 PAD
HD15# HA18# 28 DMI_MTX_IRX_N2 DMITXN2 CFG14 T7
H_D#16 T10 A11 H_A#19 DMI_MTX_IRX_N3 AH41 H16 CFG15 PAD
HD16# HA19# 28 DMI_MTX_IRX_N3 DMITXN3 CFG15 T13
H_D#17 W11 C11 H_A#20 G18 CFG16
HD17# HA20# CFG16 CFG16 10
H_D#18 T3 A12 H_A#21 H15 CFG17 PAD
HD18# HA21# CFG17 T9
H_D#19 U7 A13 H_A#22 DMI_MTX_IRX_P0 AC37 J25 CFG18
HD19# HA22# 28 DMI_MTX_IRX_P0 DMITXP0 CFG18 CFG18 10
H_D#20 U9 E13 H_A#23 DMI_MTX_IRX_P1 AE41 K27 CFG19
HD20# HA23# 28 DMI_MTX_IRX_P1 DMITXP1 CFG19 CFG19 10
H_D#21 U11 G13 H_A#24 DMI_MTX_IRX_P2 AF37 J26 CFG20
HD21# HA24# 28 DMI_MTX_IRX_P2 DMITXP2 CFG20 CFG20 10
H_D#22 T11 F12 H_A#25 DMI_MTX_IRX_P3 AG41
HD22# HA25# 28 DMI_MTX_IRX_P3 DMITXP3
H_D#23 W9 B12 H_A#26
H_D#24 HD23# HA26# H_A#27 CLK_MCH_3GPLL
T1 HD24# HA27# B14 G_CLKP AG33 CLK_MCH_3GPLL 14
H_D#25 T8 C12 H_A#28 AY35 AF33 CLK_MCH_3GPLL#
HD25# HA28# 12 DDRA_CLK0 SM_CK0 G_CLKN CLK_MCH_3GPLL# 14
H_D#26 T4 A14 H_A#29 AR1
HD26# HA29# 12 DDRA_CLK1 SM_CK1
H_D#27 W7 C14 H_A#30 AW7 A27 CLK_DREF_96M#
CLK
HD27# HA30# 13 DDRB_CLK0 SM_CK2 D_REF_CLKN CLK_DREF_96M# 14
H_D#28 U5 D14 H_A#31 AW40 A26 CLK_DREF_96M
HD28# HA31# 13 DDRB_CLK1 SM_CK3 D_REF_CLKP CLK_DREF_96M 14
H_D#29 T9
H_D#30 HD29# CLK_DREF_SSC#
W6 HD30# 12 DDRA_CLK0# AW35 SM_CK0# D_REF_SSCLKN C40 CLK_DREF_SSC# 14
H_D#31 T5 AT1 D41 CLK_DREF_SSC
H_D#32 AB7
HD31#
HD32#
HOST HREQ#0 D8 H_REQ#0
H_REQ#[0..4] 4 12
13
DDRA_CLK1#
DDRB_CLK0# AY7
SM_CK1#
SM_CK2#
D_REF_SSCLKP CLK_DREF_SSC 14
H_D#33 AA9 G8 H_REQ#1 AY40 H32 MCH_CLKREQ#
HD33# HREQ#1 13 DDRB_CLK1# SM_CK3# CLK_REQ# MCH_CLKREQ# 14
H_D#34 W4 B8 H_REQ#2
H_D#35 HD34# HREQ#2 H_REQ#3
W3 HD35# HREQ#3 F8 12 DDRA_CKE0 AU20 SM_CKE0
DDR MUXING
H_D#36 Y3 A8 H_REQ#4 AT20
HD36# HREQ#4 12 DDRA_CKE1 SM_CKE1
H_D#37 Y7 BA29 A3
C HD37# 13 DDRB_CKE0 SM_CKE2 NC0 C
H_D#38 W5 AY29 A39
HD38# 13 DDRB_CKE1 SM_CKE3 NC1
H_D#39 Y10 B9 H_ADSTB#0 A4
HD39# HADSTB#0 H_ADSTB#0 4 NC2
H_D#40 AB8 C13 H_ADSTB#1 AW13 A40
HD40# HADSTB#1 H_ADSTB#1 4 12 DDRA_SCS#0 SM_CS0# NC3
H_D#41 W2 AW12 AW1
HD41# 12 DDRA_SCS#1 SM_CS1# NC4
H_D#42 AA4 AG1 CLK_MCH_BCLK# AY21 AW41
HD42# HCLKN CLK_MCH_BCLK# 14 13 DDRB_SCS#0 SM_CS2# NC5
H_D#43 AA7 AG2 CLK_MCH_BCLK AW21 AY1
HD43# HCLKP CLK_MCH_BCLK 14 13 DDRB_SCS#1 SM_CS3# NC6
H_D#44 AA2 BA1
NC
H_D#45 HD44# H_DSTBN#0 M_OCDOCMP0 NC7
AA6 HD45# HDSTBN#0 K4 H_DSTBN#0 4 T17 PAD AL20 SM_OCDCOMP0 NC8 BA2
H_D#46 AA10 T7 H_DSTBN#1 PAD M_OCDOCMP1 AF10 BA3
HD46# HDSTBN#1 H_DSTBN#1 4 T6 SM_OCDCOMP1 NC9
H_D#47 Y8 Y5 H_DSTBN#2 BA39
H_D#48 HD47# HDSTBN#2 H_DSTBN#3 H_DSTBN#2 4 NC10
AA1 HD48# HDSTBN#3 AC4 H_DSTBN#3 4 12 DDRA_ODT0 BA13 SM_ODT0 NC11 BA40
H_D#49 AB4 K3 H_DSTBP#0 BA12 BA41
HD49# HDSTBP#0 H_DSTBP#0 4 12 DDRA_ODT1 SM_ODT1 NC12
H_D#50 AC9 T6 H_DSTBP#1 AY20 C1
HD50# HDSTBP#1 H_DSTBP#1 4 +1.8V 13 DDRB_ODT0 SM_ODT2 NC13
H_D#51 AB11 AA5 H_DSTBP#2 AU21 AY41
HD51# HDSTBP#2 H_DSTBP#2 4 13 DDRB_ODT1 SM_ODT3 NC14
H_D#52 AC11 AC5 H_DSTBP#3 B2
H_D#53 HD52# HDSTBP#3 H_DSTBP#3 4 R47 SMRCOMPN NC15
AB3 HD53# 1 2 80.6_0402_1% AV9 SM_RCOMPN NC16 B41
+1.05VS H_D#54 AC2 R46 1 2 80.6_0402_1% SMRCOMPP AT9 C41
H_D#55 HD54# H_DINV#0 SM_RCOMPP NC17
AD1 HD55# HDINV#0 J7 H_DINV#0 4 NC18 D1
H_D#56 AD9 W8 H_DINV#1 AK1
H_D#57 HD56# HDINV#1 H_DINV#2 H_DINV#1 4 SMVREF SM_VREF0
AC1 HD57# HDINV#2 U3 H_DINV#2 4 AK41 SM_VREF1
H_D#58 AD7 AB10 H_DINV#3 T32
HD58# HDINV#3 H_DINV#3 4 RESERVED1
2
2
54.9_0402_1%
54.9_0402_1%
R532
RESERVED
PM
H_D#62 AD4 E8 H_ADS# PM_EXTTS#1 H26 AG11
HD62# HADS# H_ADS# 4 PM_EXTTS1# RESERVED5
H_D#63 AC8 E7 H_TRDY# 4,27 H_THERMTRIP# H_THERMTRIP# G6 AF11
H_TRDY# 4
1
24.9_0402_1%
SMVREF trace
1
R529
B4 H_RS#0
HRS0# H_RS#1
HRS1# E6 is 20/20.
D6 H_RS#2
HRS2# R127 @ 0_0402_5%
H_RS#[0..2] 4
2
GMCH_PWROK 1 2 VGATE
+1.8V VGATE 14,28,56
CALISTOGA_FCBGA1466~D
PM@ R130 0_0402_5%
1 2 SYS_PWROK
SYS_PWROK 28,43
2
R577
100_0402_1%
Layout Note:
1
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 / SMVREF
H_SWNG1 trace width and spacing is 10/20.
2
0.1U_0402_16V4Z
+3VS
1 R578 R111
+1.05VS +1.05VS 100_0402_1% 10K_0402_5%
C46
PM_EXTTS#0 1 2
+1.05VS
1
2 R100
1
1
221_0603_1%
221_0603_1%
@ 10K_0402_5%
2
100_0402_1%
1 2 PM_EXTTS#1 1 2
28,56 PM_DPRSLPVR
R528
R527
R121 0_0402_5%
R60
A A
2005/09/20
2
H_SWNG0 H_SWNG1
1
H_VREF
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
100_0402_1%
100_0402_1%
0.1U_0402_16V4Z
1 1
1
200_0603_1%
1
R53
R44
C48
R526
C641
C66
2
Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (1/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 6 of 59
5 4 3 2 1
5 4 3 2 1
DDRB_SDQ[0..63]
13 DDRB_SDQ[0..63]
DDRA_SDQ[0..63]
12 DDRA_SDQ[0..63] DDRB_SMA[0..13]
13 DDRB_SMA[0..13]
DDRA_SMA[0..13]
D
12 DDRA_SMA[0..13] D
U40D U40E
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (2/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 7 of 59
5 4 3 2 1
5 4 3 2 1
D D
U40C
H27 D40 PEG_COMP 1 2 +1.5VS_PCIE
25 SDVO_SDAT SDVOCTRL_DATA EXP_COMPI
H28 D38 10mils R138 24.9_0402_1%
25 SDVO_SCLK SDVOCTRL_CLK EXP_COMPO
F34 PCIE_GTX_C_MRX_N0
GMCH_TXOUT0+ EXP_RXN0 PCIE_GTX_C_MRX_N1 PCIE_MTX_C_GRX_N[0..15]
23 GMCH_TXOUT0+ B37 LA_DATA0 EXP_RXN1 G38 PCIE_MTX_C_GRX_N[0..15] 15
GMCH_TXOUT1+ B34 H34 PCIE_GTX_C_MRX_N2
23 GMCH_TXOUT1+ LA_DATA1 EXP_RXN2 PCIE_MTX_C_GRX_P[0..15]
GMCH_TXOUT2+ A36 J38 PCIE_GTX_C_MRX_N3
23 GMCH_TXOUT2+ LA_DATA2 EXP_RXN3 PCIE_MTX_C_GRX_P[0..15] 15
L34 PCIE_GTX_C_MRX_N4
GMCH_TXOUT0- EXP_RXN4 PCIE_GTX_C_MRX_N5 PCIE_GTX_C_MRX_N[0..15]
23 GMCH_TXOUT0- C37 LA_DATA#0 EXP_RXN5 M38 PCIE_GTX_C_MRX_N[0..15] 15
GMCH_TXOUT1- B35 N34 PCIE_GTX_C_MRX_N6
23 GMCH_TXOUT1- LA_DATA#1 EXP_RXN6 PCIE_GTX_C_MRX_P[0..15]
GMCH_TXOUT2- A37 P38 PCIE_GTX_C_MRX_N7
23 GMCH_TXOUT2- LA_DATA#2 EXP_RXN7 PCIE_GTX_C_MRX_P[0..15] 15
R34 PCIE_GTX_C_MRX_N8
GMCH_TZOUT0+ EXP_RXN8 PCIE_GTX_C_MRX_N9
23 GMCH_TZOUT0+ F30 LB_DATA0 EXP_RXN9 T38
GMCH_TZOUT1+ PCIE_GTX_C_MRX_N10
LVDS
23 GMCH_TZOUT1+ D29 LB_DATA1 EXP_RXN10 V34
GMCH_TZOUT2+ F28 W38 PCIE_GTX_C_MRX_N11
23 GMCH_TZOUT2+ LB_DATA2 EXP_RXN11
Y34 PCIE_GTX_C_MRX_N12
GMCH_TZOUT0- EXP_RXN12 PCIE_GTX_C_MRX_N13
23 GMCH_TZOUT0- G30 LB_DATA#0 EXP_RXN13 AA38
GMCH_TZOUT1- D30 AB34 PCIE_GTX_C_MRX_N14
23 GMCH_TZOUT1- LB_DATA#1 EXP_RXN14
GMCH_TZOUT2- F29 AC38 PCIE_GTX_C_MRX_N15
23 GMCH_TZOUT2- LB_DATA#2 EXP_RXN15
GMCH_TXCLK+ A32 D34 PCIE_GTX_C_MRX_P0
23 GMCH_TXCLK+ LA_CLK EXP_RXP0
GMCH_TXCLK- A33 F38 PCIE_GTX_C_MRX_P1
23 GMCH_TXCLK- LA_CLK# EXP_RXP1
GMCH_TZCLK+ E26 G34 PCIE_GTX_C_MRX_P2
23 GMCH_TZCLK+ LB_CLK EXP_RXP2
GMCH_TZCLK- E27 H38 PCIE_GTX_C_MRX_P3
23 GMCH_TZCLK- LB_CLK# EXP_RXP3
J34 PCIE_GTX_C_MRX_P4
PCI-EXPRESS GRAPHICS
R108 GM@ 0_0402_5% EXP_RXP4 PCIE_GTX_C_MRX_P5
D32 LBKLT_CTL EXP_RXP5 L38
C C
15,40 ENBKL 1 2 LBKLT_EN LBKLT_EN J30 LBKLT_EN EXP_RXP6 M34 PCIE_GTX_C_MRX_P6
LCTLA_CLK H30 N38 PCIE_GTX_C_MRX_P7
LCTLB_DATA LCTLA_CLK EXP_RXP7 PCIE_GTX_C_MRX_P8
H29 LCTLB_DATA EXP_RXP8 P34
23 GMCH_LCD_CLK GMCH_LCD_CLK G26 R38 PCIE_GTX_C_MRX_P9
GMCH_LCD_DATA LDDC_CLK EXP_RXP9 PCIE_GTX_C_MRX_P10
23 GMCH_LCD_DATA G25 LDDC_DATA EXP_RXP10 T34
GMCH_ENVDD F32 V38 PCIE_GTX_C_MRX_P11
23 GMCH_ENVDD LVDD_EN EXP_RXP11
LIBG B38 W34 PCIE_GTX_C_MRX_P12
LIBG EXP_RXP12 PCIE_GTX_C_MRX_P13
C35 LVBG EXP_RXP13 Y38
C33 AA34 PCIE_GTX_C_MRX_P14
LVREFH EXP_RXP14 PCIE_GTX_C_MRX_P15
C32 LVREFL EXP_RXP15 AB38
TV
L36 PCIE_MTX_GRX_N4 C733 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N4
EXP_TXN4
1 2 TV_IREF J20 TV_IREF EXP_TXN5 M40 PCIE_MTX_GRX_N5 C708 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N5
R82 4.99K_0402_1% N36 PCIE_MTX_GRX_N6 C732 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N6
EXP_TXN6 PCIE_MTX_GRX_N7 C706 1 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N7
B16 TV_IRTNA EXP_TXN7 P40 2
B18 R36 PCIE_MTX_GRX_N8 C729 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N8
TV_IRTNB EXP_TXN8 PCIE_MTX_GRX_N9 C704 1 PCIE_MTX_C_GRX_N9
B19 TV_IRTNC EXP_TXN9 T40 2 PM@ 0.1U_0402_16V4Z
V36 PCIE_MTX_GRX_N10 C727 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N10
EXP_TXN10 PCIE_MTX_GRX_N11 C702 1
J29 TV_DCONSEL1 EXP_TXN11 W40 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N11
K30 Y36 PCIE_MTX_GRX_N12 C725 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N12
TV_DCONSEL0 EXP_TXN12 PCIE_MTX_GRX_N13 C700 1
EXP_TXN13 AA40 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N13
AB36 PCIE_MTX_GRX_N14 C723 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N14
EXP_TXN14 PCIE_MTX_GRX_N15 C743 1 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N15
EXP_TXN15 AC40 2
GMCH_CRT_CLK C26
24 GMCH_CRT_CLK DDCCLK
CRT
CALISTOGA_FCBGA1466~D
R122 1 2 10K_0402_5% GMCH_LCD_CLK PM@
R104 1 2 10K_0402_5% GMCH_LCD_DATA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (3/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 8 of 59
5 4 3 2 1
5 4 3 2 1
D7 R101
@ RB751V_SOD323 @ 10_0402_5%
+1.05VS 2 1 1 2 +2.5VS
D6 R93
@ RB751V_SOD323 @ 10_0402_5%
+1.5VS 2 1 1 2 +3VS
D +2.5VS D
0.1U_0402_16V4Z
0.1U_0402_16V4Z
(800mA) AB14 B30 +2.5VS
VTT1 VCCTX_LVDS0
W14 VTT2 VCCTX_LVDS1 C30 1 1
V14 A30 +1.5VS_PCIE R580
VTT3 VCCTX_LVDS2 1 1
C683
C196
T14 0_0805_5% + C687 + C690
R14
VTT4
VTT5 VCC3G0 AB41 W=60 mils 2 1 +1.5VS
P14 AJ41 330U_D2E_2.5VM 330U_D2E_2.5VM
VTT6 VCC3G1 2 2 2 2
10U_0805_10V4Z
10U_0805_10V4Z
N14 L41 (1500mA) 1
VTT7 VCC3G2
M14 VTT8 VCC3G3 N41 1 1
L14 R41 C739 +
VTT9 VCC3G4 +2.5VS
C712
C722
AD13 VTT10 VCC3G5 V41
0.1U_0402_16V4Z
AC13 Y41 220U_D2_2VMR15
VTT11 VCC3G6 2 2 2
AB13 VTT12 1
1 AA13 VTT13 VCCA_3GPLL AC33 +1.5VS_3GPLL
C194
Y13 VTT14 VCCA_3GBG G41 +2.5VS
C629 + W13 H41 (2mA) +3VS_TVDACB L7 +3VS +3VS_TVDACA L5 +3VS
VTT15 VSSA_3GBG L8 2 MBK1608301YZF_0603 MBK1608301YZF_0603
V13 VTT16
220U_D2_2VMR15 U13 MBK1608301YZF_0603 2 1 2 1 2005/09/19
2 VTT17
0.022U_0402_16V7K
0.022U_0402_16V7K
T13 VTT18 VCCA_CRTDAC0 E21 (70mA) +2.5VS_CRTDAC 2 1 +2.5VS
0.022U_0402_16V7K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
R13 VTT19 VCCA_CRTDAC1 F21 1
0.1U_0402_16V4Z
N13 VTT20 VSSA_CRTDAC2 G21 1 close pin G41 1 1 1 1
+ C49
M13 VTT21 1 1 2005/09/21
C105
C92
C84
C85
L13 + C887
VTT22
C118
C106
AB12 VTT23 VCCA_DPLLA B26 (50mA) +1.5VS_DPLLA 220U_D2_4VM
2 2 2 2 2
AA12 VTT24 VCCA_DPLLB C39 (50mA) +1.5VS_DPLLB 220U_D2_4VM
2 2 2
Y12 VTT25 VCCA_HPLL AF1 (45mA) +1.5VS_HPLL
C
W12 VTT26 CRTDAC: Route caps within C
V12 VTT27
U12 A38 (10mA) +2.5VS
250mil of Alviso. Route FB
VTT28 VCCA_LVDS
T12 VTT29 VSSA_LVDS B39 within 3" of Calistoga
R12 VTT30
P12 VTT31
N12 AF2 (45mA)
M12
VTT32
VTT33
P O W E R VCCA_MPLL +1.5VS_MPLL +3VS_TVDACC L4 +3VS
+2.5VS
2.2U_0805_10V6K
4.7U_0805_10V4Z
0.022U_0402_16V7K
1 1 P11 (120mA)
VTT36
0.01U_0402_16V7K
C627
C67
0.1U_0402_16V4Z
0.1U_0402_16V4Z
N11 VTT37
M11 VTT38 VCCA_TVDACA0 E19 +3VS_TVDACA 1 1
R10 VTT39 VCCA_TVDACA1 F19
2 2
C93
C107
P10 VTT40 VCCA_TVDACB0 C20 +3VS_TVDACB 1 1
C195
C180
N10 VTT41 VCCA_TVDACB1 D20
2 2
M10 VTT42 VCCA_TVDACC0 E20 +3VS_TVDACC
P9 VTT43 VCCA_TVDACC1 F20
2 2
N9 VTT44
M9 VTT45
R8 VTT46 VCCD_HMPLL0 AH1 (150mA) +1.5VS
P8 VTT47 VCCD_HMPLL1 AH2
N8 VTT48 close pin A38
M8 VTT49
P7 VTT50 VCCD_LVDS0 A28
N7 B28 (20mA)
VTT51 VCCD_LVDS1
M7 C28
R6
P6
VTT52
VTT53
VCCD_LVDS2
D21 (24mA) +1.5VS_TVDAC
+3VS_TVBG R90
0_0603_5%
+3VS
PCI-E/MEM/PSB PLL decoupling
VTT54 VCCD_TVDAC
M6 VTT55 VCCDQ_TVDAC H19 2 1
0.022U_0402_16V7K
MCH_A6 A6 VTT56 +1.5VS_3GPLL +1.5VS +1.5VS_TVDAC +1.5VS
0.47U_0603_16V4Z
0.1U_0402_16V4Z
R5 A23 +3VS R112 R568
VTT57 VCCHV0 (40mA) 0_0603_5% 0_0603_5%
P5 VTT58 VCCHV1 B23 1 1
0.1U_0402_16V4Z
10U_0805_10V4Z
B B
1 N5 VTT59 VCCHV2 B25 2 1 2 1
0.022U_0402_16V7K
C643
C108
C109
0.1U_0402_16V4Z
0.1U_0402_16V4Z
M5 VTT60 1 1
C111
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
P4 VTT61 VCCAUX0 AK31
2 2
C127
C141
C140
C119
C672
M4 VTT63 VCCAUX2 AE31
2 2
C94
C139
R3 VTT64 VCCAUX3 AC31
P3 AL30 @ @
VTT65 VCCAUX4 2 2 2 2 2 2
N3 VTT66 VCCAUX5 AK30
M3 VTT67 VCCAUX6 AJ30
+1.5VS
0.22U_0603_16V7K
0.1U_0402_16V4Z
MCH_D2 D2 AE30
VTT71 VCCAUX10
0.22U_0603_16V7K
2 VTT73 VCCAUX12
C68
0.1U_0402_16V4Z
0.1U_0402_16V4Z
VCCAUX18 AG28
C632
10U_0805_10V4Z
10U_0805_10V4Z
VCCAUX19 AF28
VCCAUX20 AE28 1 1 1 1
2
C637
C638
VCCAUX21 AH22
C636
C631
VCCAUX22 AJ21
AG14 VCCAUX32 VCCAUX23 AH21
2 2 2 2
AF14 VCCAUX33 VCCAUX24 AJ20
AE14 VCCAUX34 VCCAUX25 AH20
Y14 VCCAUX35 VCCAUX26 AH19
AF13 VCCAUX36 VCCAUX27 P19
AE13 VCCAUX37 VCCAUX28 P16
+1.5VS AF12 AH15
A VCCAUX38 VCCAUX29 A
AE12 VCCAUX39 VCCAUX30 P15
AD12 VCCAUX40 VCCAUX31 AH14
CALISTOGA_FCBGA1466~D
PM@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (4/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 9 of 59
5 4 3 2 1
5 4 3 2 1
AD27 VCC_NCTF0 VCCAUX_NCTF0 AG27 AA33 VCC0 VCC_SM0 AU41 011 = 667MT/s FSB
(3500mA) AC27 AF27 W33 AT41 MCH_AT41 CFG[2:0] 001 = 533MT/s FSB
VCC_NCTF1 VCCAUX_NCTF1 VCC1 VCC_SM1 MCH_AM41
AB27 VCC_NCTF2 VCCAUX_NCTF2 AG26 P33 VCC2 VCC_SM2 AM41
AA27 VCC_NCTF3 VCCAUX_NCTF3 AF26 N33 VCC3 VCC_SM3 AU40 0 = DMI x 2
0.47U_0603_16V4Z
0.47U_0603_16V4Z
Y27 VCC_NCTF4 VCCAUX_NCTF4 AG25 L33 VCC4 VCC_SM4 BA34 CFG5 1 = DMI x 4 *(Default)
W27 VCC_NCTF5 VCCAUX_NCTF5 AF25 J33 VCC5 VCC_SM5 AY34
V27 VCC_NCTF6 VCCAUX_NCTF6 AG24 AA32 VCC6 VCC_SM6 AW34 1 1 0 = Reserved
C718
C717
D D
U27 VCC_NCTF7 VCCAUX_NCTF7 AF24 Y32 VCC7 VCC_SM7 AV34 CFG7 1 = Mobile Yonah CPU*(Default)
T27 VCC_NCTF8 VCCAUX_NCTF8 AG23 W32 VCC8 VCC_SM8 AU34
0.22U_0603_16V7K
0.22U_0603_16V7K
0.22U_0603_16V7K
C42
C640
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
U25 VCC_NCTF27 VCCAUX_NCTF27 AA17 U30 VCC27 VCC_SM27 AH28 CFG18 1 = 1.5V
1U_0603_10V4Z
10U_0805_10V4Z
R25 VCC_NCTF29 VCCAUX_NCTF29 V17 R30 VCC29 VCC_SM29 AH27 0 = Normal Operation * (Default)
C75
C86
C121
C129
1 1 1 AD24 VCC_NCTF30 VCCAUX_NCTF30 T17 P30 VCC30 VCC_SM30 BA26 CFG19 1 = DMI Lane Reversal Enable
AC24 VCC_NCTF31 VCCAUX_NCTF31 R17 N30 VCC31 VCC_SM31 AY26
2 2 2 2
C45
C44
C43
AB24 VCC_NCTF32 VCCAUX_NCTF32 AG16 M30 VCC32 P O W E R VCC_SM32 AW26 0 = No SDVO Device Present *
2 2 2
AA24 VCC_NCTF33 VCCAUX_NCTF33 AF16 L30 VCC33 VCC_SM33 AV26 (Default)
Y24 VCC_NCTF34 VCCAUX_NCTF34 AE16 AA29 VCC34 VCC_SM34 AU26 SDVO_CTRLDATA
W24 VCC_NCTF35 VCCAUX_NCTF35 AD16 Y29 VCC35 VCC_SM35 AT26 1 = SDVO Device Present
V24 VCC_NCTF36 VCCAUX_NCTF36 AC16 W29 VCC36 VCC_SM36 AR26
U24 VCC_NCTF37 VCCAUX_NCTF37 AB16 V29 VCC37 VCC_SM37 AJ26
C
T24 VCC_NCTF38 VCCAUX_NCTF38 AA16 U29 VCC38 VCC_SM38 AH26 0 = Only PCIE or SDVO is C
R24 VCC_NCTF39 VCCAUX_NCTF39 Y16 R29 VCC39 VCC_SM39 AJ25 CFG20 operational. *(Default)
AD23 VCC_NCTF40 VCCAUX_NCTF40 W16 P29 VCC40 VCC_SM40 AH25
V23 VCC_NCTF41 VCCAUX_NCTF41 V16 M29 VCC41 VCC_SM41 AJ24 (PCIE/SDVO select) 1 = PCIE/SDVO are operating
U23 U16 L29 AH24
T23
VCC_NCTF42 VCCAUX_NCTF42
T16 AB28
VCC42 VCC_SM42
BA23 simu.
VCC_NCTF43 VCCAUX_NCTF43 VCC43 VCC_SM43
R23 VCC_NCTF44 VCCAUX_NCTF44 R16 AA28 VCC44 VCC_SM44 AJ23
0.47U_0603_16V4Z
1 AD22 VCC_NCTF45 VCCAUX_NCTF45 AG15 Y28 VCC45 VCC_SM45 BA22
V22 VCC_NCTF46 VCCAUX_NCTF46 AF15 V28 VCC46 VCC_SM46 AY22
C41 + U22 AE15 U28 AW22
VCC_NCTF47 VCCAUX_NCTF47 VCC47 VCC_SM47 1
C679
T22 VCC_NCTF48 VCCAUX_NCTF48 AD15 T28 VCC48 VCC_SM48 AV22
220U_D2_2VMR15 R22 AC15 R28 AU22
2 VCC_NCTF49 VCCAUX_NCTF49 VCC49 VCC_SM49
AD21 VCC_NCTF50 VCCAUX_NCTF50 AB15 P28 VCC50 VCC_SM50 AT22
2 R58
V21 VCC_NCTF51 VCCAUX_NCTF51 AA15 N28 VCC51 VCC_SM51 AR22 6 CFG5 1 2 @ 2.2K_0402_5%
U21 VCC_NCTF52 VCCAUX_NCTF52 Y15 M28 VCC52 VCC_SM52 AP22
T21 W15 L28 AK22 R81 1 2 @ 2.2K_0402_5%
VCC_NCTF53 VCCAUX_NCTF53 VCC53 VCC_SM53 6 CFG7
R21 VCC_NCTF54 VCCAUX_NCTF54 V15 P27 VCC54 VCC_SM54 AJ22
AD20 U15 N27 AK21 R67 1 2 @ 2.2K_0402_5%
VCC_NCTF55 VCCAUX_NCTF55 VCC55 VCC_SM55 6 CFG9
V20 VCC_NCTF56 VCCAUX_NCTF56 T15 M27 VCC56 VCC_SM56 AK20 Place near pin BA23
U20 R15 L27 BA19 2005/09/20 R57 1 2 @ 2.2K_0402_5%
VCC_NCTF57 VCCAUX_NCTF57 VCC57 VCC_SM57 6 CFG11
T20 VCC_NCTF58 P26 VCC58 VCC_SM58 AY19
R20 N26 AW19 R59 1 2 @ 2.2K_0402_5%
VCC_NCTF59 VCC59 VCC_SM59 6 CFG12
10U_0805_10V4Z
10U_0805_10V4Z
AD19 VCC_NCTF60 VSS_NCTF0 AE27 L26 VCC60 VCC_SM60 AV19 1
1 V19 AE26 N25 AU19 1 1 R69 1 2 @ 2.2K_0402_5%
VCC_NCTF61 VSS_NCTF1 VCC61 VCC_SM61 + C735 6 CFG13
U19 VCC_NCTF62 VSS_NCTF2 AE25 M25 VCC62 VCC_SM62 AT19
C720
C719
C40 + T19 AE24 L25 AR19 R68 1 2 @ 2.2K_0402_5%
VCC_NCTF63 VSS_NCTF3 VCC63 VCC_SM63 6 CFG16
@ AD18 AE23 P24 AP19 330U_D2E_2.5VM_R9
220U_D2_2VMR15 VCC_NCTF64 VSS_NCTF4 VCC64 VCC_SM64 2 2 2
AC18 VCC_NCTF65 VSS_NCTF5 AE22 N24 VCC65 VCC_SM65 AK19
2
AB18 VCC_NCTF66 VSS_NCTF6 AE21 M24 VCC66 VCC_SM66 AJ19
AA18 VCC_NCTF67 VSS_NCTF7 AE20 AB23 VCC67 VCC_SM67 AJ18
Y18 VCC_NCTF68 VSS_NCTF8 AE19 AA23 VCC68 VCC_SM68 AJ17
W18 VCC_NCTF69 VSS_NCTF9 AE18 Y23 VCC69 VCC_SM69 AH17
V18 VCC_NCTF70 VSS_NCTF10 AC17 P23 VCC70 VCC_SM70 AJ16
B
U18 Y17 N23 AH16 +3VS B
VCC_NCTF71 VSS_NCTF11 VCC71 VCC_SM71
T18 VCC_NCTF72 VSS_NCTF12 U17 M23 VCC72 VCC_SM72 BA15
+1.05VS L23 AY15 R92 1 2 @ 1K_0402_5%
VCC73 VCC_SM73 6 CFG18
0.47U_0603_16V4Z
AC22 VCC74 VCC_SM74 AW15
+1.8V R95
M19 VCC100 AB22 VCC75 VCC_SM75 AV15 6 CFG19 1 2 @ 1K_0402_5%
L19 VCC101 VCC_SM100 AR6 Y22 VCC76 VCC_SM76 AU15 1
C650
N18 AP6 W22 AT15 R118 1 2 @ 1K_0402_5%
VCC102 VCC_SM101 VCC77 VCC_SM77 6 CFG20
M18 VCC103 VCC_SM102 AN6 P22 VCC78 VCC_SM78 AR15
L18 VCC104 VCC_SM103 AL6 N22 VCC79 VCC_SM79 AJ15
2
P17 VCC105 VCC_SM104 AK6 M22 VCC80 VCC_SM80 AJ14
N17 VCC106 VCC_SM105 AJ6 L22 VCC81 VCC_SM81 AJ13
M17 VCC107 VCC_SM106 AV1 MCH_AV1 AC21 VCC82 VCC_SM82 AH13
N16 VCC108 VCC_SM107 AJ1 MCH_AJ1 AA21 VCC83 VCC_SM83 AK12
M16 VCC109 W21 VCC84 VCC_SM84 AJ12
0.47U_0603_16V4Z
0.47U_0603_16V4Z
C634
CALISTOGA_FCBGA1466~D
A A
PM@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (5/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 10 of 59
5 4 3 2 1
5 4 3 2 1
U40I U40J
AC41 VSS0 VSS100 AE34 AN21 VSS200 VSS280 AG10
AA41 VSS1 VSS101 AC34 AL21 VSS201 VSS281 AC10
W41 VSS2 VSS102 C34 AB21 VSS202 VSS282 W10
T41 VSS3 VSS103 AW33 Y21 VSS203 VSS283 U10
P41 VSS4 VSS104 AV33 P21 VSS204 VSS284 BA9
M41 VSS5 VSS105 AR33 K21 VSS205 VSS285 AW9
D D
J41 VSS6 VSS106 AE33 J21 VSS206 VSS286 AR9
F41 VSS7 VSS107 AB33 H21 VSS207 VSS287 AH9
AV40 VSS8 VSS108 Y33 C21 VSS208 VSS288 AB9
AP40 VSS9 VSS109 V33 AW20 VSS209 VSS289 Y9
AN40 VSS10 VSS110 T33 AR20 VSS210 VSS290 R9
AK40 VSS11 VSS111 R33 AM20 VSS211 VSS292 G9
AJ40 VSS12 VSS112 M33 AA20 VSS212 VSS291 E9
AH40 VSS13 VSS113 H33 K20 VSS213 VSS293 A9
AG40 VSS14 VSS114 G33 B20 VSS214 VSS294 AG8
AF40 VSS15 VSS115 F33 A20 VSS215 VSS295 AD8
AE40 VSS16 VSS116 D33 AN19 VSS216 VSS296 AA8
B40 VSS17 VSS117 B33 AC19 VSS217 VSS297 U8
AY39 VSS18 VSS118 AH32 W19 VSS218 VSS298 K8
AW39 VSS19 VSS119 AG32 K19 VSS219 VSS299 C8
AV39 VSS20 VSS120 AF32 G19 VSS220 VSS300 BA7
AR39 VSS21 VSS121 AE32 C19 VSS221 VSS301 AV7
AN39 VSS22 VSS122 AC32 AH18 VSS222 VSS302 AP7
AJ39 VSS23 VSS123 AB32 P18 VSS223 VSS303 AL7
AC39 VSS24 VSS124 G32 H18 VSS224 VSS304 AJ7
AB39 VSS25 VSS125 B32 D18 VSS225 VSS305 AH7
AA39 VSS26 VSS126 AY31 A18 VSS226 VSS306 AF7
Y39 VSS27 VSS127 AV31 AY17 VSS227 VSS307 AC7
W39 VSS28 VSS128 AN31 AR17 VSS228 VSS308 R7
V39 AJ31 AP17 G7
T39
VSS29
VSS30
VSS129
VSS130 AG31 AM17
VSS229
VSS230
P O W E R VSS309
VSS310 D7
R39 VSS31 VSS131 AB31 AK17 VSS231 VSS311 AG6
P39 VSS32 VSS132 Y31 AV16 VSS232 VSS312 AD6
N39 VSS33 VSS133 AB30 AN16 VSS233 VSS313 AB6
M39 E30 AL16 Y6
L39
VSS34
VSS35
P O W E R VSS134
VSS135 AT29 J16
VSS234
VSS235
VSS314
VSS315 U6
J39 VSS36 VSS136 AN29 F16 VSS236 VSS316 N6
H39 VSS37 VSS137 AB29 C16 VSS237 VSS317 K6
C C
G39 VSS38 VSS138 T29 AN15 VSS238 VSS318 H6
F39 VSS39 VSS139 N29 AM15 VSS239 VSS319 B6
D39 VSS40 VSS140 K29 AK15 VSS240 VSS320 AV5
AT38 VSS41 VSS141 G29 N15 VSS241 VSS321 AF5
AM38 VSS42 VSS142 E29 M15 VSS242 VSS322 AD5
AH38 VSS43 VSS143 C29 L15 VSS243 VSS323 AY4
AG38 VSS44 VSS144 B29 B15 VSS244 VSS324 AR4
AF38 VSS45 VSS145 A29 A15 VSS245 VSS325 AP4
AE38 VSS46 VSS146 BA28 BA14 VSS246 VSS326 AL4
C38 VSS47 VSS147 AW28 AT14 VSS247 VSS327 AJ4
AK37 VSS48 VSS148 AU28 AK14 VSS248 VSS328 Y4
AH37 VSS49 VSS149 AP28 AD14 VSS249 VSS329 U4
AB37 VSS50 VSS150 AM28 AA14 VSS250 VSS330 R4
AA37 VSS51 VSS151 AD28 U14 VSS251 VSS331 J4
Y37 VSS52 VSS152 AC28 K14 VSS252 VSS332 F4
W37 VSS53 VSS153 W28 H14 VSS253 VSS333 C4
V37 VSS54 VSS154 J28 E14 VSS254 VSS334 AY3
T37 VSS55 VSS155 E28 AV13 VSS255 VSS335 AW3
R37 VSS56 VSS156 AP27 AR13 VSS256 VSS336 AV3
P37 VSS57 VSS157 AM27 AN13 VSS257 VSS337 AL3
N37 VSS58 VSS158 AK27 AM13 VSS258 VSS338 AH3
M37 VSS59 VSS159 J27 AL13 VSS259 VSS339 AG3
L37 VSS60 VSS160 G27 AG13 VSS260 VSS340 AF3
J37 VSS61 VSS161 F27 P13 VSS261 VSS341 AD3
H37 VSS62 VSS162 C27 F13 VSS262 VSS342 AC3
G37 VSS63 VSS163 B27 D13 VSS265 VSS343 AA3
F37 VSS64 VSS164 AN26 B13 VSS264 VSS344 G3
D37 VSS65 VSS165 M26 AY12 VSS263 VSS345 AT2
AY36 VSS66 VSS166 K26 AC12 VSS266 VSS346 AR2
AW36 VSS67 VSS167 F26 K12 VSS267 VSS347 AP2
AN36 VSS68 VSS168 D26 H12 VSS268 VSS348 AK2
AH36 VSS69 VSS169 AK25 E12 VSS269 VSS349 AJ2
B B
AG36 VSS70 VSS170 P25 AD11 VSS270 VSS350 AD2
AF36 VSS71 VSS171 K25 AA11 VSS271 VSS351 AB2
AE36 VSS72 VSS172 H25 Y11 VSS272 VSS352 Y2
AC36 VSS73 VSS173 E25 J11 VSS273 VSS353 U2
C36 VSS74 VSS174 D25 D11 VSS274 VSS354 T2
B36 VSS75 VSS175 A25 B11 VSS275 VSS355 N2
BA35 VSS76 VSS176 BA24 AV10 VSS276 VSS356 J2
AV35 VSS77 VSS177 AU24 AP10 VSS277 VSS357 H2
AR35 VSS78 VSS178 AL24 AL10 VSS278 VSS358 F2
AH35 VSS79 VSS179 AW23 AJ10 VSS279 VSS359 C2
AB35 VSS80 VSS180 AT23 VSS360 AL1
AA35 VSS81 VSS181 AN23
Y35 AM23 CALISTOGA_FCBGA1466~D
VSS82 VSS182
W35 VSS83 VSS183 AH23 PM@
V35 VSS84 VSS184 AC23
T35 VSS85 VSS185 W23
R35 VSS86 VSS186 K23
P35 VSS87 VSS187 J23
N35 VSS88 VSS188 F23
M35 VSS89 VSS189 C23
L35 VSS90 VSS190 AA22
J35 VSS91 VSS191 K22
H35 VSS92 VSS192 G22
G35 VSS93 VSS193 F22
F35 VSS94 VSS194 E22
D35 VSS95 VSS195 D22
AN34 VSS96 VSS196 A22
AK34 VSS97 VSS197 BA21
AG34 VSS98 VSS198 AV21
AF34 VSS99 VSS199 AR21
CALISTOGA_FCBGA1466~D
A A
PM@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (6/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 11 of 59
5 4 3 2 1
5 4 3 2 1
+1.8V +1.8V
1
DDRA_SDQ4 5 6 DDRA_SDQ0
DDRA_SDQ1 DQ0 DQ5 R153
7 DQ1 VSS 8
9 10 DDRA_SDM0
DDRA_SDQS0# VSS DM0 1K_0402_1%
7 DDRA_SDQS0# 11 DQS0# VSS 12
DDRA_SDQS0 13 14 DDRA_SDQ5 20mils
2
7 DDRA_SDQS0 DQS0 DQ6 DDRA_SDQ7
15 VSS DQ7 16 +DIMM_VREF
DDRA_SDQ2 17 18
DQ2 VSS
1
DDRA_SDQ3 19 20 DDRA_SDQ13 1 1
DQ3 DQ12 DDRA_SDQ12 C281 C294 R156
21 VSS DQ13 22
DDRA_SDQ8 23 24
D DDRA_SDQ14 DQ8 VSS DDRA_SDM1 0.1U_0402_16V4Z 2.2U_0805_10V6K 1K_0402_1% D
25 DQ9 DM1 26
2 2
27 28
2
DDRA_SDQS1# VSS VSS
7 DDRA_SDQS1# 29 DQS1# CK0 30 DDRA_CLK0 6
DDRA_SDQS1 31 32
7 DDRA_SDQS1 DQS1 CK0# DDRA_CLK0# 6
33 VSS VSS 34
DDRA_SDQ9 35 36 DDRA_SDQ11
DDRA_SDQ15 DQ10 DQ14 DDRA_SDQ10
37 DQ11 DQ15 38
39 VSS VSS 40
DDRA_SMA[0..13]
7 DDRA_SMA[0..13]
41 VSS VSS 42
DDRA_SDQ16 43 44 DDRA_SDQ20 DDRA_SDQ[0..63]
DDRA_SDQ17 DQ16 DQ20 DDRA_SDQ21 7 DDRA_SDQ[0..63]
45 DQ17 DQ21 46
47 48 0_0402_5% DDRA_SDM[0..7]
VSS VSS 7 DDRA_SDM[0..7]
DDRA_SDQS2# 49 50 R119 1 2
7 DDRA_SDQS2# DQS2# NC PM_EXTTS#0 6,13 +1.8V
DDRA_SDQS2 51 52 DDRA_SDM2
7 DDRA_SDQS2 DQS2 DM2
53 VSS VSS 54
DDRA_SDQ18 55 56 DDRA_SDQ23
DDRA_SDQ19 DQ18 DQ22 DDRA_SDQ22
57 DQ19 DQ23 58
59 VSS VSS 60 1 1 1 1 1
DDRA_SDQ29 61 62 DDRA_SDQ28 C71 C53 C123 C125 C54
DDRA_SDQ24 DQ24 DQ28 DDRA_SDQ25
63 DQ25 DQ29 64
65 66 2.2U_0805_10V6K 2.2U_0805_10V6K 2.2U_0805_10V6K 2.2U_0805_10V6K 2.2U_0805_10V6K
DDRA_SDM3 VSS VSS DDRA_SDQS3# 2 2 2 2 2
67 DM3 DQS3# 68 DDRA_SDQS3# 7
69 70 DDRA_SDQS3
NC DQS3 DDRA_SDQS3 7
71 VSS VSS 72
DDRA_SDQ26 73 74 DDRA_SDQ31
DDRA_SDQ27 DQ26 DQ30 DDRA_SDQ30
75 DQ27 DQ31 76
77 78 +1.8V
DDRA_CKE0 VSS VSS DDRA_CKE1 +0.9VS
6 DDRA_CKE0 79 CKE0 NC/CKE1 80 DDRA_CKE1 6
81 VDD VDD 82
83 84 DDRA_SBS2# 1 4
C DDRA_SBS2# NC NC/A15 DDRA_CKE0 C
7 DDRA_SBS2# 85 BA2 NC/A14 86 2 3 1 1 1 1
87 88 RP41 56_0404_4P2R_5% C115 C113 C62 C63
DDRA_SMA12 VDD VDD DDRA_SMA11
89 A12 A11 90
DDRA_SMA9 91 92 DDRA_SMA7 DDRA_SMA9 1 4 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRA_SMA8 A9 A7 DDRA_SMA6 DDRA_SMA12 2 2 2 2
93 A8 A6 94 2 3
95 96 RP39 56_0404_4P2R_5%
DDRA_SMA5 VDD VDD DDRA_SMA4
97 A5 A4 98
DDRA_SMA3 99 100 DDRA_SMA2 DDRA_SMA5 1 4
DDRA_SMA1 A3 A2 DDRA_SMA0 DDRA_SMA8
101 A1 A0 102 2 3
103 104 RP37 56_0404_4P2R_5%
DDRA_SMA10 VDD VDD DDRA_SBS1#
105 A10/AP BA1 106 DDRA_SBS1# 7
DDRA_SBS0# 107 108 DDRA_SRAS# DDRA_SMA1 1 4
7 DDRA_SBS0# BA0 RAS# DDRA_SRAS# 7 +0.9VS
DDRA_SWE# 109 110 DDRA_SCS#0 DDRA_SMA3 2 3
7 DDRA_SWE# WE# S0# DDRA_SCS#0 6
111 112 RP35 56_0404_4P2R_5%
DDRA_SCAS# VDD VDD DDRA_ODT0
7 DDRA_SCAS# 113 CAS# ODT0 114 DDRA_ODT0 6
DDRA_SCS#1 115 116 DDRA_SMA13 DDRA_SBS0# 1 4
6 DDRA_SCS#1 NC/S1# NC/A13
117 118 DDRA_SMA10 2 3 1 1 1 1 1
DDRA_ODT1 VDD VDD RP33 56_0404_4P2R_5% C645 C648 C653 C660 C667
6 DDRA_ODT1 119 NC/ODT1 NC 120
121 VSS VSS 122
DDRA_SDQ37 123 124 DDRA_SDQ39 DDRA_SCAS# 1 4 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRA_SDQ36 DQ32 DQ36 DDRA_SDQ38 DDRA_SWE# 2 2 2 2 2
125 DQ33 DQ37 126 2 3
127 128 RP31 56_0404_4P2R_5%
DDRA_SDQS4# VSS VSS DDRA_SDM4
7 DDRA_SDQS4# 129 DQS4# DM4 130
DDRA_SDQS4 131 132 DDRA_ODT1 1 4
7 DDRA_SDQS4 DQS4 VSS DDRA_SDQ34 DDRA_SCS#1
133 VSS DQ38 134 2 3
DDRA_SDQ35 135 136 DDRA_SDQ33 RP29 56_0404_4P2R_5% +0.9VS
DDRA_SDQ32 DQ34 DQ39
137 DQ35 VSS 138
139 140 DDRA_SDQ45
DDRA_SDQ40 VSS DQ44 DDRA_SDQ43
141 DQ40 DQ45 142
DDRA_SDQ44 143 144 DDRA_CKE1 1 4 1 1 1 1 1
DQ41 VSS DDRA_SDQS5# DDRA_SMA11 C671 C678 C104 C69 C76
145 VSS DQS5# 146 DDRA_SDQS5# 7 2 3
DDRA_SDM5 147 148 DDRA_SDQS5 RP12 56_0404_4P2R_5%
B DM5 DQS5 DDRA_SDQS5 7 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z B
149 VSS VSS 150
DDRA_SDQ41 DDRA_SDQ47 DDRA_SMA7 2 2 2 2 2
151 DQ42 DQ46 152 1 4
DDRA_SDQ46 153 154 DDRA_SDQ42 DDRA_SMA6 2 3
DQ43 DQ47 RP10 56_0404_4P2R_5%
155 VSS VSS 156
DDRA_SDQ49 157 158 DDRA_SDQ52
DDRA_SDQ48 DQ48 DQ52 DDRA_SDQ53 DDRA_SMA4
159 DQ49 DQ53 160 1 4
161 162 DDRA_SMA2 2 3 +0.9VS
VSS VSS RP8 56_0404_4P2R_5%
163 NC,TEST CK1 164 DDRA_CLK1 6
165 VSS CK1# 166 DDRA_CLK1# 6
DDRA_SDQS6# 167 168 DDRA_SMA0 1 4
7 DDRA_SDQS6# DDRA_SDQS6 DQS6# VSS DDRA_SDM6 DDRA_SBS1#
7 DDRA_SDQS6 169 DQS6 DM6 170 2 3 1 1 1
171 172 RP6 56_0404_4P2R_5% C80 C88 C95
DDRA_SDQ54 VSS VSS DDRA_SDQ51
173 DQ50 DQ54 174
DDRA_SDQ50 175 176 DDRA_SDQ55 DDRA_SRAS# 1 4 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DQ51 DQ55 DDRA_SCS#0 2 2 2
177 VSS VSS 178 2 3
DDRA_SDQ60 179 180 DDRA_SDQ57 RP4 56_0404_4P2R_5%
DDRA_SDQ61 DQ56 DQ60 DDRA_SDQ56
181 DQ57 DQ61 182
183 184 DDRA_ODT0 1 4
DDRA_SDM7 VSS VSS DDRA_SDQS7# DDRA_SMA13
185 DM7 DQS7# 186 DDRA_SDQS7# 7 2 3
187 188 DDRA_SDQS7 RP2 56_0404_4P2R_5%
DDRA_SDQ59 VSS DQS7 DDRA_SDQS7 7
189 DQ58 VSS 190
DDRA_SDQ58 191 192 DDRA_SDQ62
DQ59 DQ62 DDRA_SDQ63
193 VSS DQ63 194
D_CK_SDATA 195 196
13,14 D_CK_SDATA SDA VSS
D_CK_SCLK 197 198 R23 1 2 10K_0402_5%
13,14 D_CK_SCLK SCL SAO
+3VS 199 200 R21 1 2 10K_0402_5%
VDDSPD SA1
P-TWO_A5692A-A0G16-N
Change PCB Footprint
A
DIMM0 STD H:9.2mm (BOT) A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM0
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 12 of 59
5 4 3 2 1
A B C D E
+1.8V +1.8V
JP21 ***
1 2 +DIMM_VREF +1.8V
+DIMM_VREF VREF VSS
3 4 DDRB_SDQ5
DDRB_SDQ0 VSS DQ4 DDRB_SDQ4
5 DQ0 DQ5 6
DDRB_SDQ1 7 8 1 1
DQ1 VSS DDRB_SDM0
9 VSS DM0 10 1 1 1 1 1 1
DDRB_SDQS0# 11 12 C263 C276 C39 + C290 + C78 C89 C79 C90
7 DDRB_SDQS0# DDRB_SDQS0 DQS0# VSS DDRB_SDQ6
7 DDRB_SDQS0 13 DQS0 DQ6 14
15 16 DDRB_SDQ7 2.2U_0805_10V6K @ 150U_D2_6.3VM 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRB_SDQ2 VSS DQ7 2 2
0.1U_0402_16V4Z 2 2
330U_D2E_2.5VM_R9 2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z
17 DQ2 VSS 18
DDRB_SDQ3 19 20 DDRB_SDQ12
DQ3 DQ12 DDRB_SDQ13
21 VSS DQ13 22
DDRB_SDQ8 23 24
1 DDRB_SDQ9 DQ8 VSS DDRB_SDM1 1
25 DQ9 DM1 26
27 VSS VSS 28
DDRB_SDQS1# 29 30
7 DDRB_SDQS1# DQS1# CK0 DDRB_CLK1 6
DDRB_SDQS1 31 32
7 DDRB_SDQS1 DQS1 CK0# DDRB_CLK1# 6
33 VSS VSS 34
DDRB_SDQ10 35 36 DDRB_SDQ14
DDRB_SDQ11 DQ10 DQ14 DDRB_SDQ15
37 DQ11 DQ15 38
39 VSS VSS 40
41 VSS VSS 42
DDRB_SDQ17 43 44 DDRB_SDQ21 DDRB_SMA[0..13]
DQ16 DQ20 7 DDRB_SMA[0..13]
DDRB_SDQ20 45 46 DDRB_SDQ16
DQ17 DQ21 0_0402_5% DDRB_SDQ[0..63]
47 VSS VSS 48 7 DDRB_SDQ[0..63]
DDRB_SDQS2# 49 50 R120 1 2
7 DDRB_SDQS2# DQS2# NC PM_EXTTS#0 6,12 DDRB_SDM[0..7]
DDRB_SDQS2 51 52 DDRB_SDM2 7 DDRB_SDM[0..7]
7 DDRB_SDQS2 DQS2 DM2
53 VSS VSS 54
DDRB_SDQ18 55 56 DDRB_SDQ22 +1.8V
DDRB_SDQ19 DQ18 DQ22 DDRB_SDQ23
57 DQ19 DQ23 58
59 VSS VSS 60
DDRB_SDQ28 61 62 DDRB_SDQ26
DDRB_SDQ25 DQ24 DQ28 DDRB_SDQ24
63 DQ25 DQ29 64 1 1 1 1 1
65 66 C50 C55 C124 C126 C70
DDRB_SDM3 VSS VSS DDRB_SDQS3#
67 DM3 DQS3# 68 DDRB_SDQS3# 7
69 70 DDRB_SDQS3 2.2U_0805_10V6K 2.2U_0805_10V6K 2.2U_0805_10V6K
NC DQS3 DDRB_SDQS3 7 2 2
2.2U_0805_10V6K 2 2
2.2U_0805_10V6K 2
71 VSS VSS 72
DDRB_SDQ30 73 74 DDRB_SDQ29
DDRB_SDQ31 DQ26 DQ30 DDRB_SDQ27
75 DQ27 DQ31 76
77 VSS VSS 78
DDRB_CKE0 79 80 DDRB_CKE1
6 DDRB_CKE0 CKE0 NC/CKE1 DDRB_CKE1 6 +0.9VS +1.8V
81 VDD VDD 82
83 NC NC/A15 84
2 DDRB_SBS2# 2
7 DDRB_SBS2# 85 BA2 NC/A14 86
87 88 DDRB_SBS2# 1 4
DDRB_SMA12 VDD VDD DDRB_SMA11 DDRB_CKE0
89 A12 A11 90 2 3 1 1 1 1
DDRB_SMA9 91 92 DDRB_SMA7 RP13 56_0404_4P2R_5% C64 C61 C114 C116
DDRB_SMA8 A9 A7 DDRB_SMA6
93 A8 A6 94
95 96 DDRB_SMA9 1 4 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRB_SMA5 VDD VDD DDRB_SMA4 DDRB_SMA12 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2
97 A5 A4 98 2 3
DDRB_SMA3 99 100 DDRB_SMA2 RP11 56_0404_4P2R_5%
DDRB_SMA1 A3 A2 DDRB_SMA0
101 A1 A0 102
103 104 DDRB_SMA5 1 4
DDRB_SMA10 VDD VDD DDRB_SBS1# DDRB_SMA8
105 A10/AP BA1 106 DDRB_SBS1# 7 2 3
DDRB_SBS0# 107 108 DDRB_SRAS# RP9 56_0404_4P2R_5%
7 DDRB_SBS0# BA0 RAS# DDRB_SRAS# 7
DDRB_SWE# 109 110 DDRB_SCS#0
7 DDRB_SWE# WE# S0# DDRB_SCS#0 6
111 112 DDRB_SMA1 1 4
DDRB_SCAS# VDD VDD DDRB_ODT0 DDRB_SMA3 +0.9VS
7 DDRB_SCAS# 113 CAS# ODT0 114 DDRB_ODT0 6 2 3
DDRB_SCS#1 115 116 DDRB_SMA13 RP7 56_0404_4P2R_5%
6 DDRB_SCS#1 NC/S1# NC/A13
117 VDD VDD 118
DDRB_ODT1 119 120 DDRB_SBS0# 1 4
6 DDRB_ODT1 NC/ODT1 NC
121 122 DDRB_SMA10 2 3 1 1 1 1 1
DDRB_SDQ32 VSS VSS DDRB_SDQ36 RP5 56_0404_4P2R_5% C669 C677 C647 C652 C659
123 DQ32 DQ36 124
DDRB_SDQ33 125 126 DDRB_SDQ37
DQ33 DQ37 DDRB_SCAS# 0.1U_0402_16V4Z 0.1U_0402_16V4Z
127 VSS VSS 128 1 4
DDRB_SDQS4# DDRB_SDM4 DDRB_SWE# 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z
7 DDRB_SDQS4# 129 DQS4# DM4 130 2 3
DDRB_SDQS4 131 132 RP3 56_0404_4P2R_5%
7 DDRB_SDQS4 DQS4 VSS DDRB_SDQ39
133 VSS DQ38 134
DDRB_SDQ34 135 136 DDRB_SDQ38 DDRB_ODT1 1 4
DDRB_SDQ35 DQ34 DQ39 DDRB_SCS#1
137 DQ35 VSS 138 2 3
139 140 DDRB_SDQ44 RP1 56_0404_4P2R_5% +0.9VS
DDRB_SDQ40 VSS DQ44 DDRB_SDQ45
141 DQ40 DQ45 142
DDRB_SDQ41 143 144
DQ41 VSS DDRB_SDQS5# DDRB_CKE1
145 VSS DQS5# 146 DDRB_SDQS5# 7 1 4
DDRB_SDM5 147 148 DDRB_SDQS5 DDRB_SMA11 2 3 1 1 1 1 1
3 DM5 DQS5 DDRB_SDQS5 7 RP40 56_0404_4P2R_5% C662 C87 C91 C97 C110 3
149 VSS VSS 150
DDRB_SDQ42 151 152 DDRB_SDQ46
DDRB_SDQ43 DQ42 DQ46 DDRB_SDQ47 DDRB_SMA7 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
153 DQ43 DQ47 154 1 4
DDRB_SMA6 2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2
155 VSS VSS 156 2 3
DDRB_SDQ48 157 158 DDRB_SDQ52 RP38 56_0404_4P2R_5%
DDRB_SDQ49 DQ48 DQ52 DDRB_SDQ53
159 DQ49 DQ53 160
161 162 DDRB_SMA4 1 4
VSS VSS DDRB_SMA2 +0.9VS
163 NC,TEST CK1 164 DDRB_CLK0 6 2 3
165 166 RP36 56_0404_4P2R_5%
VSS CK1# DDRB_CLK0# 6
DDRB_SDQS6# 167 168
7 DDRB_SDQS6# DDRB_SDQS6 DQS6# VSS DDRB_SDM6 DDRB_SMA0
7 DDRB_SDQS6 169 DQS6 DM6 170 1 4
171 172 DDRB_SBS1# 2 3 1 1 1
DDRB_SDQ51 VSS VSS DDRB_SDQ54 RP34 56_0404_4P2R_5% C65 C73 C77
173 DQ50 DQ54 174
DDRB_SDQ50 175 176 DDRB_SDQ55
DQ51 DQ55 DDRB_SRAS# 0.1U_0402_16V4Z 0.1U_0402_16V4Z
177 VSS VSS 178 1 4
DDRB_SDQ56 DDRB_SDQ60 DDRB_SCS#0 2 2
0.1U_0402_16V4Z 2
179 DQ56 DQ60 180 2 3
DDRB_SDQ61 181 182 DDRB_SDQ57 RP32 56_0404_4P2R_5%
DQ57 DQ61
183 VSS VSS 184
DDRB_SDM7 185 186 DDRB_SDQS7# DDRB_ODT0 1 4
DM7 DQS7# DDRB_SDQS7 DDRB_SDQS7# 7 DDRB_SMA13
187 VSS DQS7 188 DDRB_SDQS7 7 2 3
DDRB_SDQ59 189 190 RP30 56_0404_4P2R_5%
DDRB_SDQ58 DQ58 VSS DDRB_SDQ62
191 DQ59 DQ62 192
193 194 DDRB_SDQ63
D_CK_SDATA VSS DQ63
12,14 D_CK_SDATA 195 SDA VSS 196
D_CK_SCLK 197 198 1 2
12,14 D_CK_SCLK SCL SAO
+3VS 199 200 R24 1 2 10K_0402_5% +3VS
VDDSPD SA1 R22 10K_0402_5%
P-TWO_A5652C-A0G16
4
DIMM1 STD H:5.2mm (BOT) 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 13 of 59
A B C D E
A B C D E F G H
R377
0_0805_5% 40mil
+CLK_VDD1
Clock Generator
FSLC FSLB FSLA CPU SRC PCI +CLK_VDD48 +CLK_VDDREF +3VS 1 2
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz 1 1 1 1 1 1 1 1
C432 C444 C474
C452 C477 C443 C469 C475
0 0 1 133 100 33.3 10U_0805_10V4Z 0.047U_0402_16V7K 0.047U_0402_16V7K 10U_0805_10V4Z 0.047U_0402_16V7K 0.047U_0402_16V7K 0.047U_0402_16V7K 0.047U_0402_16V7K
2 2 2 2 2 2 2 2
1
14 CLK_CPU0 R375 1 2 0_0402_5% CLK_CPU_BCLK
+3VS CPUCLKT0LP CLK_CPU_BCLK 4
Y3 CLK_XTALIN 20
C468 X1 CLK_CPU0# R374 1
**SEL_PCI5=1=PCICLK5 CPUCLKC0LP 13 2 0_0402_5% CLK_CPU_BCLK#
CLK_CPU_BCLK# 4
33P_0402_50V8J 14.31818MHz_20P_1BX14318BE1A
2
1 2 CLK_REF 1 2 CLK_XTALOUT 19
R712 10K_0402_5% X2
CPUCLKT2_ITP/SRCCLKT10LP 6
CLK_ICH_48M R288 1 2 12_0402_5%
28 CLK_ICH_48M
CLK_SD_48M R307 1 2 12_0402_5% CLKSEL0 41 5 CLK_MCH_BCLK 1 2
32 CLK_SD_48M USB_48MHz/FSLA CPUCLKC2_ITP/SRCCLKC10LP
1 2 CLK_PCI0 R383 @ 49.9_0402_1%
R619 10K_0402_5% CLKSEL1 45 CLK_MCH_BCLK# 1 2
FSLB/TEST_MODE/24Mhz CLK_SRC9 R371 1 EXP@ CLK_PCIE_CARD
ITP_EN/PCICLK_F0=0=SRC pair SRCCLKT9LP 3 2 0_0402_5% CLK_PCIE_CARD 37
R382 @ 49.9_0402_1%
CLK_14M_SIO R349 2 1 33_0402_5% CLKSEL2 23 CLK_CPU_BCLK 1 2
39 CLK_14M_SIO REF0/FSLC/TEST_SEL
2 CLK_SRC9# R370 1 EXP@ 2 0_0402_5% CLK_PCIE_CARD# R385 @ 49.9_0402_1%
SRCCLKC9LP CLK_PCIE_CARD# 37
CLK_CPU_BCLK# 1 2
1 2 CLK_PCI4 39 CLK_PCI_SIO
CLK_PCI_SIO R326 1 FIR@ 2 12_0402_5% CLK_PCI4 34 PCICLK4/FCTSEL1 CLKREQ9# 72 EXP_CLKREQ# 37
R384 @ 49.9_0402_1%
2 R711 10K_0402_5% CLK_PCI_MINI R327 1 2
36 CLK_PCI_MINI 2 12_0402_5% R658 1 2 10K_0402_5% +3VS
CLK_PCI_LAN R333 1 4401@ 2 33_0402_5% CLK_PCI3 33 70 CLK_SRC8 R367 1 MINI2@ 2 0_0402_5% CLK_PCIE_MINI2
34 CLK_PCI_LAN SEL_48M/PCICLK3 SRCCLKT8LP CLK_PCIE_MINI2 36
2005/08/31
CLK_PCI_PCM R338 1 2 33_0402_5% CLK_PCI2 32 69 CLK_SRC8# R365 1 MINI2@ 2 0_0402_5% CLK_PCIE_MINI2#
32 CLK_PCI_PCM SEL_24M/PCICLK2 SRCCLKC8LP CLK_PCIE_MINI2# 36
CLK_PCIE_VGA 1 2
CLK_PCI_LPC R345 1 2 33_0402_5% CLK_PCI1 27 71 R322 @ 49.9_0402_1%
40 CLK_PCI_LPC SEL_PCI6/PCICLK1 CLKREQ8# MINI2_CLKREQ# 36
CLK_PCI_TPM R344 1 @ 2 12_0402_5% R659 1 2 10K_0402_5% +3VS CLK_PCIE_VGA# 1 2
39 CLK_PCI_TPM
66 R328 @ 49.9_0402_1%
CLK_ICH_14M R353 1 CLK_REF SRCCLKT7LP CLK_PCIE_MINI2 1
28 CLK_ICH_14M 2 33_0402_5% 22 SEL_PCI5/REF1 2
67 R366 @ 49.9_0402_1%
SRCCLKC7LP CLK_PCIE_MINI2# 1 2
CLK_DREF_96M R306 1 2 0_0402_5% CLK_DOT 43 38 R364 @ 49.9_0402_1%
6 CLK_DREF_96M DOTT_96MHz/27MHz_Nonspread
CLKREQ7#/48Mhz_1 CLK_PCIE_ICH 1 2
CLK_DREF_96M# R305 1 2 0_0402_5% CLK_DOT# 44 63 CLK_SRC6 R355 1 2 0_0402_5% CLK_PCIE_SATA R346 @ 49.9_0402_1%
6 CLK_DREF_96M# DOTC_96MHz/27MHz_spread SRCCLKT6LP CLK_PCIE_SATA 27
CLK_PCIE_ICH# 1 2
64 CLK_SRC6# R361 1 2 0_0402_5% CLK_PCIE_SATA# R350 @ 49.9_0402_1%
SRCCLKC6LP CLK_PCIE_SATA# 27
CLK_PCI_ICH R308 1 2 33_0402_5% CLK_PCI0 37 CLK_PCIE_MINI1 1 2
26 CLK_PCI_ICH ITP_EN/PCICLK_F0
62 R283 @ 49.9_0402_1%
CLKREQ6# SATA_CLKREQ# 28
R647 1 2 10K_0402_5% +3VS CLK_PCIE_MINI1# 1 2
CLK_ENABLE# 39 60 CLK_SRC5 R347 1 2 0_0402_5% CLK_PCIE_ICH R282 @ 49.9_0402_1%
56 CLK_ENABLE# VTT_PWRGD#/PD SRCCLKT5LP CLK_PCIE_ICH 28
CLK_PCIE_SATA 1 2
61 CLK_SRC5# R351 1 2 0_0402_5% CLK_PCIE_ICH# R354 @ 49.9_0402_1%
SRCCLKC5LP CLK_PCIE_ICH# 28
R657 1 2 0_0402_5% CLKIREF 9 CLK_PCIE_SATA# 1 2
+3VS GND R637 1
2005/10/18 15mil CLKREQ5#/PCICLK6 29 2 10K_0402_5% +3VS R360 @ 49.9_0402_1%
CLK_DREF_SSC 1 2
58 CLK_SRC4 R336 1 8789@ 2 0_0402_5% CLK_PCIE_LAN R285 @ 49.9_0402_1%
SRCCLKT4LP CLK_PCIE_LAN 34
1 2 CLK_ENABLE# D_CK_SCLK 16 CLK_DREF_SSC# 1 2
12,13 D_CK_SCLK SMBCLK
R620 10K_0402_5% 59 CLK_SRC4# R340 1 8789@ 2 0_0402_5% CLK_PCIE_LAN# R284 @ 49.9_0402_1%
SRCCLKC4LP CLK_PCIE_LAN# 34
CLK_DREF_96M 1 2
57 R640 1 2 @ 10K_0402_5% +3VS R287 @ 49.9_0402_1%
D_CK_SDATA CLKREQ4# CLK_DREF_96M# 1
12,13 D_CK_SDATA 17 SMBDAT 2
55 CLK_SRC3 R323 1 VGA@ 2 0_0402_5% CLK_PCIE_VGA R286 @ 49.9_0402_1%
3 SRCCLKT3LP CLK_PCIE_VGA 15 3
CLK_PCIE_CARD 1 2
4 56 CLK_SRC3# R329 1 VGA@ 2 0_0402_5% CLK_PCIE_VGA# R381 @ 49.9_0402_1%
+3VS GNDSRC SRCCLKC3LP CLK_PCIE_VGA# 15
CLK_PCIE_CARD# 1 2
R387 15 28 CLK_PCI5 R636 1 2 @ 10K_0402_5% +3VS R380 @ 49.9_0402_1%
4.7K_0402_5% GNDCPU CLKREQ3#/PCICLK5 R334 2 1394@ 1 33_0402_5% CLK_PCI_1394 CLK_MCH_3GPLL 1
CLK_PCI_1394 38 2
2
ICS9LPR325AKLFT_MLF72
+1.05VS +1.05VS G72@ +1.05VS
G73M: ICS9LPR325CKLFT_MLF72: SA00000RE20
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Clock Generator
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 14 of 59
A B C D E F G H
5 4 3 2 1
U42A
NC
PCIE_MTX_C_GRX_N7 PEX_RX7 MIOAD0 SUB_VENDOR LVDSB0- IFPB_TXD4 NC_12
AL21 PEX_RX7_N MIOAD1 N2 SUB_VENDOR 18 23 LVDSB0- AM5 IFPB_TXD4_N NC_13 W1
PCIE_MTX_C_GRX_P8 AM21 N1 23 LVDSB1+ LVDSB1+ AM7 W3
PCIE_MTX_C_GRX_N8 PEX_RX8 MIOAD2 LVDSB1- IFPB_TXD5 NC_14
AM22 PEX_RX8_N MIOAD3 N3 23 LVDSB1- AL7 IFPB_TXD5_N NC_15 W4
PCIE_MTX_C_GRX_P9 AK22 M1 23 LVDSB2+ LVDSB2+ AK6 W5
PCIE_MTX_C_GRX_N9 PEX_RX9 MIOAD4 LVDSB2- IFPB_TXD6 NC_16
AK23 M3 23 LVDSB2- AK5 Y5
LVDS/TMDS
PCIE_MTX_C_GRX_P10 PEX_RX9_N MIOAD5 PEX_CFG0 IFPB_TXD6_N NC_17
AL23 PEX_RX10 MIOAD6 P5 PEX_CFG0 18 AK7 IFPB_TXD7 NC_18 Y6
DVO / GPIO
PCIE_MTX_C_GRX_N10 AL24 N6 AL8 Y30
PCIE_MTX_C_GRX_P11 PEX_RX10_N MIOAD7 PEX_CFG1 IFPB_TXD7_N NC_19
AM24 PEX_RX11 MIOAD8 N5 PEX_CFG1 18 NC_20 AC26
PCIE_MTX_C_GRX_N11 AM25 M4 PEX_CFG2 R570 1 2 @ 1K_0402_5% AL5 AG12
PEX_RX11_N MIOAD9 PEX_CFG2 18 IFPAB_RSET NC_21
PCIE_MTX_C_GRX_P12 AK25 L4 AH13
PCIE_MTX_C_GRX_N12 PEX_RX12 MIOAD10 VGA_DVI_TXC+ NC_22
AK26 PEX_RX12_N MIOAD11 L5 25 VGA_DVI_TXC+ AM2 IFPC_TXC NC_23 AM8
PCIE_MTX_C_GRX_P13 AL26 25 VGA_DVI_TXC- VGA_DVI_TXC- AM3 AM9
PCIE_MTX_C_GRX_N13 PEX_RX13 VGA_DVI_TXD0+ IFPC_TXC_N NC_24
AL27 PEX_RX13_N MIOA_HSYNC R3 1 2 +3VS 25 VGA_DVI_TXD0+ AE2 IFPC_TXD0 NC_25 AM10
PCIE_MTX_C_GRX_P14 AM27 R1 R562 VGA@ 2K_0402_5% 25 VGA_DVI_TXD0- VGA_DVI_TXD0- AE1
PCIE_MTX_C_GRX_N14 PEX_RX14 MIOA_VSYNC VGA_DVI_TXD1+ IFPC_TXD0_N
AM28 PEX_RX14_N MIOA_DE P1 1 2 25 VGA_DVI_TXD1+ AF1 IFPC_TXD1 BUFRST_N F3
PCIE_MTX_C_GRX_P15 AL28 P3 R543 @ 2K_0402_5% 25 VGA_DVI_TXD1- VGA_DVI_TXD1- AF2 AE26
PCIE_MTX_C_GRX_N15 PEX_RX15 MIOA_CTL3 VGA_DVI_TXD2+ IFPC_TXD1_N MEMSTRAPSEL0 FAE recommand 6/29
AL29 PEX_RX15_N 25 VGA_DVI_TXD2+ AG1 IFPC_TXD2 MEMSTRAPSEL1 AD26
M5 R96 2 1 10K_0402_5% VGA_DVI_TXD2- AH1 AH31
GENERAL
MIOA_CLKIN 25 VGA_DVI_TXD2- IFPC_TXD2_N MEMSTRAPSEL2
PCIE_GTX_C_MRX_P0 C183 1 2 VGA@ 0.1U_0402_16V4Z PCIE_GTX_MRX_P0 AJ15 R4 VGA@ AG3 AH32
PCIE_GTX_C_MRX_N0 C191 1 VGA@ 0.1U_0402_16V4Z PCIE_GTX_MRX_N0 PEX_TX0 MIOA_CLKOUT IFPD_TXC MEMSTRAPSEL3
2 AK15 PEX_TX0_N MIOA_CLKOUT_N P4 AH2 IFPD_TXC_N STEREO T3
PCIE_GTX_C_MRX_P1 C193 1 2 VGA@ 0.1U_0402_16V4Z PCIE_GTX_MRX_P1 AH16 AK1 F1
PCIE_GTX_C_MRX_N1 C204 1 VGA@ 0.1U_0402_16V4Z PCIE_GTX_MRX_N1 PEX_TX1 IFPD_TXD4 STRAP
2 AG16 PEX_TX1_N MIOA_VREF L2 AJ1 IFPD_TXD4_N SWAPRDY_A M6
PCIE_GTX_C_MRX_P2 C208 1 2 VGA@ 0.1U_0402_16V4Z PCIE_GTX_MRX_P2 AG17 AL2 J1 D-
PCIE_GTX_C_MRX_N2 C214 1 VGA@ 0.1U_0402_16V4Z PCIE_GTX_MRX_N2 PEX_TX2 RAM_CFG0 IFPD_TXD5 THERMDN D+
2 AH17 PEX_TX2_N MIOBD0 AC3 RAM_CFG0 18 AL1 IFPD_TXD5_N THERMDP K1
PCIE_GTX_C_MRX_P3 C217 1 2 VGA@ 0.1U_0402_16V4Z PCIE_GTX_MRX_P3 AG18 AC1 RAM_CFG1 AJ2
PEX_TX3 MIOBD1 RAM_CFG1 18 IFPD_TXD6
PCI EXPRESS
PCIE_GTX_C_MRX_N3 C225 1 2 VGA@ 0.1U_0402_16V4Z PCIE_GTX_MRX_N3 AH18 AC2 CRYSTAL_0 AJ3 AA7
C PEX_TX3_N MIOBD2 CRYSTAL_0 18 IFPD_TXD6_N ROM_SCLK C
PCIE_GTX_C_MRX_P4 C226 1 2 VGA@ 0.1U_0402_16V4Z PCIE_GTX_MRX_P4 AK18 AB2 PCI_DEVID2 W2
PEX_TX4 MIOBD3 PCI_DEVID2 18 ROM_SI
PCIE_GTX_C_MRX_N4 C236 1 VGA@ 0.1U_0402_16V4Z PCIE_GTX_MRX_N4 PCI_DEVID0 R569 1 2 @ 1K_0402_5%
PCIE_GTX_C_MRX_P5 C244
2
1 2 VGA@ 0.1U_0402_16V4Z PCIE_GTX_MRX_P5
AJ18
AJ19
PEX_TX4_N MIOBD4 AB1
AA1 PCI_DEVID1
PCI_DEVID0 18 AH3 IFPCD_RSET SERIAL ROM_SO AA6
AA4
PEX_TX5 MIOBD5 PCI_DEVID1 18 ROMCS_N
PCIE_GTX_C_MRX_N5 C250 1 2 VGA@ 0.1U_0402_16V4Z PCIE_GTX_MRX_N5 AH19 AB3 CRYSTAL_1
PEX_TX5_N MIOBD6 CRYSTAL_1 18
PCIE_GTX_C_MRX_P6 C251 1 2 VGA@ 0.1U_0402_16V4Z PCIE_GTX_MRX_P6 AG20 AA3 MOBILE_MODE
PEX_TX6 MIOBD7 MOBILE_MODE 18
PCIE_GTX_C_MRX_N6 C256 1 2 VGA@ 0.1U_0402_16V4Z PCIE_GTX_MRX_N6 AH20 AC5 RAM_CFG2 NV43M_BGA820
PEX_TX6_N MIOBD8 RAM_CFG2 18
PCIE_GTX_C_MRX_P7 C257 1 2 VGA@ 0.1U_0402_16V4Z PCIE_GTX_MRX_P7 AG21 AB5 RAM_CFG3 G73@
PEX_TX7 MIOBD9 RAM_CFG3 18
PCIE_GTX_C_MRX_N7 C264 1 2 VGA@ 0.1U_0402_16V4Z PCIE_GTX_MRX_N7 AH21 AB4
PCIE_GTX_C_MRX_P8 C265 PCIE_GTX_MRX_P8 PEX_TX7_N MIOBD10 PCI_DEVID3
1 2 VGA@ 0.1U_0402_16V4Z AK21 PEX_TX8 MIOBD11 AA5 PCI_DEVID3 18
VGA termination, close chip
PCIE_GTX_C_MRX_N8 C274 1 2 VGA@ 0.1U_0402_16V4Z PCIE_GTX_MRX_N8 AJ21 VGA_TV_LUMA R97 1 2 VGA@ 150_0402_1%
PCIE_GTX_C_MRX_P9 C275 PCIE_GTX_MRX_P9 PEX_TX8_N VGA_TV_CRMA
1 2 VGA@ 0.1U_0402_16V4Z AJ22 PEX_TX9 MIOB_HSYNC AF3 R102 1 2 VGA@ 150_0402_1%
PCIE_GTX_C_MRX_N9 C278 1 2 VGA@ 0.1U_0402_16V4Z PCIE_GTX_MRX_N9 AH22 AE3 VGA_TV_COMPS R113 1 2 VGA@ 150_0402_1%
PCIE_GTX_C_MRX_P10 C279 PEX_TX9_N MIOB_VSYNC
1 2 VGA@ 0.1U_0402_16V4Z PCIE_GTX_MRX_P10 AG23 PEX_TX10 MIOB_DE AD1
PCIE_GTX_C_MRX_N10 C282 1 2 VGA@ 0.1U_0402_16V4Z PCIE_GTX_MRX_N10 AH23 AD3 VGA_CRT_R R126 1 2 VGA@ 150_0402_1%
PCIE_GTX_C_MRX_P11 C283 PEX_TX10_N MIOB_CTL3
1 2 VGA@ 0.1U_0402_16V4Z PCIE_GTX_MRX_P11 AK24 PEX_TX11
VGA_CRT_G R131 1 2 VGA@ 150_0402_1%
PCIE_GTX_C_MRX_N11 C291 1 2 VGA@ 0.1U_0402_16V4Z PCIE_GTX_MRX_N11 AJ24 AE4 R61 2 VGA@ 1 10K_0402_5% VGA_CRT_B R124 1 2 VGA@ 150_0402_1%
PCIE_GTX_C_MRX_P12 C292 PEX_TX11_N MIOB_CLKIN
1 2 VGA@ 0.1U_0402_16V4Z PCIE_GTX_MRX_P12 AJ25 PEX_TX12 MIOB_CLKOUT AD4
PCIE_GTX_C_MRX_N12 C295 1 2 VGA@ 0.1U_0402_16V4Z PCIE_GTX_MRX_N12 AH25 AD5
PCIE_GTX_C_MRX_P13 C297 PCIE_GTX_MRX_P13 PEX_TX12_N MIOB_CLKOUT_N
1 2 VGA@ 0.1U_0402_16V4Z AH26 PEX_TX13
PCIE_GTX_C_MRX_N13 C299 1 2 VGA@ 0.1U_0402_16V4Z PCIE_GTX_MRX_N13 AG26 Y2
PCIE_GTX_C_MRX_P14 C300 PCIE_GTX_MRX_P14 PEX_TX13_N MIOB_VREF
1 2 VGA@ 0.1U_0402_16V4Z AK27 PEX_TX14
PCIE_GTX_C_MRX_N14 C308 1 2 VGA@ 0.1U_0402_16V4Z PCIE_GTX_MRX_N14 AJ27 AF10 VGA_CRT_HSYNC VGA_CRT_HSYNC 24
PCIE_GTX_C_MRX_P15 C310 PEX_TX14_N DACA_HSYNC
1 2 VGA@ 0.1U_0402_16V4Z PCIE_GTX_MRX_P15 AJ28 PEX_TX15 DACA_VSYNC AK10 VGA_CRT_VSYNC VGA_CRT_VSYNC 24
PCIE_GTX_C_MRX_N15 C316 1 2 VGA@ 0.1U_0402_16V4Z PCIE_GTX_MRX_N15 AH27 AH11 VGA_CRT_R VGA_CRT_R 24
PEX_TX15_N DACA_RED VGA_CRT_B
DACA_BLUE AH12 VGA_CRT_B 24
14 CLK_PCIE_VGA CLK_PCIE_VGA AH14 AJ12 VGA_CRT_G VGA_CRT_G 24
CLK_PCIE_VGA# PEX_REFCLK DACA_GREEN
14 CLK_PCIE_VGA# AJ14 PEX_REFCLK_N DACA_IDUMP AG9
AH9 DACA_RSET R571 1 2 124_0603_1%
PLTRST_VGA# DACA_RSET VGA@
26 PLTRST_VGA# AH15 PEX_RST_N
AH10 DACAVREF 1 2
DACA_VREF C155 0.01U_0402_16V7K
AM12 AG7 VGA@
B PEX_TSTCLK_OUT DACC_HSYNC +3VS B
DACs
J4 VGA_DVI_SDATA VGA_DVI_SDATA 25
I2C
I2CB_SDA
1
Y5 G2 I2CC_SCL I2CC_SCL 23
I2CC_SCL I2CC_SDA R554
4 GND OUT 3 T1 XTALSSIN I2CC_SDA G1 I2CC_SDA 23
G3 200_0402_5% I2C address
I2CH_SCL C665 VGA@ VGA@ 1001 101x
1 IN GND 2 I2CH_SDA H3
0.1U_0402_16V4Z U38
2
27MHZ_16PF_X7S027000BG1H-U 2 1 1 VCC 8
SMBCLK EC_SMB_CK1 40,41,45,53
1 VGA@ 1 NV43M_BGA820 G73@
C663 C664 R538 OSC_SPREAD 1 D+ 2 7
+3VS DXP SMBDATA EC_SMB_DA1 40,41,45,53
VGA@ VGA@ 1 2 OSC_OUT C666
18P_0402_50V8J 2005/09/23 18P_0402_50V8J VGA@ 22_0402_5% 2200P_0402_50V7K 3 6 THER_ALERT#
DXN ALERT
1
2 2 I2CC_SCL R556 1 D-
2 VGA@ 4.7K_0402_5%
A R540 R537 I2CC_SDA R555 1 2 @ A
2 VGA@ 4.7K_0402_5% 4 THERM GND 5
@ 10K_0402_5% @ 10K_0402_5% Close to Sensor
G781-1_SOP8
2
VGA@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
G72/G73 Main
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 15 of 59
5 4 3 2 1
5 4 3 2 1
FBAD[0..63] FBCD[0..63]
FBAD[0..63] 19,20 FBCD[0..63] 21,22
FBAA[0..12] FBCA[0..12]
FBAA[0..12] 19,20 FBCA[0..12] 21,22
D D
FBBA[2..5] FBDA[2..5]
FBBA[2..5] 20 FBDA[2..5] 22
FBADQS[0..7] FBCDQS[0..7]
FBADQS[0..7] 19,20 FBCDQS[0..7] 21,22
FBADQS#[0..7] FBCDQS#[0..7]
FBADQS#[0..7] 19,20 FBCDQS#[0..7] 21,22
FBADQM#[0..7] FBCDQM#[0..7]
FBADQM#[0..7] 19,20 FBCDQM#[0..7] 21,22
U42B U42C
FBAD0 N27 P32 FBAA3 FBCD0 B7 C13 FBCA3
FBAD1 FBAD0 Part 2 of 6 FBA_CMD0 FBAA0 FBCD1 FBCD0 Part 3 of 6 FBC_CMD0 FBCA0
M27 FBAD1 FBA_CMD1 U27 A7 FBCD1 FBC_CMD1 A16
FBAD2 N28 P31 FBAA2 FBCD2 C7 A13 FBCA2
FBAD3 FBAD2 FBA_CMD2 FBAA1 FBCD3 FBCD2 FBC_CMD2 FBCA1
L29 FBAD3 FBA_CMD3 U30 A2 FBCD3 FBC_CMD3 B17
FBAD4 K27 Y31 FBBA3 FBCD4 B2 B20 FBDA3
FBAD5 FBAD4 FBA_CMD4 FBBA4 FBCD5 FBCD4 FBC_CMD4 FBDA4
K28 FBAD5 FBA_CMD5 W32 C4 FBCD5 FBC_CMD5 A19
FBAD6 J29 W31 FBBA5 FBCD6 A5 B19 FBDA5
FBAD7 FBAD6 FBA_CMD6 FBACS1# FBCD7 FBCD6 FBC_CMD6 FBCCS1#
J28 FBAD7 FBA_CMD7 T32 PAD T24 B5 FBCD7 FBC_CMD7 B14 PAD T22
FBAD8 P30 V27 FBACS0# FBCD8 F9 E16 FBCCS0#
FBAD8 FBA_CMD8 FBACS0# 19,20 FBCD8 FBC_CMD8 FBCCS0# 21,22
FBAD9 N31 T28 FBAWE# FBCD9 F10 A14 FBCWE#
FBAD9 FBA_CMD9 FBAWE# 19,20 FBCD9 FBC_CMD9 FBCWE# 21,22
FBAD10 N30 T31 FBA_BA0 FBCD10 D12 C15 FBC_BA0
FBAD10 FBA_CMD10 FBA_BA0 19,20 FBCD10 FBC_CMD10 FBC_BA0 21,22
FBAD11 N32 U32 FBA_CKE FBCD11 D9 B16 FBC_CKE
FBAD11 FBA_CMD11 FBA_CKE 19,20 FBCD11 FBC_CMD11 FBC_CKE 21,22
FBAD12 L31 W29 AODT0 R183 1 2 FBAODT0 FBCD12 E12 F17 CODT0 R140 1 2 FBCODT0
FBAD12 FBA_CMD12 FBAODT0 19,20 FBCD12 FBC_CMD12 FBCODT0 21,22
1
FBAD13 L30 W30 FBBA2 64@ 0_0402_5% FBCD13 D11 C19 FBDA2 256@ 0_0402_5%
FBAD13 FBA_CMD13 FBCD13 FBC_CMD13
1
FBAD14 J30 T27 FBAA12 R185 FBCD14 E8 D15 FBCA12
FBAD15 FBAD14 FBA_CMD14 FBARAS# 10K_0402_5% FBCD15 FBCD14 FBC_CMD14 FBCRAS# R136
L32 FBAD15 FBA_CMD15 V28 FBARAS# 19,20 D8 FBCD15 FBC_CMD15 C17 FBCRAS# 21,22
FBAD16 H30 V30 FBAA11 VGA@ FBCD16 E7 A17 FBCA11 10K_0402_5%
C FBAD17 FBAD16 FBA_CMD16 FBAA10 FBCD17 FBCD16 FBC_CMD16 FBCA10 256@ C
K30 U31 F7 C16
2
FBAD18 FBAD17 FBA_CMD17 FBA_BA1 FBCD18 FBCD17 FBC_CMD17 FBC_BA1
H31 R27 FBA_BA1 19,20 D6 D14 FBC_BA1 21,22
2
FBAD19 FBAD18 FBA_CMD18 FBAA8 FBCD19 FBCD18 FBC_CMD18 FBCA8
F30 FBAD19 FBA_CMD19 V29 D5 FBCD19 FBC_CMD19 F16
FBAD20 H32 T30 FBAA9 FBCD20 D3 C14 FBCA9
FBAD21 FBAD20 FBA_CMD20 FBAA6 FBCD21 FBCD20 FBC_CMD20 FBCA6
E31 FBAD21 FBA_CMD21 W28 E4 FBCD21 FBC_CMD21 C18
FBAD22 D30 R29 FBAA5 FBCD22 C3 E14 FBCA5
FBAD23 FBAD22 FBA_CMD22 FBAA7 FBCD23 FBCD22 FBC_CMD22 FBCA7
E30 FBAD23 FBA_CMD23 R30 B4 FBCD23 FBC_CMD23 B13
FBAD24 H28 P29 FBAA4 FBCD24 C10 E15 FBCA4
FBAD25 FBAD24 FBA_CMD24 FBACAS# FBCD25 FBCD24 FBC_CMD24 FBCCAS#
H29 FBAD25 FBA_CMD25 U28 FBACAS# 19,20 B10 FBCD25 FBC_CMD25 F15 FBCCAS# 21,22
FBAD26 E29 Y32 FBCD26 C8 A20
FBAD27 FBAD26 FBA_CMD26 FBCD27 FBCD26 FBC_CMD26
J27 FBAD27 A10 FBCD27
MEMORY INTERFACE A
MEMORY INTERFACE B
FBAD28 F27 M29 FBADQM#0 FBCD28 C11 A4 FBCDQM#0
FBAD29 FBAD28 FBADQM0 FBADQM#1 FBCD29 FBCD28 FBCDQM0 FBCDQM#1
E27 FBAD29 FBADQM1 M30 C12 FBCD29 FBCDQM1 E11
FBAD30 E28 G30 FBADQM#2 FBCD30 A11 F5 FBCDQM#2
FBAD31 FBAD30 FBADQM2 FBADQM#3 FBCD31 FBCD30 FBCDQM2 FBCDQM#3
F28 FBAD31 FBADQM3 F29 B11 FBCD31 FBCDQM3 C9
FBAD32 AD29 AA29 FBADQM#4 FBCD32 B28 C28 FBCDQM#4
FBAD33 FBAD32 FBADQM4 FBADQM#5 FBCD33 FBCD32 FBCDQM4 FBCDQM#5
AE29 FBAD33 FBADQM5 AK30 C27 FBCD33 FBCDQM5 F24
FBAD34 AD28 AC30 FBADQM#6 FBCD34 C26 C24 FBCDQM#6
FBAD35 FBAD34 FBADQM6 FBADQM#7 FBCD35 FBCD34 FBCDQM6 FBCDQM#7
AC28 FBAD35 FBADQM7 AG30 B26 FBCD35 FBCDQM7 E20
FBAD36 AB29 FBCD36 C30
FBAD37 FBAD36 FBADQS#0 FBCD37 FBCD36 FBCDQS#0
AA30 FBAD37 FBADQS_RN0 M28 B31 FBCD37 FBCDQS_RN0 C6
FBAD38 Y28 K32 FBADQS#1 FBCD38 C29 E9 FBCDQS#1
FBAD39 FBAD38 FBADQS_RN1 FBADQS#2 FBCD39 FBCD38 FBCDQS_RN1 FBCDQS#2
AB30 FBAD39 FBADQS_RN2 G31 A31 FBCD39 FBCDQS_RN2 E6
FBAD40 AM30 G27 FBADQS#3 FBCD40 D28 A8 FBCDQS#3
FBAD41 FBAD40 FBADQS_RN3 FBADQS#4 FBCD41 FBCD40 FBCDQS_RN3 FBCDQS#4
AF30 FBAD41 FBADQS_RN4 AA28 D27 FBCD41 FBCDQS_RN4 B29
FBAD42 AJ31 AL31 FBADQS#5 FBCD42 F26 E25 FBCDQS#5
FBAD43 FBAD42 FBADQS_RN5 FBADQS#6 FBCD43 FBCD42 FBCDQS_RN5 FBCDQS#6
AJ30 FBAD43 FBADQS_RN6 AF31 D24 FBCD43 FBCDQS_RN6 A25
FBAD44 AJ32 AH29 FBADQS#7 FBCD44 E23 F21 FBCDQS#7
FBAD45 FBAD44 FBADQS_RN7 FBCD45 FBCD44 FBCDQS_RN7
AK29 FBAD45 E26 FBCD45
FBAD46 AM31 L28 FBADQS0 FBCD46 E24 C5 FBCDQS0 +1.8VS
FBAD47 FBAD46 FBADQS_WP0 FBADQS1 +1.8VS FBCD47 FBCD46 FBCDQS_WP0 FBCDQS1
AL30 FBAD47 FBADQS_WP1 K31 F23 FBCD47 FBCDQS_WP1 E10
FBAD48 AE32 G32 FBADQS2 FBCD48 B23 E5 FBCDQS2
FBAD48 FBADQS_WP2 FBCD48 FBCDQS_WP2
1
B FBAD49 FBADQS3 FBCD49 FBCDQS3 B
AE30 FBAD49 FBADQS_WP3 G28 A23 FBCD49 FBCDQS_WP3 B8
1
2
FBAD54 FBAD53 FBADQS_WP7 FBCD54 FBCD53 FBCDQS_WP7
AB32 C21
2
1
FBAD58 AH28 R28 C752 R588 FBCD58 D21 F13 1
FBAD58 FBA_CLK0_N FBACLK0# 19 FBCD58 FBC_CLK0_N FBCCLK0# 21
FBAD59 AG28 Y27 VGA@ 1K_0402_1% FBCD59 E21 F18 C736 R581
FBAD59 FBA_CLK1 FBACLK1 20 FBCD59 FBC_CLK1 FBCCLK1 22
FBAD60 AG29 AA27 0.1U_0402_16V4Z VGA@ FBCD60 E18 E17 @ 1K_0402_1%
FBAD60 FBA_CLK1_N FBACLK1# 20 2 FBCD60 FBC_CLK1_N FBCCLK1# 22
FBAD61 AD27 D32 FBCD61 D19 B1 0.1U_0402_16V4Z @
2
2
FBAD63 FBAD62 FBA_REFCLK_N FBA_DEBUG FBCD63 FBCD62 FBC_REFCLK_N FBC_DEBUG
AE28 FBAD63 FBA_DEBUG AC27 PAD T23 E19 FBCD63 FBC_DEBUG F12 PAD T21
NV43M_BGA820 NV43M_BGA820
G73@ FB_VREF1=0.5 x FBVDD G73@
FB_VREF2=0.5 x FBVDD
FBAODT0 FBCODT0
1
1
R186 R139
10K_0402_5% 10K_0402_5%
A VGA@ VGA@ A
2
2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
G72/G73 Memory
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 16 of 59
5 4 3 2 1
5 4 3 2 1
L13
+1.2VS MBK1608121YZF_0603
VGA@
1 2 NV_PLLVDD +1.2VS
8mA 1420mA
1 1 0.022U_0402_16V7K 0.022U_0402_16V7K
C82 C162 +VGA_CORE
VGA@ VGA@ U42E 1 1 1 1 1
0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z K16 AD23 C249 C243 C229 C238 C266
2.2U_0603_6.3V6K 2 2 VDD_0 Part 5 of 6 PEX_IOVDD_0
K17 VDD_1 PEX_IOVDD_1 AF23
1 1 1 1 1 1 N13 AF24 VGA@ VGA@ VGA@ VGA@ VGA@ 0.022U_0402_16V7K
C203 C184 C174 C175 C185 C218 VDD_2 PEX_IOVDD_2 2 2 2 2 2
N14 VDD_3 PEX_IOVDD_3 AF25
N16 VDD_4 PEX_IOVDD_4 AG24
D VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ 0.022U_0402_16V7K 0.022U_0402_16V7K D
N17 VDD_5 PEX_IOVDD_5 AG25
L11 2 2 2 2 2 2
N19 VDD_6
+2.5VS MBK1608121YZF_0603 N20 AC16
VGA@ 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z VDD_7 PEX_IOVDDQ_0
P13 VDD_8 PEX_IOVDDQ_1 AC17
1 2 4700P_0402_25V7K VID_PLLVDD P14 AC21 0.01U_0402_16V7K 0.01U_0402_16V7K 0.01U_0402_16V7K 10U_0805_10V4Z
VDD_9 PEX_IOVDDQ_2
40mA P16 VDD_10 PEX_IOVDDQ_3 AC22 1 1 1 1 1 1 1 1 1
1 1 1 P17 AE18 C255 C228 C248 C254 C260 C262 C56 C57 C52
C172 C137 C151 VDD_11 PEX_IOVDDQ_4
P19 VDD_12 PEX_IOVDDQ_5 AE21
VGA@ VGA@ VGA@ R16 AE22 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
4700P_0402_25V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z VDD_13 PEX_IOVDDQ_6 2 2 2 2 2 2 2 2 2
R17 VDD_14 PEX_IOVDDQ_7 AF12
2.2U_0603_6.3V6K 2 2 2 NV_PLLVDD T13
VDD_15 PEX_IOVDDQ_8 AF18
1 1 1 1 1 1 T14 VDD_16 PEX_IOVDDQ_9 AF21
470P_0402_50V7K C223 C211 C224 C181 C190 C182 T15 AF22 0.01U_0402_16V7K 0.01U_0402_16V7K 0.01U_0402_16V7K 10U_0805_10V4Z 10U_0805_10V4Z L15 +1.2VS
VDD_17 PEX_IOVDDQ_10 VGA@
T18 VDD_18
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ T19 AF15 +PEX_PLLAVDD 100mA 1 2
L47 2 2 2 2 2 2 VDD_19 PEX_PLLAVDD +PEX_PLLDVDD 20mA MBK1608121YZF_0603
U13 VDD_20 PEX_PLLDVDD AE15
+2.5VS MBK1608121YZF_0603 U14 +3VS
VDD_21 1 1
VGA@ 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z U15 M7 C197 C192
4700P_0402_25V7K PLLVDD VDD_22 MIOA_VDDQ_0 0.1U_0402_16V4Z +1.8VS
1 2 U19 VDD_23 MIOA_VDDQ_1 M8
30mA V16 R8 1 1 L3 VGA@ VGA@
VDD_24 MIOA_VDDQ_2 C136 C135 VGA@ 2 2 2.2U_0603_6.3V6K
1 1 1 V17 VDD_25 MIOA_VDDQ_3 T8
C693 C150 C149 4700P_0402_25V7K 4700P_0402_25V7K W13 U9 4700P_0402_25V7K 1 2 0.1U_0402_16V4Z L14
VGA@ VGA@ VGA@ VDD_26 MIOA_VDDQ_4 VGA@ VGA@ MBK1608121YZF_0603 VGA@
W14 VDD_27 MIOB_VDDQ_0 AA8
2 2
1 1 1 1 W16 VDD_28 MIOB_VDDQ_1 AB7 1 1 1 1 2
2.2U_0603_6.3V6K 2 2 2 C189 C202 C219 C201 0.1U_0402_16V4Z C81 C142 C74 MBK1608121YZF_0603
W17 VDD_29 MIOB_VDDQ_2 AB8
W19 VDD_30 MIOB_VDDQ_3 AC6 1 1
470P_0402_50V7K VGA@ VGA@ VGA@ VGA@ Y13 AC7 VGA@ VGA@ VGA@ C179 C83
2 2 2 2 VDD_31 MIOB_VDDQ_4 2 2 2 2.2U_0603_6.3V6K
Y14 VDD_32 MIOACAL_PD_VDDQ L1
L16 Y16 Y1 VGA@ VGA@
+1.2VS MBK1608121YZF_0603 4700P_0402_25V7K 4700P_0402_25V7K VDD_33 MIOBCAL_PD_VDDQ 470P_0402_50V7K 2 2 2.2U_0603_6.3V6K
Y17 VDD_34
VGA@ Y19 AF9 130mA IFPA_IOVDD 0.1U_0402_16V4Z
FBA_PLLAVDD VDD_35 IFPA_IOVDD 130mA
1 2 Y20 VDD_36 IFPB_IOVDD AF8
C
U18 AD6 150mA +2.5VS C
VDD_37 IFPC_IOVDD +3VSDVI
1 1 AE7 150mA IFPD_IOVDD 1 2 L12
C222 C259 470P_0402_50V7K 470P_0402_50V7K IFPD_IOVDD VGA@ R103 10K_0402_5% VGA@
P20 VDD_LP_0
VGA@ VGA@ 1 1 1 1 T20 AC9 35mA IFPAB_CD_PLLVDD 4700P_0402_25V7K 1 2
C178 C163 C161 C210 VDD_LP_1 IFPAB_PLLVDD
T23 VDD_LP_2 IFPCD_PLLVDD AA10 35mA 1 1 1 MBK1608121YZF_0603
2.2U_0603_6.3V6K 2 2 C152 C146 C692 +5VS
U20 VDD_LP_3
VGA@ VGA@ VGA@ VGA@ U23 AD10 135mA DACA_VDD
4700P_0402_25V7K 10U_0805_10V4Z 2 2 2 2 VDD_LP_4 DACA_VDD 200mA DACB_VDD VGA@ VGA@ VGA@
W20 VDD_LP_5 DACB_VDD V8
2
+3VS 470P_0402_50V7K 200mA DACC_VDD 2 2 2 2.2U_0603_6.3V6K R536
DACC_VDD AD7
470P_0402_50V7K 10K_0402_5%
4700P_0402_25V7K 0.022U_0402_16V7K 0.022U_0402_16V7K H7 A3 VGA@
VDD33_0 FBVDD_0
1 1 1 1 1 1 J7 VDD33_1 FBVDD_1 A6
1
C143 C132 C157 C165 C145 C138 K7 A9
1
VDD33_2 FBVDD_2 R110 @ 0.1U_0402_16V4Z
L7 VDD33_3 FBVDD_3 A12
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ L8 A15 10K_0402_5% 57 VDD_PWRGOOD 1 2
2 2 2 2 2 2 VDD33_4 FBVDD_4
L10 VDD33_5 FBVDD_5 A18 VGA@
4700P_0402_25V7K 0.022U_0402_16V7K 0.022U_0402_16V7K M10 A21 C646
2
VDD33_6 FBVDD_6
2
+3VSDVI +3VS
G
AC11 VDD33_7 FBVDD_7 A24
AC12 VDD33_8 FBVDD_8 A27
0.1U_0402_16V4Z AC24 A30 1 3
L10 VDD33_9 FBVDD_9
AD24 C32
S
1 1 1 VDD33_10 FBVDD_10 1 1
+1.2VS MBK1608121YZF_0603 C661 C156 C164 AE11 F32 C649 C658 Q30
POWER
VGA@ VDD33_11 FBVDD_11 VGA@ AO3402_SOT23
AE12 VDD33_12 FBVDD_12 J32
1 2 FBC_PLLAVDD VGA@ VGA@ VGA@ M32 2.2U_0603_6.3V6K VGA@ VGA@
1U_0603_10V4Z 2 2 2 VID_PLLVDD 40mA FBVDD_13 2 2 L44
T10 VID_PLLVDD FBVDD_14 R32
1 1 0.1U_0402_16V4Z PLLVDD 30mA T9 V32 4700P_0402_25V7K 1 2
C177 C147 PLLVDD FBVDD_15 @
FBVDD_16 AA32
VGA@ VGA@ AD32 MBK1608121YZF_0603
2.2U_0603_6.3V6K FBA_PLLAVDD 30mA FBVDD_17
G25 FBA_PLLAVDD FBVDD_18 AG32
2 2 FBC_PLLAVDD 30mA For NV43 DVI leakage issue
G10 FBC_PLLAVDD FBVDD_19 AK32
G23 +1.8VS
4700P_0402_25V7K FBA_PLLVDD
G8 FBC_PLLVDD FBVDDQ_0 G11
B +1.8VS R152 1 2 K26 G12 B
VGA@ 40.2_0402_1% FBCAL_PD_VDDQ FBVDDQ_1
FBVDDQ_2 G15
0.1U_0402_16V4Z 0.01U_0402_16V7K 0.01U_0402_16V7K H16 G18 +1.8VS
FBVTT_0 FBVDDQ_3
1 1 1 1 1 1 1 H17 FBVTT_1 FBVDDQ_4 G21
C98 C144 C148 C230 C252 C187 C200 J9 G22 4700P_0402_25V7K 4700P_0402_25V7K 4700P_0402_25V7K 0.022U_0402_16V7K 4.7U_0805_10V4Z
FBVTT_2 FBVDDQ_5
J10 FBVTT_3 FBVDDQ_6 H11 1 1 1 1 1 1 1 1 1 1
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ J23 H12 C271 C212 C220 C237 C261 C267 C270 C272 C334 C332
2 2 2 2 2 2 2 FBVTT_4 FBVDDQ_7
J24 FBVTT_5 FBVDDQ_8 H15
4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K 0.01U_0402_16V7K K9 H18 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
FBVTT_6 FBVDDQ_9 2 2 2 2 2 2 2 2 2 2
K11 FBVTT_7 FBVDDQ_10 H21
K12 FBVTT_8 FBVDDQ_11 L25
K21 L26 4700P_0402_25V7K 4700P_0402_25V7K 0.022U_0402_16V7K 0.022U_0402_16V7K 4.7U_0805_10V4Z
L9 FBVTT_9 FBVDDQ_12
K22 FBVTT_10 FBVDDQ_13 M25
MBK1608121YZF_0603 K24 M26
VGA@ FBVTT_11 FBVDDQ_14 0.022U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
L23 FBVTT_12 FBVDDQ_15 R25
+3VS 1 2 4700P_0402_25V7K DACA_VDD M23 R26 1 1 1 1 1 1 1 1 1
FBVTT_13 FBVDDQ_16 C213 C221 C247 C199 C227 C198 C186 C268 C269
T25 FBVTT_14 FBVDDQ_17 V25
1 1 1 U25 FBVTT_15 FBVDDQ_18 V26
C134 C154 C153 AA23 AA25 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
VGA@ VGA@ VGA@ FBVTT_16 FBVDDQ_19 2 2 2 2 2 2 2 2 2
AB23 FBVTT_17 FBVDDQ_20 AA26
2.2U_0603_6.3V6K AB25 0.022U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 FBVDDQ_21
FBVDDQ_22 AB26
F6 CLAMP FBVDDQ_23 H22
470P_0402_50V7K
L6 NV43M_BGA820
MBK1608121YZF_0603 2005/10/20 G73@
VGA@ +VGA_CORE +1.8VS
1 2 4700P_0402_25V7K DACB_VDD
1 1 1 1 1 1 1 2005/09/21
C72 C131 C133 C253 C96
A VGA@ VGA@ VGA@ VGA@ + + VGA@ + C362 + C529 A
2.2U_0603_6.3V6K 330U_D2E_2.5VM 330U_D2E_2.5VM VGA@ VGA@
2 2 2 330U_D2E_2.5VM 330U_D2E_2.5VM
2 2 2 2
470P_0402_50V7K
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
G72/G73 Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 17 of 59
5 4 3 2 1
5 4 3 2 1
G73M G72MV
STRAPS PIN DESCRIPTION Value Value
+3VS
1
T4 GND_65 GND_150 AM26
T16 AM29 R55 R539 R51 R48 R557 R558 R542 R54 R786 R76 R788
GND_66 GND_151 X76@ X76@ X76@ X76@ G72@ G72@ G72@ G73@ VGA@ @ @
T17 GND_67 GND_152 D16
T24 GND_68 GND_153 W27
T29 W15
2
B GND_69 GND_154 B
U8 GND_70
U16 AD9 RAM_CFG0
GND_71 IFPAB_PLLGND 15 RAM_CFG0
U17 AB10 RAM_CFG1
GND_72 IFPCD_PLLGND 15 RAM_CFG1
U24 RAM_CFG2
GND_73 15 RAM_CFG2
U29 L3 RAM_CFG3
GND_74 MIOACAL_PU_GND 15 RAM_CFG3
V2 Y3 PCI_DEVID0
GND_75 MIOBCAL_PU_GND 15 PCI_DEVID0
V13 PCI_DEVID1
GND_76 15 PCI_DEVID1
V14 AE16 PCI_DEVID2
GND_77 PEX_PLLGND 15 PCI_DEVID2
V15 PCI_DEVID3
GND_78 15 PCI_DEVID3
V18 U10 PEX_CFG0
GND_79 PLLGND 15 PEX_CFG0
V19 PEX_CFG1
GND_80 15 PEX_CFG1
V20 G24 PEX_CFG2
GND_81 FBA_PLLGND 15 PEX_CFG2
V31 G9 PEX_PLL_TERM
GND_82 FBC_PLLGND 15 PEX_PLL_TERM
W6 GND_83
H26 R148 1 VGA@ 2 30.1_0402_1%
FBCAL_PU_GND R150 1
FBCAL_TERM_GND J26 2 0_0402_5%
@
1
NV43M_BGA820 NVidia suggestion
G73@ Bandwidth RAM Type Vendor R56 R553 R52 R49 R72 R71 R70 R63 R560 R787 R77 R559
X76@ X76@ X76@ X76@ @ @ @ @ @ VGA@ VGA@ VGA@
FULL R49 32M R51 Samsung R553, R55 2K_0402_5%
2
HALF R48 16M R52 Hynix R539, R55
Infineon R553, R56 10K_0402_5% 10K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5%
2K_0402_5%
2K_0402_5%
10K_0402_5% 10K_0402_5% 2K_0402_5% 2K_0402_5%
Package
A
(10*12.5) Infineon GDDR2(400): SA00000S800 (HYB18T256161AFL-25) Infineon GDDR2(350): SA00000T700 (HYB18T256161AF-28) A
(11*13) Samsung GDDR2 (400): SA00000FG10 (K4N56163QF-ZC25) Samsung GDDR2 (350): SA00000TB00 (K4N56163QF-ZC2A)
(8*13) Hynix GDDR2 (400): SA00000FF10 (HY5PS561621AFP-25) Hynix GDDR2 (350): SA00000TJ00 (HY5PS561621AFP-28)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
G72/G73 GND & STRAP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 18 of 59
5 4 3 2 1
5 4 3 2 1
U46 U11
FBA_BA0 L2 B9 FBAD14 FBA_BA0 L2 B9 FBAD25
FBA_BA1 BA0 DQ15 FBAD11 FBA_BA1 BA0 DQ15 FBAD31
L3 BA1 DQ14 B1 L3 BA1 DQ14 B1
D9 FBAD13 D9 FBAD27
D FBAA12 DQ13 FBAD8 FBAA12 DQ13 FBAD30 D
R2 A12 DQ12 D1 R2 A12 DQ12 D1
FBAA11 P7 D3 FBAD9 FBAA11 P7 D3 FBAD26
FBAA10 A11 DQ11 FBAD12 FBAA10 A11 DQ11 FBAD28
M2 A10/AP DQ10 D7 M2 A10/AP DQ10 D7
FBAA9 P3 C2 FBAD10 FBAA9 P3 C2 FBAD29 FBAD[0..63]
A9 DQ9 A9 DQ9 16,20 FBAD[0..63]
FBAA8 P8 C8 FBAD15 FBAA8 P8 C8 FBAD24
FBAA7 A8 DQ8 FBAD6 FBAA7 A8 DQ8 FBAD18
P2 A7 DQ7 F9 P2 A7 DQ7 F9
FBAA6 N7 F1 FBAD1 FBAA6 N7 F1 FBAD23 FBAA[0..12]
A6 DQ6 A6 DQ6 16,20 FBAA[0..12]
FBAA5 N3 H9 FBAD7 FBAA5 N3 H9 FBAD17
FBAA4 A5 DQ5 FBAD0 FBAA4 A5 DQ5 FBAD21
N8 A4 DQ4 H1 N8 A4 DQ4 H1
FBAA3 N2 H3 FBAD3 FBAA3 N2 H3 FBAD19 FBADQS[0..7]
A3 DQ3 A3 DQ3 16,20 FBADQS[0..7]
FBAA2 M7 H7 FBAD5 FBAA2 M7 H7 FBAD16
FBAA1 A2 DQ2 FBAD2 FBAA1 A2 DQ2 FBAD22
M3 A1 DQ1 G2 M3 A1 DQ1 G2
FBAA0 M8 G8 FBAD4 FBAA0 M8 G8 FBAD20 FBADQS#[0..7]
A0 DQ0 A0 DQ0 16,20 FBADQS#[0..7]
VSSQ8 VSSQ8
J2 VREF VSSQ9 H2 J2 VREF VSSQ9 H2
1
(SSTL-1.8) VREF = .5*VDDQ H8 (SSTL-1.8) VREF = .5*VDDQ H8 R596 is 120 Ohm (SD028120080) for G72MV
VSSQ10 VSSQ10
1
1 A2 1 A2 R596
R597 C790 E2
NC#A2
A3 C340 E2
NC#A2
A3 120_0402_5% R596 is 475 Ohm (SD034475080) for G73M
1K_0402_1% 0.047U_0402_16V4Z NC#E2 VSS1 0.047U_0402_16V4Z NC#E2 VSS1 64@
L1 NC#L1 VSS2 E3 L1 NC#L1 VSS2 E3
64@ 64@ R3 J3 64@ R3 J3
2
2 NC#R3 VSS3 2 NC#R3 VSS3
R7 N1 R7 N1
2
+1.8VS +1.8VS
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM DDRA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 19 of 59
5 4 3 2 1
5 4 3 2 1
D D
U45 U12
FBA_BA0 L2 B9 FBAD44 FBA_BA0 L2 B9 FBAD32
FBA_BA1 BA0 DQ15 FBAD46 FBA_BA1 BA0 DQ15 FBAD36
L3 BA1 DQ14 B1 L3 BA1 DQ14 B1
D9 FBAD41 D9 FBAD33 FBAD[0..63]
DQ13 DQ13 16,19 FBAD[0..63]
FBAA12 R2 D1 FBAD40 FBAA12 R2 D1 FBAD38
FBAA11 A12 DQ12 FBAD45 FBAA11 A12 DQ12 FBAD39
P7 A11 DQ11 D3 P7 A11 DQ11 D3
FBAA10 M2 D7 FBAD43 FBAA10 M2 D7 FBAD35 FBAA[0..12]
A10/AP DQ10 A10/AP DQ10 16,19 FBAA[0..12]
FBAA9 P3 C2 FBAD47 FBAA9 P3 C2 FBAD37
FBAA8 A9 DQ9 FBAD42 FBAA8 A9 DQ9 FBAD34
P8 A8 DQ8 C8 P8 A8 DQ8 C8
FBAA7 P2 F9 FBAD63 FBAA7 P2 F9 FBAD50 FBBA[2..5]
A7 DQ7 A7 DQ7 16 FBBA[2..5]
FBAA6 N7 F1 FBAD58 FBAA6 N7 F1 FBAD55
FBBA5 A6 DQ6 FBAD61 FBBA5 A6 DQ6 FBAD49
N3 A5 DQ5 H9 N3 A5 DQ5 H9
FBBA4 N8 H1 FBAD56 FBBA4 N8 H1 FBAD54 FBADQS[0..7]
A4 DQ4 A4 DQ4 16,19 FBADQS[0..7]
FBBA3 N2 H3 FBAD60 FBBA3 N2 H3 FBAD52
FBBA2 A3 DQ3 FBAD57 FBBA2 A3 DQ3 FBAD53
M7 A2 DQ2 H7 M7 A2 DQ2 H7
FBAA1 M3 G2 FBAD59 FBAA1 M3 G2 FBAD51 FBADQS#[0..7]
A1 DQ1 A1 DQ1 16,19 FBADQS#[0..7]
FBAA0 M8 G8 FBAD62 FBAA0 M8 G8 FBAD48
A0 DQ0 A0 DQ0
FBADQM#[0..7]
16,19 FBADQM#[0..7]
FBACLK1# K8 A9 FBACLK1# K8 A9
FBACLK1 CK VDDQ1 FBACLK1 CK VDDQ1
J8 CK VDDQ2 C1 J8 CK VDDQ2 C1
C3 C3 FBA_BA0
VDDQ3 VDDQ3 16,19 FBA_BA0
FBA_CKE K2 C7 FBA_CKE K2 C7
CKE VDDQ4 CKE VDDQ4 FBA_BA1
VDDQ5 C9 VDDQ5 C9 16,19 FBA_BA1
VDDQ6 E9 VDDQ6 E9
G1 +1.8VS G1 +1.8VS FBAODT0
VDDQ7 VDDQ7 16,19 FBAODT0
FBACS0# L8 G3 FBACS0# L8 G3
CS VDDQ8 CS VDDQ8 FBA_CKE
VDDQ9 G7 VDDQ9 G7 16,19 FBA_CKE
FBAWE# K3 G9 FBAWE# K3 G9
C WE VDDQ10 WE VDDQ10 FBARAS# C
16,19 FBARAS#
FBARAS# K7 A1 FBARAS# K7 A1
RAS VDD1 RAS VDD1 FBACAS#
VDD2 E1 VDD2 E1 16,19 FBACAS#
FBACAS# L7 J9 FBACAS# L7 J9
CAS VDD3 CAS VDD3 FBAWE#
VDD4 M9 VDD4 M9 16,19 FBAWE#
FBADQM#7 F3 R1 FBADQM#6 F3 R1
FBADQM#5 LDM VDD5 FBADQM#4 LDM VDD5 FBACS0#
B3 UDM B3 UDM 16,19 FBACS0#
VDDL J1 VDDL J1
VSSDL J7 1 1 VSSDL J7 1 1
FBAODT0 K9 C757 C758 FBAODT0 K9 C321 C325
ODT 0.1U_0402_16V4Z 1U_0402_6.3V4Z ODT 0.1U_0402_16V4Z 1U_0402_6.3V4Z
128@ 128@ 128@ 128@
FBADQS7 2 2 FBADQS6 2 2
F7 LDQS F7 LDQS
+1.8VS FBADQS#7 E8 A7 FBADQS#6 E8 A7
LDQS VSSQ1 LDQS VSSQ1
VSSQ2 B2 VSSQ2 B2
VSSQ3 B8 VSSQ3 B8
1
VSSQ4 D2 VSSQ4 D2
R592 FBADQS5 B7 D8 FBADQS4 B7 D8
+VRAM_VREFB 1K_0402_1% FBADQS#5 UDQS VSSQ5 +VRAM_VREFB FBADQS#4 UDQS VSSQ5
A8 UDQS VSSQ6 E7 A8 UDQS VSSQ6 E7
128@ F2 F2
VSSQ7 VSSQ7
F8 F8
2
VSSQ8 VSSQ8
J2 VREF VSSQ9 H2 J2 VREF VSSQ9 H2
(SSTL-1.8) VREF = .5*VDDQ H8 H8
VSSQ10 VSSQ10
1
1
Close to U9 R8 NC#R8 VSS5 P9 Close to U10 R8 NC#R8 VSS5 P9
R200
120_0402_5%
X76@ HY5PS561621F-25 X76@ HY5PS561621F-25 128@
B B
2
FBACLK1#
16 FBACLK1#
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM DDRB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 20 of 59
5 4 3 2 1
5 4 3 2 1
U41 U4
FBC_BA0 L2 B9 FBCD26 FBC_BA0 L2 B9 FBCD19
FBC_BA1 BA0 DQ15 FBCD31 FBC_BA1 BA0 DQ15 FBCD21
L3 BA1 DQ14 B1 L3 BA1 DQ14 B1
D FBCD24 FBCD16 D
DQ13 D9 DQ13 D9
FBCA12 R2 D1 FBCD28 FBCA12 R2 D1 FBCD22
FBCA11 A12 DQ12 FBCD29 FBCA11 A12 DQ12 FBCD20
P7 A11 DQ11 D3 P7 A11 DQ11 D3
FBCA10 M2 D7 FBCD27 FBCA10 M2 D7 FBCD17
FBCA9 A10/AP DQ10 FBCD30 FBCA9 A10/AP DQ10 FBCD23 FBCD[0..63]
P3 A9 DQ9 C2 P3 A9 DQ9 C2 16,22 FBCD[0..63]
FBCA8 P8 C8 FBCD25 FBCA8 P8 C8 FBCD18
FBCA7 A8 DQ8 FBCD15 FBCA7 A8 DQ8 FBCD0
P2 A7 DQ7 F9 P2 A7 DQ7 F9
FBCA6 N7 F1 FBCD12 FBCA6 N7 F1 FBCD5 FBCA[0..12]
A6 DQ6 A6 DQ6 16,22 FBCA[0..12]
FBCA5 N3 H9 FBCD8 FBCA5 N3 H9 FBCD2
FBCA4 A5 DQ5 FBCD10 FBCA4 A5 DQ5 FBCD3
N8 A4 DQ4 H1 N8 A4 DQ4 H1
FBCA3 N2 H3 FBCD9 FBCA3 N2 H3 FBCD7 FBCDQS[0..7]
A3 DQ3 A3 DQ3 16,22 FBCDQS[0..7]
FBCA2 M7 H7 FBCD11 FBCA2 M7 H7 FBCD6
FBCA1 A2 DQ2 FBCD13 FBCA1 A2 DQ2 FBCD4
M3 A1 DQ1 G2 M3 A1 DQ1 G2
FBCA0 M8 G8 FBCD14 FBCA0 M8 G8 FBCD1 FBCDQS#[0..7]
A0 DQ0 A0 DQ0 16,22 FBCDQS#[0..7]
VSSQ8 VSSQ8
J2 VREF VSSQ9 H2 J2 VREF VSSQ9 H2
1
VSSQ10 H8 VSSQ10 H8
1
2
2 NC#R3 VSS3 2 NC#R3 VSS3
R7 N1 R7 N1
2
B
DDR2 BGA MEMORY DDR2 BGA MEMORY B
+1.8VS +1.8VS
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM DDRC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 21 of 59
5 4 3 2 1
5 4 3 2 1
U43 U5
FBC_BA0 L2 B9 FBCD33 FBC_BA0 L2 B9 FBCD57
FBC_BA1 BA0 DQ15 FBCD39 FBC_BA1 BA0 DQ15 FBCD63 FBCD[0..63]
L3 BA1 DQ14 B1 L3 BA1 DQ14 B1 16,21 FBCD[0..63]
D FBCD35 FBCD59 D
DQ13 D9 DQ13 D9
FBCA12 R2 D1 FBCD37 FBCA12 R2 D1 FBCD62
FBCA11 A12 DQ12 FBCD38 FBCA11 A12 DQ12 FBCD60 FBCA[0..12]
P7 A11 DQ11 D3 P7 A11 DQ11 D3 16,21 FBCA[0..12]
FBCA10 M2 D7 FBCD32 FBCA10 M2 D7 FBCD58
FBCA9 A10/AP DQ10 FBCD36 FBCA9 A10/AP DQ10 FBCD61
P3 A9 DQ9 C2 P3 A9 DQ9 C2
FBCA8 P8 C8 FBCD34 FBCA8 P8 C8 FBCD56 FBDA[2..5]
A8 DQ8 A8 DQ8 16 FBDA[2..5]
FBCA7 P2 F9 FBCD52 FBCA7 P2 F9 FBCD41
FBCA6 A7 DQ7 FBCD48 FBCA6 A7 DQ7 FBCD44
N7 A6 DQ6 F1 N7 A6 DQ6 F1
FBDA5 N3 H9 FBCD54 FBDA5 N3 H9 FBCD40 FBCDQS[0..7]
A5 DQ5 A5 DQ5 16,21 FBCDQS[0..7]
FBDA4 N8 H1 FBCD50 FBDA4 N8 H1 FBCD47
FBDA3 A4 DQ4 FBCD49 FBDA3 A4 DQ4 FBCD43
N2 A3 DQ3 H3 N2 A3 DQ3 H3
FBDA2 M7 H7 FBCD53 FBDA2 M7 H7 FBCD42 FBCDQS#[0..7]
A2 DQ2 A2 DQ2 16,21 FBCDQS#[0..7]
FBCA1 M3 G2 FBCD51 FBCA1 M3 G2 FBCD46
FBCA0 A1 DQ1 FBCD55 FBCA0 A1 DQ1 FBCD45
M8 A0 DQ0 G8 M8 A0 DQ0 G8
FBCDQM#[0..7]
16,21 FBCDQM#[0..7]
FBCCLK1# K8 A9 FBCCLK1# K8 A9
FBCCLK1 CK VDDQ1 FBCCLK1 CK VDDQ1 FBC_BA0
J8 CK VDDQ2 C1 J8 CK VDDQ2 C1 16,21 FBC_BA0
VDDQ3 C3 VDDQ3 C3
FBC_CKE K2 C7 FBC_CKE K2 C7 FBC_BA1
CKE VDDQ4 CKE VDDQ4 16,21 FBC_BA1
VDDQ5 C9 VDDQ5 C9
E9 E9 FBCODT0
VDDQ6 +1.8VS VDDQ6 +1.8VS 16,21 FBCODT0
VDDQ7 G1 VDDQ7 G1
FBCCS0# L8 G3 FBCCS0# L8 G3 FBC_CKE
CS VDDQ8 CS VDDQ8 16,21 FBC_CKE
VDDQ9 G7 VDDQ9 G7
FBCWE# K3 G9 FBCWE# K3 G9 FBCRAS#
WE VDDQ10 WE VDDQ10 16,21 FBCRAS#
FBCRAS# K7 A1 FBCRAS# K7 A1 FBCCAS#
RAS VDD1 RAS VDD1 16,21 FBCCAS#
VDD2 E1 VDD2 E1
FBCCAS# L7 J9 FBCCAS# L7 J9 FBCWE#
CAS VDD3 CAS VDD3 16,21 FBCWE#
VDD4 M9 VDD4 M9
FBCDQM#6 F3 R1 FBCDQM#5 F3 R1 FBCCS0#
C LDM VDD5 LDM VDD5 16,21 FBCCS0# C
FBCDQM#4 B3 FBCDQM#7 B3
UDM UDM
VDDL J1 VDDL J1
VSSDL J7 1 1 VSSDL J7 1 1
FBCODT0 K9 C745 C684 FBCODT0 K9 C289 C120
ODT 0.1U_0402_16V4Z 1U_0402_6.3V4Z ODT 0.1U_0402_16V4Z 1U_0402_6.3V4Z
256@ 256@ 256@ 256@
+1.8VS FBCDQS6 2 2 FBCDQS5 2 2
F7 LDQS F7 LDQS
FBCDQS#6 E8 A7 FBCDQS#5 E8 A7
LDQS VSSQ1 LDQS VSSQ1
VSSQ2 B2 VSSQ2 B2
VSSQ3 B8 VSSQ3 B8
1
VSSQ4 D2 VSSQ4 D2
R585 FBCDQS4 B7 D8 FBCDQS7 B7 D8
+VRAM_VREFD 1K_0402_1% FBCDQS#4 UDQS VSSQ5 +VRAM_VREFD FBCDQS#7 UDQS VSSQ5
A8 UDQS VSSQ6 E7 A8 UDQS VSSQ6 E7
256@ F2 F2
VSSQ7 VSSQ7
F8 F8
2
1
256@ 256@ R3 J3 256@ R3 J3
2 NC#R3 VSS3 2 NC#R3 VSS3 R170
R7 N1 R7 N1
2
2
X76@ HY5PS561621F-25 X76@ HY5PS561621F-25
FBCCLK1#
16 FBCCLK1#
Close to U14
B
R170 is 120 Ohm (SD028120080) for G72MV B
DDR2 BGA MEMORY DDR2 BGA MEMORY R170 is 481 Ohm (SD00000CA80) for G73M
+1.8VS +1.8VS
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM DDRD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 22 of 59
5 4 3 2 1
5 4 3 2 1
+3VALW +3VS
+LCDVDD
W=60mils
1
1
R493 C12
R485 100K_0402_5%
D 300_0402_5% 4.7U_0805_10V4Z D
2
1 2
3
D S
G
Q25 2 2 1 2 Q28 AOS 3413
2N7002_SOT23 G R496 1K_0402_5%
S 1 SI2301BDS_SOT23
3
C600 +LCDVDD
D
W=60mils
1
1
GM@ D 0.047U_0402_16V7K
R495 1 2
8 GMCH_ENVDD 2 0_0402_5% 2 Q1
VGA@ G 2N7002_SOT23 1 1
R494 1 2 0_0402_5% S C593 C597
15 ENVDD
3
1
4.7U_0805_10V4Z 0.1U_0402_16V4Z
R490 2 2
10K_0402_5%
2
+3VS
1
R492
4.7K_0402_5%
D27 TXOUT0- R25 1 2 VGA@ 0_0402_5% LVDSA0- LVDSA0- 15
2
BKOFF# 1 2 RB751V_SOD323 DISPOFF# TXOUT0+ R26 1 2 VGA@ 0_0402_5% LVDSA0+ LVDSA0+ 15
40 BKOFF#
TXOUT1- R27 1 2 VGA@ 0_0402_5% LVDSA1- LVDSA1- 15
TXOUT1+ R28 1 2 VGA@ 0_0402_5% LVDSA1+ LVDSA1+ 15
C C
TXOUT2+ R29 1 2 VGA@ 0_0402_5% LVDSA2+ LVDSA2+ 15
TXOUT2- R30 1 2 VGA@ 0_0402_5% LVDSA2- LVDSA2- 15
TXCLK- R31 1 2 VGA@ 0_0402_5% LVDSAC- LVDSAC- 15
TXCLK+ R32 1 2 VGA@ 0_0402_5% LVDSAC+ LVDSAC+ 15
TZOUT0- R33 1 2 VGA@ 0_0402_5% LVDSB0-
LCD/PANEL BD. Conn. TZOUT0+ R34 1 2 VGA@ 0_0402_5% LVDSB0+
LVDSB0- 15
LVDSB0+ 15
TZOUT1+ R35 1 2 VGA@ 0_0402_5% LVDSB1+ LVDSB1+ 15
TZOUT1- R36 1 2 VGA@ 0_0402_5% LVDSB1- LVDSB1- 15
JP1
+INVPWR_B+ DAC_BRIG TZOUT2+ R37 1 2 VGA@ 0_0402_5% LVDSB2+ LVDSB2+ 15
40 20 DAC_BRIG 40
INVT_PWM TZOUT2- R38 1 2 VGA@ 0_0402_5% LVDSB2- LVDSB2- 15
39 19 INVT_PWM 40
DISPOFF#
38 18 TZCLK- R39
+3VS 37 17 +LCDVDD 1 2 VGA@ 0_0402_5% LVDSBC- LVDSBC- 15
I2CC_SCL (60 MIL) TZCLK+ R40 1 2 VGA@ 0_0402_5% LVDSBC+ LVDSBC+ 15
15 I2CC_SCL 36 16
I2CC_SDA
15 I2CC_SDA 35 15
TZOUT0- 34 14 TXOUT0-
TZOUT0+ 33 13 TXOUT0+
32 12 I2CC_SCL R41
31 11 1 2 GM@ 0_0402_5% GMCH_LCD_CLK GMCH_LCD_CLK 8
TZOUT1+ TXOUT1- I2CC_SDA R42 1 2 GM@ 0_0402_5% GMCH_LCD_DATA GMCH_LCD_DATA 8
TZOUT1- 30 10 TXOUT1+
29 9 TXOUT0- R509 1 GMCH_TXOUT0-
28 8 2 GM@ 0_0402_5% GMCH_TXOUT0- 8
TZOUT2+ TXOUT2+ TXOUT0+ R508 1 2 GM@ 0_0402_5% GMCH_TXOUT0+
27 7 GMCH_TXOUT0+ 8
TZOUT2- TXOUT2-
26 6 TXOUT1- R507 1 GMCH_TXOUT1-
25 5 2 GM@ 0_0402_5% GMCH_TXOUT1- 8
TZCLK- TXCLK- TXOUT1+ R506 1 2 GM@ 0_0402_5% GMCH_TXOUT1+
24 4 GMCH_TXOUT1+ 8
TZCLK+ TXCLK+
23 3 TXOUT2+ R505 1
22 2 2 GM@ 0_0402_5% GMCH_TXOUT2+
GMCH_TXOUT2+ 8
B TXOUT2- R504 1 B
21 1 2 GM@ 0_0402_5% GMCH_TXOUT2-
GMCH_TXOUT2- 8
ACES_88107-4000G TXCLK- R503 1 2 GM@ 0_0402_5% GMCH_TXCLK-
GMCH_TXCLK- 8
TXCLK+ R502 1 2 GM@ 0_0402_5% GMCH_TXCLK+
GMCH_TXCLK+ 8
(SAME AS ACES_87216-4016) TZOUT0- R525 1 2 GM@ 0_0402_5% GMCH_TZOUT0-
GMCH_TZOUT0- 8
TZOUT0+ R524 1 2 GM@ 0_0402_5% GMCH_TZOUT0+
GMCH_TZOUT0+ 8
TZOUT1+ R523 1 2 GM@ 0_0402_5% GMCH_TZOUT1+
+LCDVDD GMCH_TZOUT1+ 8
TZOUT1- R522 1 2 GM@ 0_0402_5% GMCH_TZOUT1-
+INVPWR_B+ +3VS GMCH_TZOUT1- 8
TZOUT2+ R521 1 2 GM@ 0_0402_5% GMCH_TZOUT2+
GMCH_TZOUT2+ 8
L1 2 1 TZOUT2- R520 1 2 GM@ 0_0402_5% GMCH_TZOUT2-
B+ GMCH_TZOUT2- 8
KC FBM-L11-201209-221LMAT_0805 1 1 1
C11 C586 C591 TZCLK- R519 1 2 GM@ 0_0402_5% GMCH_TZCLK-
GMCH_TZCLK- 8
L2 2 1 TZCLK+ R518 1 2 GM@ 0_0402_5% GMCH_TZCLK+
GMCH_TZCLK+ 8
KC FBM-L11-201209-221LMAT_0805 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z
2 2 2
1 1
C930 C10
680P_0603_50V7K 68P_0402_50V8K
2 2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LCD Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 23 of 59
5 4 3 2 1
A B C D E
1
2 1 1 2
RB411D_SOT23 1.1A_6VDC_FUSE
1
+3VS PM@ 2 1 R475
0_0603_5% C575
3
0.1U_0402_16V4Z
GM@ 2 2
+2.5VS 1 R474 +CRT_PULLUP
1 0_0603_5% 1
1
1 1 1 1 1 1 DDC_MD2 9
R477 R483 R487 C592 C581 C571 14
PM@ PM@ PM@ C580 C578 C576 4
8P_0402_50V8K 8P_0402_50V8K 8P_0402_50V8K 8P_0402_50V8K 8P_0402_50V8K 10
150_0402_1% 150_0402_1% 150_0402_1% 2 2 2 PM@ 2 PM@ 2 2 PM@ 15
2
8P_0402_50V8K 1 5
C573
SUYIN_070549FR015S208CR
+CRT_VCC CRT_HSYNC_L
1 2
L38 FCM1608C-121T_0603 2
1 2 2 1 100P_0402_50V8J DSUB_12
C584 0.1U_0402_16V4Z R489 10K_0402_5% 1 2 CRT_VSYNC_L
L40 FCM1608C-121T_0603 1
1
U35
1 1
OE#
1 2 CRT_HSYNC 2 4 CRT_HSYNC_B C574
15 VGA_CRT_HSYNC A Y
R105 PM@ 0_0402_5% C577 C579 2
G
1 2 10P_0402_50V8K 10P_0402_50V8K 68P_0402_50V8K DSUB_15
2 8 GMCH_CRT_HSYNC 2 2 2
R106 GM@ 39_0402_5% SN74AHCT1G125DCKR_SC70-5
3
+CRT_VCC 1
1
U36
OE#
1 2 CRT_VSYNC 2 4 CRT_VSYNC_B
15 VGA_CRT_VSYNC A Y
R115 PM@ 0_0402_5%
G
1 2 +3VS
8 GMCH_CRT_VSYNC +CRT_VCC
R116 GM@ 39_0402_5% SN74AHCT1G125DCKR_SC70-5
1
Place closed to chipset
R781
+3VS 4.7K_0402_5%
1
PM@
2
TV-OUT Conn. D1 D23 D24
R479
4.7K_0402_5% R478
1 2 R480
PM@ 0_0402_5% VGA_DDC_DATA 15
2
@ @ @
G
DAN217_SC59 DAN217_SC59 DAN217_SC59 4.7K_0402_5% R98 GM@ 0_0402_5%
DSUB_12 1 3 2 1
1
1
GMCH_CRT_DATA 8
S
Q27
2
2N7002_SOT23
G
DSUB_15 1 3 2 1
R129 GMCH_CRT_CLK 8
Place closed to chipset
S
2
3
Q26 GM@ 0_0402_5%
3 2N7002_SOT23 3
+3VS
1 2 R476 VGA_DDC_CLK 15
1 2 PM@ 0_0402_5%
15 VGA_TV_LUMA
R66 PM@ 0_0402_5% C582 1 2 22P_0402_50V8J JP14
1 2 TV_LUMA 1 2 3 2005/10/18
8 GMCH_TV_LUMA
2
R74 GM@ 0_0402_5% L39 PM@ FCM1608C-121T_0603 TV_CRMA_L 6
1 2 C595 1 2 22P_0402_50V8J TV_COMPS_L 7 R782
15 VGA_TV_CRMA
R75 PM@ 0_0402_5% TV_CRMA 1 2 5 4.7K_0402_5%
1 2 L43 PM@ FCM1608C-121T_0603 2 PM@
8 GMCH_TV_CRMA
R79 GM@ 0_0402_5% C588 1 2 22P_0402_50V8J TV_LUMA_L 4
1
1 2 TV_COMPS 1 2 1
15 VGA_TV_COMPS
R62 PM@ 0_0402_5% L41 PM@ FCM1608C-121T_0603 8
1 2 9 +3VS
8 GMCH_TV_COMPS
R65 GM@ 0_0402_5%
1
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT & TV-OUT Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 24 of 59
A B C D E
5 4 3 2 1
+2.5VS +3VS
0.1U_0402_16V4Z 0.1U_0402_16V4Z
+3VS
+2.5VS
1 1 1 1 1 1
C5 C3 C9 C4 C8 C6
D 7307@ 7307@ 7307@ 7307@ 7307@ 7307@ D
10U_0805_10V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2
12
28
15
21
36
42
48
1
U1
DVDD
DVDD
TVDD
TVDD
AVDD
AVDD
AVDD
AVDD_PLL
32 13 DVI_TXC-
8 SDVO_INT SDVOB_INT+ TLC#
33 14 DVI_TXC+
8 SDVO_INT# SDVOB_INT- TLC
16 DVI_TXD0- BOM structure DVI from SDVO DVI from Discrete VGA
TDC0# DVI_TXD0+
8 SDVOB_R 37 SDVOB_R+ TDC0 17
38 19 DVI_TXD1- 7307@ Stuff No_Stuff
8 SDVOB_R# SDVOB_R- TDC1#
20 DVI_TXD1+
TDC1 DVI_TXD2-
+2.5VS 8 SDVOB_G 40 SDVOB_G+ TDC2# 22 VGA@ No_Stuff Stuff
41 23 DVI_TXD2+
8 SDVOB_G# SDVOB_G- TDC2
@ No_Stuff No_Stuff
8 SDVOB_B 43 SDVOB_B+
1
R10 44 29 DVI_DET
8 SDVOB_B# SDVOB_B- HPDET
10K_0402_5%
7307@ 46 11 DVI_SCLK
8 SDVOB_CLK SDVOB_CLK+ SC_DDC
47 10 DVI_SDATA
8 SDVOB_CLK# SDVOB_CLK- SD_DDC
2
AS AS 3 9
AS SC_PROM
26,36,39 PLT_RST_BUF# 2 RESET# SD_PROM 8
1
25 VSWING
AGND_PLL
R9 5 SDVO_SDAT
SPD SDVO_SDAT 8
10K_0402_5% 27 4 SDVO_SCLK
ATPG SPC SDVO_SCLK 8
DGND
DGND
AGND
AGND
AGND
TGND
TGND
@ 26 SCEN
NC
NC
Keep 30mil spacing to other signals
2
1
+2.5VS
C R6 R1 R5 7307@ CH7307_LQFP48 C
7
30
31
39
45
18
24
6
34
35
1.2K_0402_5% 10K_0402_5% 10K_0402_5% SDVO_SDAT 1 2
7307@ 7307@ 7307@ R12 7307@ 5.6K_0402_5%
2
SDVO_SCLK 1 2
R11 7307@ 5.6K_0402_5%
4 TMDS_DATA4-
5 TMDS_DATA4+
20 TMDS_DATA5-
21 TMDS_DATA5+ Hot Plug Detect 16
2 3 DVI_TXC+ 23
15 VGA_DVI_TXC+ TMDS_Clock+
1 4 DVI_TXC- 24
15 VGA_DVI_TXC- TMDS_Clock-
RP28 DVI@ 10_0404_4P2R_5%
TMDS_DATA2/4 shield 3
Place close to CH7307C TMDS_DATA1/3 shield 11
TMDS_DATA0/5 shield 19
TMDS_Clock shield 22
+DVI_VCC
20K_0402_5%
1
1
15 VGA_DVI_SCLK R4 1 2 DVI@ 0_0402_5% DVI_SCLK DVI@
R7
D2 VGA@
A R3 A
15 VGA_DVI_SDATA 1 2 DVI@ 0_0402_5% DVI_SDATA @ SKS10-04AT_TSMA 100K_0402_5%
2
(HDQ70)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CH7307 & DVI-D Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 25 of 59
5 4 3 2 1
5 4 3 2 1
ICH7M(B-0)(QK65)[QS]:SA00000V160
ICH7M-DH(B-0)(QK17)[QS]:SA00000JK60
D D
+3VS
5
R664 1 2 8.2K_0402_5% PCI_REQ#4 PCI_AD9 C14 A14 U17
PCI_AD10 AD9 GNT4# / GPIO48 PCI_REQ#5 PLT_RST#
E14 C8 2
P
R649 1 AD10 GPIO1 / REQ5# B
2 8.2K_0402_5% PCI_REQ#3 PCI_AD11 D14 AD11 GPIO17 / GNT5# D8 Y 4 PLT_RST_BUF# 25,36,39
PCI_AD12 B12 1
AD12 A
G
PCI_AD13 C13 B15 PCI_CBE#0
AD13 C/BE0# PCI_CBE#0 32,34,36,38
PCI_AD14 G15 C12 PCI_CBE#1 NC7SZ08P5X_NL_SC70-5
PCI_CBE#1 32,34,36,38
3
PCI_AD15 AD14 C/BE1# PCI_CBE#2
G13 AD15 C/BE2# D12 PCI_CBE#2 32,34,36,38
PCI_AD16 E12 C15 PCI_CBE#3
AD16 C/BE3# PCI_CBE#3 32,34,36,38
PCI_AD17 C11
PCI_AD18 AD17 PCI _IRDY#
D11 AD18 IRDY# A7 PCI_IRDY# 32,34,36,38 2 1
C PCI_AD19 PCI_PAR R331 @ 0_0402_5% C
A11 AD19 PAR E10 PCI_PAR 32,34,36,38
PCI_AD20 A10 B18 PCI_RST#
AD20 PCIRST# PCI_RST# 32,34,36,37,38
PCI_AD21 F11 A12 PCI_DEVSEL#
+3VS AD21 DEVSEL# PCI_DEVSEL# 32,34,36,38
PCI_AD22 F10 C9 PCI_PERR#
AD22 PERR# PCI_PERR# 32,34,36,38
PCI_AD23 E9 E11 PCI_PLOCK#
PCI_AD24 AD23 PLOCK# PCI_SERR#
D9 AD24 SERR# B10 PCI_SERR# 32,34,36 2 1 PLTRST_VGA# 15
R670 1 2 8.2K_0402_5% PCI_PIRQA# PCI_AD25 B9 F15 PCI_STOP# R330 0_0402_5%
AD25 STOP# PCI_STOP# 32,34,36,38
PCI_AD26 A8 F14 PCI_TRDY#
AD26 TRDY# PCI_TRDY# 32,34,36,38
R669 1 2 8.2K_0402_5% PCI_PIRQB# PCI_AD27 A6 F16 PCI_FRAME#
AD27 FRAME# PCI_FRAME# 32,34,36,38
PCI_AD28 C7
R655 1 PCI_PIRQC# PCI_AD29 AD28 PLT_RST#
2 8.2K_0402_5% B6 AD29 PLTRST# C26 PLT_RST# 6,28,31,34,39,40
PCI_AD30 E6 A9 CLK_PCI_ICH
AD30 PCICLK CLK_PCI_ICH 14
R660 1 2 8.2K_0402_5% PCI_PIRQD# PCI_AD31 D6 B19 PCI_PME#
AD31 PME# PCI_PME# 34,36,40
R632 1 2 8.2K_0402_5% PCI_PIRQE#
CLK_PCI_ICH
B B
2
R667
10_0402_5%
@
1
1
C851
10P_0402_50V8K
@
2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7-M(1/4)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 26 of 59
5 4 3 2 1
5 4 3 2 1
C826
+RTCVCC 18P_0402_50V8J
2 1 ICH_RTCX1
10M_0402_5%
1 X3
1
3 NC OUT 4
R614
R274
32.768KHZ_12.5P_1TJS125DJ2A073 2 1
1M_0402_5% NC IN U48A
Change P/N SJ100001V00
C827
2
RTC
SM_INTRUDER# 18P_0402_50V8J AB1 AA6 LPC_AD0
RTXC1 LAD0 LPC_AD0 39,40
2 1 ICH_RTCX2 AB2 AB5 LPC_AD1
D RTCX2 LAD1 LPC_AD1 39,40 D
AC4 LPC_AD2
LAD2 LPC_AD2 39,40
+RTCVCC 1 2 ICH_RTCRST# AA3 Y6 LPC_AD3
RTCRST# LAD3 LPC_AD3 39,40
LPC
+RTCVCC ENABLE INTERNAL R263
1.05V 20K_0402_5% ICH_INTVRMEN W4 AC3 LPC_DRQ0#
INTVRMEN LDRQ0# LPC_DRQ#0 39
SUSPEND SM_INTRUDER# Y5 AA5
INTRUDER# LDRQ1# / GPIO23
REGULARTOR
1
2 1 AB3 LPC_FRAME#
LFRAME# LPC_FRAME# 39,40
R278 close to RAM door J3 @ JOPEN W1
332K_0402_1% EE_CS
Y1 EE_SHCLK 2 1 R249 10K_0402_5% +3VS
Y2 AE22 EC_GA20
EE_DOUT A20GATE EC_GA20 40
LAN
C427 W3 AH28 H_A20M#
H_A20M# 4
2
EE_DIN A20M#
CPU
1U_0603_10V4Z
ICH_INTVRMEN 1 2 V3 AG27 H_CPUSLP_R# PAD
LAN_CLK CPUSLP# T25
U3 AF24 DPRSTP# R240 1 2 0_0402_5%
LAN_RSTSYNC TP1 / DPRSTP# H_DPRSTP# 4,56
AH25 H_DPSLP#
+3VS TP2 / DPSLP# H_DPSLP# 4
U5 R604 2 1 56_0402_5% +1.05VS
LAN_RXD0 H_FERR#
V4 LAN_RXD1 FERR# AG26 H_FERR# 4
T5 LAN_RXD2
1
INIT# H_INTR
INTR AF25 H_INTR 4
1 2 ICH_AC_BITCLK
42 ICH_BITCLK_MDC +1.05VS
AC-97/AZALIA
SATA_LED# R627 39_0402_5% U1 R239 2 1 10K_0402_5%
ACZ_BCLK +3VS
42 ICH_SYNC_MDC 1 2 ICH_AC_SYNC_R R6 AG23 EC_KBRST#
ACZ_SYNC RCIN# EC_KBRST# 40
R298 39_0402_5%
1
1 2 ICH_AC_RST_R# R5 AF23 H_SMI#
42 ICH_RST_MDC# ACZ_RST# SMI# H_SMI# 4
R313 39_0402_5% AH24 H_NMI R605
NMI H_NMI 4
1 2 ICH_AC_BITCLK 44 ICH_AC_SDIN0 T2
C 44 ICH_BITCLK_AUDIO ACZ_SDIN0 C
R634 39_0402_5% 42 ICH_AC_SDIN1 T3 AH22 H_STPCLK# 56_0402_5%
ACZ_SDIN1 STPCLK# H_STPCLK# 4
T1
2
ICH_AC_SYNC_R ACZ_SDIN2 THRMTRIP_ICH# R606 1
44 ICH_SYNC_AUDIO 1 2 THERMTRIP# AF26 2 24.9_0402_1% H_THERMTRIP#
H_THERMTRIP# 4,6
R297 39_0402_5% 1 2 ICH_AC_SDOUT_R T4
42 ICH_SDOUT_MDC ACZ_SDOUT
R292 39_0402_5% IDE_DA[0..2] 30,31
1 2 ICH_AC_RST_R# AH17 IDE_DA0
44 ICH_RST_AUDIO# DA0
R320 39_0402_5% 40 SATA_LED# SATA_LED# AF18 AE17 IDE_DA1
SATALED# DA1 IDE_DA2
DA2 AF17
44 ICH_SDOUT_AUDIO 1 2 ICH_AC_SDOUT_R
MAINPWON 50,51,53
R291 39_0402_5% 30 SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_N0 AF3 AE16 IDE_DCS1# IDE_DCS1# 30,31
SATA_DTX_C_IRX_P0 SATA0RXN DCS1# IDE_DCS3#
30 SATA_DTX_C_IRX_P0 AE3 SATA0RXP DCS3# AD16 IDE_DCS3# 30,31
SATA_ITX_DRX_N0 AG2 R222
SATA0TXN
1
SATA
SATA_ITX_DRX_P0 AH2 @ 330_0402_5% C
SATA0TXP IDE_DD[0..15] 30,31
AB15 IDE_DD0 +1.05VS 1 2 2 Q6
SATA_DTX_C_IRX_N2 DD0 IDE_DD1 B
AF7 SATA2RXN DD1 AE14
SATA_DTX_C_IRX_P2 AE7 AG13 IDE_DD2 E 2SC2411K_SC59
3
SATA2RXP DD2 IDE_DD3 @
AG6 SATA2TXN DD3 AF13
AH6 AD14 IDE_DD4
SATA2TXP DD4 IDE_DD5 H_THERMTRIP#
DD5 AC13
CLK_PCIE_SATA# AF1 AD12 IDE_DD6
14 CLK_PCIE_SATA# SATA_CLKN DD6
CLK_PCIE_SATA AE1 AC12 IDE_DD7
14 CLK_PCIE_SATA SATA_CLKP DD7
AE12 IDE_DD8
DD8 IDE_DD9
AH10 SATARBIASN DD9 AF12
R613 1 2 24.9_0402_1% SATARBIAS AG10 AB13 IDE_DD10
SATARBIASP DD10 IDE_DD11
10mils DD11 AC14
IDE_DD12
DD12 AF14
AH13 IDE_DD13
DD13 IDE_DD14
R612 1 2 4.7K_0402_5% IDE_ DIORDY IDE_ DIORDY AG16
IDE DD14 AH14
AC15 IDE_DD15
+3VS 30,31 IDE_DIORDY IORDY DD15
IDE_IRQ AH16
30,31 IDE_IRQ IDEIRQ
IDE_DDACK# AF16
30,31 IDE_DDACK# DDACK#
R611 1 2 8.2K_0402_5% IDE_IRQ IDE_DIOW# AH15 AE15 IDE_DDREQ
B 30,31 IDE_DIOW# DIOW# DDREQ IDE_DDREQ 30,31 B
IDE_DIOR# AF15
30,31 IDE_DIOR# DIOR#
ICH7_BGA652~D
SATA_ITX_DRX_N0 1 2 SATA_ITX_C_DRX_N0
C824 3900P_0402_50V7K SATA_ITX_C_DRX_N0 30
SATA_ITX_DRX_P0 1 2 SATA_ITX_C_DRX_P0
C823 3900P_0402_50V7K SATA_ITX_C_DRX_P0 30
close ICH7
1 2 SATA_DTX_C_IRX_N2
R248 1K_0402_5%
1 2 SATA_DTX_C_IRX_P2
R254 1K_0402_5%
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7-M(2/4)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom HBL50 LA-2921P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, November 11, 2005 Sheet 27 of 59
5 4 3 2 1
5 4 3 2 1
1
8.2K_0402_5% R656 R258
1
R609 1 2 PM_CLKRUN# 10_0402_5% 10_0402_5%
R325 R332 @ @
10K_0402_5% 2.2K_0402_5% 2.2K_0402_5%
2
R256 1 2 ICH_VGATE U48C
1 1
2
14,34,36,37 ICH_SMBCLK ICH_SMBCLK C22 AF19 C844 C406
D +3VALW ICH_SMBDATA SMBCLK GPIO21 / SATA0GP 10P_0402_50V8K 10P_0402_50V8K D
14,34,36,37 ICH_SMBDATA B22 SMBDATA GPIO19 / SATA1GP AH18
SMB
SATA
GPIO
10K_0402_5% LINKALERT# A26 AH19 @ @
R671 1 EC_SWI# ICH_SMLINK0 LINKALERT# GPIO36 / SATA2GP 2 2
2 B25 SMLINK0 GPIO37 / SATA3GP AE19 1 R608 2
ICH_SMLINK1 A25 100_0402_5%
10K_0402_5% SMLINK1
R352 1 2 ICH_SMLINK0
AC1 CLK_ICH_14M
CLK14 CLK_ICH_14M 14
Clocks
10K_0402_5% EC_SWI# A28 B2 CLK_ICH_48M
40 EC_SWI# RI# CLK48 CLK_ICH_48M 14
R359 1 2 ICH_SMLINK1
SB_SPKR A19
44 SB_SPKR SPKR
10K_0402_5% 39,41 SUS_STAT# SUS_STAT# A27 C20 SUS_CLK
R672 1 LINKALERT# ITP_DBRESET# SUS_STAT# SUSCLK
2 4 ITP_DBRESET# A22 SYS_RST#
SYS
B24 PM_SLP_S3#
SLP_S3# PM_SLP_S3# 40
150_0402_1% PM_BMBUSY# AB18 D23 SLP_S4#
R342 1 ITP_DBRESET# 6 PM_BMBUSY# GPIO0 / BM_BUSY# SLP_S4# SLP_S5#
2 SLP_S5# F22
SMBALERT# B23
1K_0402_5% GPIO11 / SMBALERT# SYS_PWROK R264
PWROK AA4 SYS_PWROK 6,43
POWER MGT
R314 1 2 ICH_PCIE_WAKE# 14 PM_STP_PCI#
PM_STP_PCI# AC20 GPIO18 / STPPCI# 1 2 10K_0402_5%
GPIO
PM_STP_CPU# AF21 AC22 PM_DPRSLPVR
14 PM_STP_CPU# GPIO20 / STPCPU# GPIO16 / DPRSLPVR PM_DPRSLPVR 6,56
8.2K_0402_5% PM_DPRSLPVR : Need to series
R321 2 1 PM_BATLOW# A21 C21 PM_BATLOW#
37 CP_PE# GPIO26 TP0 / BATLOW# a 500Ohm resistor to IMVP6
10K_0402_5% PROJECT_ID0 B21 C23 PBTN_OUT#
GPIO27 PWRBTN# PBTN_OUT# 40
R310 1 2 SPI_MOSI PROJECT_ID1 E23 GPIO28
LAN_RST# C19 PLT_RST# 6,26,31,34,39,40
10K_0402_5% PM_CLKRUN# AG18
R635 1 SPI_MISO 34,36,39 PM_CLKRUN# GPIO32 / CLKRUN# EC_RSMRST#
2 RSMRST# Y4 EC_RSMRST# 40
AC19 R277 10K_0402_5%
41 SB_INT_FLASH_SEL# GPIO33 / AZ_DOCK_EN#
10K_0402_5% 2005/09/05 IDE_HRESET# U2 1 2
31 IDE_HRESET# GPIO34 / AZ_DOCK_RST#
R311 1 2 SPI_CS#
ICH_PCIE_WAKE# F20 E20 EC_SCI#
34,36,37 ICH_PCIE_WAKE# WAKE# GPIO9 EC_SCI# 40 +3VALW
10K_0402_5% SERIRQ AH21 A20
C 32,39,40 SERIRQ SERIRQ GPIO10 ACIN 40,54 C
R348 1 2 SMBALERT# EC_THERM# AF20 F19 C451
40 EC_THERM# THRM# GPIO12
E19 EC_LID_OUT# 0.1U_0402_16V4Z 2 1
GPIO13 EC_LID_OUT# 40
GEN@ 10K_0402_5% 2 1 ICH_VGATE AD22 R4
6,14,56 VGATE VRMPWRGD GPIO14
R676 1 2 R255 0_0402_5% E22
GPIO15
5
R3 U18
GRA@ 10K_0402_5% GPIO24 EC_FLASH# SLP_S4#
AC21 GPIO D20 2
P
GPIO6 GPIO25 EC_FLASH# 41 B
R675 1 2 PROJECT_ID0 AC18 AD21 4
GPIO7 GPIO35 / SATAREQ# SATA_CLKREQ# 14 Y PM_SLP_S5# 40
EC_SMI# E21 AD20 SLP_S5# 1
40 EC_SMI# GPIO8 GPIO38 A
G
10K_0402_5% AE20
R674 1 PROJECT_ID1 GPIO39 NC7SZ08P5X_NL_SC70-5
2
3
ICH7_BGA652~D Need update symbol
100K_0402_5%
R262 1 2 PM_DPRSLPVR
@ 10K_0402_5%
R677 1 2 SUS_CLK U48D
PCIE_PTX_C_IRX_N1 F26 V26 DMI_MTX_IRX_N0
37 PCIE_PTX_C_IRX_N1 PERn1 DMI0RXN DMI_MTX_IRX_N0 6
PCIE_PTX_C_IRX_P1 F25 V25 DMI_MTX_IRX_P0
37 PCIE_PTX_C_IRX_P1 PERp1 DMI0RXP DMI_MTX_IRX_P0 6
PCI-EXPRESS
00 = Grapevine PCIE_PTX_C_IRX_N3 K26 AB26 DMI_MTX_IRX_N2
34 PCIE_PTX_C_IRX_N3 PERn3 DMI2RXN DMI_MTX_IRX_N2 6
PCIE_PTX_C_IRX_P3 K25 AB25 DMI_MTX_IRX_P2
34 PCIE_PTX_C_IRX_P3 PERp3 DMI2RXP DMI_MTX_IRX_P2 6
01 = Geneva 34 PCIE_ITX_C_PRX_N3 C831 2 1 8789@ 0.1U_0402_16V4Z PCIE_ITX_PRX_N3 J28 AA28 DMI_ITX_MRX_N2
PETn3 DMI2TXN DMI_ITX_MRX_N2 6
34 PCIE_ITX_C_PRX_P3 C830 2 1 8789@ 0.1U_0402_16V4Z PCIE_ITX_PRX_P3 J27 AA27 DMI_ITX_MRX_P2
PETp3 DMI2TXP DMI_ITX_MRX_P2 6
PCIE_PTX_C_IRX_N4 M26 AD25 DMI_MTX_IRX_N3
B 36 PCIE_PTX_C_IRX_N4 PERn4 DMI3RXN DMI_MTX_IRX_N3 6 B
PCIE_PTX_C_IRX_P4 M25 AD24 DMI_MTX_IRX_P3
36 PCIE_PTX_C_IRX_P4 PERp4 DMI3RXP DMI_MTX_IRX_P3 6
36 PCIE_ITX_C_PRX_N4 C829 2 1 MINI1@0.1U_0402_16V4Z PCIE_ITX_PRX_N4 L28 AC28 DMI_ITX_MRX_N3
PETn4 DMI3TXN DMI_ITX_MRX_N3 6
36 PCIE_ITX_C_PRX_P4 C828 2 1 MINI1@0.1U_0402_16V4Z PCIE_ITX_PRX_P4 L27 AC27 DMI_ITX_MRX_P3
PETp4 DMI3TXP DMI_ITX_MRX_P3 6
P26 AE28 CLK_PCIE_ICH#
PERn5 DMI_CLKN CLK_PCIE_ICH# 14
P25 AE27 CLK_PCIE_ICH
PERp5 DMI_CLKP CLK_PCIE_ICH 14
N28 PETn5
N27 C25 R673 24.9_0402_1% Within 500 mils
PETp5 DMI_ZCOMP DMI_IRCOMP
DMI_IRCOMP D25 1 2 +1.5VS
T25 PERn6
T24 F1 USB20_N0
PERp6 USBP0N USB20_N0 37
R28 F2 USB20_P0
PETn6 USBP0P USB20_P0 37
R27 G4 USB20_N1
PETp6 USBP1N USB20_N1 37
RP44 G3 USB20_P1
USBP1P USB20_P1 37
5 4 USB_OC#1 R2 H1 USB20_N2
+3VALW SPI_CLK USBP2N USB20_N2 37
6 3 USB_OC#2 SPI_CS# P6 H2 USB20_P2
SPI_CS# SPI USBP2P USB20_P2 37
7 2 USB_OC#3 P1 J4 USB20_N3
SPI_ARB USBP3N USB20_N3 36
8 1 USB_OC#4 J3 USB20_P3
USBP3P USB20_P3 36
SPI_MOSI P5 K1 USB20_N4
SPI_MOSI USBP4N USB20_N4 42
10K_1206_8P4R_5% SPI_MISO P2 K2 USB20_P4
SPI_MISO USBP4P USB20_P4 42
L4 USB20_N5
USBP5N USB20_N5 42
L5 USB20_P5
USBP5P USB20_P5 42
RP43 USB_OC#0 D3 M1 USB20_N6
37 USB_OC#0 OC0# USBP6N USB20_N6 42
5 4 USB_OC#6 USB_OC#1 C4 OC1# USB USBP6P M2 USB20_P6
USB20_P6 42
6 3 USB_OC#7 USB_OC#2 D5 OC2# USBP7N N4 USB20_N7
USB20_N7 36
7 2 USB_OC#5 USB_OC#3 D4 OC3# USBP7P N3 USB20_P7
USB20_P7 36
8 1 USB_OC#4 E5
USB_OC#5 OC4# R653 22.6_0402_1%
C3 OC5# / GPIO29
10K_1206_8P4R_5% USB_OC#6 A2 D2 USBRBIAS 1 2
USB_OC#7 OC6# / GPIO30 USBRBIAS#
B3 OC7# / GPIO31 USBRBIAS D1
Within 500 mils
A ICH7_BGA652~D A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7-M(3/4)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom HBL50 LA-2921P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, November 11, 2005 Sheet 28 of 59
5 4 3 2 1
5 4 3 2 1
+1.05VS
U48F U48E
A4 VSS[0] VSS[98] P28
ICH_V5REF_RUN G10 L11 0.1U_0402_16V4Z A23 R1
V5REF[1] Vcc1_05[1] VSS[1] VSS[99]
Vcc1_05[2] L12 B1 VSS[2] VSS[100] R11
AD17 V5REF[2] Vcc1_05[3] L14 1 B8 VSS[3] VSS[101] R12
Vcc1_05[4] L16 1 1 B11 VSS[4] VSS[102] R13
+1.5VS ICH_V5REF_SUS F6 L17 C426 C439 + C390 B14 R14
+5VS +3VS V5REF_Sus Vcc1_05[5] VSS[5] VSS[103]
Vcc1_05[6] L18 B17 VSS[6] VSS[104] R15
D 0.1U_0402_16V4Z 220U_D2_2VMR15 D
AA22 Vcc1_5_B[1] Vcc1_05[7] M11 B20 VSS[7] VSS[105] R16
2 2 2
1 AA23 Vcc1_5_B[2] Vcc1_05[8] M18 B26 VSS[8] VSS[106] R17
2
2
1 1 1 AB22 Vcc1_5_B[3] Vcc1_05[9] P11 B28 VSS[9] VSS[107] R18
R259 D11 C433 + C408 C449 C853 AB23 P18 C2 T6
Vcc1_5_B[4] Vcc1_05[10] 1U_0603_10V4Z VSS[10] VSS[108]
AC23 Vcc1_5_B[5] Vcc1_05[11] T11 C6 VSS[11] VSS[109] T12
100_0402_5% RB751V_SOD323 220U_D2_2VMR15 AC24 T18 C27 T13
2 2 2 2 Vcc1_5_B[6] Vcc1_05[12] VSS[12] VSS[110]
AC25 U11 D10 T14
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1U_0603_10V4Z 0.1U_0402_16V4Z P23 B13 H4 AA1
1 1 Vcc1_5_B[35] Vcc3_3[13] VSS[42] VSS[139]
R22 Vcc1_5_B[36] Vcc3_3[14] B16 1 1 1 H5 VSS[43] VSS[140] AA24
R23 Vcc1_5_B[37] Vcc3_3[15] B7 H24 VSS[44] VSS[141] AA25
C409
C413
C415
(1uF x1, 0.1uF x1) R24 Vcc1_5_B[38] Vcc3_3[16] C10 H27 VSS[45] VSS[142] AA26
R25 Vcc1_5_B[39] Vcc3_3[17] D15 H28 VSS[46] VSS[143] AB4
2 2 2
R26 Vcc1_5_B[40] Vcc3_3[18] F9 J1 VSS[47] VSS[144] AB6
+3VS T22 G11 J2 AB11
Vcc1_5_B[41] Vcc3_3[19] VSS[48] VSS[145]
T23 Vcc1_5_B[42] Vcc3_3[20] G12 J5 VSS[49] VSS[146] AB14
T26 Vcc1_5_B[43] Vcc3_3[21] G16 2005/09/12 J24 VSS[50] VSS[147] AB16
T27 Vcc1_5_B[44] J25 VSS[51] VSS[148] AB19
1 T28 Vcc1_5_B[45] VccRTC W5 +RTCVCC J26 VSS[52] VSS[149] AB21
C855 U22 K24 AB24
Vcc1_5_B[46] VSS[53] VSS[150]
0.1U_0402_16V4Z
1U_0402_6.3V4Z
U23 Vcc1_5_B[47] VccSus3_3[1] P7 +3VALW K27 VSS[54] VSS[151] AB27
0.1U_0402_16V4Z V22 1 1 1 1 K28 AB28
2 Vcc1_5_B[48] VSS[55] VSS[152]
C431
C437
V23 A24 C856 C854 L13 AC2
Vcc1_5_B[49] VccSus3_3[2] VSS[56] VSS[153]
W22 Vcc1_5_B[50] VccSus3_3[3] C24 L15 VSS[57] VSS[154] AC5
W23 D19 0.1U_0402_16V4Z 0.1U_0402_16V4Z L24 AC9
Vcc1_5_B[51] VccSus3_3[4] 2 2 2 2 VSS[58] VSS[155]
Y22 Vcc1_5_B[52] VccSus3_3[5] D22 L25 VSS[59] VSS[156] AC11
Place closely pin AG28 within 100mlis. Y23 Vcc1_5_B[53] VccSus3_3[6] G19 L26 VSS[60] VSS[157] AD1
M3 VSS[61] VSS[158] AD3
+1.5VS R226 +1.5VS_DMIPLLR +1.5VS_DMIPLL
B27 K3 M4 AD4
0.5_0603_1% R225 Vcc3_3[1] VccSus3_3[7] +3VALW VSS[62] VSS[159]
VccSus3_3[8] K4 1 1 M5 VSS[63] VSS[160] AD7
0.01U_0402_16V7K
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7-M(4/4)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B HBL50 LA-2921P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, November 11, 2005 Sheet 29 of 59
5 4 3 2 1
A B C D E
+3VS
2005/10/20
1
U26 R395
100K_0402_5%
PIDE_DD0 62 32 SATA_DTX_IRX_P0 @ R394
PIDE_DD1 HDD0 TXP SATA_DTX_IRX_N0 8040@ 0_0402_5%
64 31
2
PIDE_DD2 HDD1 TXM SATA_ITX_C_DRX_P0 SATA_RESET# IDE_RST#
PIDE_DD3
2
5
HDD2 SATA RXP 27
28 SATA_ITX_C_DRX_N0 SATA_ITX_C_DRX_P0 27
1
1 2
1
Parallel ATA
PIDE_DD12 3 39 T6 R805 1 2 @ 10K_0402_5%
PIDE_DD13 HDD12 T6 R800
1 HDD13 T7 40
PIDE_DD14 63 20 0_0402_5%
PIDE_DD15 HDD14 CNFG2 CNFG1 R406 1
61 HDD15 CNFG1 19 2 @ 10K_0402_5% 8040@
18 CNFG0 R397 1 2 @ 10K_0402_5%
2
CNFG0 ATAIOSEL R407 1
ATAIOSEL 21 2 8040@ 10K_0402_5%
PIDE_DA0 50 R411 1M_0402_5%
PIDE_DA1 HDA0 SATA_XTALI 8040@
51 HDA1 XTLIN/OSC 22
PIDE_DA2 49 23 SATA_XTALO 1 1 SATA SATA SATA
PIDE_CS0# HDA2 XTLOUT C498 C500
PIDE_CS1#
48 HCS0# 12P_0402_50V8J 12P_0402_50V8J
ICH7M SATA Bridge R Connector
47 HCS1#
26 R415 1 2 12.1K_0603_1% 8040@ 8040@
PIDE_HIOCS16# ISET 8040@ 2 2
52 HIOCS16# VDDIO_0 44
PIDE_INTRQ 53 4 +3VS
HINTRQ VDDIO_1
2
PIDE_DMACK# 54 9 +1.8VS
R798 PIDE_DIORDY HDMACK# VDD_0 +3VS
55 HIORDY VDD_1 41
10K_0402_5% PIDE_DIOR# 58 56
PIDE_DIOW# HDIOR# VDD_2
@ 59 HDIOW# VAA1 24
PIDE_DREQ 60 29 +1.8VS_VDDA 1 2
1
88SA8040_QFN64
2 SATA@ 2
8040@
SATA_DTX_R_IRX_N0 2 3 SATA_DTX_IRX_N0
+1.8VS +3VS SATA_DTX_R_IRX_P0 1 4 SATA_DTX_IRX_P0
RP46 0_0404_4P2R_5%
0.1U_0402_16V4Z 0.1U_0402_16V4Z
+3VS
Place closed to Connector
PIDE_DIORDY
SATA HDD Conn.
1 2
R419 8040@ 4.7K_0402_5% JP32
PIDE_R_RESET# 1 2 PIDE_RESET# 1
R807 8040@ 33_0402_5% SATA_ITX_C_R_DRX_P0 GND
2 HTX+
PIDE_DREQ 1 2 SATA_ITX_C_R_DRX_N0 3
R408 8040@ 5.6K_0402_5% HTX-
4 GND
PIDE_INTRQ 1 2 SATA_DTX_R_IRX_N0 5
R426 8040@ 10K_0402_5% SATA_DTX_R_IRX_P0 HRX-
6 HRX+
PIDE_DD7 1 2 7
R356 @ 10K_0402_5% GND
IDE_DD[0..15]
IDE_DD[0..15] 27,31
2005/09/04
3 IDE_DA[0..2] 8 3
IDE_DA[0..2] 27,31 +3VS VCC3.3
9 VCC3.3
10 VCC3.3
+5VS PIDE_DD2 1 2 IDE_DD2 PIDE_DIOR# 1 2 IDE_DIOR# 11
R713 PATA@ 0_0402_5% R729 PATA@ 0_0402_5% IDE_DIOR# 27,31 GND
12 GND
0.1U_0402_16V4Z 10U_0805_10V4Z PIDE_DD12 1 2 IDE_DD12 PIDE_DIOW# 1 2 IDE_DIOW# 13
R714 PATA@ 0_0402_5% R730 PATA@ 0_0402_5% IDE_DIOW# 27,31 GND
+5VS 14 VCC5
1 1 1 1 1 PIDE_DD3 1 2 IDE_DD3 PIDE_DREQ 1 2 IDE_DDREQ 15
C868 C869 C530 C531 C867 R715 PATA@ 0_0402_5% R731 PATA@ 0_0402_5% IDE_DDREQ 27,31 VCC5
16 VCC5
PIDE_DD11 1 2 IDE_DD11 PIDE_DD15 1 2 IDE_DD15 17
R716 PATA@ 0_0402_5% R732 PATA@ 0_0402_5% GND
18 RESERVED
2 2 2 2 2 PIDE_DD4 IDE_DD4 PIDE_DA1 IDE_DA1
1 2 1 2 19 GND
R717 PATA@ 0_0402_5% R733 PATA@ 0_0402_5% 20
1000P_0402_50V7K 1U_0603_10V4Z 10U_0805_10V4Z PIDE_DD10 IDE_DD10 PIDE_INTRQ IDE_IRQ VCC12
1 2 1 2 IDE_IRQ 27,31 21 VCC12
R718 PATA@ 0_0402_5% R734 PATA@ 0_0402_5% 22
PIDE_DD5 IDE_DD5 PIDE_DMACK# IDE_DDACK# VCC12
1 2 1 2
PATA HDD Conn. PIDE_DD9
R719 PATA@ 0_0402_5%
IDE_DD9 PIDE_DIORDY
R735 PATA@ 0_0402_5%
IDE_ DIORDY
IDE_DDACK# 27,31
OCTEK_SAT-22SG1G_NR
1 2 1 2 IDE_DIORDY 27,31
JP33 R720 PATA@ 0_0402_5% R736 PATA@ 0_0402_5%
PIDE_RESET# PIDE_DD6 IDE_DD6 PIDE_CS1# IDE_DCS3#
PIDE_DD7
1
3
1 2 2
4 PIDE_DD8
1
R721
2
PATA@ 0_0402_5%
1
R737
2
PATA@ 0_0402_5% IDE_DCS3# 27,31 (NEW)
PIDE_DD6 3 4 PIDE_DD9 PIDE_DD8 IDE_DD8 PIDE_CS0# IDE_DCS1#
PIDE_DD5
5 5 6 6
PIDE_DD10
1
R722
2
PATA@ 0_0402_5%
1
R738
2
PATA@ 0_0402_5% IDE_DCS1# 27,31 Change Library
7 7 8 8
PIDE_DD4 9 10 PIDE_DD11 PIDE_DD7 1 2 IDE_DD7 PIDE_DA2 1 2 IDE_DA2
PIDE_DD3 9 10 PIDE_DD12 R723 PATA@ 0_0402_5% R739 PATA@ 0_0402_5%
11 11 12 12
PIDE_DD2 13 14 PIDE_DD13 PIDE_RESET# 1 2 IDE_RST# PIDE_DA0 1 2 IDE_DA0
PIDE_DD1 13 14 PIDE_DD14 R724 PATA@ 0_0402_5% IDE_RST# 31 R740 PATA@ 0_0402_5%
15 15 16 16
PIDE_DD0 17 18 PIDE_DD15 PIDE_DD0 1 2 IDE_DD0
17 18 R725 PATA@ 0_0402_5%
19 19 20 20
PIDE_DREQ 21 22 PIDE_DD14 1 2 IDE_DD14
PIDE_DIOW# 21 22 R726 PATA@ 0_0402_5%
23 23 24 24
PIDE_DIOR# 25 26 PIDE_DD1 1 2 IDE_DD1 PIDE_LED# 1 2 IDE_LED#
4 PIDE_DIORDY 25 26 PCSEL 1 R727 PATA@ 0_0402_5% R435 PATA@ 0_0402_5% IDE_LED# 31,40 4
27 27 28 28 2
PIDE_DMACK# 29 30 R417 475_0402_1% PIDE_DD13 1 2 IDE_DD13 PIDE_PDIAG# 1 2 IDE_PDIAG#
PIDE_INTRQ 29 30 R728 PATA@ 0_0402_5% R428 PATA@ 0_0402_5% IDE_PDIAG# 31
31 31 32 32
PIDE_DA1 33 34 PIDE_PDIAG#
PIDE_DA0 33 34 PIDE_DA2
35 36
PIDE_CS0# 37
35 36
38 PIDE_CS1# For PATA HDD+ODD only
PIDE_LED# 37 38
39 39 40 40
41 42
+5VS
43
41 42
44
+5VS Security Classification Compal Secret Data Compal Electronics, Inc.
43 44
Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title
OCTEK_HDD-22SG1G_NR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SATA Bridge
Size Document Number Rev
(NEW) AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 30 of 59
A B C D E
A B C D E F G H
0.1U_0402_16V4Z 10U_0805_10V4Z
1 1 1 1 1
C207 C231
+3VS
C206 C205 C232
2 2 2 2 2 IDE_DD[0..15] C293
1 27,30 IDE_DD[0..15] 1
1 2 0.1U_0402_16V4Z
1000P_0402_50V7K 1U_0603_10V4Z 10U_0805_10V4Z IDE_DA[0..2]
27,30 IDE_DA[0..2]
5
U6
IDE_HRESET# 2
P
28 IDE_HRESET# B
4 IDE_RST#
Y IDE_RST# 30
PLT_RST# 1
6,26,28,34,39,40 PLT_RST# A
G
NC7SZ08P5X_NL_SC70-5
3
JP24 2005/10/20
1 1 2 2
3 3 4 4
IDE_RST# 5 6 IDE_DD8
IDE_DD7 5 6 IDE_DD9
7 7 8 8
IDE_DD6 9 10 IDE_DD10
IDE_DD5 9 10 IDE_DD11
11 11 12 12
IDE_DD4 13 14 IDE_DD12
IDE_DD3 13 14 IDE_DD13
15 15 16 16
IDE_DD2 17 18 IDE_DD14
IDE_DD1 17 18 IDE_DD15
19 19 20 20
IDE_DD0 21 22 IDE_DDREQ
21 22 IDE_DDREQ 27,30
23 24 IDE_DIOR#
23 24 IDE_DIOR# 27,30
IDE_DIOW# 25 26
27,30 IDE_DIOW# 25 26
IDE_ DIORDY 27 28 IDE_DDACK#
27,30 IDE_DIORDY 27 28 IDE_DDACK# 27,30
IDE_IRQ 29 30
27,30 IDE_IRQ 29 30
IDE_DA1 31 32 IDE_PDIAG# 1 2 R149 +5VS
IDE_DA0 31 32 IDE_DA2 100K_0402_5%
33 33 34 34
27,30 IDE_DCS1# IDE_DCS1# 35 36 IDE_DCS3# IDE_DCS3# 27,30
IDE_LED# 35 36
30,40 IDE_LED# 37 37 38 38
+5VS 39 39 40 40 +5VS
2 2
41 41 42 42
43 43 44 44
45 45 46 46
+5VS 1 2 IDE_CSEL 47 48
R133 @ 475_0402_1% 47 48 IDE_PDIAG#
49 49 50 50 IDE_PDIAG# 30
1 2
R134 475_0402_1% OCTEK_CDR-50JL1G
IDE_CSEL
(NEW)
Grounding for Master (When use SATA HDD)
Open or High for Slaver (Normal) IDE_LED#
+5VS 2 1
R146 100K_0402_5%
3 3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ODD & SATA HDD Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 31 of 59
A B C D E F G H
A B C D E
+S1_VCC +3VS
VPPD0
33 VPPD0
VPPD1
33 VPPD1
VCCD0#
+3VS 33 VCCD0#
40mil VCCD1#
33 VCCD1#
M13
M12
G13
N13
N12
D12
H11
S1_A[0..25]
G1
C8
N4
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
A7
B4
K2
F3
L9
L6
S1_A[0..25] 33
U22
1 1 1 1 1 1 1 S1_D[0..15]
VCCD1#
VCCD0#
VPPD1
VPPD0
VCCA2
VCCA1
VCC10
VCC9
VCC8
VCC7
VCC6
VCC5
VCC4
VCC3
VCC2
VCC1
S1_D[0..15] 33
C857 C863 C848 C861 C862 C850 C849
0.1U_0402_16V4Z
2 2 2 2 2 2 2
PCI_AD31 C2 B2 S1_D10
1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z PCI_AD30 AD31 CAD31/D10 S1_D9 1
C1 AD30 CAD30/D9 C3
PCI_AD29 D4 B3 S1_D1
PCI_AD28 AD29 CAD29/D1 S1_D8
D2 AD28 CAD28/D8 A3
PCI_AD27 D1 C4 S1_D0 +3VS
PCI_AD26 AD27 CAD27/D0 S1_A0
E4 AD26 CAD26/A0 A6
PCI_AD25 E3 D7 S1_A1
PCI_AD24 AD25 CAD25/A1 S1_A2
E2 AD24 CAD24/A2 C7 1 1
PCI_AD23 F2 A8 S1_A3 C472 C859
PCI_AD[0..31] PCI_AD22 AD23 CAD23/A3 S1_A4
26,34,36,38 PCI_AD[0..31] F1 AD22 CAD22/A4 D8
PCI_AD21 G2 A9 S1_A5 4.7U_0805_10V4Z 0.1U_0402_16V4Z
PCI_CBE#[0..3] PCI_AD20 AD21 CAD21/A5 S1_A6 2 2
26,34,36,38 PCI_CBE#[0..3] G3 AD20 CAD20/A6 C9
PCI_AD19 H3 A10 S1_A25
PCI_AD18 AD19 CAD19/A25 S1_A7
H4 AD18 CAD18/A7 B10
PCI_AD17 J1 D10 S1_A24
PCI_AD16 AD17 CAD17/A24 S1_A17
J2 AD16 CAD16/A17 E12
PCI_AD15 N2 F10 S1_IOWR#
AD15 CAD15/IOWR# S1_IOWR# 33
CLK_PCI_PCM CLK_SD_48M PCI_AD14 M3 E13 S1_A9
PCI_AD13 AD14 CAD14/A9 S1_IORD# +S1_VCC
N3 AD13 CAD13/IORD# F13 S1_IORD# 33
1
PCI_AD12 K4 F11 S1_A11
R393 R678 PCI_AD11 AD12 CAD12/A11 S1_OE#
M4 AD11 CAD11/OE# G10 S1_OE# 33
@ 10_0402_5% @ 10_0402_5% PCI_AD10 K5 G11 S1_CE2# 1 1
+3VS AD10 CAD10/CE2# S1_CE2# 33
PCI_AD9 L5 G12 S1_A10 C864 C860
PCI_AD8 AD9 CAD9/A10 S1_D15
M5 H12
2
SM_CD# PCI_AD7 AD8 CAD8/D15 S1_D7 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 2 1 1 K6 AD7 CAD7/D7 H10
R662 43K_0402_5% C485 C858 PCI_AD6 S1_D13 2 2
M6 AD6 CAD6/D13 J11
PCI_AD5 N6 J12 S1_D6
@ 15P_0402_50V8J @ 15P_0402_50V8J PCI_AD4 AD5 CAD5/D6 S1_D12
M7 AD4 CAD4/D12 K13
2 2 PCI_AD3 S1_D5
N7 J10
PCI Interface
PCI_AD2 AD3 CAD3/D5 S1_D11
L7 AD2 CAD2/D11 K10
CARDBUS
PCI_AD1 K7 K12 S1_D4
PCI_AD0 AD1 CAD1/D4 S1_D3
N8 AD0 CAD0/D3 L13
2 PCI_CBE#3 S1_REG# 2
E1 CBE3# CCBE3#/REG# B7 S1_REG# 33
PCI_CBE#2 J3 A11 S1_A12
PCI_CBE#1 CBE2# CCBE2#/A12 S1_A8
N1 CBE1# CCBE1#/A8 E11
PCI_CBE#0 N5 H13 S1_CE1#
CBE0# CCBE0#/CE1# S1_CE1# 33
PCI_RST# G4 B9 S1_RST
26,34,36,37,38 PCI_RST# PCIRST# CRST#/RESET S1_RST 33
26,34,36,38 PCI_FRAME# J4 B11 S1_A23
FRAME# CFRAME#/A23 S1_A15
26,34,36,38 PCI_IRDY# K1 IRDY# CIRDY#/A15 A12
26,34,36,38 PCI_TRDY# K3 A13 S1_A22
TRDY# CTRDY#/A22 S1_A21
26,34,36,38 PCI_DEVSEL# L1 DEVSEL# CDEVSEL#/A21 B13
L2 C12 S1_A20
26,34,36,38 PCI_STOP# STOP# CSTOP#/A20
L3 C13 S1_A14
26,34,36,38 PCI_PERR# PERR# CPERR#/A14
M1 A5 S1_WAIT#
26,34,36 PCI_SERR# SERR# CSERR#/WAIT# S1_WAIT# 33
26,34,36,38 PCI_PAR M2 D13 S1_A13
PCI_REQ#2 PAR CPAR/A13 S1_INPACK#
26 PCI_REQ#2 A1 PCIREQ# CREQ#/INPACK# B8 S1_INPACK# 33
B1 C11 S1_WE#
26 PCI_GNT#2 PCIGNT# CGNT#/WE# S1_WE# 33
CLK_PCI_PCM H1 B12 1 2 S1_A16
14 CLK_PCI_PCM PCICLK CCLK/A16 R416 33_0402_5%
L8 C5 S1_BVD1
RIOUT#_PME# CSTSCHG/BVD1_STSCHG# S1_BVD1 33
+3VS 1 2 L11 D5 S1_WP
SUSPEND# CCLKRUN#/WP_IOIS16# S1_WP 33
R663 10K_0402_5%
PCI_AD20 1 2 F4 D11 S1_A19
R680 100_0402_5% IDSEL CBLOCK#/A19
K8 D6 S1_RDY# S1_CD2# S1_CD1#
26 PCI_PIRQA# MFUNC0 CINT#/READY_IREQ# S1_RDY# 33
R368 1 2 SD_PULLHIGH N9 2 2
33 MS_PWREN# MFUNC1
0_0402_5% K9 M9 PCM_SPK# C506 C487
26 PCI_PIRQB# MFUNC2 SPKROUT PCM_SPK# 44
@ N10 B5 S1_BVD2
28,39,40 SERIRQ MFUNC3 CAUDIO/BVD2_SPKR# S1_BVD2 33
SM_CD# L10 10P_0402_50V8K 10P_0402_50V8K
5IN1_LED# MFUNC4 S1_CD2# 1 1
40 5IN1_LED# N11 MFUNC5 CCD2#/CD2# A4 S1_CD2# 33
M11 L12 S1_CD1#
MFUNC6 CCD1#/CD1# S1_CD1# 33
SDOC# J9 D9 S1_VS2
33 SDOC# MFUNC7 CVS2/VS2# S1_VS2 33
C6 S1_VS1
3 CVS1/VS1 S1_VS1 33 3
A2 S1_D2
PCI_RST# CRSV3/D2 S1_A18
M10 GRST# CRSV2/A18 E10
MFUNC5[3:0] = (0 1 0 1) J13 S1_D14
CRSV1/D14
MFUNC5[4] = 1
E7
SD/MMC/MS/SM H7
+VCC_SD VCC_SD MSINS# MS_INS# 33
J8 XD_PWREN#
MSPWREN#/SMPWREN# XD_PWREN# 33
SD_CD# E8 H8 MSBS_XDD1
33 SD_CD# SDCD# MSBS/SMDATA1 MSBS_XDD1 33
SD_WP# F8 E9 MS_CLK R683 1 4IN1@ 2 33_0402_5%
33 SD_WP# SDWP/SMWPD# MSCLK/SMRE# MSCLK_XDRE# 33
SD_PWREN# G7 G9 MSD0_XDD2
33 SD_PWREN# SDPWREN33# MSDATA0/SMDATA2 MSD0_XDD2 33
H9 MSD1_XDD6
MSDATA1/SMDATA6 MSD1_XDD6 33
CLK_SD_48M H5 G8 MSD2_XDD5
14 CLK_SD_48M SDCLKI MSDATA2/SMDATA5 MSD2_XDD5 33
F9 MSD3_XDD3
MSDATA3/SMDATA3 MSD3_XDD3 33
R681 1 4IN1@ 2 33_0402_5% SD_CLK F6
33 SDCK_XDWE# SDCLK/SMWE#
SDCM_XDALE E5
33 SDCM_XDALE SDCMD/SMALE
SDDA0_XDD7 E6 H6
33 SDDA0_XDD7 SDDAT0/SMDATA7 SMBSY# XD_BSY# 33
SDDA1_XDD0 F7 J7 XD_CD#
33 SDDA1_XDD0 SDDAT1/SMDATA0 SMCD# XD_CD# 33
SDDA2_XDCL F5 J6 XD_WP#
33 SDDA2_XDCL SDDAT2/SMCLE SMWP# XD_WP# 33
SDDA3_XDD4 G6 J5
33 SDDA3_XDD4 SDDAT3/SMDATA4 SMCE# XD_CE# 33
2
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
G5 GND_SD R661
2.2K_0402_5%
CB714_LFBGA169 4IN1@
D3
H2
L4
M8
K11
F12
C10
B6
4IN1@
1
**CB714 use B0 version
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cardbus Controller CB714
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 32 of 59
A B C D E
A B C D E
PCMCIA Socket 1
JP9
GND
35 GND
S1_D3 2
S1_CD1# DATA3
32 S1_CD1# 36 CD1#
S1_D4 3
+S1_VCC S1_D11 DATA4
37
PCMCIA Power Control S1_D5
S1_D12
4
38
DATA11
DATA5
S1_D6 DATA12
1 1 5 DATA6
+S1_VCC C502 C494 S1_D13 39
S1_D7 DATA13
6 DATA7
10U_0805_10V4Z 0.1U_0402_16V4Z S1_D14 40
2 2 S1_CE1# DATA14
1 U23
40mil 32 S1_CE1# S1_D15
7 CE1# 1
41 DATA15
13 S1_A10 8
VCC S1_CE2# ADD10
VCC 12 32 S1_CE2# 42 CE2#
9 11 S1_OE# 9
12V VCC +S1_VPP 32 S1_OE# S1_VS1 OE#
32 S1_VS1 43 VS1#
40mil S1_A11 10
+5VS +S1_VPP S1_IORD# ADD11
32 S1_IORD# 44 IORD#
W=40mil 1 S1_A9 11
S1_IOWR# ADD9
VPP 10 32 S1_IOWR# 45 IOWR#
1 1 C522 1 1 S1_A8 12
C479 0.1U_0402_16V4Z C493 C520 S1_A17 ADD8
5 5V 46 ADD17
C480 2 S1_A13
6 5V 13 ADD13
10U_0805_10V4Z 0.1U_0402_16V4Z S1_A[0..25] S1_A18 47
2 2 2 2 32 S1_A[0..25] ADD18
0.1U_0402_16V4Z 1 VCCD0# 10U_0805_10V4Z S1_A14 14
VCCD0 VCCD0# 32 S1_D[0..15] ADD14
2 VCCD1# 32 S1_D[0..15] S1_A19 48
+3VS VCCD1 VCCD1# 32 ADD19
15 VPPD0 S1_WE# 15
VPPD0 VPPD0 32 32 S1_WE# WE#
14 VPPD1 S1_A20 49
VPPD1 VPPD1 32 ADD20
W=40mil S1_RDY# 16
32 S1_RDY# S1_A21 READY
3 3.3V 50 ADD21
1 1 4 3.3V OC 8 +S1_VCC 17 VCC
SHDN
C482 C481 51
GND
+S1_VCC VCC
+S1_VPP 18 VPP
10U_0805_10V4Z +S1_VPP 52 VPP
1
2 2
0.1U_0402_16V4Z CP2211FD3_SSOP16 S1_OE# S1_A16
1 2 +S1_VCC 19
7
16
G528_SO8 2
10U_0805_10V4Z 2
(HDQ70)
1
XD_CE# MS-VCC
1 2
2
TAITW_R007-520-L3
4IN1@
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCMCIA Socket
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 33 of 59
A B C D E
5 4 3 2 1
+3VALW
+2.5V_LAN +3V_LAN +LAN_18_12
0.1U_0402_16V4Z 0.1U_0402_16V4Z
0.1U_0402_16V4Z 0.1U_0402_16V4Z +3VALW 1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1 1 1 R224 4401@ 0_0805_5%
C379 C359 C355 C350 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C317 C311 C384 +3VS 1 2 C363 C319 C333 C328 C341 C318 C312 C347 C346 C345 C303
8789@ 8789@ 8789@ R223 5789@ 0_0805_5%
2 2 2 2
2 2 2
5789 only 2 2 2 2 2 2 2 2 2 2 2
4.7U_0805_10V4Z 0.1U_0402_16V4Z
0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
PCI_AD0 R237 1 2 4401@ 0_0402_5% AD0
R216 5787@ 0_0402_5%
PCI_AD1 R232
1
1
2
2 4401@ 0_0402_5% AD1 +REGOUT25 R214 1 2 4401@ 0_0603_5% +3VALW
For BCM5789 +3VALW
D R221 5787@ 0_0402_5% D
1 2
PCI_AD2 R231 1 2 4401@ 0_0402_5% AD2 2 1 R220 1 2 8789@ 0_0603_5% +2.5V_LAN 1K_0402_5% 1 2
R230 5787@ 0_0402_5% C387 100U_B2_4VM 8789@
+
1 2
For BCM4401E
1
PCI_AD3 R228 1 2 4401@ 0_0402_5% AD3 8789@ C315
R217 1 2 5787@ 0_0402_5% Colsed to M14 +3VALW R187 R188 R189 0.1U_0402_16V4Z
PCI_AD4 R229 1 2 4401@ 0_0402_5% AD4 1 2 U8 1K_0402_5% 1K_0402_5%
R218 1 2 5787@ 0_0402_5% C361 0.1U_0402_16V4Z SPROM_CS 1 8 8789@ 8789@ 8789@
PCI_AD5 R236 4401@ 0_0402_5% AD5 U13A SPROM_CLK CS VCC
1 2 2 7 1
2
R215 5787@ 0_0402_5% SPROM_DOUT SK NC C301 U7
1 2 3 DI NC 6
AD0 M7 E13 LAN_MIDI3+ SPROM_DIN 4 5 0.1U_0402_16V4Z 8 1
AD0/(NC) DC_E13/(TRD3+) LAN_MIDI3+ 35 DO GND VCC A0
AD1 N7 E14 LAN_MIDI3- 4401@ SPROM_WP 7 2
AD1/(NC) DC_E14/(TRD3-) LAN_MIDI3- 35 2 WP A1
PCI_AD11 R783 1 2 4401@ 0_0402_5% AD11 AD2 P7 D13 LAN_MIDI2+ AT93C46-10SI-2.7_SO8 SPROM_CLK 6 3
AD2/(NC) DC_D13/(TRD2+) LAN_MIDI2+ 35 SCL NC
PCI_AD14 R784 1 2 4401@ 0_0402_5% AD14 AD3 P5 D14 LAN_MIDI2- 4401@ SPROM_CS 5 4
PCI_AD16 R785 1 2 4401@ 0_0402_5% AD16 AD4 N5
AD3/(NC) BCM4401E DC_D14/(TRD2-)
C13 LAN_MIDI1+
LAN_MIDI2- 35 SDA GND
AD4/(NC) TRD1+ LAN_MIDI1+ 35
AD5 LAN_MIDI1- AT24C256_SO8
L23 PCI_AD6
M5
P4
AD5/(NC) /(BCM5789) TRD1- C14
B13 LAN_MIDI0+
LAN_MIDI1- 35
8789@
AD6/(NC) TRD0+ LAN_MIDI0+ 35
BLM18AG601SN1D_0603 2005/10/20 PCI_AD7 N4 B14 LAN_MIDI0-
AD7/(NC) TRD0- LAN_MIDI0- 35
+3VALW 1 2 +LAN_XTALVDD PCI_AD8 P3 U13B R806 5787@
4401@ PCI_AD9 AD8/(NC) +3VALW
1 N3 AD9/(NC) Place closed to L14 & K14 1 2 4.7K_0402_5%
L22 C336 PCI_AD10 +PLLVDD
BLM18AG601SN1D_0603 AD11
N2
M1
AD10/(NC) PLLVDD/(GPHY_PLLVDD) G14
C360 1 2 0.1U_0402_16V4Z
+LAN_18_12 B8
E5
VDDC_B8 BCM4401E DC_A9/(NC) A9
B9
0.1U_0402_16V4Z PCI_AD12 AD11/(NC) VDDC_E5 DC_B9/(NC)
+2.5V_LAN 1 2
8789@ 2 PCI_AD13
M2
M3
AD12/(NC)
L14 C354 1 2 4.7U_0805_10V4Z
E6
E7
VDDC_E6 /(BCM5789) DC_C10/(NC) C10
C12 C12 +3VALW
AD14 AD13/(NC) REGSUP18_1/(REGSUP25) VDDC_E7 DC_C12/(CS#) D9
L1 AD14/(NC) REGSUP18_0/(REGSUP12) K14 E8 VDDC_E8 DC_D9/NC) D9
3
L19 PCI_AD15 L2 Q4 E9 D10 D10 1 2
BLM18AG601SN1D_0603 AD16 AD15/(NC) VDDC_E9 DC_D10/(NC) C388 5787@
K1 AD16/(NC) E10 VDDC_E10 DC_F11/(SO) F11
+3VALW 1 2 +LAN_BIASVDD PCI_AD17 E3 J13 1 MMJT9435T1G_SOT223 F5 K9 0.1U_0402_16V4Z
4401@ PCI_AD18 AD17/(NC) DC_J13/(REGCTL12) 8789@ VDDC_F5 DC_K9 5787@
1 D1 AD18/(NC) F10 VDDC_F10 DC_K10 K10 1 2
L18 C314 PCI_AD19 D2 +LAN_18_12 G4 L5 R250 4.7K_0402_5% C389 5787@
BLM18AG601SN1D_0603 PCI_AD20 AD19/(NC) VDDC_G4 DC_L5 4.7U_0805_10V4Z
D3 J14 J4 L7 1 2
2
4
0.1U_0402_16V4Z PCI_AD21 AD20/(NC) REG18OUT/(REGSEN12) VDDC_J4 DC_L7/(NC)
+2.5V_LAN 1 2 C1 AD21/(NC) J5 VDDC_J5 DC_L8 L8
4
8789@ 2 PCI_AD22 Q5
B1 AD22/(NC) 1 1 J10 VDDC_J10 DC_H11 H11
C PCI_AD23 +REGOUT25 C348 C352 MBT35200MT1G_TSOP6 C
B2 AD23/(NC) REGSUP18/(REGOUT25) M14 K4 VDDC_K4 DC_L11 L11
PCI_AD[0..31] PCI_AD24 D4 K5 L12 5787@
26,32,36,38 PCI_AD[0..31] AD24/(NC) VDDC_K5 DC_L12/(NC)
PCI_AD25 A5 0.1U_0402_16V4Z 10U_0805_10V4Z K6 L13 CTL25 3
PCI_AD26 AD25/(NC) SPROM_CS 2 2 VDDC_K6 DC_L13/(NC) R251 5787@ 0_0402_5%
B5 AD26/(NC) SPROM_CS/(EEDATA) L10 K7 VDDC_K7 DC_M9 M9
+3VALW R177 1 2 5787@ 4.7K_0402_5% SERR# PCI_AD27 B6 K11 SPROM_CLK K8 M10 1 2
PCI_AD28 AD27/(NC) SPROM_CLK/(EECLK) SPROM_DOUT VDDC_K8 DC_M10/(NC)
C6 J11 M11
1
2
5
6
R808 1 AD28/(NC) SPROM_DOUT/(NC) DC_M11
+3VS 2 5789@ 4.7K_0402_5% PCI_AD29 C7 AD29/(NC) SPROM_DIN/(NC) N13 SPROM_DIN
DC_M12/(NC) M12
PCI_AD30 C8 +3V_LAN A7 M13 R234 5787@ 0_0402_5%
R212 1 CBE#1 PCI_AD31 AD30/(NC) VDDIOPCI_A7 DC_M13/(NC)
+3VS 2 @ 1K_0402_5% C9 AD31/(NC) B3 VDDIOPCI_B3 DC_N11/(NC) N11 1 2
J12 R181 1 2 1K_0402_5% +3VALW 2 1 C376 C5 N14 R233 5787@ 0_0402_5%
VAUX_PRSNT R168 1 VDDIOPCI_C5 DC_N14/(NC)
GPIO0/(GPIO0_TST_CLKOUT) G12 2 @ 10K_0402_5% E1 VDDIOPCI_E1 DC_P11/(NC) P11 1 2
M4 H13 SPROM_WP 4.7U_0805_10V4Z E4 P14
26,32,36,38 PCI_CBE#0 CBE0#/(NC) GPIO1 VDDIOPCI_E4 DC_P14/(NC)
R213 1 2 4401@ 0_0402_5% CBE#1 L3 G13 R197 1 2 10K_0402_5% 2 1 C351 G1
26,32,36,38 PCI_CBE#1 CBE1#/(NC) DC_G13/(GPIO2) VDDIOPCI_G1
F3 8789@ K3
26,32,36,38 PCI_CBE#2 CBE2#/(NC) VDDIOPCI_K3
R172 1 2 4401@ 0_0402_5% CBE#3 C4 0.1U_0402_16V4Z L4 B4 +REGOUT25
26,32,36,38 PCI_CBE#3 CBE3#/(NC) VDDIOPCI_L4 VSS_B4
LINK_LED10/(LINKLED#) A11 LAN_LINK# 35 2 1 C358 P2 VDDIOPCI_P2 VSS_B7 B7
PCI_AD17 1 2 LAN_IDSEL A4 B11 B12
R179 4401@ 100_0402_5% IDSEL/(NC) LINK_LED100/(SPD100LED#) R180 1 VSS_B12
COL_LED/(SPD1000LED#) A12 2 8789@ 0_0402_5% 0.1U_0402_16V4Z
VSS_E2 E2
26,32,36,38 PCI_FRAME# F2 FRAME#/(NC) ACT_LED/(TRAFFICLED#) B10 LAN_ACTIVITY# 35 2 1 C324 P1 VESD1 VSS_F6 F6
26,32,36,38 PCI_IRDY# F1 IRDY#/(NC) G2 VESD2 VSS_F7 F7 Change Q5 P/N:SB000004M10
G3 0.1U_0402_16V4Z A1 F8
26,32,36,38 PCI_TRDY# TRDY#/(NC) VESD3 VSS_F8
R206 1 2 4401@ 0_0402_5% DEVSEL# H3 D7 TCK R166 1 2 4401@ 4.7K_0402_5% F9
26,32,36,38 PCI_DEVSEL# DEVSEL#/(NC) TCK VSS_F9
26,32,36,38 PCI_STOP# H1 STOP#/(NC) TDI H12 VSS_G5 G5
R211 1 2 4401@ 0_0402_5% PERR# J2 D6 +3VALW D11 G6
26,32,36,38 PCI_PERR# PERR#/(ATTN_IND#) TDO VDDIO_D11 VSS_G6
R176 1 2 4401@ 0_0402_5% SERR# A2 C11 TMS R184 1 2 5789@ 4.7K_0402_5% G11 G7
26,32,36 PCI_SERR# SERR#/(ATTN_BTTN#) TMS VDDIO_G11 VSS_G7
J1 D12 TRST# R167 1 2 4.7K_0402_5% K12 G8
26,32,36,38 PCI_PAR PAR/(NC) TRST# VDDIO_K12 VSS_G8
CLK_PCI_LAN A3 G9
14 CLK_PCI_LAN PCI_CLK/(NC) VSS_G9
VSS_G10 G10
R204 1 2 4401@ 0_0402_5% H14 +LAN_XTALVDD H5
26 PCI_PIRQF# R242 1 XTALVDD VSS_H5
26,32,36,37,38 PCI_RST# 2 4401@ 0_0402_5% LAN_INTA# H2 INTA#/(PWR_IND#) XTALO N12 XTALO R219 1 2 200_0402_5% LAN_XTALO +AVDDL F12 AVDD_F12/(AVDDL) VSS_H6 H6
R243 1 2 8789@ 0_0402_5% LAN_RESET# C2 P12 LAN_XTALI F13 H7
6,26,28,31,39,40 PLT_RST# PCI_RST#/(PERST#) XTALI AVDD_F13/(AVDDL) VSS_H7
J3 +PCIE_PLLVDD M8 H8
B 26 PCI_GNT#3 GNT#/(NC) DC_M8/(PCIE_PLLVDD) VSS_H8 B
C3 +PCIE_SDSVDD M6 H9
26 PCI_REQ#3 REQ#/(NC) DC_M6/(PCIE_SDS_VDD) VSS_H9
PM_CLKRUN# H4 E12 H10
28,36,39 PM_CLKRUN# CLKRUN#/(NC) EEDATA_PXE/(SI) VSS_H10
26,36,40 LAN_PME# 2005/09/21 R175 1 2 0_0402_5% A6 PME#/(WAKE#) EECLK_PXE/(SCLK) E11 VSS_J6 J6
R182 1 2 @ 0_0402_5% +2.5V_LAN A8 J7
28,36,37 ICH_PCIE_WAKE# DC_A8/(VDDP) VSS_J7
D5 DC_D5/(VDDP) VSS_J8 J8
28 PCIE_PTX_C_IRX_P3 C381 1 2 8789@ 0.1U_0402_16V4Z PCIE_PTX_IRX_P3 N6 L9 P13 J9
C380 1 PCIE_PTX_IRX_N3 NC_N6/(PCIE_TXDP) EXT_POR/(DC) DC_P13/(VDDP) VSS_J9
28 PCIE_PTX_C_IRX_N3 2 8789@ 0.1U_0402_16V4Z P6 NC_P6/(PCIE_TXDN) VREF/(NC) K13 VSS_K2 K2
L6 R171 1 2 10K_0402_5% +AVDD_A13 A13 N1
PCIE_ITX_C_PRX_P3 TEST_MODE/(LOW_PWR) DC_A13/(AVDD) VSS_N1
28 PCIE_ITX_C_PRX_P3 P10 RESERVED_P10/(PCIE_RXDP) VSS_N9 N9
PCIE_ITX_C_PRX_N3 N10 D8 R174 1 2 5789@ 4.7K_0402_5% +AVDD_F14 F14 P9
28 PCIE_ITX_C_PRX_N3 RESERVED_N10/(PCIE_RXDN) DC_D8/(PCIE_TST) DC_F14/(AVDD) VSS_P9
14 CLK_PCIE_LAN N8 RESERVED_N8/(REFCLK+)
CLK_PCI_LAN P8 A14 +LAN_BIASVDD BCM4401E_BCM5789
14 CLK_PCIE_LAN# RESERVED_P8/(REFCLK-) BIASVDD
5789 only 4401@
1
1
C302 L26 L17
18P_0402_50V8J L21 BLM18AG601SN1D_0603 BLM18AG601SN1D_0603
@ BLM18AG601SN1D_0603 Y1 +LAN_18_12 1 2 +PCIE_PLLVDD +2.5V_LAN 1 2 +AVDD_A13
2 +AVDDL LAN_XTALI LAN_XTALO 8789@ 8789@
+LAN_18_12 1 2 1 2 1 1 1
1 1 C400 C385 C313
C322 C320 1 25MHZ_20PF_6X25000017 1 8789@ 8789@ 8789@
(SA00000OD10) (SA00000SZ00) (SA00000YJ00) 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
4.7U_0805_10V4Z 0.47U_0603_16V4Z C382 C383 2 2 2
2 2 27P_0402_50V8J 27P_0402_50V8J
2 2 L25 L20
PIN 4401E(10/100 LAN) 5789(10/100/1000 LAN) 5787(10/100/1000 LAN)
L24 BLM18AG601SN1D_0603 BLM18AG601SN1D_0603
RDAC 1.27K 1.24K 1.24K BLM18AG601SN1D_0603 +LAN_18_12 1 2 +PCIE_SDSVDD +2.5V_LAN 1 2 +AVDD_F14
A +PLLVDD 8789@ 8789@ A
+LAN_18_12 1 2 1 1 1
1 1 C378 C377 C327
C326 C330 8789@ 8789@ 8789@
BOM structure 4401E(10/100 LAN) 5789(10/100/1000 LAN) 5787(10/100/1000 LAN) 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
4.7U_0805_10V4Z 0.1U_0402_16V4Z 2 2 2
2 2
4401@ Stuff No_Stuff No_Stuff
5789@ No_Stuff Stuff No_Stuff Security Classification Compal Secret Data Compal Electronics, Inc.
5787@ No_Stuff No_Stuff Stuff Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title
8789@ No_Stuff Stuff Stuff THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN BCM4401E/Jade15
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
@ No_Stuff No_Stuff No_Stuff B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 34 of 59
5 4 3 2 1
5 4 3 2 1
1 2
1 1
GbE Transformer: GST5009 (SP050005610)
C287 C288 C932
0.1U_0402_16V4Z 0.1U_0402_16V4Z 10/100 Transformer : TST1284-LF (SP050001X10) 220P_0402_50V7K
5789@ 5789@ JP23
2 2 +2.5V_LAN +3VALW LAN_ACTIVITY#
34 LAN_ACTIVITY# 12 Amber LED-
1
MBK1608301YZF_0603 RJ45_MIDI3- 8 PR4-
1
2
PR2-
2
1 24 RJ45_MIDI2- 5
LAN_MIDI3- TCT1 MCT1 RJ45_MIDI3- PR3-
34 LAN_MIDI3- 2 TD1+ MX1+ 23
34 LAN_MIDI3+ LAN_MIDI3+ 3 22 RJ45_MIDI3+ RJ45_MIDI2+ 4
TD1- MX1- PR3+
4 21 RJ45_MIDI1+ 3
LAN_MIDI2- TCT2 MCT2 RJ45_MIDI2- PR2+
34 LAN_MIDI2- 5 TD2+ MX2+ 20
34 LAN_MIDI2+ LAN_MIDI2+ 6 19 RJ45_MIDI2+ RJ45_MIDI0- 2
TD2- MX2- PR1-
SHLD2 14
7 18 RJ45_MIDI0+ 1
LAN_MIDI1- TCT3 MCT3 RJ45_MIDI1- PR1+
34 LAN_MIDI1- 8 TD3+ MX3+ 17 SHLD1 13
34 LAN_MIDI1+ LAN_MIDI1+ 9 16 RJ45_MIDI1+ LAN_LINK# 10
TD3- MX3- 34 LAN_LINK# Green LED-
10 TCT4 MCT4 15 +3VALW 2 1R155 2 1 300_0402_5% 9 Green LED+
34 LAN_MIDI0- LAN_MIDI0- 11 14 RJ45_MIDI0- L56
LAN_MIDI0+ TD4+ MX4+ RJ45_MIDI0+ MBK1608301YZF_0603 SUYIN_100073FR012S100ZL
34 LAN_MIDI0+ 12 TD4- MX4- 13
1 2
1
1
49.9_0402_1% 49.9_0402_1% 0.1U_0402_16V4Z 0.5u_GST5009 220P_0402_50V7K
49.9_0402_1% 49.9_0402_1% 0189@ 4401@
0189@ 0189@ 0189@ R147 R145 RJ45_GND 1 2 LANGND
2
1 1 1 1 75_0402_1% 75_0402_1% 1 1
C258 C245 C188 C215 C284
2
1 1 1000P_1206_2KV7K C296 C298
C286 C285 0.1U_0402_16V4Z 4.7U_0805_10V4Z
0189@ 0189@ 2 2 2 2 2 2
B 0.1U_0402_16V4Z 0.1U_0402_16V4Z B
2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
RJ45_TER2
RJ45_TER3
RJ45_MIDI3+ R141 1 2 4401@ 0_0402_5%
RJ45_MIDI3- R137 1 2 4401@ 0_0402_5%
RJ45_GND
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN Magnetic & RJ45/RJ11
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 35 of 59
5 4 3 2 1
A B C D E
+3VALW
+5VS +3VS
1 1 1 1 1 1
W=40mils C14 C605 C603 C602 C604 C601
0.1U_0402_16V4Z 1000P_0402_50V7K 0.1U_0402_16V4Z MINI1@ MINI1@ MINI1@ MINI1@ MINI1@ MINI1@
4.7U_0805_10V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2
1 1 1 1 1 1 1 1 1 1 1
C797
C794 C393 C392 C798 C800 C801 C394 C796 C795 C792
10U_0805_10V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2 2 2 2 JP17
ICH_PCIE_WAKE# 1 2 +3VS
1 1000P_0402_50V7K 28,34,37 ICH_PCIE_WAKE# 1 2 1
1000P_0402_50V7K 1000P_0402_50V7K 0.1U_0402_16V4Z WLAN_BT_DATA 3 4
WLAN_BT_CLK 3 4
5 5 6 6 +1.5VS
14 MINI1_CLKREQ# 7 7 8 8
9 9 10 10
14 CLK_PCIE_MINI1# 11 11 12 12
14 CLK_PCIE_MINI1 13 13 14 14
15 15 16 16
17 17 18 18
PCI_AD[0..31] 2005/09/05 19 20 MINI1_OFF#
PCI_AD[0..31] 26,32,34,38 19 20 MINI1_OFF# 40
21 22 PLT_RST_BUF#
21 22 PLT_RST_BUF# 25,26,39
28 PCIE_PTX_C_IRX_N4 23 23 24 24 +3VALW
JP28 25 26
TIP RING 28 PCIE_PTX_C_IRX_P4 25 26
1 1 2 2 27 27 28 28
29 30 ICH_SMBCLK ICH_SMBCLK 14,28,34,37
KEY KEY 29 30
3 4 28 PCIE_ITX_C_PRX_N4 31 32 ICH_SMBDATA ICH_SMBDATA 14,28,34,37
3 4 31 32
5 5 6 6 28 PCIE_ITX_C_PRX_P4 33 33 34 34
7 7 8 8 35 35 36 36
9 9 10 10 37 37 38 38
D10
11 11 12 12 39 39 40 40
WL_OFF# 1 2 13 14 41 42
40 WL_OFF# 13 14 41 42
RB751V_SOD323 15 16 43 44 (MINI1_LED#)
15 16 43 44
26 PCI_PIRQH# 17 17 18 18 W=40mils +5VS 45 45 46 46
+3VS W=40mils 19 19 20 20 PCI_PIRQG# 26 47 47 48 48
S_YIN 21 22 S_CIN 49 50
42 S_YIN 21 22 S_CIN 42 49 50
23 23 24 24 W=40mils +3VALW 51 51 52 52
CLK_PCI_MINI 25 26
14 CLK_PCI_MINI 25 26 PCI_RST# 26,32,34,37,38
W=40mils
G1
G2
G3
G3
27 27 28 28 +3VS
PCI_REQ#1 29 30 PCI_GNT#1
26 PCI_REQ#1 29 30 PCI_GNT#1 26
31 32 FOX_AS0B226-S99N-7F
53
54
55
56
PCI_AD31 31 32 MINI1@
33 33 34 34 MINI_PME# 26,34,40
2 PCI_AD29 WLAN_BT_CLK 2
35 35 36 36 WLAN_BT_CLK 42
37 38 PCI_AD30
PCI_AD27 37 38
39 39 40 40
PCI_AD25 41 42 PCI_AD28 +3VS +1.5VS +3VALW
WLAN_BT_DATA 41 42 PCI_AD26
42 WLAN_BT_DATA 43 43 44 44
45 46 PCI_AD24
26,32,34,38 PCI_CBE#3 45 46
CLK_PCI_MINI PCI_AD23 47 48 MINI_IDSEL1 1 2 R598 PCI_AD18 1 1 1 1 1 1
47 48 100_0402_5% C450 C420 C436 C421 C429 C386
49 49 50 50
PCI_AD21 51 52 PCI_AD22 MINI2@ MINI2@ MINI2@ MINI2@ MINI2@ MINI2@
51 52
1
61 62 PCI_FRAME# ICH_PCIE_WAKE#
1 63 63 64 64 PCI_FRAME# 26,32,34,38 1 1 2 2 +3VS
C395 65 66 PCI_TRDY# WLAN_BT_DATA 3 4
28,34,39 PM_CLKRUN# 65 66 PCI_TRDY# 26,32,34,38 3 4
PCI_SERR# 67 68 PCI_STOP# WLAN_BT_CLK 5 6 +1.5VS
PCI_STOP# 26,32,34,38
@ 10P_0402_50V8K 26,32,34 PCI_SERR# 69
67 68
70 14 MINI2_CLKREQ# 7
5 6
8 +UIM_PWR +UIM_PWR
2 PCI_PERR# 69 70 PCI_DEVSEL# 7 8 UIM_DATA
26,32,34,38 PCI_PERR# 71 71 72 72 PCI_DEVSEL# 26,32,34,38 9 9 10 10
PCI_CBE#1 73 74 11 12 UIM_CLK
26,32,34,38 PCI_CBE#1 73 74 14 CLK_PCIE_MINI2# 11 12
PCI_AD14 75 76 PCI_AD15 13 14 UIM_RESET
75 76 14 CLK_PCIE_MINI2 13 14
77 78 PCI_AD13 15 16 UIM_VPP
PCI_AD12 77 78 PCI_AD11 15 16
79 79 80 80
PCI_AD10 81 82
81 82 PCI_AD9
83 83 84 84 17 17 18 18
PCI_AD8 85 86 PCI_CBE#0 2005/09/05 19 20 MINI2_OFF#
85 86 PCI_CBE#0 26,32,34,38 19 20 MINI2_OFF# 40
PCI_AD7 87 88 21 22 PLT_RST_BUF#
87 88 PCI_AD6 21 22
89 89 90 90 28 PCIE_PTX_C_IRX_N2 23 23 24 24 +3VALW
PCI_AD5 91 92 PCI_AD4 25 26
91 92 28 PCIE_PTX_C_IRX_P2 25 26
CVBS_IN 93 94 PCI_AD2 27 28
42 CVBS_IN 93 94 27 28
PCI_AD3 95 96 PCI_AD0 29 30 ICH_SMBCLK
95 96 29 30 ICH_SMBDATA
+5VS W=40mils 97 97 98 98 TV_THERM# 40,56 28 PCIE_ITX_C_PRX_N2 31 31 32 32
3 PCI_AD1 3
99 99 100 100 28 PCIE_ITX_C_PRX_P2 33 33 34 34
101 101 102 102 35 35 36 36 USB20_N7 28
103 103 104 104 37 37 38 38 USB20_P7 28
105 105 106 106 +3VS 39 39 40 40
107 108 41 42 (WWAN_LED#)
107 108 41 42
109 109 110 110 43 43 44 44
111 112 AUDIO_INR 45 46 JP43
111 112 AUDIO_INR 42 45 46
113 114 2005/09/27 modified. 47 48 +UIM_PWR +UIM_PWR
113 114 47 48 UIM_RESET 1
115 115 116 116 49 49 50 50 2
117 118 Base on OPTION GTM351E Datasheet Rev0.1 51 52 UIM_CLK
117 118 51 52 3
119 119 120 120 4
AUDIO_INL Vcc 3.3V +/- 8% UIM_VPP
G1
G2
G3
G3
42 AUDIO_INL 121 121 122 122 5
123 124 +3VALW UIM_DATA
+5VS 123 124 Peak Icc 2750mA 6
W=30mils W=20mils FOX_AS0B226-S99N-7F
53
54
55
56
P-TWO_A53921-A0G16-P MINI2@ ACES_85201-0605
with max supply droop 50mA
Average Icc 1000mA
(Change to SP070003200) C836 1 2 1U_0603_10V4Z JP31
@
+UIM_PWR +UIM_PWR 1 2
UIM_RESET GND1 RES0
3 IAC_SDATA_OUT RES1 4
+5VS UIM_CLK 5 6
GND2 3.3V
7 IAC_SYNC GND3 8
UIM_VPP 9 10
UIM_DATA IAC_SDATA_IN GND4
1 11 IAC_RESET# IAC_BITCLK 12
2005/09/06
@
@
22P_0402_50V8J
22P_0402_50V8J
22P_0402_50V8J
0.1U_0402_16V4Z
C895 1 1 1 1
0.1U_0402_16V4Z U49
GND
GND
GND
GND
GND
GND
JP38 2
GEN@ 1 K1 K4 5
1 1
2 2 2 2 ACES_88018-124G
2 USB20_N3 28 2
13
14
15
16
17
18
2 A
C847
C846
C845
C843
4 4
3 3 USB20_P3 28 Mini Card Power Rating @
4 4 3 K2 K3 4
5 5 Power Primary Power (mA) Auxiliary Power (mA) Connector for MDC Rev1.5
6 NNCD6.8RL-A
GND1 @
GND2 7 Peak Normal Normal
ACES_88266-05001 +3VS 1000 750
GEN@
+3VALW 330 250 250 (wake enable)
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title
+1.5VS 500 375 5 (Not wake enable) MINI-PCI Slot (WLAN)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 36 of 59
A B C D E
A B C D E
GND
28 CP_PE#
NC1
NC2
NC3
NC4
NC5
CPPE#
1
+3VS 1 18
14 CLK_PCIE_CARD# REFCLK-
R685 C873 19
14 CLK_PCIE_CARD REFCLK+
TPS2231PWPR_PWP24 10K_0402_5% 20
11
1
10
12
13
24
GND
1
EXP@ 0.1U_0402_16V4Z 21
2 EXP@ 28 PCIE_PTX_C_IRX_N1 PERn0
R686 EXP@ 22
28 PCIE_PTX_C_IRX_P1
2
PERp0
5
10K_0402_5% U50 23
CLKREQ1# GND
2 24
G Vcc
B 28 PCIE_ITX_C_PRX_N1 PETn0
EXP@ 4 28 PCIE_ITX_C_PRX_P1 25
EXP_CLKREQ# 14
2
Y PETp0
1 A 26 GND
1
D NC7SZ32P5X_NL_SC70-5 EXP@ 27
3
RCLKEN1 2 Q36 GND
28 GND
G 2N7002_SOT23
+3VS +3VALW +1.5VS S EXP@ TYCO_1759056-1
3
EXP@
C524
1
C541
1
C523
1 (NEW)
2 2
10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z
EXP@ 2 EXP@ 2 EXP@ 2
+USB_VCCA
W=80mils +USB_VCCA
W=80mils
1 1
1 1
+ C651 C644 + C681 C689
USB20_N0 1 USB20_N2 1
+5VALW 28 USB20_N0 2 28 USB20_N2 2
1
IN OUT R534
1 4 EN# FLG 5
C668 10K_0402_5% ECQ60 ECQ60
G528_SO8 1 2 USB_OC#0 28
4.7U_0805_10V4Z 1
2 C642
D29 D28
USB_EN# 0.1U_0402_16V4Z 1 4 +USB_VCCA 1 4 +USB_VCCA
40,42 USB_EN# 2 GND VCC GND VCC
SUYIN_020173MR004G533ZR_4P
SUYIN_020173MR004G533ZR_4P
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NEW CARD SOCKET
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B HBL50 LA-2921P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, November 11, 2005 Sheet 37 of 59
A B C D E
A B C D E
+3VS +2.5VS_1394
+3VS
2005/10/20
1 1 1 1 1 1 1 1 U14
C461 C454 C463 C402 C462 C414 C438 C396 1 8
A0 VCC
2 A1 WP 7
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 3 6 EECK
A2 SCL
1
2 2 2 2 2 2 2 2 EEDI
1394@ 1394@ 1394@ 1394@ 1394@ 1394@ 1394@ 1394@ 4 GND SDA 5
R253
AT24C02N-10SU-2.7_SO8 510_0402_5%
@ @
2
EECK and EEDI is pull high internal
1 +2.5VS_1394 +3VS External pull high circuit is unnecessary 1
111
122
110
U15 2 2 2 2 Un-populate R261
46
30
21
99
36
17
87
86
73
72
62
59
5
0.1U_0402_16V4Z
VDD4
VDD3
VDD2
VDD1
VCC6
VCC5
VCC4
VCC3
VCC2
VCC1
PVA5
PVA4
PVA3
PVA2
PVA1
PVA0
2005/10/20
+3VS
PCI_AD31 94
VT6311S EECS 26
27
EECS R261 1 2 1394@ 4.7K_0402_5%
3
PCI_AD21 109 E
PCI_AD20 AD21 REG_OUT REG_OUT Q35
113 AD20 REG_OUT 85 2
PCI_AD19 114 C398 B 2SB1197K_SOT23
PCI_AD18 AD19 R227 1 C
115 60 2 1394@ 1K_0402_5% 10P_0402_50V8K @
1
PCI_AD17 AD18 XCPS XREXT R235 1
116 AD17 XREXT 63 2 1394@ 6.19K_0603_1% 1 2 1394@
2 PCI_AD16 C399 1 2
117 AD16 10mils 2 1394@ 47P_0402_50V8J
2
PCI_AD15 2 57 1394_XI Y2 REG_FB +2.5VS_1394
PCI_AD14 AD15 XI 1394@
PCI_AD13
3
4
AD14
AD13
OSCILLATOR XO 58 1394_XO 24.576MHZ_16P_X8A024576FG1H When use external BJT
PCI_AD12 7 Populate Q35, R279
1
PCI_AD11 AD12 TPB0-
8 AD11 XTPB0M 67 1 2
PCI_AD10 9 68 TPB0+
PCI_AD9 AD10 XTPB0P TPA0- C401
PCI_AD8
10
11
AD9
AD8
PHY PORT0 XTPA0M
XTPA0P
69
70 TPA0+ 10P_0402_50V8K
IDSEL:PCI_AD16 PCI_AD7 14 71 TPBIAS0 1394@
PCI_AD6 15
AD7
AD6
PCI I/F XTPBIAS0
PCI_AD16 1 2 1394_IDSEL PCI_AD5 16 74
R341 1394@ 100_0402_5% PCI_AD4 AD5 XTPB1M
18 AD4 XTPB1P 75
PCI_AD3
PCI_AD2
19
20
AD3
AD2
PHY PORT1XTPA1M
XTPA1P
76
77
PCI_AD1 24 78
PCI_AD0 AD1 XTPBIAS1
25 AD0
26,32,34,36 PCI_CBE#3 104 CBE3# NC17 83
26,32,34,36 PCI_CBE#2 119 CBE2# NC16 82
26,32,34,36 PCI_CBE#1 1 CBE1# NC15 64
26,32,34,36 PCI_CBE#0 12 CBE0# NC14 54
PCI_STOP# 125 53
26,32,34,36 PCI_STOP# STOP# NC13
PCI_PERR# 127 52
26,32,34,36 PCI_PERR# PERR# NC12
PCI_PAR 128 51
26,32,34,36 PCI_PAR PAR NC11
PCI_PIRQE# 88 50
26 PCI_PIRQE# INTA# NC10
26,32,34,36,37 PCI_RST# 89 PCIRST# NC9 49
CLK_PCI_1394 90 48
14 CLK_PCI_1394 PCICLK NC8
PCI_GNT#0 92 45
26 PCI_GNT#0 GNT# NC7
PCI_REQ#0 93 44
26 PCI_REQ#0 REQ# NC6
1394_IDSEL 105 42
IDSEL NC5
34 PME# NC4 41
PCI _IRDY# 121 40
3 26,32,34,36 PCI_IRDY# IRDY# NC3 3
PCI_TRDY# 123 39
26,32,34,36 PCI_TRDY# TRDY# NC2
PCI_DEVSEL# 124 37
26,32,34,36 PCI_DEVSEL# DEVSEL# NC1
PCI_FRAME# 120 35
26,32,34,36 PCI_FRAME# FRAME# NC0
GNDARX1
GNDARX2
GNDATX1
GNDATX2
15mils
GND19
GND18
GND17
GND16
GND15
GND10
GND9
GND8
GND7
GND6
GND5
GND4
GND3
GND2
GND1
GND0
1
C445
VT6311S_LQFP128 R293 R309 0.33U_0603_10V7K
66
65
80
79
118
112
108
100
91
61
56
47
38
33
31
23
22
6
13
126
2
TPBIAS0 JP29
TPA0+ 4
CLK_PCI_1394 TPA0- 4
3 3 6 6
TPB0+ 2 5
2 5
1
TPB0- 1
R319 1
1
@ 10_0402_5% FOX_UV31413-4R1-TR
R275 R289 1394@
54.9_0402_1% 54.9_0402_1%
(ECQ60)
2
1 1394@ 1394@
C456
2
@ 10P_0402_50V8K
1
2
1
C434 R276
270P_0402_50V7K 4.99K_0402_1%
1394@ 1394@
2
2
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IEEE1394 VIA VT6311S
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 38 of 59
A B C D E
SUPER I/O SMsC LPC47N207
+3VS
0.1U_0402_16V4Z
1 1 1
C786 C817 C818
FIR@ FIR@ FIR@
0.1U_0402_16V4Z
2 2 2
0.1U_0402_16V4Z
+3VALW
+3VS +3VS
+3VS
17
31
42
60
48
5
U47
24
19
10
1
U31
3.3V
3.3V
3.3V
3.3V
3.3V
VTR
Base I/O Address R441
VSB
VDD
VDD
VDD
LPC_AD0 64 0 = 02Eh 4.7K_0402_5%
27,40 LPC_AD0 LAD0 +3VS
LPC_AD1 @
27,40 LPC_AD1
LPC_AD2
2 LAD1 GPIO10 27
LPC_AD0
* 1 = 04Eh
27,40 LPC_AD2 4 28 26 28
2
LPC_AD3 LAD2 GPIO11 LPC_AD1 LAD0 LPCPD# SUS_STAT# 28,41
27,40 LPC_AD3 7 LAD3 GPIO12/IO_SMI# 30 1 2 23 LAD1 TESTB1/BADD 9
32 R603 FIR@ 10K_0402_5% LPC_AD2 20 8 R437 1 2 @ 0_0402_5%
GPIO13/IRQIN1 LAD2 TEST1
1
33 1 2 LPC_AD3 17
GPIO14/IRQIN2 R599 FIR@ 10K_0402_5% LAD3 TPM_XTALO R444
10 LPC_CLK_33 GPIO15 34 XTALO 14
12 35 13 TPM_XTALI 4.7K_0402_5%
LPC_DRQ#0 LDRQ1# GPIO16 TPM XTALI @
27 LPC_DRQ#0 24 LDRQ0# GPIO17 36
LPC_FRAME# CLK_PCI_TPM SLB 9635 TT 1.1
GPIO
27,40 LPC_FRAME# 14 38 14 CLK_PCI_TPM 21
2
PM_CLKRUN# LFRAME# GPIO30 LPC_FRAME# LCLK
LPC I/F
28,34,36 PM_CLKRUN# 16 CLKRUN# GPIO31 39 22 LFRAME# GPIO2 2
SERIRQ 19 40 16 6
28,32,40 SERIRQ SERIRQ GPIO32 25,26,36 PLT_RST_BUF# LRESET# GPIO
CLK_PCI_SIO 21 41 SERIRQ 27
14 CLK_PCI_SIO PCI_CLK GPIO33 SERIRQ
PLT_RST# 22 43 PM_CLKRUN# 15
6,26,28,31,34,40 PLT_RST# PCIRST# GPIO34 CLKRUN#
CLK_14M_SIO 23 44 +3VS R432 1 2 @ 4.7K_0402_5% 7 1
14 CLK_14M_SIO SIO_14M GPIO35 PP NC
1 2 SIO_PD# 25 46 3
+3VS R602 1 FIR@ 210K_0402_5% SIO_PME# LPCPD# GPIO36 NC
47 61 12
GND
GND
GND
GND
+3VS R595 FIR@ 10K_0402_5% IO_PME# GPIO37 NC
SLB-9635-TT-1.2_TSSOP28
4
11
18
25
@
C551
63 52 RXD1 CLK_PCI_TPM 18P_0402_50V8J
DLAD0 RXD1 TXD1 TPM_XTALI
SERIAL I/F
1 DLAD1 TXD1 53 1 2
2
3 54 DSR#1 @
DLAD2 DRSR1#
@
10M_0402_5%
6 55 RTS#1 1 2 R439 X2
DLAD3 RTS1#/SYSOPT0
1
CTS#1 R198 FIR@ 10K_0402_5% @ 10_0402_5%
DLPC I/F
CTS1# 56 1 IN NC 2
57 DTR#1 1 2
DTR1#/SYSOPT1 RI#1 R199 FIR@ 10K_0402_5%
9 58 4 3
1
DLPC_CLK_33 RI1# OUT NC
R448
11 59 DCD#1 2
DLDRQ1# DCD1# 32.768KHZ_12.5P_1TJS125DJ2A073
13
2
DLFRAME# IRTXOUT C536 @
15 DCLKRUN# IRTX2 49
18 50 IRRX 1 2 @ 15P_0402_50V8J TPM_XTALO 1 2
DSER_IRQ IRRX2 IRMODE R591 FIR@ 1 @
IR
26 DSIO_14M IRMODE/IRRX3 51
10K_0402_5% C552
18P_0402_50V8J
GND0
GND1
GND2
GND3
GND4
GND5
LPC47N207-JN_STQFP64
8
20
29
37
45
62
FIR@
RTS#1
Base I/O Address
CLK_14M_SIO CLK_PCI_SIO * 0 = 02Eh
1 = 04Eh
2
R601 R600
@ 10_0402_5% @ 33_0402_5%
1
2 2
C822 C821 +IR_ANODE
@ 15P_0402_50V8J @ 22P_0402_50V8J
1 1
+3VS 1 FIR@ 2
R195 0_1206_5%
1 1 FIR@ 2
C323 R202 0_1206_5%
FIR@
FIR Module 2
4.7U_0805_10V4Z
W=60mil
Place on the BOT side(near MINIPCI conn.)
IR1
+5VS 1
JP35 +IR_3VS IRED_A IRTXOUT
2 IRED_C TXD 3 T = 12mil
+3VS IRRX 4 5 T = 12mil IRMODE
1 RP42 RXD SD/MODE
2 +3VS 1 FIR@ 2 +IR_3VS 6 VCC MODE 7
RXD1 DCD#1 1 8 R210 W=40mil 8
TXD1 3 RI#1 47_1206_5% GND
4 2 7 1 1
DSR#1 CTS#1 3 6 C357 C356 TFDU6102-TR3_8P
RTS#1 5 DSR#1 FIR@ FIR@
6 4 5 FIR@
CTS#1 10U_0805_10V4Z 0.1U_0402_16V4Z
DTR#1 7 4.7K_1206_8P4R_5% 2 2
RI#1 8 FIR@
DCD#1 9
10
ACES_85201-10051
@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SIO1036 & FIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 39 of 59
5 4 3 2 1
+3VALW
KBA[0..19]
KBA[0..19] 41 L29 +3VALW For EC Tools
ADB[0..7] 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 2+EC_VCCA
ADB[0..7] 41 +3VALW
1 1 C416 1 1 2 2 FBM-L11-160808-800LMT_0603 20mil
C473 1 JP26
C453 C467 C491 C478 KSI[0..7]
1000P_0402_50V7K 1000P_0402_50V7K C423
20mil KSI[0..7] 41,42 1 1
E51_RXD
1 1 2 2
L28 2 2 2 2 1 1 C496 C484 KSO[0..15] E51_TXD
KSO[0..15] 41 3 3
ECAGND
ECAGND 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z
1 2 4 4
FBM-L11-160808-800LMT_0603 20mil 0.1U_0402_16V4Z 1U_0603_10V4Z
2 2 @ ACES_85205-0400
123
136
157
166
161
159
D D
16
34
45
95
96
U20
LPC_AD0 15
VCCA
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AGND
BATGND
VCCBAT
27,39 LPC_AD0 LAD0
C497 LPC_AD1 14 49 KSO0
27,39 LPC_AD1 LAD1 GPOK0/KSO0
@ 22P_0402_50V8J LPC_AD2 13 50 KSO1 Analog Board ID definition, SKU ID definition,
27,39 LPC_AD2 LAD2 GPOK1/KSO1
2 1 R402 2 1 @ 33_0402_5% LPC_AD3 10 51 KSO2
27,39 LPC_AD3 LAD3 GPOK2/KSO2 Please see page 3. Please see page 3.
KSO3
27,39 LPC_FRAME# 9 LFRAME# LPC Interface GPOK3/KSO3 52
KSO4
6,26,28,31,34,39 PLT_RST# 165 LRST#/GPIO2C GPOK4/KSO4 53
ENE-KB910-B4
18 56 KSO5
14 CLK_PCI_LPC LCLK GPOK5/KSO5
7 57 KSO6 +3VALW +3VALW
28,32,39 SERIRQ SERIRQ GPOK6/KSO6 KSO7
45 DSP_WP# 25 CLKRUN#/GPIO0C * GPOK7/KSO7 58
24 59 KSO8
42 3G_LED# LPCPD#/GPIO0B * GPOK8/KSO8
2
+3VALW 60 KSO9
FR D# GPOK9/KSO9 KSO10 R273 R312
41 FRD# 150 RD# GPOK10/KSO10 61
FWR# KSO11 100K_0402_5% GM@ 100K_0402_5%
Internal Keyboard
41 FWR# 151 WR# GPOK11/KSO11 64 Ra Rc
2
1
10K_0402_5% ADB0 IOCS# GPOK13/KSO13 KSO14 AD_BID0 SKU_ID
138 D0 GPOK14/KSO14 67
ADB1 139 68 KSO15
D1 GPOK15/KSO15
2
ADB2 140 153 KSO16 1 1
KSO16 42
1
X-BUS Interface
ADB6 146 72 KSI1 0.1U_0402_16V4Z PM@
1
D6 GPIK1/KSI1
26,34,36 PCI_PME# 1 2 3GSW_EN# ADB7 147 D7 GPIK2/KSI2 73 KSI2
R706 100K_0402_5% KBA0 124 74 KSI3
A0 GPIK3/KSI3
1 2 BTSW_EN# KBA1 125 A1/XIOP_TP GPIK4/KSI4 77 KSI4 R168 change to 8.2K (GM@)
R369 100K_0402_5% KBA2 126 78 KSI5
A2 GPIK5/KSI5
1 2 WLSW_EN# KBA3 127 A3 GPIK6/KSI6 79 KSI6
R403 100K_0402_5% KBA4 128 80 KSI7
KBA5 A4/DMRP_TP GPIK7/KSI7
131 A5/EMWB_TP
+3VALW 1 2 TV_BTN# KBA6 132 32 INVT_PWM
C A6 GPOW0/PWM0 INVT_PWM 23 C
R708 100K_0402_5% KBA7 133 33 BEEP#
A7 GPOW1/PWM1 BEEP# 44
1 2 MUSIC_BTN# KBA8 143 A8 FAN2PWM/GPOW2/PWM2 36 MUTE_WOOFER# 47
2
4
3 6 E-MAIL_BTN# BKOFF# 28 174 EC_PWROK
23 BKOFF# GPIO0E GPODA7/DA7 EC_PWROK 43
4 5 USER_BTN# FSTCHG 48 10P_0402_50V8K 10P_0402_50V8K
IN
OUT
52 FSTCHG GPIO10 2 2
EC_SMI# 62 85 PW R_LED PWR_LED 42
28 EC_SMI# GPIO13 * GPIO18/XIO8CS#
100K_1206_8P4R_5% IDE_LED# 63 86 PWR_SUSP_LED# PWR_SUSP_LED# 42
30,31 IDE_LED# USER_BTN# GPIO14 * GPIO19/XIO9CS# BATT_GRN_LED# X1
42 USER_BTN# 69 GPIO15 91 BATT_GRN_LED# 42
+3VS *GPIO1A/XIOACS# BATT_AMB_LED#
NC
NC
28 EC_SWI# 70 GPIO16 GPIO * GPIO1B/XIOBCS# 92 BATT_AMB_LED# 42
75 Expanded I/O * GPIO1C/XIOCCS# 93 WL_LED# WL_LED# 42
42 ARCADE# GPIO17
1 2 5IN1_LED# 42 3GSW_EN#
3GSW_EN# 109 94 BT_LED# BT_LED# 42
3
R357 10K_0402_5% LID_SW# GPIO24 * GPIO1D/XIODCS# E-MAIL_LED#
43 LID_SW# 118 GPIO25 97 E-MAIL_LED# 42
BT_ON# 119 * GPIO1E/XIOECS# 98 MEDIA_LED# MEDIA_LED# 42
42 BT_ON# GPIO26 * GPIO1F/XIOFCS#
SYSON 148
37,49,55 SYSON GPIO27
SUSP# 149 171 FAN_SPEED1 32.768KHZ_12.5P_1TJS125DJ2A073
+5VALW 37,41,43,49,54 SUSP# GPIO28 GPIO2E/TOUT1/FANFB1 FAN_SPEED1 48
VR_ON 155 12 DPLL_TP
56 VR_ON GPIO29 DPLL_TP/GPIO06/FANFB3
RP19 156 FANTEST_TP/GPIO05/FAN3PWM 11 TEST_TP Change P/N SJ100001V00
32 5IN1_LED# GPIO2A
1 8 EC_SMB_CK1 BTSW_EN# 162
42 BTSW_EN# GPIO2B
2 7 EC_SMB_DA1 PBTN_OUT# 168 175 EC_THERM#
28 PBTN_OUT# GPIO2D TOUT2/GPIO2F EC_THERM# 28
3 6 EC_SMB_CK2 Timer Pin
4 5 EC_SMB_DA2 55 3
C492 0.1U_0402_16V4Z CAPS_LED# FnLock#/GPIO12 * E51IT0/GPIO00 WLSW_EN# EC_RSMRST# 28
42 CAPS_LED# 54 CapLock#/GPIO011 * E51IT1/GPIO01 4 WLSW_EN# 42
4.7K_1206_8P4R_5% 2 1 NUM_LED# 23 106 E51_RXD 1 2 EAPD
42 NUM_LED# NumLock#/GPIO0A * E51RXD/GPIO21/ISPCLK EAPD 44
27 SATA_LED# SATA_LED# 41 107 E51_TXD R270 0_0402_5%
+5VS ScrollLock#/GPIO0F * E51TXD/GPIO22/ISPDAT
+3VALW 2 1 19 ECRST# MISC 1 2 HD_EAPD# 44
R409 47K_0402_5% 5 158 C RY2 R793 @ 0_0402_5%
TP_CLK 27 EC_GA20 GA20/GPIO02 XCLKI C RY1
2 1 27 EC_KBRST# 6 KBRST#/GPIO03 XCLKO 160
4.7K_0402_5% R269 31
GND
GND
GND
GND
GND
GND
ECSCI#
2 1 TP_DATA
4.7K_0402_5% R268
KB910Q B4_LQFP176
17
35
46
122
137
167
R260 +3VS
+3VALW 100K_0402_5%
KB910 C1 VERSION EAPD 2 1
A KBA1 ENBKL A
2 1 1 2
1K_0402_5% R267 R404 100K_0402_5% @
2 1 KBA4 1 2 DPLL_TP
1K_0402_5% R266 R401 1K_0402_5%
2 1 KBA5 1 2 TEST_TP
1K_0402_5% R265 R400 1K_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC ENE KB910
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 40 of 59
5 4 3 2 1
+3VALW +3VALW
C526
1
1 2 R434
100K_0402_5%
SUSP# 37,40,43,49,54
0.1U_0402_16V4Z
2
G
5
U29
2
2 1 3
G Vcc
B EC_FLASH# 28
FWE# 4
S
Y
A 1
Q18
NC7SZ32P5X_NL_SC70-5 2N7002_SOT23
3
FWR# 40
1
C503 1 2 0.1U_0402_16V4Z
R413
100K_0402_5%
U24 (Right) JP8
2
8 1 KSO15
VCC A0 KSO14 24
7 WP A1 2 23
6 3 KSO13
15,40,45,53 EC_SMB_CK1 SCL A2 22
5 4 KSO12
15,40,45,53 EC_SMB_DA1 SDA GND 21
KSI0
AT24C16N10SC-2.7_SO8 KSO11 20
KSO10 19
KSI1 18
17
1
KSI2
R398 KSO9 16
KSI3 15
100K_0402_5% KSO8 14
KSO7 13
2
KSO6 12
KSO5 11
KSO4 10
KSO3 9
KSI4 8
KSO2 7
KSO1 6
KSO0 5
KSI5 4
KSI6 3
KSI7 2
1
(Left)
ACES_85201-24051
FOR DEBUG ONLY INT_FLASH_EN# C490 1 2 @ 0.1U_0402_16V4Z
+3VALW +3VALW
R391 1 2 @ 100K_0402_5%
SB_INT_FLASH_SEL# 28
5
1
P
P
OE#
OE#
2 4 INT_FLASH_SEL FSEL# 2 4 1 2 INT_FSEL#
28,39 SUS_STAT# A Y 40 FSEL# A Y R390 @ 22_0402_5%
G
1
U30
@ R388
3
SN74AHCT1G125DCKR_SC70-5 3 @
U21 10K_0402_5%
@
2
SN74AHCT1G125DCKR_SC70-5
KBA[0..19]
40 KBA[0..19] KSI0 C763 1 100P_0402_50V8J KSO3 C775 1 100P_0402_50V8J
2 2
ADB[0..7]
40 ADB[0..7]
+3VALW 1MB ROM Socket KSO11 C764 1 2 100P_0402_50V8J KSI4 C776 1 2 100P_0402_50V8J
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS, I/O Port & K/B Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 41 of 59
1 2 +3VALW
R343 100K_0402_5%
D13
2 ARCADE# 40
ARCADE_BTN#1
To CD-PLAY/B Conn. 3 51ON#
51ON# 43,50
JP11 DAN202U_SC70
ARCADE_BTN# GEN@ +3VALW
MOVIEBTN# 24
TVBTN#
MUSICBTN#
23
22
D32
2
MDC Conn. 1
C599
21 TV_BTN# 40
TVBTN# 1 JP3
20 51ON# 1U_0603_10V4Z
19 3
2
18 1 GND1 RES0 2
+5VS DAN202U_SC70 ICH_SDOUT_MDC 3 4 20mil
17 27 ICH_SDOUT_MDC IAC_SDATA_OUT RES1
GEN@ 5 6
16 GND2 3.3V +3VALW
27 ICH_SYNC_MDC ICH_SYNC_MDC 7 8
15 D33 R491 1 IAC_SYNC GND3
14 27 ICH_AC_SDIN1 2 33_0402_5% 9 IAC_SDATA_IN GND4 10
2005/09/04 2 ICH_RST_MDC# 11 12 ICH_BITCLK_MDC
13 MOVIE_BTN# 40 27 ICH_RST_MDC# IAC_RESET# IAC_BITCLK ICH_BITCLK_MDC 27
KSI6 MOVIEBTN# 1 1
40,41 KSI6 12
3 51ON# C598
11
GND
GND
GND
GND
GND
GND
KSI0 10 DAN202U_SC70 22P_0402_50V8J
40,41 KSI0 9 2
KSI1 GEN@
40,41 KSI1 8
KSI2 D34 ACES_88018-124G
40,41 KSI2
13
14
15
16
17
18
KSI5 7
40,41 KSI5 6 2 MUSIC_BTN# 40
KSO16 +5VS MUSICBTN# 1
40 KSO16 5
KSI3 3 51ON# Connector for MDC Rev1.5
40,41 KSI3 4
KSI4
40,41 KSI4 3
KSO17 C555 DAN202U_SC70
40 KSO17 2
5WAY_BTN GEN@ GEN@
40 5WAY_BTN 1 0.1U_0402_16V4Z LED9
ACES_85201-24051 2 1
GEN@
HT-170UYG-DT GRN_0805 JP37 2005/09/04 JP6
GEN@ +5VS
R472 LED3 1 1
300_0402_5% WLSW_EN# 2 2
PWR_LED# WL_LED# 3 3
+5VS 1 2 2 1 4 4
3 BTSW_EN# KSO17
BT_LED# 5 KSI2 5
HT-110UYG_1204 3GSW_EN# 6 KSI5 6
GRA@ 3G_LED# 7 KSO16 7
LED8 8 KSI3 8
9 KSI4 9
2 1 10 10
HT-170UD_0805 ACES_85201-10051 ACES_85201-10051
GEN@ GEN@ GRA@
R704 LED6
300_0402_5%
PWR_LED# +5VALW 1 2 2 1 PWR_SUSP_LED# PWR_SUSP_LED# 40
3
HT-110UD_1204
GRA@ +5VALW
LED10
1
D
2 1
40 PWR_LED 2
G HT-170UYG-DT GRN_0805 C2
S Q9 GEN@ Delete C7
3
2 1 1 1 2 2 +5VALW
R470 R471 PWR_LED# 3 4
HT-170UD_0805 3 4
40 MEDIA_LED# 5 5 6 6
300_0402_5% 300_0402_5% GEN@ 7 8
40 CAPS_LED# 7 8
R703 LED5 9 10 USB20_N4
40 NUM_LED# USB20_N4 28
2
300_0402_5% 9 10 USB20_P4
40 E-MAIL_LED# 11 11 12 12 USB20_P4 28
+5VALW 1 2 2 1 BATT_AMB_LED# BATT_AMB_LED# 40 13 14
43 ON/OFFBTN# 13 14
3
2
3
2
3 15 16 USB20_N6
40 E-MAIL_BTN# 15 16 USB20_N6 28
LED2 LED1 17 18 USB20_P6
40 IE_BTN# 17 18 USB20_P6 28
HT-110UD_1204 HT-110NBQA_BULE_1204 HT-110UD_1204 19 20
40 USER_BTN# 19 20
GRA@ 21 22
40 EMPWR_BTN# 21 22 USB_EN# 37,40
23 23 24 24
R707 LED7 25 26
36 CVBS_IN
1
MINI2@ 300_0402_5% 25 26
36 S_YIN 27 27 28 28 AUDIO_INL 36
WL_LED# BT_LED# 1 2 2 1 3G_LED# 29 30
GND
GND
GND
GND
GND
GND
WL_LED# 40 BT_LED# 40 +5VS 3G_LED# 40 36 S_CIN 29 30 AUDIO_INR 36
3
31
32
33
34
35
36
MINI2@
BT_SW & 3G_SW WL_SW
+3VALW
5
2005/09/04 2005/09/12
1 +3VALW
5
1
1
2 R705
3GSW_EN# 2 100_0805_5%
2 3GSW_EN# 40 CIR
1
3 CIR@ 1
3 R796 C929 C874
2
3
2
S
SW8 1 2
6
2
SW9 HSS110_4P GND GND G
Q37 JP36
1 40 BT_ON# 2
5
7
1
2 4
Geneva 2005/09/04 Grapevine W=40mils 5
+BT_VCC 36 WLAN_BT_DATA 6
36 WLAN_BT_CLK 7
KSO16 KSO17 KSO16 KSO17 1
C875 C877 8
KSI0 VOL_UP LEFT ACES_87212-0800
4.7U_0805_10V4Z 0.1U_0402_16V4Z
2
KSI1 RIGHT VOL_DOWN
KSI2 PLAY ENTER KSI2 PLAY
KSI3 STOP KSI3 STOP VOL_UP
KSI4 NEXT KSI4 NEXT VOL_DOWN
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title
KSI5 REV KSI5 REV ARCADE_TV CD-PLAY / MDC / BT / CIR / LED
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KSI6 RECORD AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 42 of 59
A B C D E
J1
2 1
@ JOPEN +3VALW
+3VALW - BATT1 + +RTCBATT
1
1 1
2
R8
R399 Lid Switch 100K_0402_5% 45@ RTCBATT
1
100K_0402_5% D30
2
Change P/N : SN111000207
1
D14 BAS40-04_SOT23
SW1
2 3 1 +RTCVCC
ON/OFF 40 LID_SW# 40
ON/OFFBTN# 1
42 ON/OFFBTN#
2
3 51ON#
51ON# 42,50
3
DAN202U_SC70
CHGRTC
4 2 1
D3 C833
MPU-101-81_4P @
PSOT24C_SOT23 0.1U_0402_16V4Z
1
2
2 2005/09/04
1
C495 D15
1000P_0402_50V7K RLZ20A_LL34
1
2
Scroll Up
1
D
EC_ON 2 Q16 SW2
40 EC_ON
G EVQPLHA15_4P
2
S 2N7002_SOT23 SCRL_U 3 1
3
2 R414 2
4 2 SCRL_R
10K_0402_5%
BTN_R
1
5
6
Scroll Left Scroll Right
3
SW5 SW6 D17
EVQPLHA15_4P EVQPLHA15_4P @
SCRL_L 3 1 SCRL_R 3 1 PSOT24C_SOT23
1
4 2 4 2
Power ON Circuit
5
6
5
6
SCRL_L
Scroll Down
Change P/N : SA00000LR00 SCRL_U
+3VS SW7
3
EVQPLHA15_4P
+3VALW +3VALW SCRL_D 3 1
D19
1
4 2 @
2005/10/20 U28A U28B PSOT24C_SOT23
R420 SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14
14
14
5
6
1
180K_0402_5%
Left Right
P
P
2
1 I O 2 3 I O 4 1 2 SYS_PWROK 6,28
R789 @ 0_0402_5% SW3 SW4 SCRL_D
1
G C512
3
Q41 S 1U_0805_25V4Z 4 2 4 2
3
3 2N7002_SOT23 1 3
40 EC_PWROK 1 2
R790 0_0402_5% D18
5
6
5
6
@
PSOT24C_SOT23
2005/10/20
1
+3VS
+3VALW +3VALW
To TP/B Conn.
1
14
40 TP_DATA
2
14
4 SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14 4
R422 PM@ 62K_0402_1%
P
+3VS 1 2
7
D37 RB751V_SOD323
2
Security Classification Compal Secret Data Compal Electronics, Inc.
PM@ C513 2005/06/20 2006/06/20 Title
PM@
Issued Date Deciphered Date
0.1U_0402_16V4Z
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power OK, Reset and RTC Circuit, TP
1 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 43 of 59
A B C D E
A B C D E F G H
+VDDA
28.7K for Module Design (VDDA = 4.702)
1
R689 +5VAMP (output = 250 mA)
10K_0402_5% 60mil U34
+5VS L32 1 2 4 VIN VOUT 5 40mil +VDDA
KC FBM-L11-201209-221LMAT_0805
2
1 1 2 DELAY SENSE or ADJ 6 1 4.85V
1 2 L33 1 2 C550 C553 R452
C542 1U_0603_10V4Z KC FBM-L11-201209-221LMAT_0805 7 1 30K_0402_1% C558
ERROR CNOISE
1
10U_0805_10V4Z 10U_0805_10V4Z
R688 2 2
0.1U_0402_16V4Z 2
8 3 1
1
10K_0402_5% SD GND C548
1 SI9182DH-AD_MSOP8 1
R430
1
C527 1 2 1 2
40 BEEP#
2
1U_0603_10V4Z C535 2
560_0402_5% 1 2 MONO_IN R451
0.1U_0402_16V4Z 10K_0402_1%
1U_0603_10V4Z
2
1
C 1 2
C528 1 R433 Q19
32 PCM_SPK# 2 1 2 2 R687
1U_0603_10V4Z B
560_0402_5% E 2SC2411K_SC59 2.4K_0402_5%
3
C533 1 R438
28 SB_SPKR 2 1 2
1U_0603_10V4Z
1
560_0402_5%
D16
R442 RB751V_SOD323
10K_0402_5%
2
HD Audio Codec
L57
+AVDD_AC97 MBK1608301YZF_0603
20mil 0.1U_0402_16V4Z +3VS_DVDD 2 1 +3VS
L34 1 2 0.1U_0402_16V4Z 40mil 1 1 1
+VDDA
FBM-L11-160808-800LMT_0603 1 1 1 C537 C539 C532
C545 C559
2 C549 10U_0805_10V4Z 2
10U_0805_10V4Z 2 2 2
25
38
9
2 2 2 U33
0.1U_0402_16V4Z 0.1U_0402_16V4Z
AVDD1
AVDD2
DVDD1
DVDD2
14 35 AMP_LEFT
LINE2_L FRONT_OUT_L AMP_LEFT 45,46
15 36 AMP_RIGHT
LINE2_R FRONT_OUT_R AMP_RIGHT 45,46
16 MIC2_L SURR_OUT_L 39
17 MIC2_R SURR_OUT_R 41
LINE_L 1 2 LINE_C_L 23 45
46 LINE_L LINE1_L SIDESURR_OUT_L
C556 1U_0603_10V4Z
LINE_R 1 2 LINE_C_R 24 46
46 LINE_R LINE1_R SIDESURR_OUT_R
C557 1U_0603_10V4Z
1 2 CD_L_RC 18 43
C543 @ 1U_0603_10V4Z CD_L CEN_OUT
2005/10/26
1 2 C D_R_RC 20 44
CD_R LFE_OUT MONO_OUT 47
C546 @ 1U_0603_10V4Z
1 2 CD_AGND_RC19 C538 1 2 22P_0402_50V8J
C544 @ 1U_0603_10V4Z CD_GND
BIT_CLK 6 ICH_BITCLK_AUDIO 27
MIC1_L 1 2 MIC1_C_L 21
46 MIC1_L MIC1_L
C547 1U_0603_10V4Z
MIC1_R 1 2 MIC1_C_R 22 8 R443 1 2 33_0402_5% ICH_AC_SDIN0 27
46 MIC1_R MIC1_R SDATA_IN
C554 1U_0603_10V4Z
MONO_IN 12 37
PCBEEP PIN37_VREFO
2005/09/12
LINE1_VREFO 29
3 3
27 ICH_RST_AUDIO# 11 RESET#
LINE2_VREFO 31
27 ICH_SYNC_AUDIO 10 SYNC 10mil
MIC1_VREFO_L 28 MIC1_VREFO_L
27 ICH_SDOUT_AUDIO 5 SDATA_OUT
MIC1_VREFO_R 32 MIC1_VREFO_R
J4 @ 2
40 EAPD GPIO0
1 1 2 2 46,47 NBA_PLUG 3 GPIO1 MIC2_VREFO 30
JUMP_43X79
13 SENSE A AC97_VREF
10mil
34 SENSE B VREF 27
1
J5 @ 47 40
40 HD_EAPD# SPDIFI/EAPD JDREF C561
1 1 2 2
1
48 33 10U_0805_10V4Z
JUMP_43X79 46 SPDIF SPDIFO VAUX R445 2
4 26 20K_0402_1%
DVSS1 AVSS1
7 DVSS2 AVSS2 42 @
1 2
2
1
R440
2
0_0603_5%
DGND AGND
2005/09/20
1 2
R695 0_0603_5%
4
GND GNDA 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD Audio Codec ALC883
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 44 of 59
A B C D E F G H
A B C D E
1 VOUT BP 5 1 2 1 2 1 2
C896 L52 FBM-L11-160808-800LMT_0603 L53 FBM-L11-160808-800LMT_0603
+5VAMP 2 0.01U_0402_16V7K VP1020@ VP1020@ VP1020@
2 GND 1 2 1 1 1 1 2 1
1 VP1020@ C899 C900 C901 C904 C905 1
C897 3 4 +5VAMP C898 C902 C903
1U_0603_10V4Z VIN SHDN# 4.7U_0805_10V4Z 1U_0603_10V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 1U_0603_10V4Z
VP1020@ 1 2 VP1020@ VP1020@1 2
0.1U_0402_16V4Z 2 2
4.7U_0805_10V4Z 2 VP1020@ 1
VP1020@ 2
0.1U_0402_16V4Z
1
APL5301-18BC-TR_SOT23-5 VP1020@ VP1020@ VP1020@
C906 VP1020@
1U_0603_10V4Z
VP1020@ 2 closed to Pin37
+3VS_DSP
+1.8VS_DSPA
VP1020@
C907 1 2 4.7U_0805_10V4Z U59 GPIO5: High for SHI, Low for EEPROM
33
37
19
35
2
4
R742 1 2 1 2 closed to Codec
VDD_S
NC
NC
VDD_D
V10
V15
MIC1_VREFO_L
2.2K_0402_5% R743 1K_0402_5% 5 20 VP1020@ R744 1 2 100K_0402_5%
VP1020@ VP1020@ NC GPIO6
6 NC GPIO5 21 VP1020@ R745 1 2 100K_0402_5%
17 @ R746 1 2 10K_0402_5% +3VS_DSP
VP1020@ VP1020@ GPIO7 VP1020@ R747 1 10K_0402_5% VP1020@
2
MIC1_DSP_P R748 12 100_0402_5% C908 2 1 R749 1 2 39 0.1U_0402_16V4Z
46 MIC1_DSP_P VP1020@ 0.1U_0402_16V4Z 1K_0402_5% MIC0_P VP1020@ R750 1 C910 2
1 LINE_OUT 47 2 1 2 1 1 2 INT_MIC_L INT_MIC_L 46
2 MIC1_DSP_N C912 C911 2 R752 1 C909 100_0402_5% R751 0_0402_5% 2
46 MIC1_DSP_N 1 2 40 MIC0_N
VP1020@ 0.1U_0402_16V4Z 1K_0402_5% 0.1U_0402_16V4Z VP1020@ 1 2 VP1020@
0.012U_0603_25V7K VP1020@ VP1020@ 41 16 DSP_EECK C913
R7531 2 NC SCL_EE DSP_EEDA 0.039U_0603_16V7K
2 1 2 SDA_EE 15
+5VAMP 2.2K_0402_5% R754 100_0402_5% 42 VP1020@
VP1020@ VP1020@ VP1020@ VP1020@ NC R755 1
UART_TX 13 2 100K_0402_5%
1 2 R7561 2 1K_0402_5% C915 2 1 1 2 43 12 VP1020@
LINE_IN UART_RX
1
VP1020
1M_0402_5% VP1020@ C917 2 1 0.039U_0603_16V7K 34
VP1020@ U61A VP1020@ SW10
SW15 36
8
1U_0603_10V4Z 2 VP1020@ 3
IN- SPK_OUT_N
G
NC BYPASS
1
20P_0402_50V8J 9 NC
1
VP1020@ Y6 VP1020@R763 27 10 VP1020@ R7641 2 100K_0402_5%
+5VAMP 13MHZ_16PF_X6G013000FG1H 1M_0402_5% XTAL_IN SEG_SEL C921
28
2
XTAL_OUT
Change P/N : SA00000QP00 46 VP1020@ C922 1 2 1U_0603_10V4Z 1U_0603_10V4Z
1
VSS_REF
1M_0402_5% VP1020@ R767 1 VOLDN
2 100K_0402_5% 26 22 VP1020@ R7681 2 100K_0402_5%
GND_D
VSS_D
VSS_D
VSS_A
VSS_A
VP1020@ U61B VOLUP GPIO4
8
LM358M_SO8
2
1 2 5 VP1020@
P
45
38
7
18
29
1
3 1U_0603_10V4Z VP1020@ 3
6 IN-
G
VP1020@
R780 DSP_SMB_CK 1 2 +3VS_DSP
4
+3VS
2
DSP_SMB_DA 1 2 +3VS_DSP R802
2
R773 10K_0402_5%
@ R803 +3VS 10K_0402_5%
VP1020@
1
10K_0402_5% DSP_RST#
VP1020@
5
+3VS_DSP VP1020@
1
DSP_WP# DSP_ENABLE# D
1
P
40 DSP_WP# 46 DSP_ENABLE# A 2N7002_SOT23
Y 4 2
2 G Q44
B
2
G
G
3
2
+3VS U62
3
2
2
2N7002_SOT23 10K_0402_5%
G
VP1020@ 10K_0402_5% 10K_0402_5% U60 VP1020@
VP1020@ 10K_0402_5% VP1020@ 8 VCC 1 1 1 3
1
VP1020@ A0
7 WP 2
S
DSP_WP# DSP_EECK A1
6 SCL A2 3 1
DSP_EEDA 5 SDA 4
GND C931 Q43
2
AT24C02N-10SU-2.7_SO8 2N7002_SOT23
G
1U_0603_10V4Z
R774 VP1020@ 2 VP1020@
VP1020@
15,40,41,53 EC_SMB_DA1 1 3 DSP_EEDA 10K_0402_5%
4 Q40 4
VP1020@
D
2N7002_SOT23
1 2
VP1020@
D Q42
DSP_WP# 2 VP1020@
G 2N7002_SOT23
S
3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Echo Cancellation
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 45 of 59
A B C D E
A B C D E
JP12
SPKL+ R462 1 2 0_0603_5% SPK_L+
SPKL- R464 0_0603_5% SPK_L- 1
1 2 2
+5VAMP SPKR+ R466 1 2 0_0603_5% SPK_R+
SPKR- R469 0_0603_5% SPK_R- 3
1 2 4
1
20mil ACES_85204-0400
R458 Speaker Conn.
10K_0402_5%
1 1
2
VOL_AMP +5VAMP
(0.65V -> 10dB ) W=40mil +5VAMP
1
R455 R457 1 1
1
@ +5VAMP
5.1K_0402_1% 1.5K_0402_1% C881 C892 R467
0.1U_0402_16V4Z 4.7U_0805_10V4Z 100K_0402_5% +5VAMP
1 2
1
2 2
D R468 R698
2
SPDIF_PLUG# 2 100K_0402_5% 100K_0402_5%
3
S
Q20 G 1 2 G
2N7002_SOT23 @ S U56 2 SPDIF_PLUG#
3
2
10 1 EC_MUTE NBA_PLUG
VDD MUTE EC_MUTE 40,47 44,47 NBA_PLUG
15 2 Q22
VDD SHUTDOWN#
1
C882 2 D
1 0.1U_0402_16V4Z D SI2301BDS_SOT23
9 SPKL- 2 SPDIF_PLUG#
1
VOL_AMP LOUT- G Q21
7 VOLUME
16 SPKR- S 2N7002_SOT23
3
VOLMAX ROUT-
C927
2
R690
1
0_0402_5%
8 VOLMAX SPKL+
+5VSPDIF 20mil
LOUT+ 11
0.47U_0603_16V4Z NBA_PLUG 13
AMP_LEFT_C-1 SE/BTL# SPKR+
44,45 AMP_LEFT 1 2 1 2 ROUT+ 14
C566 1U_0603_10V4Z AMP_LEFT_C 6
AMP_RIGHT_C-1 AMP_RIGHT_C LIN-
44,45 AMP_RIGHT 1 2 1 2 3 RIN-
C928 C568 1U_0603_10V4Z 5
0.47U_0603_16V4Z BYPASS GND
47 BYPASS 4 BYPASS GND 12
20mil
1
1 APA2068KAI-TRL_SOP16
R791 R792
@ @ C886
1K_0402_5% 1K_0402_5% 4.7U_0805_10V4Z
2 2 2
2 2
2
C563 C562
330P_0402_50V7K
S/PDIF Out JACK
330P_0402_50V7K
1 1
HPF Fc = 338Hz JP40
2005/09/05
1
SPKL+ 2 HPOUT_L_1 HPOUT_L_2 HPOUT_L_3
+
1 1 2 1 2 2
C891 150U_D_6.3VM R702 47_0603_5% L51 FBM-11-160808-700T_0603 6
SPKR+ 2 HPOUT_R_1 HPOUT_R_2 HPOUT_R_3
+
1 1 2 1 2 3
C888 150U_D_6.3VM R699 47_0603_5% L50 FBM-11-160808-700T_0603
+5VAMP 2 1 SPDIF_PLUG# 5
R456 100K_0402_5%
4
SPDIF 7
44 SPDIF
1
+5VSPDIF 8
R794 R795 10
@ @
1K_0402_5% 1K_0402_5% SPDIF 9
1
2
ACES_20234-0101
C879 GRA@
100P_0402_50V8J
2
@
LINE-IN JACK
JP41
5
4
3 L48 FBM-11-160808-700T_0603 3
LINE_R 1 2 LINE_R_R 3
44 LINE_R
6
LINE_L 1 2 LINE_L_R 2
44 LINE_L
L49 FBM-11-160808-700T_0603 1
1 1
SUYIN_010164FR006G118ZL
C885 C884 GRA@
220P_0402_50V7K 220P_0402_50V7K
2 2
DSP_ENABLE#
DSP_ENABLE# 45
1
JP42 MIC1_R_1 3
Int MIC Conn. R775 R776
5 LINE_R_R
LINE_L_R
4
3
4
45 MIC1_DSP_P INT_MIC_L 45 5 5
2.2K_0402_5% 2.2K_0402_5% 4 6
HPOUT_R_3 6
2005/09/06 7
2
2
JP13 7
15mil 44 MIC1_R 1 2 FBM-11-160808-700T_0603 MIC1_R_1 3 8 8
1 2 INT_MIC_L L54 6 HPOUT_L_3 9
1 R741 MIC1_L_1 DSP_ENABLE# 9
2 44 MIC1_L 1 2 FBM-11-160808-700T_0603 2 10 10
0_0402_5% L35 1 SPDIF_PLUG# 11
ACES_85204-0200 INTMIC@ 11
1 1 +5VSPDIF 12 12
SUYIN_010164FR006G118ZL SPDIF 13
C569 C876 13
MIC1_DSP_N 45 GRA@ 14 14
220P_0402_50V7K 220P_0402_50V7K 15
4 2 2 40,42 RCIRRX 15 4
+3VALW 16 16
ACES_87213-1600G
GEN@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Amplifier & Audio Jack
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 46 of 59
A B C D E
A B C D E
1 1
+5VAMP
SUB@
C567 1U_0603_10V4Z
BYPASS 1 2 1 2 C889 1 2 0.68U_0603_10V6K
46 BYPASS R460 0_0402_5% SUB@
SUB@ +5VAMP
1 2 U57A
8
C565 TLV2462CDR_SO8
8
0.1U_0402_16V4Z 3 SUB@ R700 R701
P
SUB@ + C890
O 1 2 1 2 1 5
P
+
44 MONO_OUT 1 2 2 1 R459 1 2 C564 2 -
1K_0402_5% 10K_0402_5%
O 7 2 1 MIX_OUT
G
C560 1U_0603_10V4Z 100K_0402_5% SUB@ SUB@ 6 - 10mil
G
SUB@ SUB@ 1U_0603_10V4Z U57B 0.22U_0603_16V7K
4
SUB@ 2 TLV2462CDR_SO8 SUB@
4
C570 SUB@
2 1 SUB@
R461 0.47U_0603_16V4Z
43K_0402_5% 1
SUB@
BYPASS
2 2
10mil
fo= 725 Hz
1
D G 2N7002_SOT23 TPA0211DGN_MSOP8
2 2
2 Q23 S SUB@ C880 C878 SUB@ R691
40,46 EC_MUTE
3
0.1U_0402_16V4Z 1 1 0.47U_0603_16V4Z
2
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Subwoofer
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 47 of 59
A B C D E
H1 H4 H3 H2 H5
H_S394D138 H_S315D138 H_C236D162 H_S366D138 H_C197D197N
FAN1 Conn @ @ @ @ @
1
+5VS
C47 10U_1206_16V4Z +5VS
1 2
H7 H8 H9 H10 H6
1
H_TC236BC165D165 H_TC236BC165D165 H_TC236BC165D165 H_TC236BC165D165 H_C236D162
U2 D4
1 8 1SS355_SOD323
VEN GND @ @ @ @ @
2 7
1
+VCC_FAN1 VIN GND D5
3 6
2
EN_DFAN1 VO GND 1N4148_SOT23
40 EN_DFAN1 4 VSET GND 5
1 2
G993P1UF_SOP8
H14 H15 H13 H23 H22
C51 H_S394D138 H_S394D138 H_S374X354D138 H_TS559X295BS394X276D138 H_S394D138
10U_1206_16V4Z
1 2
@ @ @ @ @
1
+3VS C58
1000P_0402_50V7K
1 2
1
R45 H16 H19 H20 H21 H24
10K_0402_5% H_TC177BC144D144 H_TC177BC144D144 H_C158D158N H_S394X374D138 H_S354X293D138
40mil JP19
2
+VCC_FAN1 @ @ @ @ @
1
1
40 FAN_SPEED1 2
3
1 2005/09/20
C59 ACES_85205-03001
1000P_0402_50V7K H29 H28 H26 H27 H25
H_C236D162 H_S354X335D138 H_O217X157D217X157N H_S315D138 H_S374X354D138
2
@ @ @ @ @
1
H18 H12 H17 H11
H_O87X68D47X28 H_O87X68D47X28 H_O87X68D47X28 H_O87X68D47X28
@ @ @ @
1
FAN2 Conn
+5VS
C338 10U_1206_16V4Z +5VS
1 2
FD2 FD1 FD3 FD5 FD4 FD6
1
U10 D8
1 8 1SS355_SOD323 @ @ @ @ @ @
1
VEN GND
2 VIN GND 7
+VCC_FAN2 3 6 D9
2
C339
10U_1206_16V4Z @ @ @ @ @ @ @ @ @ @
1
1 2
+3VS C343
1000P_0402_50V7K CF17 CF16 CF19 CF13 CF9 CF1 CF2 CF3 CF5 CF11
1 2
1
R207 @ @ @ @ @ @ @ @ @ @
1
10K_0402_5%
40mil JP25 CF8
2
+VCC_FAN2
1
40 FAN_SPEED2 2 @
1
3
1
C344 ACES_85204-0300
1000P_0402_50V7K
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FAN & Screw Hole
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 48 of 59
A B C D E
+5VALW
2
R294
100K_0402_5%
1
SYSON#
+5VALW TO +5VS
1
D
1 +5VALW +5VS SYSON 2 Q8 1
37,40,55 SYSON
G 2N7002_SOT23
U16 S
3
1
8 D S 1
7 2 R295
D S
2
6 3 1 1 100K_0402_5%
D S C464 C465 R358
1 1 5 D G 4
C418 C419 470_0603_5%
2
SI4800BDY_SO8 10U_0805_10V4Z
10U_0805_10V4Z 2 2
1U_0603_10V4Z
AOS 4422
1
2 2
10U_0805_10V4Z
1
D
2 SUSP
G
+VSB 2 1 5VS_GATE S Q12
3
R317 2N7002_SOT23
200K_0402_5% 1
1
D C455
SUSP 2
Q11G 0.1U_0603_25V7K
2N7002_SOT23 S 2
3
+5VALW
2
R362
100K_0402_5%
2 2
1
SUSP
43,53,54 SUSP
1
D
2 Q13
37,40,41,43,54 SUSP#
G 2N7002_SOT23
S
3
1
R363
100K_0402_5%
2
+3VALW TO +3VS
+1.8V to +1.8VS
+3VALW +3VS +1.8V +1.8VS
U27 U44
8 D S 1 8 D S 1
7 D S 2 7 D S 2 1 1
2
2
6 3 1 1 6 3 C755 C756
D S C514 C518 R423 D S R590
1 1 5 D G 4 1 1 5 D G 4
C508 C509 470_0603_5% C741 C740 10U_0805_10V4Z 470_0603_5%
SI4800BDY_SO8 10U_0805_10V4Z SI4800BDY_SO8 2 2
1U_0603_10V4Z
10U_0805_10V4Z 2 2
1U_0603_10V4Z 10U_0805_10V4Z
AOS 4422 AOS 4422
1 1
1
2 2
10U_0805_10V4Z 2 2
10U_0805_10V4Z
D
1
D
2 SUSP
G 2 SUSP
3 S Q17 G 3
3
3
R586 2N7002_SOT23
510K_0402_5% 1
C746
1
D
SUSP 2 0.1U_0603_25V7K
G 2
Q31 S
3
2N7002_SOT23
1
1
D D D D D D
2 SUSP 2 SUSP 2 SUSP 2 SUSP 2 SUSP 2 SYSON#
G G G G G G
S Q10 S Q7 S Q29 S Q2 S Q3 S Q32
3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 49 of 59
A B C D E
A B C D
PL2 PR1
PCN1 ADPIN VIN
VIN PD1 1K_1206_5% PQ1 B+
FBMA-L18-453215-900LMA90T_1812 2 1 1 2 3 TP0610K-T1-E3_SOT23
1
1 1 2
1
1 1N4148_SOD80 PR3 1
PR2 1K_1206_5%
G 2 10_1206_5% 1 2
12P_0402_50V8J
560P_0402_50V7K
470K_0402_5%
470K_0402_5%
G
1
PR4
12P_0402_50V8J
560P_0402_50V7K
3 PR6
1 2
1
1
PC1
PR5
1K_1206_5%
2
PC2
PC3
PC4
SINGA_2DC-G756I200 1 2
PD2
2
RLZ24B_LL34 PR7
2
1K_1206_5%
1 2
1
PR8
470K_0402_5%
1 2
1
PQ2 PQ3
DTC115EUA_SC70 DTC115EUA_SC70
40,52 ACOFF 2 2
3
2 2
BATT+ VIN
2
2
PD4
PD3 1N4148_SOD80
RB751V-40TE17_SOD323-2
1
PR9
1
33_1206_5%
PQ4 VL PR10 B+
TP0610K-T1-E3_SOT23 2.2M_0402_5%
2 1
2
CHGRTCP 3 1 VS
0.22U_1206_25V7K
1
1
VS PR11
1
PR12 499K_0402_1%
1
PC5
100K_0402_5% PC6
0.1U_0603_25V4Z PR13
2
2
PR14 100K_0402_1% LM393DR_SO8
2
22K_0402_5% PU1A
42,43 51ON# 1 2
8
27,51,53 MAINPWON PD5
2 3
P
3 3
+
1 1 O
0.01U_0402_25V7Z
52 ACON 3 - 2
PC7
1000P_0402_50V7K
RB715F_SOT323 PR15
4
1
1
191K_0402_1%
PC9
PC8 PR16
2
0.1U_0402_16V7K
PRG++ 2
2
1
499K_0402_1%
PR17 RTCVREF
200_0603_5% PU2
G920AT24U_SOT89 3.3V ACIN RHU002N06_SOT323
2
1
34K_0402_1% D 47K_0402_5%
2 IN OUT 3 1 2 1 2 CHGRTC
Min. typ. Max. RTCVREF 2 1 2 2 1
PACIN 52,54
1
4.7U_0805_6.3V6K
560_0402_5% 560_0402_5% G
1
1
GND
PC11
PC10
H-->L 14.589V 14.84V 15.243V S
3
1U_0805_25V4Z
2
1
1 PQ6
L-->H 15.562V 15.97V 16.388V
2
PR22 DTC115EUA_SC70
@ 66.5K_0402_1% 2 +5VALWP
BATT ONLY
2
Precharge detector
3
Min. typ. Max.
4
H-->L 6.138V 6.214V 6.359V 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN/DECTOR/RTC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 50 of 59
A B C D
A B C D
1 1
PC12 PC13
0.1U_0603_25V7K 0.1U_0603_25V7K
B+
1 2 BST5B_5V BST3B_3V 1 2
2
2
PR23
0_0402_5% PD6 3HG
PL3 5HG 1 2 MAX8734A_B+ CHP202UPT_SOT323-3
FBMA-L11-322513-151LMA50T_1210
1
VL
1
MAX8734A_B+
4.7_1206_5%
2
1
PR24
MAX8734A_B+ PQ7 MAX8734A_B+
8 1 PR26
G2 D2
1
2200P_0402_50V7K
7 2 0_0402_5% PQ8
D1/S2/K D2
4.7U_1206_25V6K
2200P_0402_50V7K
6 3 DL5 PC14 1 8
D1/S2/K G1 D2 G2
4.7U_1206_25V6K
5 4 0.1U_0603_25V7K 2 7
2
D1/S2/K S1/A D2 D1/S2/K
1
1
PC16
3 G1 D1/S2/K 6
1
PC15
0.1U_0603_25V7K
47_0402_5%
AO4916L_SO8 4 5
S1/A D1/S2/K
PC17
PC18
2
1U_1206_25V7K
PR27
AO4916L_SO8
2
1
PC20
2 2
2
PC19
1
VL PR28
2
10U_LF919AS-100M-P3_4.5A_20%
0_0402_5%
4.7U_0805_6.3V6K
1
1U_0805_16V7K
1
PC21
1
10U_LF919AS-100M-P3_4.5A_20%
PC22
2
PR29
2
2
0_0402_5%
PL4
18
20
13
17
BST5A_5V 14
V+
LD05
TON
VCC
1
BST5 ILM3
ILIM3 5
2
DH5 16
1
DH5
PL5
LX5 15
+5VALWP DL5 19
LX5
11 ILM5
DL5 ILIM5
21 OUT5
9 PU3 28 BST3A
1
FB5 BST3
10.2K_0402_1%
PR31 1 26 DH3
N.C.MAX8734AEEI+_QSOP28 DH3
2
47K_0402_5% 24 DL3
DL3
PR30
VS 1 2 1 2 6 27 LX3 +3VALWP
SHDN# LX3
1 4 ON5 OUT3 22
2
100K_0402_5%
3 ON3
1
150U_D_6.3VM
PR32
@ 3.57K_0402_1%
+ @ PZD1 7
1
FB3
2
PC23
RLZ5.1B_LL34 PC24 12 2
SKIP# PGOOD SPOK 53
PR33
3 0.047U_0402_16V7-K 3
2
PRO#
LDO3
0_0402_5% 8
GND
1
1
REF
2
0_0402_5%
PR34
PR35
+ PC25
1
2
150U_D_6.3VM
23
25
10
PR36 2VREF_1999
2VREF_1999
1
0_0402_5% 2
1
2
100K_0402_1%
100K_0402_1%
2
2
0.22U_0603_10V7K
4.7U_0805_10V6K
PR38
PR39
PR37
0_0402_5%
1
2
PC27
PC26
PR40
0_0402_5%
2
1
1
1
ILM3 ILM5
1
27,50,53 MAINPWON 1 2
2
499K_0402_1%
PR42
499K_0402_1%
PR41
PR43
47K_0402_5%
1
PC28 PC29
1
1U_0603_6.3V6M 0.047U_0402_16V7-K
2
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+5VALWP/+3VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 51 of 59
A B C D
A B C D E
Charger
Iadp=0~4.74A(90W)
P2
PQ9 PQ10 PR44 B+ PL6 CHG_B+ PQ11
AO4407L_SO8~N AO4407L_SO8~N P3 AO4407L_SO8~N
0.01_2512_1% FBMA-L18-453215-900LMA90T_1812
VIN 8
7
1
2
1
2
8
7
2 1 1 2 1
2
8
7
2200P_0402_50V7K
0.1U_0603_25V7K
6 3 3 6 3 6
4.7U_1206_25V6K
4.7U_1206_25V6K
5 5 5
1
1 1
PC30
PC31
PC32
PC33
4
4
1
PC146 PC147 PR47
2
1
0.1U_0603_25V7K 0.1U_0603_25V7K 47K_0402_1%
1
1 2
VIN
2
PR45
2
1
10K_0402_1%
0.1U_0603_25V7K
SI4810BDY-T1-E3_SO8
200K_0402_1%
2
PR46
5
6
7
8
47K_0402_5%
2
1
PR49
D
D
D
D
3
PC34
PQ12 1SS355_SOD323
2
PQ15
DTA144EUA_SC70
PD13
2
1
47K
ACOFF#
G
S
S
S
2 47K VIN 2 1
4
3
2
1
1
53 6C/8C#
2
G
PC149 PQ13
0.1U_0603_25V7K PU4 DTC115EUA_SC70
SI4810BDY-T1-E3_SO8
3 1 MAX1908ETI_QFN28
1
2
1
ACOFF
D
1 DCIN 2 ACOFF 40,50
5
6
7
8
PQ42 27
PC148 SI2301DS_SOT23~D CSSP
D
D
D
D
1
1U_0603_10V6K
PQ41
2 PQ14 2 1 17 PC150
3
DTC115EUA_SC70 57.6K_0402_1% PR197 CELLS @ 1000P_0402_50V7K
26
2
CSSN
G
S
S
S
PR198 @ 0_0402_5%
2 1 4
4
3
2
1
REF
150K_0402_5%
25 charger_DHI
3
DHI
1
RHU002N06_SOT323
3 PR61
CLS
PQ16
PR55
0.015_2512_1%
1908LDO BATT+
1
D charger_LX
LX 23 1 2 1 2
1
100K_0402_1%
2 2 1 2 1 12 REFIN
1
2 G 2
2
10U_LF919AS-100M-P3_4.5A_20%
PR201
DLO
4.7U_1206_25V6K
4.7U_1206_25V6K
4.7U_1206_25V6K
PL7
0.1U_0402_16V7K 9.31K_0402_1% 15K_0402_1% PC152
2
15 0.1U_0603_25V7K
2
1
VCTL
1
PC46
PC47
PC48
13 24 charger_BST 1 2
ICTL BST
1
11 PR202 0_0402_5%
2
ACOK# charger_DLOV PD14
8 SHDN# DLOV 22
1
D
10 ACIN 1SS355_SOD323
2 9 ICHG LDO 2 2 1
0.01U_0402_25V7K
G 2 1
2
S PQ17 40 IREF 28 PR203
3
2
CCV
PC153
PR204 19
CSIP
1
2
PGND
18
GND
CCS
PD8 CSIN
CCI
PR205 16 PC154
BATT
2
ACOFF# 1 2 100K_0402_1% 1U_0603_10V6K
1
1K_0402_1%
PC155
14
20
2
1U_0805_25V4Z
2
1
1N4148_SOD80
PR206
PR64 MAX1908-CCS
22K_0402_5%
0.01U_0402_25V7K
0.01U_0402_25V7K
50,54 PACIN 1 2
2
PC156
PC157
1
1
50 ACON
2
3 BATT+ 3
PC158
PR207 0.1U_0402_16V7K
0_0402_5%
Charge voltage
1 2
40 FSTCHG VS BATT+
4S CC-CV MODE : 16.8V
2
1
10K_0402_5%
1
PR209
PR67
0.01U_0402_25V7Z
PR208 PC159 845K_0603_1%
100K_0402_5% 0.1U_0402_16V7K
2
LI-4S :17.8V--BATT-OVP=1.9758V
1
2
1
PC49
+3VALWP
BATT-OVP=0.111*BATT+
1
2
PR68
1
300K_0603_0.1%
IREF=0.832*Icharge PR210 PR211
8
PU5B 511K_0402_1% RHU002N06_SOT323 10K_0402_5%
2
IREF=0.73~3.3V 5 1 2
P
+ PQ43
7
2
0
VS 40 BATT_OVP - 6
1
D
1
LM358ADR_SO8 2
1
PR71 G
2P4S:4800mAH/cell
8
1
0.01U_0402_25V7Z D
0.8C=3.84A + 3
P
2
1 2 6C/8C# 53
2
0 G
- 2
G
S RHU002N06_SOT323
3
4 LM358ADR_SO8 4
PQ44
4
OVP voltage :
LI-3S :17.8V----BATT-OVP=1.9758V
BATT-OVP=0.111*BATT+ Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Charger
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 52 of 59
A B C D E
A B C D
PR212
100K_0402_5%
1 2
PH1 under CPU botten side :
+3VALWP
BATT+ BATT++ CPU thermal protection at 80 degree C
PR213
PL8 1K_0402_5%
Recovery at 44(45) degree C
BATT+
2 1
FBMA-L18-453215-900LMA90T_1812 6C/8C# 52 1 2
1 2 BATT++
1
VL PR77 1
2
442K_0603_1%
1
1
PR214 VL
PC54 @1K_0402_5% VS
2
1000P_0402_50V7K
2
0.1U_0603_25V7K
PC53 PR81 PR80
1
0.01U_0402_25V7Z 10.7K_0402_1% 150K_0402_1%
PC55
1
2
2
61.9K_0402_1%
8
PR83 PU1B
PR84 1 2 5
P
7 1K_0402_5% + MAINPWON 27,50,51
PJP2 battery connector 6
2 1 TM_REF1 6
O 7
5 -
G
4
SM ART LM393DR_SO8
4
3
100K_0603_1%_TH11-4H104FT
PR85
Batter y: 2
1
1K_0402_5%
1 .GND 1 2 BATT_TEMP
BATT_TEMP 40
1U_0805_25V4Z
2. SMC
1
SUYIN_200275MR007G161ZL PC56
PJP1
PC57
1000P_0402_50V7K PR86
3.SMD
PH1
PR87 2 1 VL
2
4.TS 6.49K_0402_1%
150K_0402_1%
1 2 +3VALWP
5 . B/I
2
6. ID PR88
1
150K_0402_1%
2 7 .BA TT+ PR89 2
100_0402_5%
1 2 EC_SMB_DA1 15,40,41,45
2
PR90
100_0402_5%
1 2 EC_SMB_CK1 15,40,41,45
+1.8V
PU6
1 VIN VCNTL 6 +3VALW
PQ20
TP0610K-T1-E3_SOT23 2 5
GND NC
1
1
PC58 3 7 PC59
10U_1206_6.3V7K VREF NC 1U_0603_6.3V6M
2
3
B+ 3 1 +VSBP PR91 4 8 3
1K_0402_1% VOUT NC
9
2
TP
1
PR92 APL5331KAC-TRL_SO8
100K_0402_5% PC60 PC61
0.22U_1206_25V7K 0.1U_0603_25V7K
+0.9VSP
2
0.1U_0402_16V7K
1K_0402_1%
2
22U_1206_6.3V6M
1
1
PR93
PC62
PC63
@ PC64
2
2
22U_1206_6.3V6M
2
VL PR94 PR95
22K_0402_5%
1
0_0402_5% D
2
SUSP 1 2 2
43,49,54 SUSP
1
PR96 G PQ21
100K_0402_5% S
3
1
RHU002N06_SOT323
PR97 PC65
1
2
51 SPOK 1 2 2
G RHU002N06_SOT323
S
3
1
PC66
@ 0.1U_0402_16V7K
2
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN. / OTP/+0.9VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 53 of 59
A B C D
5 4 3 2 1
AC Adapter Detector
PJ1 PJ2
+1.5VSP 1 2 +1.5VS +1.8VP 1 2 +1.8V
PAD-OPEN 3x3m PAD-OPEN 3x3m Vin Detector
(2.5A,100mils ,Via NO.=5) (6A,240mils ,Via NO.= 12) 17.90V/17.24V
D D
1
10K_0402_5% PR98
PR69 VS 10K_0402_5%
PJ5 PJ6 84.5K_0402_1% AC IN
1 2 ACIN 28,40
+3VALWP 1 2 +3VALW +2.5VSP 1 2 +2.5VS
PR74
2
8
22K_0402_5% PU7A
PAD-OPEN 3x3m PAD-OPEN 3x3m
1 2 3
P
+ PACIN
(4.5A,180mils ,Via NO.= 9) (0.3A,40mils ,Via NO.= 2) O 1 PACIN 50,52
2 -
G
20K_0402_1%
1
1
PJ7
PR72
PJ8 LM393DR_SO8
4
1 2 +1.05VS +VSBP 1 2 +VSB PC51 PZD2 PR99
+1.05VSP 1 2 0.1U_0603_25V7K 10K_0402_5%
RLZ4.3B_LL34
2
JUMP_43X79 PC52
PAD-OPEN 3x3m
2
1000P_0402_50V7K
2
(2A,80mils ,Via NO.= 4)
2 1 RTCVREF
C PL9 PR70 C
FBMA-L11-322513-151LMA50T_1210 10K_0402_5%
1 2 MAX8578_B+
B+
8
PU7B
0.1U_0603_25V7K
4.7U_1206_25V6K
P
+
O 7
1
6 -
G
PC70
PC71
0_0402_5%
PR106 LM393DR_SO8
2
4
1.5V_EN 1 2 SUSP# 37,40,41,43,49
2
PC72
2
2
PR107 @ 1U_0805_25V4Z
1
4.99K_0402_1% PC73
1
0.01U_0402_25V7Z
1
PU8
1.5V_OCSET 10 9 PR108
OCSET EN 0_0402_5% PQ23 PU9
1.5V_SS 2 81.5V_DH1 2 1 1.5V_DH2 8 1 CM8562IS_PSOP8
SS DH G2 D2
7 D1/S2/K D2 2
1
5 D1/S2/K S1/A 4
1.5V_VL 3 5 +2.5VSP
2
VL DL
2
PC74
4.7U_1206_25V6K
AO4916L_SO8 2 7AGND +5VALW
1.5V_DL1
VFB AGND
1
PC75
4 GND BST 6
1
B B
10_0603_1%
MAX8578EUB+T_UMAX10 3 6
2
VTT VCCA
1.5V_BST
PR110
1 2 1.5V_DL2
AGND
PC76
4.7_0402_5% 4 5
VTT REFEN
2
1U_0603_6.3V6M
4.7U_0805_6.3V6K PR109 PL10
PD9
PC77
3.0UH_SPC-07040-3R0GP_5A_30%
REF_EN
9
2 1 1 2 1 2 +1.5VSP
1
2
1 2
1
0.1U_0603_25V7K
PR111
1SS355_SOD323 PC78
PR112
4.7_1206_5%
AGND
1 200K_0402_1%
1
2
+5VS 0.1U_0603_25V7K 7.15K_0402_1% 30_0402_5% 330U_D2E_2.5VM 22U_1206_6.3V6M
PC80
PC81
+
PR116 2 1 2 1 RTCVREF
1 2
1
1.5K_0402_1%
PC83 2 PR115
1 2
680P_0603_50V8J PC82 64.9K_0402_1%
0.047U_0402_16V4Z
2
1 2
RHU002N06_SOT323
1
1
D PQ24
PR117 PC84 PC85 2 SUSP
SUSP 43,49,53
825_0402_1% 0.033U_0603_25V7K 0.1U_0603_25V7K G
1
3
2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.5VSP/RTCVREF
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 54 of 59
5 4 3 2 1
5 4 3 2 1
D D
MAX8743_B+
PL1
1 2 B+
4.7U_1206_25V6K
2200P_0402_50V7K
FBMA-L11-322513-151LMA50T_1210
PC87
PC86
+5VALW
4.7U_0805_6.3V6K
1
@
PC88
4.7U_1206_25V6K
4.7U_1206_25V6K
2200P_0402_50V7K
C C
2
PD10
PC91
DAP202U_SOT323
5
6
7
8
PC89
PC90
PQ26 PQ25
SI4800BDY-T1-E3_SO8
D
D
D
D
2
5
6
7
8
SI4800BDY-T1-E3_SO8
3
BST2B_1.05V
D
D
D
D
BST1B_1.8V
G
S
S
S
1U_0805_25V4Z
0.1U_0603_25V7K PC95
4
3
2
1
G
S
S
S
1
5
6
7
8
5
6
7
8
PQ27 PR119
D
D
D
D
4.7U_0805_6.3V6K
SI4810BDY-T1-E3_SO8 0_0402_5% PQ28
D
D
D
D
150U_D_6.3VM
150U_D_6.3VM
4.7U_0805_6.3V6K
PR120
22
1 SI4810BDY-T1-E3_SO8 1
9
PU10 0_0402_5%
1
1
1
S
S
S
PC96
PC99
PC97
+ BST1A_1.8V 25 21 +
UVP
V+
VCC
BST1 VDD
G
S
S
S
PC98
4
3
2
1
1
DH_1.8V 26 19 BST2A_1.05V
2
4
3
2
1
2
2 PR219 DH1 BST2 DH_1.05V 2
DH2 18
LX_1.8V 27 17 LX_1.05V PR121
LX1 LX2
1
2
28 MAX8743EEI_QSOP28 CS2
B CS1 B
1 OUT1 OUT2 15
14
2
FB2
2 FB1 ON2 12
1
1
PGOOD 7
TON 5
PR220 37,40,49 SYSON 2 1 11 PR122
10K_0402_1% ON1 10K_0402_1%
ILIM2 13
PR123 3 1 2 VS_ON 43
SKIP
GND
OVP
REF
2
2
0_0402_5% ILIM1
1
PR124
PC100 PR125 0_0402_5%
8
23
10
@ 0.01U_0402_25V7Z 33K_0402_1%
2
2 1
PR126
2 1 100K_0402_1%
1
100K_0402_1%
15K_0402_1%
1
PR127
PR128
PC101
0.22U_0603_10V7K
2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.05VSP/+1.8VP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 55 of 59
5 4 3 2 1
5 4 3 2 1
+5VS
CPU_B+ PL13 B+
PR129 FBMA-L11-322513-201LMA40T_1210
5VS12 1
2 1
0.01U_0402_25V7Z
0_1206_5% 1
2200P_0402_50V7K
0.1U_0603_25V7K
PR130
PC103
10_0402_5% + PC102
1
10U_1206_25VAK
10U_1206_25VAK
10U_1206_25VAK
100U_25V_M
200K_0402_5%
PC104
PC105
PC106
PC107
PC108
2
2
2 PR131 1
2
2
D D
2
PC109
2
2.2U_0603_6.3V6K
2
PR132 PC110
1
13K_0402_1% 1U_0603_6.3V6M
5
PQ29
PU11 SI7840DP_SO8
1
NTC
PH2 V CC 19 25
100K_0603_1%_TH11-4H104FT Vcc VDD 0_0402_5% 0.22U_0603_16V7K 4
1 2 6 THRM TON 8
PR135 PC111 0_0402_5%
PR134 0_0402_5% 2 1 31 30 BST1_CPU 1 2 BSTM1_CPU 1 2
5 CPU_VID0 D0 BST1 +CPU_CORE
PR215
3
2
1
PR136 0_0402_5% 2 1 32 29 1 2 PL14
5 CPU_VID1 D1 DH1 P_0.36H_ETQP4LR36WFC_24A_20%
4.7_1206_5%
PR137 0_0402_5% 2 1 33 28 LX1__CPU 2 1 +CPU_CORE
5 CPU_VID2 D2 LX1
680P_0402_50V7-K 2.1K_0402_1%
PR138 0_0402_5% 2 1 34 26 DL1__CPU
5 CPU_VID3 D3 DL1
5
6
7
8
5
6
7
8
10_0402_5%
PR139
PR141
PR140 0_0402_5% 2 1 35 27
5 CPU_VID4 D4 PGND1
PR142 0_0402_5% 2 1 36 18 @
5 CPU_VID5
2
D5 GND
1
3.48K_0402_1% NTC PH3
1
IRF8113PBF_SO8
PR143 0_0402_5% 1 2 37 17 CSP1__CPU 4 4 PR145
5 CPU_VID6 D6 CSP1
1
1 2 1 2 @
5
VCCSENSE
DL1__CPU
PR1472 71.5K_0402_1%
1 7 16 CSN1_CPU
TIME CSN1
PC112
PR144
PQ30 10KB_0603_1%_TH11-3H103FT
2
PQ31
2 1 9 12 FB_CPU 1 2
3
2
1
3
2
1
470P_0402_50V8J PC113 CCV FB IRF8113PBF_SO8
1 2 11 10 C CI_CPU PC114 0.22U_0603_16V7K
C REF CCI C
1
PR149 0_0402_5%
1 2 3 22 LX2_CPU PR151 0_0402_5% PR194
5 PSI# PSI LX2
PR150 0_0402_5% 1 2 0_0402_5%
+3VS 2 24 DL2__CPU
PWRGD DL2 PR152 @ 1K_0402_1% PC116 @ 1000P_0402_50V7K
2
2
0_0402_5%
1 23 1 2 1 2 CPU_VCC_SENSE
CLKEN PGND2
PR153
2
1
0_0402_5% VRHOT CSN2 PR157 100_0402_5%
2
4 13
1
BSTM2_CPU
6,14,28 VGATE 0_0402_5% 4700P_0402_25V7K
1
PR161 NTC PR159 PR160
1 2 @ 3K_0603_1% @ 3K_0603_1%
14 CLK_ENABLE# MAX8770GTL+_TQFN40
2
1 2 1 2
1 2 PC119
40 VR_ON
1000P_0402_50V7K PC118
1
2
CPU_B+
0.22U_0603_16V7K
PR163 PR162 470P_0402_50V8J
1
0_0402_5% PR164 +3VS 2 20K_0402_1%
PC120
@ 10K_0402_5%
1
PR165
2200P_0402_50V7K
10U_1206_25VAK
10U_1206_25VAK
10U_1206_25VAK
0.1U_0603_25V7K
PR166 100_0402_5%
VRHOT
1
56_0402_5%
1
PC122
PR167 PQ32
1
PC121
PC123
PC124
PC125
B @ 0_0402_5% SI7840DP_SO8 B
2
2
36,40 TV_THERM#
PR216
1
1 2 4
1 2 PR169
40 POUT
@ 10_0402_5%
2
PR168 10K_0402_5%
PC126
2
3
2
1
0.1U_0402_16V7K 2 1
1
4.7_1206_5%
PL15
1
P_0.36H_ETQP4LR36WFC_24A_20%
5
6
7
8
5
6
7
8
PR170
2.1K_0402_1%
IRF8113PBF_SO8
1
PQ34 @
PR171
IRF8113PBF_SO8
680P_0402_50V7-K
DL2__CPU
4 4
2
1
PC127
NTC
PR172
PQ33
3.48K_0402_1% PH4
3
2
1
3
2
1
2
1 2 1 2
10KB_0603_1%_TH11-3H103FT
@
1 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 56 of 59
5 4 3 2 1
5 4 3 2 1
POWER_SEL H L
D D
VGA_B+
PL18
2 1 B+
4.7U_1206_25V6K
4.7U_1206_25V6K
2200P_0402_50V7K
FBMA-L11-322513-151LMA50T_1210
1
PC134
+5VALW
PC133
PC132
PQ35
2
8 G2 D2 1
7 D1/S2/K D2 2
4.7U_0805_6.3V6K
4.7U_1206_25V6K
2200P_0402_50V7K
@ 6 3
D1/S2/K G1
PC130
5 D1/S2/K S1/A 4
PC131
PC129
PD12 AO4916L_SO8
2
5
DAP202U_SOT323
PQ36
SI7840DP_SO8 0_0402_5%
+VGA_CORE_P PR218
BST1B_VGA 2
3
4 2 1 BST2B_1.2V @
PL17
+VGA_CORE_P
0.56UH_ETQP4LR56WFC_21A_20%
0.1U_0603_25V7K
PC135
0.1U_0603_25V7K 1U_0805_25V4Z PR175
PC138 20_0603_5%
0.1U_0603_25V7K
PC136
PL16
3.0UH_SPC-07040-3R0GP_5A_30%
+1.2VSP
1
2
3
C 1 2 2 1 PC137 1 2 2 1 1 2 +1.2VSP C
4.7_1206_5%
5
6
7
8
5
6
7
8
1
1
2
330U_D2E_2.5VM
PR217
1 PQ37
AO4410_SO8 PR176 PR177
2
PC140
+ 2_0402_5% 0_0402_5%
4.7U_0805_6.3V6K
680P_0402_50V7-K
22
4
150U_D_6.3VM
4.7U_0805_6.3V6K
4 4 @ PU12 1
1 2
1
2 BST1A_VGA 25 21
UVP
V+
VCC
BST1 VDD
1
1
PC160
PC142
PC139
+
DL_VGA
DL_VGA
PC141
DH_VGA 26 19 BST1A_1.2V
DH1 BST2
1
2
15K_0402_1%
10K_0402_1%
18 DH_1.2V
2
3
2
1
3
2
1
2
DH2 2
PR179
PR178
PQ38 LX_VGA 27 17 LX_1.2V
DL_VGA LX1 LX2 DL_1.2V
24 DL1 DL2 20
AO4410_SO8 @ 16 @
@ CS2
28
2
1
CS1
1 OUT1 OUT2 15
14 FB_1.2V
FB_VGA FB2 VGA_ON
2 FB1 ON2 12 1 2 VGA_ON 43
PR184 0_0402_5%
7
MAX8743EEI_QSOP28 PGOOD
1
2
VDD_PWRGOOD 17
15K_0402_1%
TON 5 2 1 REF_VGA
PR196
VGA_ON 1 2 11 PR182
ON1 PR195
ILIM2 13 49.9K_0402_1%
PR185 3 @ 0_0402_5%
SKIP
GND
OVP
REF
0_0402_5% ILIM1
2
1
210K_0402_1%
23
10
1
+VGA_CORE PR188
B B
PR186
205K_0402_1%
PR180
+5VALW PR187 2 1
150K_0402_1% 1 2 REF_VGA
1REF_VGA
2 1
2
2
2
@
@ 100K_0402_1%
200K_0402_1%
PR189
100K_0402_1%
PR190 15K_0402_1%
PR191
PR192
@ 100K_0402_5%
1
D PC144
1
2 0.22U_0603_10V7K
2
G
2
S PQ39
3
PR193 @ RHU002N06_SOT323
1
@ 100K_0402_5% D
15 POWER_SEL 2 1 2
G
S
3
1
PC145
@ 0.01U_0402_25V7Z PQ40
2
@ RHU002N06_SOT323
PJ10
+1.2VSP 1 2 +1.2VS
A PAD-OPEN 3x3m A
PJ9
+VGA_CORE_P 1 2 +VGA_CORE
PAD-OPEN 3x3m Security Classification Compal Secret Data Compal Electronics, Inc.
PJ11 Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title
+VGA_CORE_P 1 2 +VGA_CORE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+VGA_CORE_P/+1.2VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
PAD-OPEN 3x3m DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 57 of 59
5 4 3 2 1
5 4 3 2 1
6. Page18 : Modify VGA Device ID for G72MV & G73. 7. Page30 : Delete R395 & C486, add R394 for SATA bridge reset timing
7. Page24 : Change VGA_DDC_CLK & VGA_DDC_DATA to Q26 & Q27 Level shift. Modify SATA HDD connector library
Add R781 & R782 4.7K_0402_5% 8. Page31 : Delete IDE_CD_L, IDE_CD_R & CD_GNDA
Change C589, C596, C583, C587, C594, C585 to 150P_0402_50V8J
9. Page34 : Add R783, R784, R785 for BCM5787M, stuff R214 when use BCM4401E,
8. Page28 : Change SB_INT_FLASH_SEL# from ICH7M GPIO38 to GPIO33. Del R168, change Q5 P/N
9. Page29 : Change C437 from 0.1U_0402_16V4Z to 1U_0402_6.3V4Z 10. Page36 : Add +3VS, GND at JP30 for 3G device
10. Page30 : Change PATA HDD+ODD select resistor form RP to R_0402 (0_0402_5%) 11. Page38 : No stuff U14, R253, R246 & stuff R261
11. Page34 : Stuff R175 & no stuff R182( 0_0402_5%) for BCM4401E/BCM5789M/BCM5787M 12. Page40 : Reserved R793 for ALC883 pin47 EAPD, & define KB910 Pin174 as EC_PWROK
12. Page35 : Modify LAN_ACTIVITY# & LAN_LINK# LED color 13. Page41 : No stuff U21, U30, C490, R391, R390, R388 & stuff R418
13. Page 36 : Add JP38 & C895 for CAMERA. 14. Page42 : Modify SW9 Pin1, Pin5 as NC, no stuff C7
Swap JP17 PCIE TX & RX Signal. 15. Page43 : Modify Power OK circuit. add R790 for EC_PWROK, reserved Q41, R420, C512
Swap JP30 PCIE TX & RX Signal. add D35, D37, Change BATT1 P/N to SP093PA0200
14. Page37 : Connect JP34 SMBus interface to ICH7M
Change JP4 & JP5 USB connector to BOTTOM. 16. Page44 : Delete ALC883 CD input circuit, add HD_EAPD# signal
17. Page46 : Add C927, C928, reserved R791, R792
15. Page38 : Add 1394@ BOM Structure.
18. Page49 : Stuff Q33
16. Page41 : Delete LCM interface Extension I/O.
C No stuff R390 & Stuff R418 for Flash ROM interface. C
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW PIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 58 of 59
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR PIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 59 of 59
5 4 3 2 1