Design and Optimization of a 2.
4GHz Integer-N
Frequency Synthesizer in 0.18-µm CMOS
Technology
V. V. Ulansky, H. M. Elsherif, E. H. Aboadla
Dep. of Electrical and Electronic Engineering
Al Fateh University
Tripoli, Libya
vulanskyi@yahoo.com
Abstract- This paper describes the design and optimization
of a CMOS PLL frequency synthesizer for Bluetooth
transceiver in commercial 0.18-µm CMOS technology with
2V supply voltage. A new criterion is used for optimizing
CMOS LC VCOs. The proposed technique is illustrated by
optimizing seven different CMOS LC VCOs. The best
performance was obtained for the PMOS differential
Colpitts VCO exhibiting a phase noise of -134.3dBc/Hz at
1MHz offset and -143.8dBc/Hz at 3MHz offset from 2.44-
GHz carrier with 6.2mW power consumption. The
programmable divider has a dual-modulus prescaler
(divide by 32/33) and two counters.
Keywords — Phase-locked loop, synthesizer, voltage-
controlled oscillators, phase noise, dual-modulus prescaler,
phase detector.
Ø INTRODUCTION
The Bluetooth standard was designed for targeting
short-range wireless communications with data rates of
1Mb/s at 10m distance [1]. Bluetooth technology
redefines a new way for connectivity. It is a short-range
radio link intended to replace the cables connecting
portable and/or fixed electronic devices. Bluetooth
system operates in the license free 2400÷2483.5 MHz
ISM band. The phase-locked loop (PLL) of a Bluetooth
transceiver has to be able to provide frequencies in the
ISM band with channel spacing of 1MHz. Special
requirements must be imposed on the settling time when
the system hops. The standard specifications require the
synthesizer to be able to hop 1600 times per 1s while
delivering data packets. In the worst case the settling
time has to be less than 200µs. The phase noise at 3MHz
offset has to be less than –124dBc/Hz.
This paper describes the design and optimization of
an integer-N frequency synthesizer using TSMC 0.18µm
CMOS technology with 2V supply voltage.
I.A. Machalin
Dep. of Telecommunication Engineering
National Aviation University
Kiev, Ukraine
migor06@rambler.ru
Ø CONCLUSIONS
An integer-N frequency synthesizer for Bluetooth
transceiver was designed and simulated using TSMC
0.18µm mixed-signal CMOS technology. The target of
this design is to improve the performance of the
synthesizer by means of reducing the VCO phase noise
and power consumption. The designed and optimized
VCO has a phase noise of -134.3dBc/Hz at 1MHz offset,
-143.8dBc/Hz at 3MHz offset, and only 6.2mW power
consumption. The performance of the designed PLL
synthesizer is summarized in Table 3.
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