*in vdd out

.subckt inv 1 3 2
MP1 2 1 3 3 CMOSP L=0.25u W=1.161u
MN1 2 1 0 0 CMOSN L=0.25u W=0.45u
.ends
*in c cn vdd out
.subckt invcom 2 1 3 5 4
MP1 6 3 5 5 CMOSP L=0.25u W=0.967u
MP2 4 2 6 5 CMOSP L=0.25u W=0.967u
MN1 4 2 7 0 CMOSN L=0.25u W=0.375u
MN2 7 1 0 0 CMOSN L=0.25u W=0.375u
.ends

.subckt nor2 1 2 4 3
MP1 5 1 4 4 CMOSP L=0.25u W=1.935u
MP2 6 2 5 5 CMOSP L=0.25u W=1.935u
MN1 3 1 0 0 CMOSN L=0.25u W=0.375u
MN2 6 2 0 0 CMOSN L=0.25u W=0.375u
.ends

.subckt nand2 1 2 4 3
MP1 3 2 4 4 CMOSP L=0.25u W=0.483u
MP2 3 1 4 4 CMOSP L=0.25u W=0.483u
MN2 3 1 5 5 CMOSN L=0.25u W=0.375u
MN1 5 2 0 0 CMOSN L=0.25u W=0.375u
.ends

.subckt and2 1 2 4 3
x1 1 2 4 3 nand2
x2 1 3 2 inv
.ends

.subckt or2 1 2 4 3
x3 1 2 4 3 nor2
x4 1 3 2 inv
.ends