Microelectronics Reliability xxx (xxxx) xxx

Contents lists available at ScienceDirect

Microelectronics Reliability
journal homepage: www.elsevier.com/locate/microrel

Design and verification of multiple SEU mitigated circuits on SRAM-based

FPGA system
Chang Cai a, b, *, Bingxu Ning c, Shuai Gao b, Tianqi Liu b, Liewei Xu a, c, Mingjie Shen c, Jian Yu a
a
State Key Laboratory of ASIC and System, Fudan University, Shanghai, China
b
Institute of Modern Physics, Chinese Academy of Sciences, Lanzhou, China
c
FPGA Development Department of Shanghai Fudan Microelectronics Group, Shanghai, China

A R T I C L E I N F O A B S T R A C T

Keywords: This paper addresses the issue of soft error mitigation for Static Random-Access Memory (SRAM)-based Field
Heavy ions Programmable Gate Arrays (FPGAs) system in radiation environment to reduce their malfunction and system
Irradiation failure rates in space missions. Seven representative circuits are designed by using the logical resources of SRAM-
Hardened
based FPGA. The accelerator tests investigate that the clock distribution of the Triple Modular Redundancy
Single event upset
(TMR) circuits is vital to achieve a high Single Event Upset (SEU) tolerance. The separated DTMR_NEW circuits
are proposed to overcome the weakness of the conventional TMR circuits, and a 25× improvement of SEU
tolerance for the separated DTMR_NEW circuits are verified. The statistical estimations are desirable for engi­
neers to assess and enhance the SEU tolerance of their designed systems at earlier stages to reduce the time and
development costs.

1. Introduction Redundancy (TMR) as one of the most popular circuit-level hardening

Modern spacecrafts use more advanced payload electronic equip­
ment than ever before to perform advanced onboard data processing to
overcome the limited downlink bandwidth and maximize data acquisi­
tions [1–4]. Hence, the Static Random-Access Memory (SRAM)-based
Field Programmable Gate Arrays (FPGAs) which can provide flexible
configuration and high-speed data processing are increasingly being
used for high-reliable and safety-critical applications to satisfy the
mission requirements [1–2]. The SRAM-based FPGAs containing a lot of
programmable logic and memory resources which are widely used to
implement the pre-defined logic functions by designed bitstreams are
sensitive to the radiation environments. If an essential bit flipped, the
pre-defined functions of FPGA may be invalided. For example, if an ion
induced Single Event Upset (SEU) occurred in a Look-Up Table (LUT),
the logical functions implemented by the LUT will be changed, and the
upset errors may be propagated from the LUT to the other related logics,
resulting in catastrophic failures [5–8]. Thus, unit-level and circuit-level
hardening strategies are proposed in recent years to mitigate the influ­
ence of SEU [9,10]. Different from the unit-level hardness, the circuit-
level hardening strategies are useful for the FPGA users due to the
flexible programmable ability of the FPGA devices. Triple Module
strategies is useful for FPGA design, by splitting each logic resource into
three copies and voting to the output value based on a majority voter
[10–12]. Significant contributions of the SEU mitigation of TMR strategy
have been investigated based on the irradiation experiments of submi­
cron and deep-submicron FPGAs [10,13–16], and the reduced SEU rate
is appealing to the electronics of spacecrafts and space stations to
improve the on-orbit safety.
In recent years, TMR strategy is implemented in many ways [10].
However, with the feature size scaling down, the issues of errors caused
by charge sharing effect of a single heavy ion become serious and even
dominate in the total SEU cross sections of unhardened FPGAs [17–21].
The Peripheral Buffer Induced Errors (PBIE) may lead the traditional
hardening techniques invalid. In addition, the PBIE may also present
considerable influence on radiation tolerance of the whole TMR circuits.
Hence, it is imperative to examine the single event sensitivity and reveal
the potential mechanisms of different hardening circuits for the
advanced SRAM-based FPGA and implement effective hardening
strategies.
This paper presents the specially designed TMR circuits to further
mitigate the SEU influence without additional resource consumption. A
comprehensive study is provided to investigate the SEU sensitivities of

* Corresponding author
E-mail address: caichang@fudan.edu.cn (C. Cai).

https://doi.org/10.1016/j.microrel.2021.114340
Received 21 May 2021; Received in revised form 14 July 2021; Accepted 15 August 2021
0026-2714/© 2021 Elsevier Ltd. All rights reserved.

Please cite this article as: Chang Cai, Microelectronics Reliability, https://doi.org/10.1016/j.microrel.2021.114340
C. Cai et al.
multiple error mitigated chains. Thus, we reexamined the TMR effi­
ciency and quantified the ratios of SEU improvements of the proposed
TMR circuits by a series of ground heavy ion experiments. We think that
the layout and routing methods for the TMR chains are useful for the
FPGA users in designing of high-reliable systems, and helpful to promote
space applications of the advanced commercial FPGAs.
The organization of this paper is as follows. In Section 2, the phi­
losophy and methodology of our designed hardening circuits are clearly
illustrated. The introductions of testing methods and evaluation plat­
forms are detailed in Section 3. The experimental results as well as some
related discussions of SEU tolerance of different circuits are provided in
Section 4. The conclusions are provided in Section 5.
2. Circuits design
There are three essential factors related to the SEU tolerance of D-
type flip-flops (DFF) chains, including the inherent critical charge of DFF
cell, the methods for cell distributions, and the peripheral buffer utili­
zations. Thus, the special circuits implemented in FPGA should concern
all of the resource configuration, distribution and constrain, and buffer
utilization.
The row-oriented and column-oriented manners of DFF chains are
designed. The triplicated DFF cells can be instantiated either in a
dependent SLICE or in different SLICEs, which is depend on the
constrain file. The PBIE may from the Global Clock Buffers (BUFG),
Regional Clock Buffers (RCLK) and Local Clock Buffers (LCLK) in SLICEs,
as shown in Fig. 1. Thus, we customize the clock buffers in DFF chains.
BUFG is the most commonly used clock resource, connecting to every
clock point and drive the global clock networks in FPGA [9]. Each RCLK
drives total 50 SLICEs in two columns or 100 SLICEs in four columns (25
SLICEs of one column is connected by switch matrix), and the local clock
buffer inside a SLICE drives all the DFFs therein [10].
The DFF shift register chains are implemented in 28 nm XC7K325T
FPGA, and each DFF chain contains 4799 stages (4799 bits in total for
each chain). Seven different DFF chains including two standard DFF
chains and five hardened DFF chains are detailed in Table 1, and a di­
agram for the structure of the multiple DFF chains are shown in Fig. 2.
The data input port, clock port, and data output port are necessary
for each DFF chain. Two standard DFF chains are configured for com­
parison, including a standard DFF chain with a synchronous reset port
(Standard_SYN), and a standard DFF chain with an asynchronous reset
port (Standard_ASYN). Five TMR hardened DFF chains are implemented
in FPGA to investigate the effective SEU mitigation strategies and
improve the reliability of FPGA-based systems. For these hardened DFF
chains, the feature of data input and data output ports are identical. The
Local placed row-oriented TMR (LTMR_ROW) chains have one global
clock port, and only for the LTMR_ROW chains, the triplicated DFFs of
each stage are instantiated in one SLICE. Both the row-oriented
Fig. 1. Diagram of the PBIE.
2
Microelectronics Reliability xxx (xxxx) xxx
Table 1
The basic information of the implemented DFF chains in FPGA.
Name Hardening strategies Orientation Specialties
Standard_SYN No Row Synchronous reset
Standard_ASYN No Row Asynchronous reset
LTMR_ROW Local TMR Row No reset
GTMR_ROW Global TMR Row No reset
DTMR_ROW Distributed TMR Row No reset
DTMR_COL Distributed TMR Column No reset
DTMR_NEW Distributed TMR Column No reset
Distributed TMR (DTMR_ROW) chains and the column-oriented
Distributed TMR (DTMR_COL) chains employ one independent global
clock port, as shown in Fig. 3. The new separated Distributed column-
oriented TMR (DTMR_NEW) chains are implemented to minimize the
influence of RCLK, and the scheme of DTMR_NEW chains are shown in
Fig. 4. While the global placed row-oriented TMR (GTMR_ROW) chains
employ three independent global clock ports. For the DTMR_COL,
GTMR_ROW, and DTMR_NEW chains, one SLICE only places one DFF
cell, indicating that the hardened cells are hard to be affected by the
charge sharing effects in radiation environments.
Though the full TMR circuits are utilized, the PBIE may still exist due
to the buffer controlling structure (shown in Fig. 3), leading the tripli­
cated DFF chains invalided. Thus, the DTMR_NEW scheme (Fig. 4) is
proposed to minimize the radiation sensitivity of both the BUFG and
RCLK. The separated RCLKs are all connected to one external clock
signal, each of which drives a different DFF.
3. Experimental setup
The XC7K325T FPGA is selected as the Device Under Test (DUT). The
backside silicon substrate of DUT is thinned down to ~60 μm, and each
thinned DUT is fixed in a test board that has individual power input and
a number of high-performance and high-range I/O pins. For the backside
irradiation of flip-chip devices, the silicon substrate is thinned. Backside
thinning with good uniformity in residual Si thickness is achieved due to
the limited area of the implemented DFF module. The thickness of the
substrate is measured during the substrate thinning. Besides, the test
board includes a controller FPGA, which realizes data writing, reading,
and comparison. The serial communication module is employed for
receiving and executing the command of the PC computer.
The DUT are irradiated in a vacuum chamber at China Institute of
Atomic Energy, and in air condition at the Heavy Ion Research Facility in
Lanzhou, in the Institute of Modern Physics, Chinese Academy of Sci­
ences. The information of experimental ions is listed in Table 2. The two
low LET ions are suitable to extract the SEU results due to the slow SEU
and interrupt rate they induced, leading the efficiency of irradiation test
improved. All irradiation tests are performed at a normal incidence, and
C. Cai et al. Microelectronics Reliability xxx (xxxx) xxx

Fig. 2. A diagram for the standard, LTMR hardened, GTMR hardened and DTMR hardened DFF chains.

Fig. 3. The sensitive DTMR_COL scheme. Two of the triple hardened cells may be affected at the same time.

3
C. Cai et al. Microelectronics Reliability xxx (xxxx) xxx

Fig. 4. The designed DTMR_NEW scheme.

and presented on the computer.

Table 2
Ions information in irradiation experiments (each irradiation condition is
repeated three times with different DUT samples). 4. Results and discussions

Ions Data Energy Surface LET Effective Ion Flux

The PBIE is mainly originated from the clock or reset buffers, as
pattern (MeV) (MeV⋅cm2/ LET range in (ions/
mg) (MeV⋅cm2/ silicon s⋅cm2) illustrated above. The PBIE generated in the reset path is easy to be
mg) (um) observed and distinguished, due to the reset function which leads data
12
C 0/1/ 80.0 1.7 2.4 127.0 1× “1” to data “0”. Considering that the reset port is not indispensable for
square 104 DFF chains, in our design, only the standard (unhardened) DFF chains
wave employ the reset ports with the controlled cell stages identical to the
19
F 0/1/ 100.5 4.4 7.4 72.7 1× clock buffers illustrated above. The examples for PBIE of the reset
square 104
buffers are shown in Fig. 5(a), (b), and (c). In Fig. 5(a), the square wave
wave
181
Ta square 1623.0 78.8 84.9 95.3 5× data pattern (10101010) is written into the DFFs, and a successive 25
wave 102 errors in total (“1” upset to “0”) may appear if ions strike the Regional
Reset Buffer (RRET). Similarly, a successive 50 errors in total (“1” upset
to “0”) may appear if the full “1” data is written into DFFs, as shown in
a 5% reduction of the nominal voltage of the DUT is utilized. The Linear
Fig. 5(b). In addition, twofold of the errors may be captured if the buffers
Energy Transfer (LET) values are calculated by the Stopping and Range drive 100 SLICEs in four columns, as shown in Fig. 5(c). However, for the
of Ions in Matter (SRIM) software. In LET calculation, the materials and
clock buffers, the influence of SEU cross sections is much different from
the thickness of layers are considered in the SRIM software. And the the reset buffer, which is dramatically depends on the data patterns. For
calculated effective LET values at the active regions mainly include the
the full “0” data pattern, the transients in peripheral clock buffer are
energy loss after penetrating the air layer and the 60-μm silicon sub­ masked. Therefore, the measured SEUs represent the intrinsic DFF up­
strate of DUTs. sets from data “0” to data “1”. For the full “1” data pattern, the transients
All the FPGAs are irradiated under a static mode, that is, after in the clock buffer are also masked. While the influence of clock cannot
configuration, all the clocks are stopped. The full “0”, full “1”, and be eliminated by the square wave test due to the different data stored in
square wave data patterns are used in irradiation test, and each data successive DFF stages. Based on the collected data, the upset numbers of
pattern is written into the DFF chain before irradiation. The PBIE can the tested DFF chains of 12C and 19F ions are presented in Fig. 6(a) and
lead the discrepancy of SEU cross sections. While for the static mode,
(b). And the detailed SEU cross sections corresponding to different ions
data are stored before irradiation and read out after irradiation, which and LET values are shown in Fig. 7.
can exclude the impact of the additional transient perturbations in pe­
ripheral circuits and reflect the actual extent of SEU sensitivities. To
avoid the occurrence of Power On Reset (POR) or Select-MAP functional 4.1. Unhardened chains
interrupt, each test is divided into multiple rounds. Once the total ion
fluence reached the preset value, the ion beam will be turned off. If a It is obvious that the actual errors of the square wave data pattern
functional interrupt occurs, the current data will be discarded, and the exceed the averaged SEUs of full “1” and full “0” data, implying that the
next test will be performed after the DUT is reset. If no SEFI occurs, the influence of PBIE is critical to the total errors. Moreover, with the in­
SEU data of the DUT will be sampled out before the bitstream is reloaded crease of LET, the proportion of PBIE increase or even dominate the total
after irradiation, then the SEU errors will be counted by the controller DFF errors.
In addition, the different SEU sensitivity of Standard_ ASYN chain is

4
C. Cai et al. Microelectronics Reliability xxx (xxxx) xxx

Fig. 5. (a) PBIE for square wave data pattern (two 25-stage DFF cells); (b) PBIE for full “1” data pattern (two 25-stage DFF cells); (c) PBIE for square wave data
pattern (four 25-stage DFF cells).

Fig. 6. (a) The comparisons of upset numbers among different chains under 12C ions irradiation; (b) the comparisons of upset numbers among different chains under
19
F ions irradiation.

Fig. 7. Heavy ion induced SEU cross sections of different chains (for this figure, the error events rather than the upset numbers are calculated in the SEU cross-section
results, indicating that one distinguished PBIE is counted as only one error event).

5
C. Cai et al.
observed. A 4799-bit error of the Standard_ ASYN chain appear once for
the full “1” data pattern under 19F ions irradiation, which is caused by an
abnormal signal of asynchronous reset port. For the Standard_ASYN
chain, 25 out of the 30 SEUs of the Standard_ASYN chain with the square
wave data pattern are captured, and these DFF cells are all driven by the
same RRET, indicating that the PBIE (“1” to “0”) is due to the sensitive
asynchronous structure.
4.2. Hardened chains
As shown in Fig. 6(a) and (b), it is observed that the LTMR_ROW
chains are robust to SEU, which reduce the SEU rates drastically in both
full “0” and full “1” data patterns. However, for the square wave data
pattern, the LTMR_ROW chains present almost the same SEU sensitivity
as the unhardened chain. It is due to the charge sharing effect that affects
the triplicated DFF cells placed in one SLICE, leading transients in a
LCLK impact the effectiveness of the triplicated redundancy and cause
an inevitable SEU eventually. However, the slightly improvement of the
SEU tolerance of LTMR_ROW chains in 19F ions irradiation is beneficial
from the reduction of the intrinsic cell upsets.
It is clear that the GTMR_ROW chains are also robust in mitigation of
the intrinsic cell SEUs for both full “0” and full “1” data patterns.
However, the GTMR_ROW chains show serious SEU sensitivity for the
square wave data pattern. The reason of increased SEU sensitivity of
GTMR_ROW chains is illustrated in Fig. 8. Take the stage2 as an
example, and the related nodes of the stage2 are marked. Ideally, even if
an SEU occurs in DFF1_tmr1 of stage1, three voters inside the stage2 will
deliver a correct value. If no clock skew (tclk_skew) exists among the
triplicated clocks during the data transition, the correct values will be
output on the nodes q2, q1 and q0 after a clock-to-Q time (tclk_q).
However, as a matter of fact, some additional clock skews are existed
due to the routing or peripheral hardware system. Assuming the rising
edge of TMR_clk2 precedes TMR_clk1 and TMR_clk0. After the first ris­
ing edge of TMR_clk2, the value of node DFF1_Q2 will be changed before
the first positive edges of TMR_clk1 and TMR_clk0 arriving. If an SEU
occurs in DFF1_tmr1 of stage1, the triplicated voters inside stage2 will
output an error data on the nodes n2, n1, and n0 after a total time of
Fig. 8. Four stages of the GTMR_ROW chains with the triplicated external clock TMR_clk2, TMR_clk1 and TMR_clk0.
6
Microelectronics Reliability xxx (xxxx) xxx
routing delay (trouting) and voting (tvoter) of the voters. If the error data
satisfy the setup time (tsetup), the data of stage2 will be erroneous
consequently. And the relationship is shown in formula (1).
tclk > tclk q + trouting + tvoter + tsetup (1)
skew
Based on the above analysis, if the clock skew is inevitable, the SEU
sensitive area will involve the approximately twofold of the unhardened
chain, which is consistent with the experimental results.
In addition, both the DTMR_ROW and DTMR_COL chains are robust
to SEU for the full “0” and full “1” data patterns. The DTMR_COL chains
are much more tolerant to SEUs than DTMR_ROW chains, because the
SEU sensitive LCLK in a SLICE is further minimized compared to the
DTMR_ROW chains. Nevertheless, 50 errors in square wave test of
DTMR_COL chains are observed in Round 1 test. By reexamining the
SEUs pattern in the log files, it is found that the 50 SEUs are entirely
caused by two PBIEs, where the 50-stage DFF are driven by the same
RCLK. As two of the triplicated DFF cells for each stage are restricted to
the same RCLK, once the RCLK is struck by ions, the triplicated redun­
dancy will cease to be effective, leading PBIE appeared.
For the DTMR_NEW chains, the triplicated BUFGs are all connected
to one external clock signal and drive a different RCLK. The comparisons
of SEU results for the DTMR_NEW chains and the other chains are also
shown in Fig. 6(a) and (b). Without considering the PBIEs from the
BUFG or RCLK, the DTMR_NEW chains exhibit an 80× improvement
over the unhardened chain and a 25× improvement over the
DTMR_ROW chains at the LET value of 7.4 MeV⋅cm2/mg. As shown in
Fig. 7, for the high-LET 81Ta ions irradiation, the SEU cross sections of
the unhardened chain and DTMR_NEW chains all increase more than
one order of magnitude. However, when the LET value equals to 84.9
MeV⋅cm2/mg, the DTMR_NEW chains still have an ~20× improvement
over the unhardened chain, indicating that a strong radiation tolerance
of DTMR_NEW chains is also verified by the high-LET irradiation. Based
on these results, it is found that the orientation method is not so critical
for the SEU sensitivities of DFF chains. While the triplicated clock buffer
is significant for the radiation tolerance of chains.
C. Cai et al.
5. Conclusion
In this paper, seven specially designed circuits are implemented on
the 28 nm SRAM-based FPGA to investigate the failure rates of nano­
scale FPGA systems and promote their further space applications. The
heavy ion experimental results under different data patterns reveal that
the PBIE is mainly from the clock buffer, which is critical to the per­
formance of TMR hardening strategy. Hence, the specially placed clock
buffers for the hardened chains are vital to achieve a desired SEU
tolerance. The irradiation results verified that the proposed DTMR_NEW
chains are suitable to be used in radiation environment due to the strong
SEU tolerance. The detailed comparison results are useful for re­
searchers to implement effective FPGA-based soft error tolerance
systems.
CRediT authorship contribution statement
Methodology, Jian Yu; software, Shuai Gao and Bingxu Ning; vali­
dation, Chang Cai; writing—original draft preparation, Jian Yu; wri­
ting—review and editing, Chang Cai and Mingjie Shen; supervision,
Tianqi Liu; project administration, Liewei Xu, Jian Yu; funding acqui­
sition, Jian Yu; conceptualization, Jian Yu.
Declaration of competing interest
The authors declare no conflict of interest.
Acknowledgements
This work is jointly supported by the fund of innovative center in
China Institute of Atomic Energy (Grant No. KFZC2020010501), the
fund of Municipal Commission of Economy and Information (GYQJ-
2020-1-01), State Key Laboratory of ASIC & System (Grant No.
2020KF009), and HIRFL (Grant No. JIZR20GY002).
References
[1] C. Norton, An evaluation of the Xilinx Virtex-4 FPGA for on- board processing in an
advanced imaging system, in: 2009 IEEE Aerospace Conference, 2009, pp. 1–9.
Mar.
[2] M. Cannon, et al., Strategies for removing common mode failures from TMR
designs deployed on SRAM FPGAs, IEEE Trans. Nucl. Sci. 66 (1) (2019) 207–215.
Jan.
[3] T. Lange, et al., On-board processing using reconfigurable hardware on the solar
orbiter PHI instrument, in: 2017 NASA/ESA Conference on Adaptive Hardware and
Systems (AHS), 2017, pp. 186–191. Jul.
Microelectronics Reliability xxx (xxxx) xxx
[4] C. Cai, X. Fan, J. Liu, D. Li, T. Liu, L. Ke, P. Zhao, Z. He, Heavy-ion induced single
event upsets in advanced 65 nm radiation hardened FPGAs, Electronics 8 (2019)
323.
[5] J. Tonfat, F.L. Kastensmidt, L. Artola, G. Hubert, N.H. Medina, N. Added, V.A.
P. Aguiar, F. Aguirre, E.L.A. Macchione, M.A.G. Silveira, Analyzing the influence of
the angles of incidence and rotation on MBU events induced by low LET heavy ions
in a 28-nm SRAM-based FPGA, IEEE Trans. Nucl. Sci. 64 (8) (2017) 2161–2168.
[6] J.S. Bi, K. Xi, B. Li, H. Wang, L.L. Ji, J. Li, M. Liu, Heavy ion induced upset errors in
90-nm 64 Mb NOR-type floating-gate flash memory, Chin. Phys. B 27 (9) (2018),
098501.
[7] M. Cannon, et al., Improving the effectiveness of TMR designs on FPGAs with SEU-
aware incremental placement, in: 2018 IEEE 26th Annual International Symposium
on Field-programmable Custom Computing Machines (FCCM), 2018, pp. 141–148.
Apr.
[8] M. Berg, et al., Effectiveness of internal versus external SEU scrubbing mitigation
strategies in a xilinx FPGA: design, test, and analysis, IEEE Trans. Nucl. Sci. 55 (4)
(2008) 2259–2266. Aug.
[9] C. Cai, T. Liu, P. Zhao, X. Fan, H. Huang, D. Li, L. Ke, Z. He, L. Xu, G. Chen, Jie Liu,
Multiple layout-hardening comparation of SEU mitigated Flip-flops in 22 nm UTBB
FD-SOI technology, IEEE Trans. Nucl. Sci. 67 (1) (2020) 374–381. Jan.
[10] K.M. Sielewicz, G.A. Rinella, M. Bonora, P. Giubilato, M. Lupi, M.J. Rossewij,
J. Schambach, T. Vanat, Experimental methods and results for the evaluation of
triple modular redundancy SEU mitigation techniques with the Xilinx Kintex-7
FPGA, in: 2017 IEEE Radiation Effects Data Workshop (REDW), 2017,
pp. 148–155.
[11] 7 Series FPGAs Clocking Resources User Guide, Xilinx, User Guide UG472, Sep, htt
ps://www.xilinx.com, 2016.
[12] 7 Series FPGAs Configurable Logic Block User Guide, Xilinx, User Guide UG474,
Sep, https://www.xilinx.com, 2016.
[13] G.R. Allen, L. Edmonds, C.W. Tseng, G. Swift, C. Carmichael, Single-event upset
(SEU) results of embedded error detect and correct enabled block random access
memory (Block RAM) within the xilinx XQR5VFX130, IEEE Trans. Nucl. Sci. 57 (6)
(2010) 3426–3431.
[14] G.M. Swift, G.R. Allen, C.W. Tseng, C. Carmichael, G. Miller, J.S. George, Static
upset characteristics of the 90nm Virtex-4QV FPGAs, in: 2008 IEEE Radiation
Effects Data Workshop, 2008, pp. 98–105.
[15] A. Evans, D. Alexandrescu, V. Ferlet-Cavrois, M. Nicolaidis, New techniques for
SET sensitivity and propagation measurement in flash-based FPGAs, IEEE Trans.
Nucl. Sci. 61 (6) (2014) 3171–3177.
[16] A. Manuzzato, S. Gerardin, A. Paccagnella, L. Sterpone, M. Violante, On the static
cross section of SRAM-Based FPGAs, in: 2008 IEEE Radiation Effects Data
Workshop, 2008, pp. 94–97.
[17] A. Ullah, P. Reviriego, A. Sánchez-Macián, J.A. Maestro, Multiple cell upset
injection in BRAMs for xilinx FPGAs, IEEE Trans. Device Mater. Reliab. 18 (4)
(2018) 636–638.
[18] L.N. Cojocariu, V.M. Placinta, L. Dumitru, Monitoring system for testing the
radiation hardness of a KINTEX-7 FPGA, in: Presented at the AIP Conference
Proceedings, 2016, https://doi.org/10.1063/1.4944199.
[19] T. Li, H. Liu, H. Yang, Design and characterization of SEU hardened circuits for
SRAM-based FPGA, IEEE Trans. Very Large Scale Integr. Syst. 27 (6) (2019)
1276–1283.
[20] L. Sterpone, L. Boragno, A probe-based SEU detection method for SRAM-based
FPGAs, Microelectron. Reliab. 76–77 (2017) 154–158.
[21] G. Furano, A. Tavoularis, L. Santos, V. Ferlet-Cavrois, C. Boatella, R.G. Alia, P.
F. Martinez, M. Kastriotou, V. Wyrwoll, S. Danzeca, M. Tali, D. Gacnik,
I. Kramberger, L. Juul, K. Maragos, G. Lentaris, FPGA SEE test with ultra-high
energy heavy ions, in: 2018 IEEE International Symposium on Defect and Fault
Tolerance in VLSI and Nanotechnology Systems (DFT), 2018, p. 18393191.