Acer Aspire 4733z Quanta - ZQ5 - RevB

5 4 3 2 1
BOM MARK
IV@: INT VGA
=46<67(0%/2&.',$*5$0 DDR3 PWR
TPS51116 P40
CHARGER
ISL88731A P36
EV@: STUFF FOR EXT VGA THERMAL 3/5V SYS PWR

SP@: STUFF FOR UMA or VGA X'TAL PROTECTION P44 RT8206 P37
14.318MHz
Penryn 478 Thermal Sensor Fan Driver
5(9%
DISCHARGER CPU CORE PWR
D
CLOCK GENERATOR uFCPGA (G780P81U) (G991) P42 ISL6266A P39
D
P3, P4 P3 P25
ICS:
SELGO: SLG8SP513VTR VGA CORE
+1.05V
P2 MAX8792 P41 UP6111A P38
FSB
667/800/1067 Mhz
EXT_LVDS
ATI-Park CRT
EXT_CRT P24
PCIE 16X
VRAM DDRIII EXT_HDMI SWITCH
DDRIII NB 512MB P18-P23 LVDS
P24
SO-DIMM 0 Dual Channel DDR3 CIRCUIT
Cantiga LVDS INT_LVDS
SO-DIMM 1 667/800 MHz
P16,P17 (GM45/ PM45/ GL40) HDMI
RGB INT_CRT P25 P25
C C
P5, P6, P7, P8, P9, P10, P11
HDMI switch
INT_HDMI
(PS8101T)
X4 DMI interface P25
HDD (SATA) *1
P26
Ext USB Port x 2
USB 0,2 P27 SATA0
PCI-Express PCIE-4 Mini Card
Int USB Port x 1 ODD (SATA) SATA1 WLAN
USB 6 P27
P26
SB P27
USB 2.0 ICH9M

Bluetooth USB1
USB3 P27
B
X'TAL PCIE-6 B
32.768KHz X'TAL
CCD Azalia P12,P13,P14,P15
25MHz
USB11 P24
Media
LPC Cardreader Giga-LAN
(AU6437)
BCM57780
USB2 P30 P30
Audio CODEC EC (WPC781)
(272) P28
P33
X'TAL
32.768KHz
Card Reader Transformer P31
Connector
P32
SPI ROM
P33
RJ45
A
Audio Amplifier MIC Jack Int. MIC P31 A
P29 P29
G1453L P28 Touch Pad K/B COON.
P26 P33
Int. 352-(&7=4
Speaker 4XDQWD&RPSXWHU,QF
P29 Size Document Number Rev
1A
Block Diagram
Date: Monday, July 12, 2010 Sheet 1 of 43
5 4 3 2 1
5 4 3 2 1
&ORFN*HQHUDWRU&/. +3V
PBY160808T-301Y-N/2A/300ohm_6
+3V
L42
C544
*0.1u/10V_4
C434 C573 C574
Modfiy it 5/4
C545 C568 C551 C546 C435

+1.05V_VDD
L43 +1.05V
PBY160808T-301Y-N/2A/300ohm_6
C437
5/7 Modfiy
PM_STPPCI#
PM_STPCPU#
R313
R316
*2.2K_4
*2.2K_4
02
*0.1u/10V_4
C542 *10u/10V_8 10u/10V_8 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 *0.1u/10V_4 CLK_PCIE_SRC11# R322 10K_4
*10u/10V_8
D C569 U15 D
0.1u/10V_4 9 55 SATA_CLKREQ#_R R324 10K_4
C557 16 VDD_PCI IO_VOUT
0.1u/10V_4 23 VDD_48 7 SMBCK1
C550 VDD_CK_VDD_REF 4 VDD_PLL3 SCLK 6 SMBDT1 LAN_CLKREQ#_R R320 10K_4
0.1u/10V_4 VDD_REF SDA
C450 46
CK505 45 PM_STPPCI#
VDD_SRC SRC5/PCI_STOP# PM_STPPCI# 14
0.1u/10V_4 62 44 PM_STPCPU# PM_STPCPU# 14 To SB CLK_PCIE_SRC3 R349 10K_4
VDD_CPU SRC5#/CPU_STOP#
+1.05V_VDD
C541 19 61
27 VDD_96_IO CPU0 60
CLK_CPU_BCLK 3
To CPU CLK_MCH_OE#_C R317 10K_4
5/5 Add
VDD_PLL3_IO CPU0# CLK_CPU_BCLK# 3
10u/10V_8 33
52 VDD_SRC_IO_1 58
VDD_SRC_IO_3 CPU1 CLK_MCH_BCLK 5
43 57 To NB
VDD_SRC_IO_2 CPU1# CLK_MCH_BCLK# 5
56 For EMI
VDD_CPU_IO 54 T91
SRC8/ITP 53 T92
SRC8#/ITP# PCLK_591_R C571 *33p/50V_4
14 SATACLKREQ# R321 475/F_4 SATA_CLKREQ#_R 8 42
PCI0/CR#_A SRC10# CLK_PCIE_3GPLL# 6
41 To NB
SRC10 CLK_PCIE_3GPLL 6
31 LAN_CLKREQ# R325 475/F_4 LAN_CLKREQ#_R 10 CLKUSB_48 C581 *15p/50V_4
PCI1/CR#_B 40 CLK_MCH_OE#_C R319 475/F_4
SRC11/CR#_H CLK_MCH_OE# 6
R330 33_4 PCLK_DEBUG_R 11 39 CLK_PCIE_SRC11# R323 475/F_4 MINI_CLKREQ# 28
28 PCLK_DEBUG PCI2/TME SRC11#/CR#_G 14M_ICH C554 *33p/50V_4
T95 PCI_CLK_SIO 12 37
PCI3 SRC9 CLK_PCIE_MINI1 28
C 38 To Mini Card 1 (WLAN) C
SRC9# CLK_PCIE_MINI1# 28
R334 33_4 PCLK_591_R 13 PCLK_ICH_R C578 *33p/50V_4
35 PCLK_591 PCI4/SRC5_EN 51 CLK_PCIE_SRC7
SRC7/CR#_F T94
PCLK_ICH R346 33_4 PCLK_ICH_R 14 50 CLK_PCIE_SRC7#
13 PCLK_ICH PCIF5/ITP_EN SRC7#/CR#_E T93
SEL2 SEL1 SEL0 Frequence select
CG_XIN 3 48
XTAL_IN SRC6 CLK_PCIE_ICH 13
47 To ICH FSC FSB FSA CPU SRC PCI
SRC6# CLK_PCIE_ICH# 13
CG_XOUT 2
R345 22_4 XTAL_OUT 34
33 CLK_Card48 R337 22_4 FSA 17 SRC4 35
CLK_PCIE_LAN 31 1 0 1 100 100 33
14 CLKUSB_48 USB_48/FSA SRC4# CLK_PCIE_LAN# 31 To LAN
CPU_BSEL0 R338 2.2K_4 0 0 1 133 100 33 Default
CPU_BSEL1 64 31 CLK_PCIE_SRC3 R348 *EV@475/F_4 PEG_CLKREQ# 19 Modfiy it 5/4
CPU_BSEL2 R314 10K_4 FSB/TEST/MODE SRC3/CR#_C 32 CLK_PCIE_SRC3#
R318 33_4 FSC 5 SRC3#/CR#_D T97 0 1 1 166 100 33
14 14M_ICH REF0/FSC/TESTSEL
65 28 0 1 0 200 100 33
VSS_BODY SRC2/SATA CLK_PCIE_SATA 12
15 29 To ICH
VSS_PCI SRC2#/SATA# CLK_PCIE_SATA# 12
C549 18 0 0 0 266 100 33
33p/50V_4 CG_XIN 22 VSS_48 24 CLK_DREFSSCLK_R
26 VSS_IO SRC1/SE1 25 CLK_DREFSSCLK#_R
VSS_PLL3 SRC1#/SE2 To NB or VGA 1 0 0 333 100 33
2
Y2 59
CL=20p 30 VSS_CPU 20 CLK_DREFCLK_R
14.318MHZ 36 VSS_SRC1 SRC0/DOT96 21 CLK_DREFCLK#_R
1 1 0 400 100 33
VSS_SRC2 SRC0#/DOT96# To NB or VGA
C548 49 1 1 1 Reserved
1
33p/50V_4 CG_XOUT 1 VSS_SRC3 63

VSS_REF CKPWRGD/PWRDWN# CK_PWRGD 14
B SLG8SP513 B
SLG8SP513VTR ,ICS9LPRS365BKLFT +3V R329 10K_4 PCLK_DEBUG_R
5/5 modify R331 *10K_4

RN15
ICS9LRS3165BKLFT RTM875T-606
+3V R336 EV@10K_4 PCLK_591_R CLK_DREFCLK_R 3 4
(ALPRS365000) (AL000875000) CLK_DREFCLK 6
PULL HIGH PULL DOWN HIGH 27MHz CLK_DREFCLK#_R 1 2 IV@0_4P2R
LOW SRC CLK_DREFCLK# 6
R332 IV@10K_4 From GMCH RN14
PCI2/TME CLK_DREFSSCLK_R 3 4
internal PD CLK_DREFSSCLK 6
Pin 11 PCI2/TME NO OVERCLOCKING (default) NORMAL RUN
+3V R342 *10K_4 PCLK_ICH_R CLK_DREFSSCLK#_R 1 2 IV@0_4P2R
CLK_DREFSSCLK# 6
PCI-3/SRC5_EN PIN37/38 IS R343 10K_4 RN10
Pin 12 PCI-3 internal PD PIN37/38 IS SRC5 PCI_STOP/CPU_STOP (default) CLK_DREFCLK_R 1 2
CLK_PCIE_VGA 18
To NB CLK_DREFCLK#_R 3 4 EV@0_4P2R
PCI-4/27M_SEL PIN 17/18 CLK_PCIE_VGA# 18
Pin 13 PCI-4/27M_SEL internal PD PIN 17/18 IS 27MHz IS SRC/DOT (default) R347 0_4
From Deisceret RN9
3 CPU_BSEL0 MCH_BSEL0 6
CLK_DREFSSCLK_R 1 2
27M_NONSS 19
PCIF-5/ITP_EN R267 0_4 MCH_BSEL1 6 CLK_DREFSSCLK#_R 3 4
Pin 14 PCIF-5/ITP_EN internal PD PIN 46/47 IS CPUITP PIN 46/47 IS SRC8 (default) 3 CPU_BSEL1 *EV@33_4P2R
R315 0_4
3 CPU_BSEL2 MCH_BSEL2 6
5/18 Modify 5/22 modify
&ORFN*HQ,&
+3V +3V
<MAIN>:ICS9LRS3165BKLFT QCI:ALPRS365000
A
R258
<SECOND>:SLG8SP513VTR QCI:AL8SP513000 R259
A
4.7K_4 <SECOND>:RTM875N-606-VD-GRT QCI:AL000875000 4.7K_4

2
Q13 Q12
14,16,28 PDAT_SMB
3 1 SMBDT1
14,16,28 PCLK_SMB
3 1 SMBCK1 352-(&7=4
2N7002E 2N7002E
4XDQWD&RPSXWHU,QF
Size Document Number Rev
REV:B 6/12 REV:B 6/11 1A
CLOCK GENERATOR
5 4 3 2 1
5 4 3 2 1
5 H_A#[3..16]
H_A#3 J4
U17A
A[3]# ADS#
H1
H_ADS# 5
03
ADDR GROUP_0
H_A#4 L5 E2 H_D#[0..15] U17B H_D#[32..47]
A[4]# BNR# H_BNR# 5 5 H_D#[0..15] H_D#[32..47] 5
H_A#5 L4 G5 H_D#0 E22 Y22 H_D#32
A[5]# BPRI# H_BPRI# 5 D[0]# D[32]#
H_A#6 K5 H_D#1 F24 AB24 H_D#33
H_A#7 M3 A[6]# H5 H_D#2 E26 D[1]# D[33]# V24 H_D#34
A[7]# DEFER# H_DEFER# 5 D[2]# D[34]#
DATA GRP 0
H_A#8 N2 F21 H_D#3 G22 V26 H_D#35
H_DRDY# 5
DATA GRP 2
H_A#9 J1 A[8]# DRDY# E1 H_D#4 F23 D[3]# D[35]# V23 H_D#36
A[9]# DBSY# H_DBSY# 5 D[4]# D[36]#
H_A#10 N3 H_D#5 G25 T22 H_D#37
H_A#11 P5 A[10]# F1 H_D#6 E25 D[5]# D[37]# U25 H_D#38
A[11]# BR0# H_BREQ# 5 D[6]# D[38]#
H_A#12 P2 H_D#7 E23 U23 H_D#39
D A[12]# D[7]# D[39]# D
CONTROL
H_A#13 L2 D20 H_IERR# R245 56_4 +1.05V H_D#8 K24 Y25 H_D#40
H_A#14 P4 A[13]# IERR# B3 H_D#9 G24 D[8]# D[40]# W22 H_D#41
A[14]# INIT# H_INIT# 12 D[9]# D[41]#
H_A#15 P1 H_D#10 J24 Y23 H_D#42
H_A#16 R1 A[15]# H4 H_D#11 J23 D[10]# D[42]# W24 H_D#43
A[16]# LOCK# H_LOCK# 5 D[11]# D[43]#
M1 H_D#12 H22 W25 H_D#44
5 H_ADSTB#0 ADSTB[0]# D[12]# D[44]#
C1 H_D#13 F26 AA23 H_D#45
5 H_REQ#[0..4] RESET# H_CPURST# 5 D[13]# D[45]#
H_REQ#0 K3 F3 H_D#14 K22 AA24 H_D#46
REQ[0]# RS[0]# H_RS#0 5 D[14]# D[46]#
H_REQ#1 H2 F4 H_D#15 H23 AB25 H_D#47
REQ[1]# RS[1]# H_RS#1 5 D[15]# D[47]#
H_REQ#2 K2 G3 J26 Y26
REQ[2]# RS[2]# H_RS#2 5 5 H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 5
H_REQ#3 J3 G2 H26 AA26
REQ[3]# TRDY# H_TRDY# 5 5 H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 5
H_REQ#4 L1 H25 U22
REQ[4]# 5 H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 5
G6
5 H_A#[17..35] HIT# H_HIT# 5 H_D#[16..31] H_D#[48..63]
H_A#17 Y2 E4 H_D#[48..63] 5
A[17]# HITM# H_HITM# 5 5 H_D#[16..31]
H_A#18 U5 H_D#16 N22 AE24 H_D#48
H_A#19 R3 A[18]# AD4 XDP_BPM#0 H_D#17 K25 D[16]# D[48]# AD24 H_D#49
A[19]# BPM[0]# T56 D[17]# D[49]#
ADDR GROUP_1
H_A#20 W6 AD3 XDP_BPM#1 T86 H_D#18 P26 AA21 H_D#50
H_A#21 U4 A[20]# BPM[1]# AD1 XDP_BPM#2 H_D#19 R23 D[18]# D[50]# AB22 H_D#51
H_A#22 Y5 A[21]# BPM[2]# AC4 XDP_BPM#3
T88
H_D#20 L23 D[19]# D[51]# AB21 H_D#52
Layout note:
A[22]# BPM[3]# T55 D[20]# D[52]# comp0,2: Zo=27.4ohm, L<0.5"
XDP/ITP SIGNALS
DATA GRP 1
H_A#23 U1 AC2 XDP_BPM#4 T89 H_D#21 M24 AC26 H_D#53
DATA GRP 3
H_A#24 R4 A[23]# PRDY# AC1 XDP_BPM#5 H_D#22 L22 D[21]# D[53]# AD20 H_D#54
H_A#25 T5 A[24]# PREQ# AC5 XDP_TCK H_D#23 M23 D[22]# D[54]# AE22 H_D#55
comp1,3: Zo=55ohm, L<0.5"
H_A#26 T3 A[25]# TCK AA6 XDP_TDI
Connect it to CPU DBR# is for ITP debug port H_D#24 P25 D[23]# D[55]# AF23 H_D#56
H_A#27 W2 A[26]# TDI AB3 XDP_TDO or CPU interposer (like ICE) to reset the system H_D#25 P23 D[24]# D[56]# AC25 H_D#57
H_A#28 W5 A[27]# TDO AB5 XDP_TMS H_D#26 P22 D[25]# D[57]# AE21 H_D#58
H_A#29 Y4 A[28]# TMS AB6 XDP_TRST# H_D#27 T24 D[26]# D[58]# AD21 H_D#59
Layout note:
H_A#30 U2 A[29]# TRST# C20 SYS_RST# +1.05V H_D#28 R24 D[27]# D[59]# AC22 H_D#60 DPRSTP# , Daisy Chain
A[30]# DBR# SYS_RST# 14 D[28]# D[60]#
H_A#31 V4 H_D#29 L25 AD23 H_D#61
H_A#32 W3 A[31]# H_D#30 T25 D[29]# D[61]# AF22 H_D#62
(SB>Power>NB>CPU)
H_A#33 AA4 A[32]# H_D#31 N25 D[30]# D[62]# AC23 H_D#63
A[33]# THERMAL D[31]# D[63]#
C H_A#34 AB2 L26 AE25 C
A[34]# 5 H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 5
H_A#35 AA3 D21 H_PROCHOT#_D R311 M26 AF24
A[35]# PROCHOT# 5 H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 5
V1 A24 H_THERMDA 1K/F_4 N24 AC20
5 H_ADSTB#1 ADSTB[1]# THERMDA 5 H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 5
B25 H_THERMDC
A6 THERMDC H_GTLREF AD26 R26 COMP0 R344 27.4/F_6
12 H_A20M# A20M# GTLREF COMP[0]
ICH
A5 C7 PM_THRMTRIP# T108 CPU_TEST1 C23 MISC U26 COMP1 R328 54.9/F_4

12 H_FERR# FERR# THERMTRIP# TEST1 COMP[1]
C4 T112 CPU_TEST2 D25 AA1 COMP2 R257 27.4/F_6
12 H_IGNNE# IGNNE# TEST2 COMP[2]
T125 CPU_TEST3 C24 Y1 COMP3 R254 54.9/F_4
D5 CPU_TEST4 AF26 TEST3 COMP[3]
12 H_STPCLK# STPCLK# T90 TEST4
C6 H CLK R312 T87 CPU_TEST5 AF1 E5
12 H_INTR LINT0 TEST5 DPRSTP# ICH_DPRSTP# 6,12,39
B4 A22 2K/F_4 T126 CPU_TEST6 A26 B5
12 H_NMI LINT1 BCLK[0] CLK_CPU_BCLK 2 TEST6 DPSLP# H_DPSLP# 12
A3 A21 T127 CPU_TEST7 C3 D24
12 H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# 2 TEST7 DPWR# H_DPWR# 5
B22 D6
2 CPU_BSEL0 BSEL[0] PWRGOOD H_PWRGD 12
M4 B23 D7
RSVD[01] 2 CPU_BSEL1 BSEL[1] SLP# H_CPUSLP# 5
N5 C21 AE6
RSVD[02] 2 CPU_BSEL2 BSEL[2] PSI# PSI# 39
T2
V3 RSVD[03] Penryn
RSVD[04]
RESERVED
B2 Layout note:
D2 RSVD[05]
D22 RSVD[06] H_GTLREF: Zo=55 ohm
D3 RSVD[07]
F6 RSVD[08] L<0.5", 2/3*VCCP+-2%
RSVD[09]
Penryn
B B
Thermal Trip +1.05V CPU Thermal monitor +3V XDP PU/PD

3
+3V
R400 SYS_RST# R391 *1K_4

2 Q18
6,14,39 DELAY_VR_PWRGOOD
200_6
DMN601K-7 +1.05V
+1.05V VCC_TH ZR6 hang up issue
1
C624
XDP_TDO R261 *54.9/F_4
R398 0.1U/10V_4
XDP_TDI R260 54.9/F_4
2
56_4
Q17 U21 XDP_TMS R264 54.9/F_4
PM_THRMTRIP# 1 3 MMBT3904 H_THERMDA
6,12 PM_THRMTRIP# SYS_SHDN# 37,44
35 2ND_MBCLK 8 1 XDP_BPM#5 R310 54.9/F_4
SCLK VCC
7 2 C621 XDP_TCK R265 54.9/F_4
35 2ND_MBDATA SDA DXP
6 3 2200p_4 XDP_TRST# R266 54.9/F_4
ALERT# DXN
No use Thermal trip CPU side still PU 56ohm.
Processor hot Use Thermal trip can share PU at SB side R401 *10K_4
4
OVERT# GND
5 H_THERMDC
+3V
+1.05V No use PROCHOT CPU side still PU 56ohm. 14 THERM_ALERT# R395 *0_4 G780P81U(MSOP-8) XDP_DBRESET# and XDP_TDO
A $''5(66+ A
Use PROCHOT to optional receiver CPU side PU reserve for XDP
68ohm and through isolat 2.2K ohm to receiver +3V R394 10K_4
R273 27 THER_OVERT#
side
56_4 GMT AL000780000 Use 2200p
4/20 Modify 352-(&7=4
4XDQWD&RPSXWHU,QF
H_PROCHOT#_D R274 *0_4 NS AL095245000 Use 2200p
H_PROCHOT# 39
&38 WINDBOND AL83L771K01 Use 2200p Size
Date:
Document Number
CPU Host Bus
Monday, July 12, 2010 Sheet 3 of
Rev
1A
43
5 4 3 2 1
5 4 3 2 1
A4
A8
A11
A14
U17D
VSS[001]
VSS[002]
VSS[003]
VSS[082]
VSS[083]
VSS[084]
P6
P21
P24
R2
VCC_CORE
A7
A9
U17C
VCC[001] VCC[068]
AB20
AB7
VCC_CORE
VCC:38A (Low power type)
VCC:47A (Standard type)
04
A16 VSS[004] VSS[085] R5 A10 VCC[002] VCC[069] AC7
A19 VSS[005] VSS[086] R22 C470 C445 C447 C444 C471 C564 C563 C424 A12 VCC[003] VCC[070] AC9
A23 VSS[006] VSS[087] R25 A13 VCC[004] VCC[071] AC12
D AF2 VSS[007] VSS[088] T1 A15 VCC[005] VCC[072] AC13
Layout Note: D
*10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 *10U/6.3V_8 10U/6.3V_8 *10U/6.3V_8 *10U/6.3V_8 *10U/6.3V_8
B6 VSS[008] VSS[089] T4 A17 VCC[006] VCC[073] AC15 Inside CPU center cavity in 2 rows
B8 VSS[009] VSS[090] T23 A18 VCC[007] VCC[074] AC17
B11 VSS[010] VSS[091] T26 A20 VCC[008] VCC[075] AC18
B13 VSS[011] VSS[092] U3 B7 VCC[009] VCC[076] AD7
VCCP : 2.5A(Supply after VCC Stable)
B21 VSS[014] VSS[095] U24 B12 VCC[012] VCC[079] AD12 4.5A(Supply before VCC Stable)
B24 VSS[015] VSS[096] V2 B14 VCC[013] VCC[080] AD14
C5 VSS[016] VSS[097] V5 C562 C590 C589 C588 C468 C466 C429 C465 B15 VCC[014] VCC[081] AD15
C8 VSS[017] VSS[098] V22 B17 VCC[015] VCC[082] AD17 +1.05V
C11 VSS[018] VSS[099] V25 10U/6.3V_8 *10U/6.3V_8 10U/6.3V_8 *10U/6.3V_8 *10U/6.3V_8 10U/6.3V_8 *10U/6.3V_8 *10U/6.3V_8 B18 VCC[016] VCC[083] AD18
C14 VSS[019] VSS[100] W1 B20 VCC[017] VCC[084] AE9
C16 VSS[020] VSS[101] W4 C9 VCC[018] VCC[085] AE10
C19 VSS[021] VSS[102] W23 C10 VCC[019] VCC[086] AE12 C428 C431 C438
C2 VSS[022] VSS[103] W26 C12 VCC[020] VCC[087] AE13 + C622
C22 VSS[023] VSS[104] Y3 C13 VCC[021] VCC[088] AE15 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4
C25 VSS[024] VSS[105] Y6 C15 VCC[022] VCC[089] AE17 330U/2V_7343
D1 VSS[025] VSS[106] Y21 C17 VCC[023] VCC[090] AE18
D4 VSS[026] VSS[107] Y24 C18 VCC[024] VCC[091] AE20
D8 VSS[027] VSS[108] AA2 D9 VCC[025] VCC[092] AF9
D11 VSS[028] VSS[109] AA5 C442 C441 C472 C433 C419 D10 VCC[026] VCC[093] AF10
D16 VSS[030] VSS[111] AA11 *10U/6.3V_8 *10U/6.3V_8 *10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 D14 VCC[028] VCC[095] AF14
C VSS[031] VSS[112] VCC[029] VCC[096] C
D19 AA14 D15 AF15
D23 VSS[032] VSS[113] AA16 D17 VCC[030] VCC[097] AF17 C426 C432 C440
E3 VSS[034] VSS[115] AA22 E7 VCC[032] VCC[099] AF20 *0.1U/10V_4 0.1U/10V_4 0.1U/10V_4
E6 VSS[035] VSS[116] AA25 E9 VCC[033] VCC[100]
E8 VSS[036] VSS[117] AB1
Layout Note: E10 VCC[034] G21
E11 VSS[037] VSS[118] AB4 Place these parts E12 VCC[035] VCCP[01] V6
E14 VSS[038] VSS[119] AB8 E13 VCC[036] VCCP[02] J6
VSS[039] VSS[120] reference to Intel demo VCC[037] VCCP[03]
E16 AB11 C446 C443 C420 E15 K6
E19 VSS[040] VSS[121] AB13 board. E17 VCC[038] VCCP[04] M6
E21 VSS[041] VSS[122] AB16 *10U/6.3V_8 *10U/6.3V_8 10U/6.3V_8 E18 VCC[039] VCCP[05] J21
E24 VSS[042] VSS[123] AB19 E20 VCC[040] VCCP[06] K21
F5 VSS[043] VSS[124] AB23 F7 VCC[041] VCCP[07] M21
F8 VSS[044] VSS[125] AB26 F9 VCC[042] VCCP[08] N21
F11 VSS[045] VSS[126] AC3 F10 VCC[043] VCCP[09] N6
F13 VSS[046] VSS[127] AC6 F12 VCC[044] VCCP[10] R21
F16 VSS[047] VSS[128] AC8 F14 VCC[045] VCCP[11] R6
F19 VSS[048] VSS[129] AC11 F15 VCC[046] VCCP[12] T21
F2 VSS[049] VSS[130] AC14 F17 VCC[047] VCCP[13] T6
F22 VSS[050] VSS[131] AC16 C425 C421 C422 C423 C567 C566 F18 VCC[048] VCCP[14] V21
F25 VSS[051] VSS[132] AC19 F20 VCC[049] VCCP[15] W21 +1.5V
G4 VSS[052] VSS[133] AC21 *10U/6.3V_8 *10U/6.3V_8 10U/6.3V_8 *10U/6.3V_8 10U/6.3V_8 *10U/6.3V_8 AA7 VCC[050] VCCP[16] VCCA:130mA
G1 VSS[053] VSS[134] AC24 AA9 VCC[051] B26
G23 VSS[054] VSS[135] AD2 AA10 VCC[052] VCCA[01] C26
B B
G26 VSS[055] VSS[136] AD5 AA12 VCC[053] VCCA[02]
H3 VSS[056] VSS[137] AD8 AA13 VCC[054] AD6 C599 C598
VSS[057] VSS[138] VCC[055] VID[0] H_VID0 39
H6 AD11 AA15 AF5
H21 AD13 AA17 AE5 0.01U/25V_4 10U/6.3V_8
H24 AD16 AA18 AF4
J2 AD19 AA20 AE3
J5 AD22 C565 C591 C587 C586 C469 C467 AB9 AF3
J22 AD25 AC10 AE2
J25 AE1 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 *10U/6.3V_8 10U/6.3V_8 *10U/6.3V_8 AB10 R308 100/F_6 VCC_CORE
K1 VSS[064] VSS[145] AE4 AB12 VCC[062]
K4 VSS[065] VSS[146] AE8 AB14 VCC[063] AF7
VSS[066] VSS[147] VCC[064] VCCSENSE VCCSENSE 39
K23 AE11 AB15
K26 VSS[067] VSS[148] AE14 AB17 VCC[065]
L3 VSS[068] VSS[149] AE16 AB18 VCC[066] AE7
VSS[069] VSS[150] VCC[067] VSSSENSE VSSSENSE 39
L6 AE19
L21 VSS[070] VSS[151] AE23 Penryn R309
L24 VSS[071] VSS[152] AE26
M2 VSS[072] VSS[153] A2 + C491 + C580 + C430 + C623 100/F_6
M5 VSS[073] VSS[154] AF6
M22 VSS[074] VSS[155] AF8 *330U/2V_7343 330U/2V_7343 330U/2V_7343 *330U/2V_7343
M25 VSS[075] VSS[156] AF11
N1 VSS[076] VSS[157] AF13
Layout Note:
N4 VSS[077] VSS[158] AF16 Z0=27.4,PU/PD L<1"
A N23 VSS[078] VSS[159] AF19 A
N26 VSS[079] VSS[160] AF21
P3 VSS[080] VSS[161] A25
VSS[081] VSS[162]
352-(&7=4
AF25
VSS[163]
4XDQWD&RPSXWHU,QF
Penryn Montevina platform : Early Reference Board Schematics Feb 2007. Rev 1.0
stuff 22U*34, NC 22U*2
&38 stuff 330U*2, NC330U*2 Size
Date:
Document Number
CPU Power
Rev
1A
43
5 4 3 2 1
5 4 3 2 1
*0&+&$17,*$
QCI P/N
3 H_D#[0..63]
H_D#0
H_D#1
H_D#2
H_D#3
F2
G8
F8
E6
U20A
H_D#_0
H_D#_1
H_D#_2
H_A#_3
H_A#_4
H_A#_5
H_A#_6
A14
C15
F16
H13
C18
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#[3..35] 3
05
H_D#4 G2 H_D#_3 H_A#_7 M16 H_A#8
H_D#5 H6 H_D#_4 H_A#_8 J13 H_A#9
Intel Cantiga (G)M AJSLB940T04 H_D#_5 H_A#_9
D H_D#6 H2 P16 H_A#10 D
H_D#7 F6 H_D#_6 H_A#_10 R16 H_A#11
H_D#8 D4 H_D#_7 H_A#_11 N17 H_A#12
Intel Cantiga (P)M AJSLB970T06 H_D#_8 H_A#_12
H_D#9 H3 M13 H_A#13
H_D#10 M9 H_D#_9 H_A#_13 E17 H_A#14
H_D#11 M11 H_D#_10 H_A#_14 P17 H_A#15
Intel Cantiga (G)L A1 AJSLGGM0T04 H_D#_11 H_A#_15
H_D#12 J1 F17 H_A#16
H_D#13 J2 H_D#_12 H_A#_16 G20 H_A#17
H_D#14 N12 H_D#_13 H_A#_17 B19 H_A#18
H_D#15 J6 H_D#_14 H_A#_18 J16 H_A#19
H_D#16 P2 H_D#_15 H_A#_19 E20 H_A#20
H_D#17 L2 H_D#_16 H_A#_20 H16 H_A#21
H_D#18 R2 H_D#_17 H_A#_21 J20 H_A#22
H_D#19 N9 H_D#_18 H_A#_22 L17 H_A#23
H_D#20 L6 H_D#_19 H_A#_23 A17 H_A#24
H_D#21 M5 H_D#_20 H_A#_24 B17 H_A#25
H_D#22 J3 H_D#_21 H_A#_25 L16 H_A#26
H_D#23 N2 H_D#_22 H_A#_26 C21 H_A#27
H_D#24 R1 H_D#_23 H_A#_27 J17 H_A#28
H_D#25 N5 H_D#_24 H_A#_28 H20 H_A#29
H_D#26 N6 H_D#_25 H_A#_29 B18 H_A#30
H_D#27 P13 H_D#_26 H_A#_30 K17 H_A#31
H_D#28 N8 H_D#_27 H_A#_31 B20 H_A#32
H_D#29 L7 H_D#_28 H_A#_32 F21 H_A#33
C H_D#30 N10 H_D#_29 H_A#_33 K21 H_A#34 C
+1.05V H_D#31 M3 H_D#_30 H_A#_34 L20 H_A#35
H_D#32 Y3 H_D#_31 H_A#_35
H_D#33 AD14 H_D#_32 H12
0.3125*VCCP H_D#34 Y6 H_D#_33 H_ADS# B16
H_ADS# 3
WIDE(10):SPACING(20) , H_D#_34 H_ADSTB#_0 H_ADSTB#0 3
H_D#35 Y10 G17
H_D#_35 H_ADSTB#_1 H_ADSTB#1 3
R411 L<0.5" H_D#36 Y12 A9
H_D#_36 H_BNR# H_BNR# 3
H_D#37 Y14 F11
H_D#_37 H_BPRI# H_BPRI# 3
221/F_4 H_D#38 Y7 G12
HOST
H_D#_38 H_BREQ# H_BREQ# 3
H_D#39 W2 E9
H_D#_39 H_DEFER# H_DEFER# 3
H_SWING H_D#40 AA8 B10
H_D#_40 H_DBSY# H_DBSY# 3
H_D#41 Y9 AH7
H_D#_41 HPLL_CLK CLK_MCH_BCLK 2
H_D#42 AA13 AH6
H_D#_42 HPLL_CLK# CLK_MCH_BCLK# 2
R410 C642 H_D#43 AA9 J11
H_D#_43 H_DPWR# H_DPWR# 3
H_D#44 AA11 F9
H_D#_44 H_DRDY# H_DRDY# 3
100/F_4 0.1U/10V_4 H_D#45 AD11 H9
H_D#_45 H_HIT# H_HIT# 3
H_D#46 AD10 E12
H_D#_46 H_HITM# H_HITM# 3
H_D#47 AD13 H11
H_D#_47 H_LOCK# H_LOCK# 3
H_D#48 AE12 C9
H_D#_48 H_TRDY# H_TRDY# 3
H_D#49 AE9
H_D#50 AA2 H_D#_49
H_D#51 AD8 H_D#_50
H_D#52 AA3 H_D#_51
H_D#_52 H_DINV#[3..0] 3
H_D#53 AD3 J8 H_DINV#0
B H_D#54 AD7 H_D#_53 H_DINV#_0 L3 H_DINV#1 B
H_RCOMP H_D#55 AE14 H_D#_54 H_DINV#_1 Y13 H_DINV#2
H_D#56 AF3 H_D#_55 H_DINV#_2 Y1 H_DINV#3
H_D#57 AC1 H_D#_56 H_DINV#_3
H_D#_57 H_DSTBN#[3..0] 3
H_D#58 AE3 L10 H_DSTBN#0
R407 H_D#59 AC3 H_D#_58 H_DSTBN#_0 M7 H_DSTBN#1
H_D#60 AE11 H_D#_59 H_DSTBN#_1 AA5 H_DSTBN#2
Layout Note: H_D#61 AE8 H_D#_60 H_DSTBN#_2 AE6 H_DSTBN#3
24.9/F_4
WIDE(10):SPACING(20) , H_D#62 AG2 H_D#_61 H_DSTBN#_3
H_D#_62 H_DSTBP#[3..0] 3
L<0.5" H_D#63 AD6 L9 H_DSTBP#0
H_D#_63 H_DSTBP#_0 M8 H_DSTBP#1
H_DSTBP#_1 AA6 H_DSTBP#2
H_SWING C5 H_DSTBP#_2 AE5 H_DSTBP#3
H_RCOMP E3 H_SWING H_DSTBP#_3
+1.05V H_RCOMP H_REQ#[0..4] 3
B15 H_REQ#0
H_REQ#_0 K13 H_REQ#1
H_REQ#_1 F13 H_REQ#2
H_REQ#_2 B13 H_REQ#3
C12 H_REQ#_3 B14 H_REQ#4
3 H_CPURST# H_CPURST# H_REQ#_4
R414 E11
3 H_CPUSLP# H_CPUSLP# H_RS#[0..2] 3
2/3*VCCP B6 H_RS#0
1K/F_4 H_RS#_0 F12 H_RS#1
WIDE(10):SPACING(20), H_RS#_1 C8 H_RS#2
H_AVREF A11 H_RS#_2
A
L<0.5" H_AVREF A
B11
H_DVREF
R415 C649 CANTIGA_PM
2K/F_4 *0.1U/10V_4 352-(&7=4

4XDQWD&RPSXWHU,QF
1A
GMCH HOST
5 4 3 2 1
5 4 3 2 1
IV@
EV@
DDR3
+3V_S5
06
REV:B
Strap table U20B R571
Add 6/11
*0_4
Pin Name Strap description Configuration M36
N36 RSVD1 AP24 TC7SH08FU
RSVD2 SA_CK_0 M_CLK0 16
5
DDR CLK/ CONTROL/COMPENSATION
000= FSB 1066MHz R33 AT21 U10 1
RSVD3 SA_CK_1 M_CLK1 16 HWPG_1.5V 35,40
CFG[2:0] 010 = FSB 800MHz T33 AV24 4
D FSB Frequency Select AH9 RSVD4 SB_CK_0 AU20 M_CLK2 17 2 D
011 = FSB 667MHz RSVD5 SB_CK_1 M_CLK3 17 SUSC# 14,35
AH10 R253 *short0402
3
CFG[4:3] AH12 RSVD6 AR24
Reserved M_CLK#0 16
R250
AH13 RSVD7 SA_CK#_0 AR21 R252 *0_4 SUSB# 14,35
RSVD8 SA_CK#_1 M_CLK#1 16 12.1K_4
0 = DMI X2 K12 AU24
RSVD9 SB_CK#_0 AV20 M_CLK#2 17
CFG5 DMI X2 Select 1 = DMI X4(Default) M_CLK#3 17
SB_CK#_1 SM_PWROK
0 = iTPM Host Interface is enabled BC28
SA_CKE_0 AY28 M_CKE0 16
CFG6 iTPM Host Interface 1 = iTPM Host Interface is disabled(Default) M_CKE1 16
T24 SA_CKE_1 AY36 R251
RSVD14 SB_CKE_0 BB36 M_CKE2 17
0 = AMT Firmware will use TLS cipher suite SB_CKE_1 M_CKE3 17 10K_4
RSVD
B31
with no confidentiality RSVD15
CFG7 ME TLS Confidentiality BA17
1 = AMT Firmware will use TLS cipher suite M1 SA_CS#_0 AY16 M_CS#0 16
with confidentiality(Default) RSVD17 SA_CS#_1 M_CS#1 16
AV16
SB_CS#_0 AR13 M_CS#2 17
AY21 SB_CS#_1 M_CS#3 17
CFG8 Reserved
RSVD20 BD17
0 = Reverse Lanes SA_ODT_0 AY17 M_ODT0 16
SA_ODT_1 M_ODT1 16 +1.5V_SUS
CFG9 PCIE Graphics Lane Reversal 1 = Normal operation(Default) B2 BF15
BG23 RSVD21 SB_ODT_0 AY13 M_ODT2 17
0 = Enabled BF23 RSVD22 SB_ODT_1 M_ODT3 17
M_RCOMP R340 80.6/F_4
BH18 RSVD23 BG22 M_RCOMP M_RCOMP# R339
CFG10 PCIE Loopback enable 1 = Disabled (Default) SM_VREF=0.5*VCC_SM 80.6/F_4
BF18 RSVD24 SM_RCOMP BH21 M_RCOMP#
CFG11 Reserved RSVD25 SM_RCOMP#
BF28 SM_RCOMP_VOH
SM_PWROK only for
0 = ALLZ mode enable SM_RCOMP_VOH BH28 SM_RCOMP_VOL DDR3.(DDR2 PD only) +1.5V_SUS
CFG12 SM_RCOMP_VOL
ALLZ 1 = disable(Default) SM_DRAMRST# only
AV42 SM_VREF SM_VREF R241 10K/F_4
0 = XOR mode enable SM_VREF AR36 SM_PWROK for DDR3.(DDR2:NC) R242 10K/F_4
CFG13 XOR SM_PWROK BF17 SM_REXT R247 499/F_4
1 = disable(Default) SM_REXT BC36
SM_DRAMRST# DDR3_DRAMRST# 16,17
CFG[15:14] Reserved B38 CLK_DREFCLK
DPLL_REF_CLK CLK_DREFCLK 2
A38 CLK_DREFCLK#
DPLL_REF_CLK# E41 CLK_DREFCLK# 2
0 = Dynamic ODT disable CLK_DREFSSCLK SM_VREF.Default use voltage divider for
C DPLL_REF_SSCLK F41 CLK_DREFSSCLK 2 C
CFG16 FSB Dynamic ODT 1 = Dynamic ODT Enable(Default) CLK_DREFSSCLK#
DPLL_REF_SSCLK# CLK_DREFSSCLK# 2 poor layout cause +SMDDR_VREF not
ME JTAG
CFG[18:17] Reserved F43 CLK_PCIE_3GPLL meet spec.And Intel circuit PU/PD is
CLK
PEG_CLK CLK_PCIE_3GPLL 2
AL34 E43 CLK_PCIE_3GPLL#
T43 ME_JTAG_TCK PEG_CLK# CLK_PCIE_3GPLL# 2 1K,But Check list PU/PD is 10K.
0 = Normal (Default)
CFG19 DMI Lane Reversal 1 = Lanes Reversed AK34
T39 ME_JTAG_TDI DMI_TXN[3:0] 13
0 = Only Digital Display port (SDVO/DP/iHDMI) AN35 AE41 DMI_TXN0
T47 ME_JTAG_TDO DMI_RXN_0
Digital Display Port or PCIE is operational (Default) AE37 DMI_TXN1
AM35 DMI_RXN_1 AE47 DMI_TXN2
(SDVO/DP/iHDMI)
CFG20 Concurrent with PCIE
1 = Digital Display port (SDVO/DP/iHDMI) and
PCIE are operating simultaneously via PEG
T44 ME_JTAG_TMS DMI_RXN_2
DMI_RXN_3
AH39 DMI_TXN3
DMI_TXP[3:0] 13
INTEL FAE Suggest PD for Ext graphics
port AE40 DMI_TXP0 CLK_DREFCLK# R184 EV@0_4
T25 DMI_RXP_0 AE38 DMI_TXP1 CLK_DREFCLK R182 EV@0_4
2 MCH_BSEL0 R25 CFG_0 DMI_RXP_1 AE48 DMI_TXP2 CLK_DREFSSCLK#
0 = No SDVO/HDMI Device Present(Default) 2 MCH_BSEL1
R190 EV@0_4
SDVO_CTRLDATA SDVO Present P25 CFG_1 DMI_RXP_2 AH40 DMI_TXP3 CLK_DREFSSCLK R187 EV@0_4
1 = SDVO/HDMI Device present 2 MCH_BSEL2 CFG_2 DMI_RXP_3 DMI_RXN[3:0] 13
T31 MCH_CFG_3 P20
0 = Digital display(HDMI/DP) device MCH_CFG_4 P24 CFG_3 AE35 DMI_RXN0
T35 CFG_4 DMI_TXN_0
DDPC_CTRLDATA Digital Display Present absent(Default) MCH_CFG_5 C25 AE43 DMI_RXN1
MCH_CFG_6 N24 CFG_5 DMI_TXN_1 AE46 DMI_RXN2
1 = Digital display(HDMI/DP) device present CFG_6 DMI_TXN_2
MCH_CFG_7 M24 AH42 DMI_RXN3
CFG_7 DMI_TXN_3 DMI_RXP[3:0] 13
T28 MCH_CFG_8 E21
CFG_8
CFG
MCH_CFG_9 C23 AD35 DMI_RXP0
DMI
MCH_CFG_10 C24 CFG_9 DMI_TXP_0 AE44 DMI_RXP1 +1.5V_SUS
MCH_CFG_11 N21 CFG_10 DMI_TXP_1 AF46 DMI_RXP2
T29 CFG_11 DMI_TXP_2
MCH_CFG_12 P21 AH43 DMI_RXP3 SM_RCOMP_VOH 1K/F_4 R327
MCH_CFG_13 T21 CFG_12 DMI_TXP_3
MCH_CFG_14 R20 CFG_13 C560 C577
T32 CFG_14
MCH_CFG_15 M20 R335
Strap pin T30
MCH_CFG_16
MCH_CFG_17
L21
H21
CFG_15
CFG_16
2.2U/6.3V_6 0.01U/25V_4
3.01K/F_4
T27 CFG_17
MCH_CFG_18 P29
GRAPHICS VID
T33 CFG_18
+3V MCH_CFG_19 R28
MCH_CFG_20 T28 CFG_19 B33 SM_RCOMP_VOL
R203 *4.02K/F_4 MCH_CFG_19 CFG_20 GFX_VID_0 B32
R207 *4.02K/F_4 MCH_CFG_20 GFX_VID_1 G33
B B
GFX_VID_2 F33 C559 C576 R326
R29 GFX_VID_3 E33
14 PM_SYNC# PM_SYNC# GFX_VID_4
B7 2.2U/6.3V_6 0.01U/25V_4 1K/F_4
3,12,39 ICH_DPRSTP# N33 PM_DPRSTP#
R417 *2.21K/F_4 MCH_CFG_5 16 PM_EXTTS#0
R214 *2.21K/F_4 MCH_CFG_6 P32 PM_EXT_TS#_0
17 PM_EXTTS#1 PM_EXT_TS#_1
PM
R197 *2.21K/F_4 MCH_CFG_7 TPM Disable AT40 C34
3,14,39 DELAY_VR_PWRGOOD PWROK GFX_VR_EN +1.05V
R239 100/F_4 RST_IN#_MCH AT11
13 PLT_RST# T20 RSTIN#
R183 *2.21K/F_4 MCH_CFG_9 R210 *0_4 THRMTRIP#_R
3,12 PM_THRMTRIP# R32 THERMTRIP#
R416 *2.21K/F_4 MCH_CFG_10
14,39 PM_DPRSLPVR DPRSLPVR NB Thermaltrip
R208 *2.21K/F_4 MCH_CFG_12 AH37 R227
MCH_CFG_13 CL_CLK AH36 CL_CLK0 14
R213 *2.21K/F_4 NB Thermal trip pin BG48 CL_DATA AN36 CL_DATA0 14
R196 *2.21K/F_4 MCH_CFG_16 1K/F_4
No use Thermal trip NB side can BF48 NC_1 CL_PWROK AJ35 MPWROK 14,35
NC_2 CL_RST# CL_RST#0 14
ME
NC.(NB has ODT) BD48 AH34 MCH_CLVREF_R
BC48 NC_3 CL_VREF
5/4 modify it for park reversal PCIE x16 BH47 NC_4 Check list note : CL_VREF=0.35V
PM_DPRSTP# BG47 NC_5 C394 R228
The Daisy chain topology should BE47 NC_6 N28 DDPC_CTRLCLK
BH46 NC_7 DDPC_CTRLCLK M28 DDPC_DDCDATA 0.1U/10V_4 511/F_4
be routed from ICH9M to IMVP , BF46 NC_8 DDPC_CTRLDATA G36
NC_9 SDVO_CTRLCLK SDVO_CTRLCLK 26
then to (G)MCH and CPU, in that
NC
BG45 E36
+3V BH44 NC_10 SDVO_CTRLDATA K36 SDVO_CTRLDATA 26
CLK_MCH_OE#
order. BH43 NC_11 CLKREQ# H36 CLK_MCH_OE# 2
SDVO_CTRLDATA BH6 NC_12 ICH_SYNC# MCH_ICH_SYNC# 14
R185 IV@2.21K/F_4
MISC
R192 IV@2.21K/F_4 SDVO_CTRLCLK BH5 NC_13

R205 *2.21K/F_4 DDPC_DDCDATA BG4 NC_14 B12 TSATN# R169 56_4
DDPC_CTRLCLK BH3 NC_15 TSATN# +1.05V DDPC_CTRL for HDMI port C
R206 *2.21K/F_4
R198 10K_4 CLK_MCH_OE# BF3 NC_16
Modify 4/19 SDVO_CTRL for HDMI port B
R204 10K_4 PM_EXTTS#0 BH2 NC_17
R200 10K_4 PM_EXTTS#1 BG2 NC_18 B28 HDA_BIT_CLK_HDMI
BE2 NC_19 HDA_BCLK B30 HDA_RST#_HDMI
HDA_BIT_CLK_HDMI 12 If HDMI not support <Checklist ver0.8>
BG1 NC_20 HDA_RST# B29 HDA_RST#_HDMI 12 HDA --> NC If TSATN# is not used, then it must be terminated
HDA_SDIN_HDMI
BF1 NC_21 HDA_SDI C29 HDA_SDIN_HDMI 12
HDA_SDOUT_HDMI VCC_HDA-->GND with a 56-ȍ pull-up resistor to VCCP.
BD1 NC_22 HDA_SDO A28 HDA_SDOUT_HDMI 12
HDA_SYNC_HDMI
HDA
A BC1 NC_23 HDA_SYNC HDA_SYNC_HDMI 12 Differential signal-->NC A

F1 NC_24
NC_25 <Pin out check issue>
Impact ICH9M VCCHDA and VCCSUSHDA supply 1.5V/3.3V Cantiga EDS 0.7 change Ball B12 to TSATN# from TSATN
CANTIGA_PM
NOTE:
If (G)MCH's HD Audio signals are connected to ICH9M for
iHDMI, VCCHDA and VCCSUSHDA on ICH9M should be
only on 1.5V. These power pins on ICH9M can be supplied 352-(&7=4
with 3.3V if and only if (G)MCH's HDA is not connected to
ICH9M. Consequently, only 1.5V audio/modem codecs can
4XDQWD&RPSXWHU,QF
*0&+&$17,*$ be used on the platform. Size
Date:
Document Number
GMCH DMI
Rev
1A
43
5 4 3 2 1
5 4 3 2 1
IV@ ,9 (9'LV(QDEOHVHWWLQJ
L<0.5" , If PCIE not support
EV@ ,9 (9'LV(QDEOHVHWWLQJ U20C
still connect to +VCC_PEG
<5/31>Montevina_Schematics_Checklist_Rev0_8
a)For TVOUT Disabled, TV_DCONSEL[1:0] Connect to GND. But
If LVDS no use,all signal can NC design guide Rev0.7 show NC.What is correct.
+1.05V b)For CRT DAC Disable, CRT_DDC_CLK, CRT_DDC_DATA .
SP@ 25 L_BKLT_CTRL
L32
G32 L_BKLT_CTRL T37 EXP_A_COMPX R209 49.9/F_4
CRT_HSYNC, CRT_VSYNCThese signals should be connected to
25 INT_LVDS_BLON GND. But design guide Rev0.7 show NC, Intel suggest follow
R201 IV@10K_4 L_CTRL_CLK M32 L_BKLT_EN PEG_COMPI T36
07
L_CTRL_CLK PEG_COMPO Design guide.
D +3V D
R199 IV@10K_4 L_CTRL_DATA M33 <check list> <check list>
L_CTRL_DATA PEG_RXN[15:0] 18
K33 H44 PEG_RXN0
25 INT_LVDS_EDIDCLK
J33 L_DDC_CLK PEG_RX#_0 J46 PEG_RXN1
For EV@ For IV@
25 INT_LVDS_EDIDDATA L_DDC_DATA PEG_RX#_1 CRT R/G/B 0ohm to GND CRT R/G/B 150ohm to GND
L44 PEG_RXN2
PEG_RX#_2 L40 PEG_RXN3 CRTIREF 0ohm to GND CRTIREF 1Kohm to GND
M29 PEG_RX#_3 N41 PEG_RXN4
25 INT_LVDS_DIGON L_VDD_EN PEG_RX#_4
R188 IV@2.37K/F_4 C44 P48 PEG_RXN5 Can support reversal routing.If CFG9=1, PCI Express
B43 LVDS_IBG PEG_RX#_5 N44 PEG_RXN6
E37 LVDS_VBG PEG_RX#_6 T43 PEG_RXN7 is normal operation. If CFG9=0, then PEG_TXP0
LVDS_VREFH PEG_RX#_7 CRTIREF
E38 U43 PEG_RXN8 becomes PEG_TXP15, PEG_TXP1 becomes
LVDS_VREFL PEG_RX#_8 For IV: 1Kohm
LVDS
INT_TXLCLKOUT- C41 Y43 PEG_RXN9
25 INT_TXLCLKOUT- LVDSA_CLK# PEG_RX#_9 PEG_TXP14, PEG_TXP2 becomes PEG_TXP13, etc.
25 INT_TXLCLKOUT+ INT_TXLCLKOUT+ C40
LVDSA_CLK PEG_RX#_10
Y48 PEG_RXN10 For EV:0ohm
B37 Y36 PEG_RXN11 similarly for PEG_RXP[15:0] and PEG_RXN[15:0]
A37 LVDSB_CLK# PEG_RX#_11 AA43 PEG_RXN12 R186 SP@1K/F_4 CRTIREF
LVDSB_CLK PEG_RX#_12 AD37 PEG_RXN13
INT_TXLOUT0- H47 PEG_RX#_13 AC47 PEG_RXN14
25 INT_TXLOUT0- LVDSA_DATA#_0 PEG_RX#_14
INT_TXLOUT1- E46 AD39 PEG_RXN15
25 INT_TXLOUT1-
25 INT_TXLOUT2-
INT_TXLOUT2- G40 LVDSA_DATA#_1
LVDSA_DATA#_2
PEG_RX#_15
PEG_RXP[15:0] 18,26
SP@
A40 H43 PEG_RXP0 CRT_R/G/B
GRAPHICS
LVDSA_DATA#_3 PEG_RX_0 J44 PEG_RXP1
25 INT_TXLOUT0+ INT_TXLOUT0+ H48 PEG_RX_1 L43 PEG_RXP2 For IV: 150ohm
LVDSA_DATA_0 PEG_RX_2
25 INT_TXLOUT1+ INT_TXLOUT1+ D45
LVDSA_DATA_1 PEG_RX_3
L41 PEG_RXP3 For EV:0ohm
INT_TXLOUT2+ F40 N40 PEG_RXP4
25 INT_TXLOUT2+ LVDSA_DATA_2 PEG_RX_4
B40 P47 PEG_RXP5 R179 SP@150_4 INT_CRT_BLU
C LVDSA_DATA_3 PEG_RX_5 N43 PEG_RXP6 C
A41 PEG_RX_6 T42 PEG_RXP7 R178 SP@150_4 INT_CRT_GRN
H38 LVDSB_DATA#_0 PEG_RX_7 U42 PEG_RXP8
G37 LVDSB_DATA#_1 PEG_RX_8 Y42 PEG_RXP9 R180 SP@150_4 INT_CRT_RED
J37 LVDSB_DATA#_2 PEG_RX_9 W47 PEG_RXP10
LVDSB_DATA#_3 PEG_RX_10 Y37 PEG_RXP11
B42 PEG_RX_11 AA42 PEG_RXP12
G38 LVDSB_DATA_0 PEG_RX_12 AD36 PEG_RXP13
F37 LVDSB_DATA_1 PEG_RX_13 AC48 PEG_RXP14
TV_A/B/C LVDSB_DATA_2 PEG_RX_14
PCI-EXPRESS
K37 AD40 PEG_RXP15
SP@ For IV: 75ohm LVDSB_DATA_3 PEG_RX_15
PEG_TXN[15:0] 18,26
For EV:0ohm PEG_TX#_0
J41 C_PEG_TXN0 C309 0.1U/10V_4 PEG_TXN0
M46 C_PEG_TXN1 C323 0.1U/10V_4 PEG_TXN1
R189 SP@75_4 INT_TV_COMP F25 PEG_TX#_1 M47 C_PEG_TXN2 C629 0.1U/10V_4 PEG_TXN2
R195 SP@75_4 INT_TV_Y/G H25 TVA_DAC PEG_TX#_2 M40 C_PEG_TXN3 C332 0.1U/10V_4 PEG_TXN3
R194 SP@75_4 INT_TV_C/R K25 TVB_DAC PEG_TX#_3 M42 C_PEG_TXN4 C330 EV@.1U/10V_4 PEG_TXN4
TVC_DAC PEG_TX#_4
TV
R48 C_PEG_TXN5 C626 EV@.1U/10V_4 PEG_TXN5
H24 PEG_TX#_5 N38 C_PEG_TXN6 C336 EV@.1U/10V_4 PEG_TXN6
TV_RTN PEG_TX#_6 T40 C_PEG_TXN7 C339 EV@.1U/10V_4 PEG_TXN7
PEG_TX#_7 U37 C_PEG_TXN8 C351 EV@.1U/10V_4 PEG_TXN8
PEG_TX#_8 U40 C_PEG_TXN9 C353 EV@.1U/10V_4 PEG_TXN9
C31 PEG_TX#_9 Y40 C_PEG_TXN10 C356 EV@.1U/10V_4 PEG_TXN10
E32 TV_DCONSEL_0 PEG_TX#_10 AA46 C_PEG_TXN11 C369 EV@.1U/10V_4 PEG_TXN11
TV_DCONSEL_1 PEG_TX#_11 AA37 C_PEG_TXN12 C376 EV@.1U/10V_4 PEG_TXN12
PEG_TX#_12 AA40 C_PEG_TXN13 C377 EV@.1U/10V_4 PEG_TXN13
B B
PEG_TX#_13 AD43 C_PEG_TXN14 C391 EV@.1U/10V_4 PEG_TXN14
PEG_TX#_14 AC46 C_PEG_TXN15 C384 EV@.1U/10V_4 PEG_TXN15
PEG_TX#_15
PEG_TXP[15:0] 18,26
INT_CRT_BLU E28 J42 C_PEG_TXP0 C311 0.1U/10V_4 PEG_TXP0
25 INT_CRT_BLU CRT_BLUE PEG_TX_0 L46 C_PEG_TXP1 C318 0.1U/10V_4 PEG_TXP1
INT_CRT_GRN G28 PEG_TX_1 M48 C_PEG_TXP2 C632 0.1U/10V_4 PEG_TXP2
25 INT_CRT_GRN CRT_GREEN PEG_TX_2 M39 C_PEG_TXP3 C334 0.1U/10V_4 PEG_TXP3
INT_CRT_RED J28 PEG_TX_3 M43 C_PEG_TXP4 C324 EV@.1U/10V_4 PEG_TXP4
25 INT_CRT_RED CRT_RED PEG_TX_4
VGA
R47 C_PEG_TXP5 C627 EV@.1U/10V_4 PEG_TXP5

6/14 Modify G29 PEG_TX_5 N37 C_PEG_TXP6 C338 EV@.1U/10V_4 PEG_TXP6
CRT_IRTN PEG_TX_6
REV:B H32 PEG_TX_7
T39
U36
C_PEG_TXP7
C_PEG_TXP8
C344
C346
EV@.1U/10V_4
EV@.1U/10V_4
PEG_TXP7
PEG_TXP8
25 INT_CRT_DDCCLK CRT_DDC_CLK PEG_TX_8
J32 U39 C_PEG_TXP9 C355 EV@.1U/10V_4 PEG_TXP9
25 INT_CRT_DDCDAT CRT_DDC_DATA PEG_TX_9
R426 IV@24.9_4 HSYNC_G J29 Y39 C_PEG_TXP10 C363 EV@.1U/10V_4 PEG_TXP10
25 INT_HSYNC CRT_HSYNC PEG_TX_10
CRTIREF E29 Y46 C_PEG_TXP11 C365 EV@.1U/10V_4 PEG_TXP11
R425 IV@24.9_4 VSYNC_G L29 CRT_TVO_IREF PEG_TX_11 AA36 C_PEG_TXP12 C371 EV@.1U/10V_4 PEG_TXP12
25 INT_VSYNC CRT_VSYNC PEG_TX_12 AA39 C_PEG_TXP13 C382 EV@.1U/10V_4 PEG_TXP13
PEG_TX_13 AD42 C_PEG_TXP14 C396 EV@.1U/10V_4 PEG_TXP14
HSYNC/VSYNC serial R place close to NB PEG_TX_14 AD46 C_PEG_TXP15 C387 EV@.1U/10V_4 PEG_TXP15
PEG_TX_15
Discrete STUFFED. CANTIGA_PM
HSYNC_G
CRTIREF pull down
for IV cantiga 1k ohm/F
A A
VSYNC_G
352-(&7=4
R413 R412
EV@0_4 EV@0_4
4XDQWD&RPSXWHU,QF
1A
GMCH VGA
5 4 3 2 1
5 4 3 2 1
08
16 M_A_DQ[63:0] 17 M_B_DQ[63:0]
U20D U20E
M_A_DQ0 AJ38 BD21 M_B_DQ0 AK47 BC16
AJ41 SA_DQ_0 SA_BS_0 BG18 M_A_BS0 16 AH46 SB_DQ_0 SB_BS_0 BB17 M_B_BS0 17
M_A_DQ1 M_B_DQ1
SA_DQ_1 SA_BS_1 M_A_BS1 16 SB_DQ_1 SB_BS_1 M_B_BS1 17
M_A_DQ2 AN38 AT25 M_B_DQ2 AP47 BB33
D AM38 SA_DQ_2 SA_BS_2 M_A_BS2 16 AP46 SB_DQ_2 SB_BS_2 M_B_BS2 17 D
M_A_DQ3 M_B_DQ3
M_A_DQ4 AJ36 SA_DQ_3 BB20 M_B_DQ4 AJ46 SB_DQ_3
SA_DQ_4 SA_RAS# M_A_RAS# 16 SB_DQ_4
M_A_DQ5 AJ40 BD20 M_B_DQ5 AJ48 AU17
AM44 SA_DQ_5 SA_CAS# AY20 M_A_CAS# 16 AM48 SB_DQ_5 SB_RAS# BG16 M_B_RAS# 17
M_A_DQ6 M_B_DQ6
SA_DQ_6 SA_WE# M_A_WE# 16 SB_DQ_6 SB_CAS# M_B_CAS# 17
M_A_DQ7 AM42 M_B_DQ7 AP48 BF14
AN43 SA_DQ_7 AU47 SB_DQ_7 SB_WE# M_B_WE# 17
M_A_DQ8 M_B_DQ8
M_A_DQ9 AN44 SA_DQ_8 M_B_DQ9 AU46 SB_DQ_8
M_A_DQ10 AU40 SA_DQ_9 M_B_DQ10 BA48 SB_DQ_9
AT38 SA_DQ_10 AM37 M_A_DM[7:0] 16 AY48 SB_DQ_10
M_A_DQ11 M_A_DM0 M_B_DQ11
SA_DQ_11 SA_DM_0 SB_DQ_11 M_B_DM[7:0] 17
M_A_DQ12 AN41 AT41 M_A_DM1 M_B_DQ12 AT47 AM47 M_B_DM0
M_A_DQ13 AN39 SA_DQ_12 SA_DM_1 AY41 M_A_DM2 M_B_DQ13 AR47 SB_DQ_12 SB_DM_0 AY47 M_B_DM1
M_A_DQ14 AU44 SA_DQ_13 SA_DM_2 AU39 M_A_DM3 M_B_DQ14 BA47 SB_DQ_13 SB_DM_1 BD40 M_B_DM2
M_A_DQ15 AU42 SA_DQ_14 SA_DM_3 BB12 M_A_DM4 M_B_DQ15 BC47 SB_DQ_14 SB_DM_2 BF35 M_B_DM3
M_A_DQ16 AV39 SA_DQ_15 SA_DM_4 AY6 M_A_DM5 M_B_DQ16 BC46 SB_DQ_15 SB_DM_3 BG11 M_B_DM4
M_A_DQ17 AY44 SA_DQ_16 SA_DM_5 AT7 M_A_DM6 M_B_DQ17 BC44 SB_DQ_16 SB_DM_4 BA3 M_B_DM5
M_A_DQ18 BA40 SA_DQ_17 SA_DM_6 AJ5 M_A_DM7 M_B_DQ18 BG43 SB_DQ_17 SB_DM_5 AP1 M_B_DM6
B
M_A_DQ19 BD43 SA_DQ_18 SA_DM_7 M_B_DQ19 BF43 SB_DQ_18 SB_DM_6 AK2 M_B_DM7
SA_DQ_19 M_A_DQS[7:0] 16 SB_DQ_19 SB_DM_7
M_A_DQ20 AV41 AJ44 M_A_DQS0 M_B_DQ20 BE45
AY43 SA_DQ_20 SA_DQS_0 AT44 BC41 SB_DQ_20 AL47 M_B_DQS[7:0] 17
M_A_DQ21 M_A_DQS1 M_B_DQ21 M_B_DQS0
M_A_DQ22 BB41 SA_DQ_21 SA_DQS_1 BA43 M_A_DQS2 M_B_DQ22 BF40 SB_DQ_21 SB_DQS_0 AV48 M_B_DQS1
SA_DQ_22 SA_DQS_2 SB_DQ_22 SB_DQS_1
MEMORY
M_A_DQ23 BC40 BC37 M_A_DQS3 M_B_DQ23 BF41 BG41 M_B_DQS2
MEMORY
M_A_DQ24 AY37 SA_DQ_23 SA_DQS_3 AW12 M_A_DQS4 M_B_DQ24 BG38 SB_DQ_23 SB_DQS_2 BG37 M_B_DQS3
M_A_DQ25 BD38 SA_DQ_24 SA_DQS_4 BC8 M_A_DQS5 M_B_DQ25 BF38 SB_DQ_24 SB_DQS_3 BH9 M_B_DQS4
M_A_DQ26 AV37 SA_DQ_25 SA_DQS_5 AU8 M_A_DQS6 M_B_DQ26 BH35 SB_DQ_25 SB_DQS_4 BB2 M_B_DQS5
M_A_DQ27 AT36 SA_DQ_26 SA_DQS_6 AM7 M_A_DQS7 M_B_DQ27 BG35 SB_DQ_26 SB_DQS_5 AU1 M_B_DQS6
AY38 SA_DQ_27 SA_DQS_7 AJ43 M_A_DQS#[7:0] 16 BH40 SB_DQ_27 SB_DQS_6 AN6
M_A_DQ28 M_A_DQS#0 M_B_DQ28 M_B_DQS7
C
BB38 SA_DQ_28 SA_DQS#_0 AT43 BG39 SB_DQ_28 SB_DQS_7 AL46 M_B_DQS#[7:0] 17 C
M_A_DQ29 M_A_DQS#1 M_B_DQ29 M_B_DQS#0
M_A_DQ30 AV36 SA_DQ_29 SA_DQS#_1 BA44 M_A_DQS#2 M_B_DQ30 BG34 SB_DQ_29 SB_DQS#_0 AV47 M_B_DQS#1
M_A_DQ31 AW36 SA_DQ_30 SA_DQS#_2 BD37 M_A_DQS#3 M_B_DQ31 BH34 SB_DQ_30 SB_DQS#_1 BH41 M_B_DQS#2
M_A_DQ32 BD13 SA_DQ_31 SA_DQS#_3 AY12 M_A_DQS#4 M_B_DQ32 BH14 SB_DQ_31 SB_DQS#_2 BH37 M_B_DQS#3
M_A_DQ33 AU11 SA_DQ_32 SA_DQS#_4 BD8 M_A_DQS#5 M_B_DQ33 BG12 SB_DQ_32 SB_DQS#_3 BG9 M_B_DQS#4
M_A_DQ34 BC11 SA_DQ_33 SA_DQS#_5 AU9 M_A_DQS#6 M_B_DQ34 BH11 SB_DQ_33 SB_DQS#_4 BC2 M_B_DQS#5
M_A_DQ35 BA12 SA_DQ_34 SA_DQS#_6 AM8 M_A_DQS#7 M_B_DQ35 BG8 SB_DQ_34 SB_DQS#_5 AT2 M_B_DQS#6
SYSTEM
AU13 SA_DQ_35 SA_DQS#_7 BH12 SB_DQ_35 SB_DQS#_6 AN5
SYSTEM
M_A_DQ36 M_B_DQ36 M_B_DQS#7
SA_DQ_36 M_A_A[14:0] 16 SB_DQ_36 SB_DQS#_7
M_A_DQ37 AV13 BA21 M_A_A0 M_B_DQ37 BF11
BD12 SA_DQ_37 SA_MA_0 BC24 BF8 SB_DQ_37 AV17 M_B_A[14:0] 17
M_A_DQ38 M_A_A1 M_B_DQ38 M_B_A0
M_A_DQ39 BC12 SA_DQ_38 SA_MA_1 BG24 M_A_A2 M_B_DQ39 BG7 SB_DQ_38 SB_MA_0 BA25 M_B_A1
M_A_DQ40 BB9 SA_DQ_39 SA_MA_2 BH24 M_A_A3 M_B_DQ40 BC5 SB_DQ_39 SB_MA_1 BC25 M_B_A2
M_A_DQ41 BA9 SA_DQ_40 SA_MA_3 BG25 M_A_A4 M_B_DQ41 BC6 SB_DQ_40 SB_MA_2 AU25 M_B_A3
M_A_DQ42 AU10 SA_DQ_41 SA_MA_4 BA24 M_A_A5 M_B_DQ42 AY3 SB_DQ_41 SB_MA_3 AW25 M_B_A4
M_A_DQ43 AV9 SA_DQ_42 SA_MA_5 BD24 M_A_A6 M_B_DQ43 AY1 SB_DQ_42 SB_MA_4 BB28 M_B_A5
M_A_DQ44 BA11 SA_DQ_43 SA_MA_6 BG27 M_A_A7 M_B_DQ44 BF6 SB_DQ_43 SB_MA_5 AU28 M_B_A6
M_A_DQ45 BD9 SA_DQ_44 SA_MA_7 BF25 M_A_A8 M_B_DQ45 BF5 SB_DQ_44 SB_MA_6 AW28 M_B_A7
M_A_DQ46 AY8 SA_DQ_45 SA_MA_8 AW24 M_A_A9 M_B_DQ46 BA1 SB_DQ_45 SB_MA_7 AT33 M_B_A8
M_A_DQ47 BA6 SA_DQ_46 SA_MA_9 BC21 M_A_A10 M_B_DQ47 BD3 SB_DQ_46 SB_MA_8 BD33 M_B_A9
M_A_DQ48 AV5 SA_DQ_47 SA_MA_10 BG26 M_A_A11 M_B_DQ48 AV2 SB_DQ_47 SB_MA_9 BB16 M_B_A10
DDR
SA_DQ_48 SA_MA_11 SB_DQ_48 SB_MA_10
DDR
M_A_DQ49 AV7 BH26 M_A_A12 M_B_DQ49 AU3 AW33 M_B_A11
M_A_DQ50 AT9 SA_DQ_49 SA_MA_12 BH17 M_A_A13 M_B_DQ50 AR3 SB_DQ_49 SB_MA_11 AY33 M_B_A12
M_A_DQ51 AN8 SA_DQ_50 SA_MA_13 AY25 M_A_A14 M_B_DQ51 AN2 SB_DQ_50 SB_MA_12 BH15 M_B_A13
M_A_DQ52 AU5 SA_DQ_51 SA_MA_14 M_B_DQ52 AY2 SB_DQ_51 SB_MA_13 AU33 M_B_A14
M_A_DQ53 AU6 SA_DQ_52 M_B_DQ53 AV1 SB_DQ_52 SB_MA_14
M_A_DQ54 AT5 SA_DQ_53 M_B_DQ54 AP3 SB_DQ_53
B B
M_A_DQ55 AN10 SA_DQ_54 M_B_DQ55 AR1 SB_DQ_54
M_A_DQ56 AM11 SA_DQ_55 M_B_DQ56 AL1 SB_DQ_55
M_A_DQ57 AM5 SA_DQ_56 M_B_DQ57 AL2 SB_DQ_56
M_A_DQ58 AJ9 SA_DQ_57 M_B_DQ58 AJ1 SB_DQ_57
M_A_DQ59 AJ8 SA_DQ_58 M_B_DQ59 AH1 SB_DQ_58
M_A_DQ60 AN12 SA_DQ_59 M_B_DQ60 AM2 SB_DQ_59
M_A_DQ61 AM13 SA_DQ_60 M_B_DQ61 AM3 SB_DQ_60
M_A_DQ62 AJ11 SA_DQ_61 M_B_DQ62 AH3 SB_DQ_61
M_A_DQ63 AJ12 SA_DQ_62 M_B_DQ63 AJ3 SB_DQ_62
SA_DQ_63 SB_DQ_63
CANTIGA_PM CANTIGA_PM
A A
352-(&7=4
4XDQWD&RPSXWHU,QF
*0&+&$17,*$ Size
Date:
Document Number
GMCH DDRII
Rev
1A
43
5 4 3 2 1
5 4 3 2 1
IV@
SP@
09
Power consumption reference to Intel
644135 Cantiga chipset EDS Volume1.
Section 10 Intel check list(Rev 0.8) Intel check list(Rev 0.8)
*07'3a:
No description for VCC_SM bulk CAP 270U*1 near to power(+V1.05M).
*67'3a:
Intel CRB(Rev 0.7) 270U*2 near to NB
330U*1 Reserve near to power Intel CRB(Rev 0.7)
307'3:
D 330U*1 near to NB 270U*3 near to power(+V1.05M). D
270U*1 near to NB
+1.05V_AXG
ESR=12m ohm
U20G
+1.5V_SUS
AP33 W28
AN33 VCC_SM_1 VCC_AXG_NCTF_1 V28 +1.05V U20F
BH32 VCC_SM_2 VCC_AXG_NCTF_2 W26
BG32 VCC_SM_3 VCC_AXG_NCTF_3 V26
C561 C558 C414 + C572 BF32 VCC_SM_4 VCC_AXG_NCTF_4 W25
BD32 VCC_SM_5 VCC_AXG_NCTF_5 V25 AG34
22U/6.3V_8 22U/6.3V_8 0.1U/10V_4 330U/2V_7343 BC32 VCC_SM_6 VCC_AXG_NCTF_6 W24 AC34 VCC_1
BB32 VCC_SM_7 VCC_AXG_NCTF_7 V24 AB34 VCC_2
BA32 VCC_SM_8 VCC_AXG_NCTF_8 W23 C375 C379 C359 C381 + C631 AA34 VCC_3
AY32 VCC_SM_9 VCC_AXG_NCTF_9 V23 Y34 VCC_4
AW32 VCC_SM_10 VCC_AXG_NCTF_10 AM21 0.1U/10V_4 0.22U/6.3V_4 0.22U/6.3V_4 22U/6.3V_8 330U/2V_7343 V34 VCC_5
AV32 VCC_SM_11 VCC_AXG_NCTF_11 AL21 U34 VCC_6
AU32 VCC_SM_12 VCC_AXG_NCTF_12 AK21 AM33 VCC_7
AT32 VCC_SM_13 VCC_AXG_NCTF_13 W21 AK33 VCC_8
AR32 VCC_SM_14 VCC_AXG_NCTF_14 V21 AJ33 VCC_9
VCC_SM_15 VCC_AXG_NCTF_15 VCC_10
9&&B609 AP32 U21 Place close to AG33
POWER
AN32 VCC_SM_16 VCC_AXG_NCTF_16 AM20 AF33 VCC_11
''50 BH31 VCC_SM_17 VCC_AXG_NCTF_17 AK20 the GMCH VCC_12
VCC_SM_18 VCC_AXG_NCTF_18
P$B6P$B6 BG31
VCC_SM_19 VCC_AXG_NCTF_19
W20 AE33
VCC_13
VCC CORE
BF31 U20 AC33
''50P$B6 BG30 VCC_SM_20 VCC_AXG_NCTF_20 AM19 AA33 VCC_14
BH29 VCC_SM_21 VCC_AXG_NCTF_21 AL19 Y33 VCC_15
''50P$B6 BG29 VCC_SM_22 VCC_AXG_NCTF_22 AK19 W33 VCC_16
BF29 VCC_SM_23 VCC_AXG_NCTF_23 AJ19 V33 VCC_17
BD29 VCC_SM_24 VCC_AXG_NCTF_24 AH19 U33 VCC_18
BC29 VCC_SM_25 VCC SM VCC_AXG_NCTF_25 AG19 AH28 VCC_19
BB29 VCC_SM_26 VCC_AXG_NCTF_26 AF19 AF28 VCC_20
BA29 VCC_SM_27 VCC_AXG_NCTF_27 AE19 AC28 VCC_21
AY29 VCC_SM_28 VCC_AXG_NCTF_28 AB19 AA28 VCC_22
AW29 VCC_SM_29 VCC_AXG_NCTF_29 AA19 AJ26 VCC_23
AV29 VCC_SM_30 VCC_AXG_NCTF_30 Y19 AG26 VCC_24
C C
AU29 VCC_SM_31 VCC_AXG_NCTF_31 W19 AE26 VCC_25
AT29 VCC_SM_32 VCC_AXG_NCTF_32 V19 AC26 VCC_26
AR29 VCC_SM_33 VCC_AXG_NCTF_33 U19 AH25 VCC_27
AP29 VCC_SM_34 VCC_AXG_NCTF_34 AM17 AG25 VCC_28
VCC_SM_35 VCC_AXG_NCTF_35 AK17 AF25 VCC_29
BA36 VCC_AXG_NCTF_36 AH17 AG24 VCC_30
BB24 VCC_SM_36/NC VCC_AXG_NCTF_37 AG17 AJ23 VCC_31
BD16 VCC_SM_37/NC VCC_AXG_NCTF_38 AF17 +1.05V +1.05V_AXG AH23 VCC_32 +1.05V
BB21 VCC_SM_38/NC VCC_AXG_NCTF_39 AE17 AF23 VCC_33
POWER
AW16 VCC_SM_39/NC VCC_AXG_NCTF_40 AC17 VCC_34 AM32
AW13 VCC_SM_40/NC VCC_AXG_NCTF_41 AB17 R384 IV@0_8 T32 VCC_NCTF_1 AL32
AT13 VCC_SM_41/NC VCC_AXG_NCTF_42 Y17 VCC_35 VCC_NCTF_2 AK32
VCC_SM_42/NC VCC_AXG_NCTF_43 W17 IV@ R381 IV@0_8 VCC_NCTF_3 AJ32
+1.05V_AXG VCC_AXG_NCTF_44 V17 VCC_NCTF_4 AH32
VCC GFX NCTF
VCC_AXG_NCTF_45 AM16 R383 IV@0_8 VCC_NCTF_5 AG32

Y26 VCC_AXG_NCTF_46 AL16 VCC_NCTF_6 AE32
VCC_AXG_1 VCC_AXG_NCTF_47 VCC_NCTF_7
9 AE25
VCC_AXG_2 VCC_AXG_NCTF_48
AK16
VCC_NCTF_8
AC32
AB25 AJ16 AA32
*UDSKLFVFRUH AA25 VCC_AXG_3 VCC_AXG_NCTF_49 AH16 VCC_NCTF_9 Y32
VCC_AXG_4 VCC_AXG_NCTF_50 VCC_NCTF_10
9&&B$;* AE24
AC24 VCC_AXG_5 VCC_AXG_NCTF_51
AG16
AF16 ,9 (9'LV(QDEOHVHWWLQJ VCC_NCTF_11
W32
U32
9&&B$;*B1&7) AA24 VCC_AXG_6 VCC_AXG_NCTF_52 AE16 Design guide(Table 72)
VCC_NCTF_12 AM30
Y24 VCC_AXG_7 VCC_AXG_NCTF_53 AC16 VCC_NCTF_13 AL30
P$ AE23 VCC_AXG_8 VCC_AXG_NCTF_54 AB16 +1.05V_AXG For INT VGA diasble.VCC_AXG power can connect to GND VCC_NCTF_14 AK30
AC23 VCC_AXG_9 VCC_AXG_NCTF_55 AA16 VCC_NCTF_15 AH30
AB23 VCC_AXG_10 VCC_AXG_NCTF_56 Y16 VCC_NCTF_16 AG30
AA23 VCC_AXG_11 VCC_AXG_NCTF_57 W16 VCC_NCTF_17 AF30
AJ21 VCC_AXG_12 VCC_AXG_NCTF_58 V16 SP@ VCC_NCTF_18 AE30
AG21 VCC_AXG_13 VCC_AXG_NCTF_59 U16 + C602 + C601 C399 C392 C367 C380 C393 C410 C370 VCC_NCTF_19 AC30
AE21 VCC_AXG_14 VCC_AXG_NCTF_60 VCC_NCTF_20 AB30
AC21 VCC_AXG_15 IV@330U/2V_7343 IV@330U/2V_7343 IV@0.47U/6.3V_4 SP@1U/10V_6 IV@10U/6.3V_8 IV@22U/6.3V_8 IV@0.1U/10V_4 IV@0.1U/10V_4 IV@0.1U/10V_4 VCC_NCTF_21 AA30
AA21 VCC_AXG_16 VCC_NCTF_22 Y30
Voltage regulator is shared between VCC_AXG_17 VCC_NCTF_23
Y21 W30
the Graphics Core Rail, VCC_AXG_18 VCC_NCTF_24
VCC NCTF
AH20 V30
VCCA_HPLL,VCCA_MPLL,VCCA_PEG_PLLVCCD_PEG_PLL, VCC_AXG_19 VCC_NCTF_25
AF20
VCC_AXG_20 Place close to the GMCH 63#,96XWIIXI Cavity Capacitors VCC_NCTF_26
U30
VCCA_SM_CK, VCCA_DPLLA, VCCA_DPLLB, VCCD_HPLL, AE20 AL29
VCCA_SM, VCC_AXF AC20 VCC_AXG_21
Intel check list(Rev 0.8) (9VWXIIRKP VCC_NCTF_27 AK29
B
AB20 VCC_AXG_22 VCC_NCTF_28 AJ29 B
AA20 VCC_AXG_23 220U*2 near to NB(ESR=15m ohm) VCC_NCTF_29 AH29
T17 VCC_AXG_24 VCC_NCTF_30 AG29
T16 VCC_AXG_25 Intel CRB(Rev 0.7) VCC_NCTF_31 AE29
AM15 VCC_AXG_26 270U*4 near to power(+V1.05S). VCC_NCTF_32 AC29
AL15 VCC_AXG_27 VCC_NCTF_33 AA29
VCC_AXG_28 330U*2 near to NB VCC_NCTF_34
AE15 Y29
AJ15 VCC_AXG_29 VCC_NCTF_35 W29
AH15 VCC_AXG_30 VCC_NCTF_36 V29
AG15 VCC_AXG_31 VCC_NCTF_37 AL28
AF15 VCC_AXG_32 VCC_NCTF_38 AK28
AB15 VCC_AXG_33 VCC_NCTF_39 AL26
AA15 VCC_AXG_34 VCC_NCTF_40 AK26
VCC_AXG_35 VCC_NCTF_41
VCC GFX
Y15 1.8V AK25

V15 VCC_AXG_36 VCC_NCTF_42 AK24
U15 VCC_AXG_37 Internal connect to power VCC_NCTF_43 AK23
AN14 VCC_AXG_38 VCC_NCTF_44
VCC_AXG_39
AM14
VCC_AXG_40 9&&
U14 AV44 VCC_SM_LF1
VCC_AXG_41 VCC_SM_LF1 9&&B1&7)
VCC SM LF
T14 BA37 VCC_SM_LF2

VCC_AXG_42 VCC_SM_LF2
VCC_SM_LF3
AM40
AV21
VCC_SM_LF3
VCC_SM_LF4
P$B(9
VCC_SM_LF4 AY5 VCC_SM_LF5 CANTIGA_PM P$B,9
VCC_SM_LF5 AM10 VCC_SM_LF6
+1.05V_AXG VCC_SM_LF6 BB13 VCC_SM_LF7
0((QJLQH
VCC_SM_LF7
P$
C418 C403 C417 C416 C404 C415 C413
R235 IV@10/F_4 AJ14 7RWDO0D[ P$
IV@ R230 IV@10/F_4 AH14 VCC_AXG_SENSE 0.1U/10V_4 0.1U/10V_4 0.22U/6.3V_4 0.22U/6.3V_4 0.47U/6.3V_4 1U/6.3V_4 1U/6.3V_4
VSS_AXG_SENSE
A CANTIGA_PM A
1. Route VCC_AXG_SENSE and VSS_AXG_SENSE differentially

2. VCC_AXG_SENSE PU to +VGFX_CORE_INT with 10ohm
and VSS_AXG_SENSE PD with 10ohm for Intel suggest
352-(&7=4
4XDQWD&RPSXWHU,QF
*0&+&$17,*$ Size
Date:
Document Number
GMCH VCC,NCTF
Rev
1A
43
5 4 3 2 1
5 4 3 2 1
If CRT have Flicker issue
STUFF 5.6 ohm ,9 (9'LV(QDEOHVHWWLQJ
10
Power consumption reference to Intel
Cantiga chipset EDS Volume1. Section 10
+3V_CRT_TV_DAC R171 IV@BLM18PG181SN1D_6 +3V_VCCA_CRT_DAC
C322 C328 C312
IV@0.1U/10V_4 SP@0.01U/25V_4 IV@10U/6.3V_8

IV@ Modify 6/18
([WHUQDO*UDSKLFV
REV:B *0&+,QWHJUDWHG*UDSKLFV'LVDEOH
63#,17XVH8
EV@ (;7XVHRKP
,9 (9'LV(QDEOHVHWWLQJ VCCSYNC_CRT GND
1210 10UH, 10% R429 IV@BLM18PG181SN1D_6 +3V_A_DAC_BG
SP@ 0.45A DCR_max = 0.39 63#,17XVH8
C651 C647 C653 9 VCCA_CRT_DAC GND
(;7XVHRKP 1.05V
D
L51 IV@10uh_8 IV@0.1U/10V_4 SP@0.01U/25V_4 IV@10U/6.3V_8
P$ FSB-1067
VCCD_LVDS GND D
+1.05V
U20H 852mA VCC_TX_LVDS GND
5/12 UMA no stuff + C644 C333 U13 VCCA_LVDS GND
VTT_1 +1.05V
T13
VTT_2
9 SP@0.1U/10V_4 B27
VCCA_CRT_DAC_1 VTT_3
U12 VCCA_TVDAC GND
9
EV@220U/6.3V_7343 A26 T12 C374 C362 C361 C360 + C619
P$IRU'3//B$% ESR=15 m VCCA_CRT_DAC_2 VTT_4
VTT_5
U11 VCCD_QDAC GND
P$ A25 VTT_6
T11
U10
0.47U/6.3V_4 2.2U/6.3V_6 4.7U/6.3V_6 4.7U/6.3V_6 330U/2V_7343
VCCA_DAC_BG GND
CRT
B25 VCCA_DAC_BG VTT_7 T10
VSSA_DAC_BG VTT_8 ESR= 12m ohm
VCCA_DPLLA/B always keep to +1.05V USE same GND plane U9 VCC_AXG GND
VTT_9 T9
1210 10UH, 10% (If no use IV dynamic core power) VTT_10 U8 VCC_AXG_NCTF GND
0.45A DCR_max = 0.39 VTT_11
+1.05VM_DPLLA F47 T8
VCCA_DPLLA VTT_12 U7
VTT
L49 IV@10uh_8 +1.05VM_DPLLB L48 VTT_13 T7
+1.05V VCCA_DPLLB VTT_14 U6
+ C638 C635 +1.05VM_HPLL AD1 VTT_15 T6
PLL
VCCA_HPLL VTT_16 U5
IV@220U/6.3V_7343 SP@0.1U/10V_4 +1.05VM_MPLL AE1 VTT_17 T5
VCCA_MPLL VTT_18 V3
ESR=15 m VTT_19
9 +1.8VSUS_TXLVDS
J48 VTT_20
U3
V2
Check list : 0.1UH
1.05V VCCA_LVDS VTT_21 CRB : 0 ohm
P$ C637 U2
A LVDS
24mA J47 VTT_22 T2 1210 0.1 ?H, 20% 1A
1.5V VSSA_LVDS VTT_23 DCR max = 78 m
R397 *0/short_6 SP@1000P/50V_4 V1 1.05V
+1.05V 414uA VTT_24 U1
C616 C611 VTT_25 321.35mA
+1.5V R388 *0/short_8 +VCCA_PEG_BG AD48 +1.05VM_AXF L52 *0/short_8 +1.05V
4.7U/6.3V_6 0.1U/10V_4 VCCA_PEG_BG
C610 1.05V C646 C652
1.05V 1.05V
A PEG
0.1U/10V_4 50mA 1U/6.3V_4 *10U/10V_8 1.8V
139.2mA 3.9 nH, 0.2 nH, 1A DDR2-800 +1.05VM_PEGPLL AA48 0805 1UH , Rdc = 0.14 - 0.26.
L48 BLM18PG181SN1D_6 VCCA_PEG_PLL DDR2-800
, DCR_max=32 m 720mA VCCA_PEG_PLL ESR = 60 m Max rated current = 220 mA
+1.25V for Teenah use(100mA) AR20 4/15 Modify
124mA
1210 0.1uH, 20%, 1A, R233 *0/short_6 +1.05VM_A_SM
C +1.05V
AP20 VCCA_SM_1 +1.5VSUS_VCC_SM_CK L44 1uh_8
DDR3 +1.5V_SUS C
DCR_max=0.078ȍ VCCA_SM_2 +1.5V_SUS
C409 C412 C402 AN20 DDR2 +1.8V_SUS
+1.05VM_MPLL_RC R393 0.5/F_6
22U/6.3V_8 4.7U/6.3V_6 1U/6.3V_4
AR17
AP17
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
POWER C575
1/F_4 R341 +1.5VSUS_SMCK_RC C570 10U/6.3V_8
AN17 0.1U/10V_4 4/15 Modify
C615 C609 AT16 VCCA_SM_6
AR16 VCCA_SM_7
A SM
22U/6.3V_8 0.1U/10V_4 AP16 VCCA_SM_8
VCCA_SM_9
,9 (9'LV(QDEOHVHWWLQJ 1.8V 0805 100 nH, DCR=160 m
1.05V 118.8mA
3.3V DDR2-800 +1.8VSUS_TXLVDS L50 IV@0.1uh_6 +1.8V
24.15mA for VCCA_TVA_DAC 26mA
39.48mA for VCCA_TVB_DAC +1.05V R231 *0/short_6 +1.05VM_A_SM_CK AP28 63#,17XVHSI C639 C643
AN28 VCCA_SM_CK_1 B22
24.15mA for VCCA_TVC_DAC
CRB : 0 ohm C408 C406 C405 AP25 VCCA_SM_CK_2 VCC_AXF_1 B21 (;7XVHRKP SP@1000P/50V_4 IV@22U/6.3V_8
AXF
Total 87.78mA AN25 VCCA_SM_CK_3 VCC_AXF_2 A21
Check list : 2.2nH AN24 VCCA_SM_CK_4 VCC_AXF_3
*2.2U/6.3V_6 22U/6.3V_8 0.1U/10V_4
AM28 VCCA_SM_CK_5
AM26 VCCA_SM_CK_NCTF_1
FB 180@100 MHz, 25% 1.5A 3.3V
A CK
AM25 VCCA_SM_CK_NCTF_2
DCR_max=90 m 79mA VCCA_SM_CK_NCTF_3
,9 (9'LV(QDEOHVHWWLQJ
AL25 BF21
L53 IV@BKP1608HS181-T_6 AM24 VCCA_SM_CK_NCTF_4 VCC_SM_CK_1 BH20 3.3V
SM CK
+3V VCCA_SM_CK_NCTF_5 VCC_SM_CK_2 +3V
AL24 BG20
VCCA_SM_CK_NCTF_6 VCC_SM_CK_3 105.3mA
63#,17XVH8 AM23
VCCA_SM_CK_NCTF_7 VCC_SM_CK_4
BF20
C666 C650 C648 C663 C654 AL23 R176 10_4 +1.05V_SD D9 1 2 CH751
(;7XVHRKP VCCA_SM_CK_NCTF_8 +1.05V
IV@10U/6.3V_8 IV@0.1U/10V_4 SP@0.01U/25V_4 *IV@10U/6.3V_8 *IV@10U/6.3V_8 C320
K47
+3V_CRT_TV_DAC B24 VCC_TX_LVDS 0.1U/10V_4
4/21 add A24 VCCA_TV_DAC_1 C35
CRB no 10U VCCA_TV_DAC_2 VCC_HV_1
TV
1.5V B35
Check list need min 10U~100U for VCCA_TV_DAC VCC_HV_2
63#,17XVH8 A35 1.05V
HV
50mA VCC_HV_3 +1.05V
R173 IV@0_6 (;7XVHRKP +VCC_HDA A32 1782mA
+1.5V VCC_HDA
HDA
V48
B
C319 +1.5V_TVDAC VCC_PEG_1 U48 B
VCC_PEG_2 V47
PEG
SP@0.1U/10V_4 VCC_PEG_3 U47 C604 C605 + C625
VCC_PEG_4
D TV/CRT
VCCD_QDAC share to TV and CRT M25 U46 1.05V
VCCD_TVDAC VCC_PEG_5 4.7U/6.3V_6 22U/6.3V_8 EV@220U/6.3V_7343
VCCD_TVDAC always keep 0.1U/0.022U/10U to +1.5V +1.5V_QDAC L28 456mA
VCCD_QDAC AH48
1.5V VCC_DMI_1
R396 *0/short_6 +1.05VM_MCH_PLL2 AF1 AF48
35mA +1.05V VCCD_HPLL VCC_DMI_2 AH47 C603
5/12 UMA no stuff
DMI
R175 *0/short_6 C606 +1.05VM_PEGPLL AA47 VCC_DMI_3 AG47
+1.5V 1.05V VCCD_PEG_PLL VCC_DMI_4 0.1U/10V_4
C327 C335 157.2mA 0.1U/10V_4
M38
VCCD_LVDS_1
LVDS
1.5V 0.1U/10V_4 0.01U/25V_4 L37 A8
VCCD_LVDS_2 VTTLF1 L1
48.363mA for CRT VTTLF2
VTTLF
AB2 1.05V
VTTLF3
5mA for TV FB 180@100 MHz, 25% 1.5A
DCR_max=90 m 1.5V C617 C634 C321 Internal connect to power
0.5mA CANTIGA_PM 0.47U/6.3V_4 0.47U/6.3V_4 0.47U/6.3V_4
L32 BKP1608HS181-T_6
C308
C345 C347
10U/6.3V_8
CRB no 10U 0.1U/10V_4 0.01U/25V_4
Check list need min 10U~100U
Power Net Name Cantiga(V)
for VCCA_QDAC
VCC_AXG_# 1.05V
VCC_AXG_NCTF_#
VCCA_PEG_BG 1.5V
FB 220 @100 MHz, 25%, 2A 1.05V
VCCA_DPLLA 1.05V
50mA
A +1.05V L47 BKP1608HS181-T_6 VCCA_DPLLB 1.05V A
C614 C613 VCCA_SM_# 1.05V

0.1U/10V_4 0.1U/10V_4 VCCA_HPLL 1.05V
+1.05VM_PEGPLL_RC R392 1/F_4 ,9 (9'LV(QDEOHVHWWLQJ VCCA_MPLL 1.05V
+1.8V R202 IV@0_6 +1.8VSUS_DLVDS
C618 VCCA_SM_CK_# 1.05V
1.8V
63#,17XVH8
352-(&7=4
10U/6.3V_8 C348 VCCA_PEG_PLL 1.05V
60.31mA
(;7XVHRKP
4XDQWD&RPSXWHU,QF
ESR=60m ohm SP@1U/6.3V_4 VCC_AXF_# 1.05V
*0&+&$17,*$
VCCD_HPLL 1.05V
VCCD_PEG_PLL 1.05V 1A
GMCH POWER
5 4 3 2 1
5 4 3 2 1
AU48
AR48
AL48
BB47
U20I
VSS_1
VSS_2
VSS_3
VSS_100
VSS_101
VSS_102
AM36
AE36
P36
L36
BG21
L12
AW 21
AU21
AP21
U20J
VSS_199
VSS_200
VSS_201
VSS_202
VSS_297
VSS_298
VSS_299
VSS_300
AH8
Y8
L8
E8
B8
11
AW 47 VSS_4 VSS_103 J36 AN21 VSS_203 VSS_301 AY7
AN47 VSS_5 VSS_104 F36 AH21 VSS_204 VSS_302 AU7
AJ47 VSS_6 VSS_105 B36 AF21 VSS_205 VSS_303 AN7
AF47 VSS_7 VSS_106 AH35 AB21 VSS_206 VSS_304 AJ7
AD47 VSS_8 VSS_107 AA35 R21 VSS_207 VSS_305 AE7
D
AB47 VSS_9 VSS_108 Y35 M21 VSS_208 VSS_306 AA7 D
Y47 VSS_10 VSS_109 U35 J21 VSS_209 VSS_307 N7
T47 VSS_11 VSS_110 T35 G21 VSS_210 VSS_308 J7
N47 VSS_12 VSS_111 BF34 BC20 VSS_211 VSS_309 BG6
L47 VSS_13 VSS_112 AM34 BA20 VSS_212 VSS_310 BD6
G47 VSS_14 VSS_113 AJ34 AW 20 VSS_213 VSS_311 AV6
BD46 VSS_15 VSS_114 AF34 AT20 VSS_214 VSS_312 AT6
BA46 VSS_16 VSS_115 AE34 AJ20 VSS_215 VSS_313 AM6
AY46 VSS_17 VSS_116 W 34 AG20 VSS_216 VSS_314 M6
AV46 VSS_18 VSS_117 B34 Y20 VSS_217 VSS_315 C6
AR46 VSS_19 VSS_118 A34 N20 VSS_218 VSS_316 BA5
AM46 VSS_20 VSS_119 BG33 K20 VSS_219 VSS_317 AH5
V46 VSS_21 VSS_120 BC33 F20 VSS_220 VSS_318 AD5
R46 VSS_22 VSS_121 BA33 C20 VSS_221 VSS_319 Y5
P46 VSS_23 VSS_122 AV33 A20 VSS_222 VSS_320 L5
H46 VSS_24 VSS_123 AR33 BG19 VSS_223 VSS_321 J5
F46 VSS_25 VSS_124 AL33 A18 VSS_224 VSS_322 H5
BF44 VSS_26 VSS_125 AH33 BG17 VSS_225 VSS_323 F5
AH44 VSS_27 VSS_126 AB33 BC17 VSS_226 VSS_324 BE4
AD44 VSS_28 VSS_127 P33 AW 17 VSS_227 VSS_325
AA44 VSS_29 VSS_128 L33 AT17 VSS_228 BC3
Y44
U44
VSS_30
VSS_31
VSS_32
VSS_129
VSS_130
VSS_131
H33
N32
R17
M17
VSS_229
VSS_230
VSS_231
VSS VSS_327
VSS_328
VSS_329
AV3
AL3
T44 K32 H17 R3
M44
F44
VSS_33
VSS_34
VSS_35
VSS VSS_132
VSS_133
VSS_134
F32
C32
C17 VSS_232
VSS_233
VSS_330
VSS_331
VSS_332
P3
F3
BC43 A31 BA16 BA2
AV43 VSS_36 VSS_135 AN29 VSS_235 VSS_333 AW 2
AU43 VSS_37 VSS_136 T29 AU16 VSS_334 AU2
AM43 VSS_38 VSS_137 N29 AN16 VSS_237 VSS_335 AR2
C C
J43 VSS_39 VSS_138 K29 N16 VSS_238 VSS_336 AP2
C43 VSS_40 VSS_139 H29 K16 VSS_239 VSS_337 AJ2
BG42 VSS_41 VSS_140 F29 G16 VSS_240 VSS_338 AH2
AY42 VSS_42 VSS_141 A29 E16 VSS_241 VSS_339 AF2
AT42 VSS_43 VSS_142 BG28 BG15 VSS_242 VSS_340 AE2
AN42 VSS_44 VSS_143 BD28 AC15 VSS_243 VSS_341 AD2
AJ42 VSS_45 VSS_144 BA28 W 15 VSS_244 VSS_342 AC2
AE42 VSS_46 VSS_145 AV28 A15 VSS_245 VSS_343 Y2
N42 VSS_47 VSS_146 AT28 BG14 VSS_246 VSS_344 M2
L42 VSS_48 VSS_147 AR28 AA14 VSS_247 VSS_345 K2
BD41 VSS_49 VSS_148 AJ28 C14 VSS_248 VSS_346 AM1
AU41 VSS_50 VSS_149 AG28 BG13 VSS_249 VSS_347 AA1
AM41 VSS_51 VSS_150 AE28 BC13 VSS_250 VSS_348 P1
AH41 VSS_52 VSS_151 AB28 BA13 VSS_251 VSS_349 H1
AD41 VSS_53 VSS_152 Y28 VSS_252 VSS_350
AA41 VSS_54 VSS_153 P28 U24
Y41 VSS_55 VSS_154 K28 AN13 VSS_351 U28
U41 VSS_56 VSS_155 H28 AJ13 VSS_255 VSS_352 U25
T41 VSS_57 VSS_156 F28 AE13 VSS_256 VSS_353 U29
M41 VSS_58 VSS_157 C28 N13 VSS_257 VSS_354 AJ6
G41 VSS_59 VSS_158 BF26 L13 VSS_258 VSS_355
B41 VSS_60 VSS_159 AH26 G13 VSS_259 AF32
BG40 VSS_61 VSS_160 AF26 E13 VSS_260 VSS_NCTF_1 AB32
BB40 VSS_62 VSS_161 AB26 BF12 VSS_261 VSS_NCTF_2 V32
AV40 VSS_63 VSS_162 AA26 AV12 VSS_262 VSS_NCTF_3 AJ30
AN40 VSS_64 VSS_163 C26 AT12 VSS_263 VSS_NCTF_4 AM29
H40 VSS_65 VSS_164 B26 AM12 VSS_264 VSS_NCTF_5 AF29
E40 VSS_66 VSS_165 BH25 AA12 VSS_265 VSS_NCTF_6 AB29
VSS NCTF
AT39 VSS_67 VSS_166 BD25 J12 VSS_266 VSS_NCTF_7 U26
B
AM39 VSS_68 VSS_167 BB25 A12 VSS_267 VSS_NCTF_8 U23 B
AJ39 VSS_69 VSS_168 AV25 BD11 VSS_268 VSS_NCTF_9 AL20
AE39 VSS_70 VSS_169 AR25 BB11 VSS_269 VSS_NCTF_10 V20
N39 VSS_71 VSS_170 AJ25 AY11 VSS_270 VSS_NCTF_11 AC19
L39 VSS_72 VSS_171 AC25 AN11 VSS_271 VSS_NCTF_12 AL17
B39 VSS_73 VSS_172 Y25 AH11 VSS_272 VSS_NCTF_13 AJ17
BH38 VSS_74 VSS_173 N25 VSS_273 VSS_NCTF_14 AA17
BC38 VSS_75 VSS_174 L25 Y11 VSS_NCTF_15 U17
BA38 VSS_76 VSS_175 J25 N11 VSS_275 VSS_NCTF_16
AU38 VSS_77 VSS_176 G25 G11 VSS_276 BH48
AH38 VSS_78 VSS_177 E25 C11 VSS_277 VSS_SCB_1 BH1
VSS SCB
AD38 VSS_79 VSS_178 BF24 BG10 VSS_278 VSS_SCB_2 A48
AA38 VSS_80 VSS_179 AD12 AV10 VSS_279 VSS_SCB_3 C1
Y38 VSS_81 VSS_180 AY24 AT10 VSS_280 VSS_SCB_4
U38 VSS_82 VSS_181 AT24 AJ10 VSS_281 A3
T38 VSS_83 VSS_182 AJ24 AE10 VSS_282 VSS_SCB_6
J38 VSS_84 VSS_183 AH24 AA10 VSS_283 E1
F38 VSS_85 VSS_184 AF24 M10 VSS_284 NC_26 D2
C38 VSS_86 VSS_185 AB24 BF9 VSS_285 NC_27 C3
BF37 VSS_87 VSS_186 R24 BC9 VSS_286 NC_28 B4
BB37 VSS_88 VSS_187 L24 AN9 VSS_287 NC_29 A5
AW 37 VSS_89 VSS_188 K24 AM9 VSS_288 NC_30 A6
AT37 VSS_90 VSS_189 J24 AD9 VSS_289 NC_31 A43
AN37 VSS_91 VSS_190 G24 G9 VSS_290 NC_32 A44
AJ37 VSS_92 VSS_191 F24 B9 VSS_291 NC_33 B45
NC
H37 VSS_93 VSS_192 E24 BH8 VSS_292 NC_34 C46
C37 VSS_94 VSS_193 BH23 BB8 VSS_293 NC_35 D47
BG36 VSS_95 VSS_194 AG23 AV8 VSS_294 NC_36 B47
BD36 VSS_96 VSS_195 Y23 AT8 VSS_295 NC_37 A46
AK15 VSS_97 VSS_196 B23 VSS_296 NC_38 F48
A A
AU36 VSS_98 VSS_197 A23 NC_39 E48
VSS_99 VSS_198 NC_40 C48
NC_41 B48
CANTIGA_PM NC_42 A47
NC_43
352-(&7=4
CANTIGA_PM
4XDQWD&RPSXWHU,QF
*0&+&$17,*$ Size
Date:
Document Number
GMCH VSS
Rev
1A
43
5 4 3 2 1
5 4 3 2 1
ICH9M
C594 15P/50V_4
12
2
1
Y3 R363
IV@ 32.768KHZ 10M_6
CLK_32KX1 C23
U23A
K5
RTCX1 FW H0/LAD0 LAD0 28,35
CLK_32KX2 C24 K4
EV@ LAD1 28,35
3
4
C593 15P/50V_4 RTCX2 FW H1/LAD1 L6 Intel ICH9M
FW H2/LAD2 LAD2 28,35 +1.05V
AJSLB8Q0T03
RTC_RST# A25 K2
RTCRST# FW H3/LAD3 LAD3 28,35
RTC
LPC
SRTC_RST# F20
R379 1M/F_6 SM_INTRUDER# C22 SRTCRST# K3
+VCCRTC INTRUDER# FW H4/LFRAME# LFRAME# 28,35
R364 330K/F_4 ICH_INTVRMEN B22 J3 T38 LDRQ0/1# : Internal PU Layout note:
D
R355 330K/F_4 LAN100_SLP A22 INTVRMEN LDRQ0# J1 R443 R406 +1.05V D
LAN100_SLP LDRQ1#/GPIO23 T122 DPRSTP# , Daisy Chain
R211 8.2K_4 +3V *56_4 *56_4
E25 N7 (SB>Power>NB>CPU)
GLAN_CLK A20GATE GATEA20 35
,QWHUQDO950HQDEOHGIRU A20M#
AJ27
H_A20M# 3
C13 R442
9FF6XVB9FF6XVB LAN_RSTSYNC AJ25 56_4
9FF&/B9FF/$1BDQG F14 DPRSTP# AE23
ICH_DPRSTP# 3,6,39
LAN / GLAN
LAN_RXD0 DPSLP# H_DPSLP# 3
9FF&/B G13
LAN_RXD1
D14 AJ26 H_FERR#_R R463 56_4
LAN_RXD2 FERR# H_FERR# 3
24.9 Ohm pull up to 1.5V D13 AD22
for GLAN_COMPI/O is LAN_TXD0 CPUPW RGD H_PWRGD 3
D12
required, no matter intel +3V_S5 E13 LAN_TXD1 AF25
LAN_TXD2 IGNNE# H_IGNNE# 3
CPU
LAN is used or not.
R378 10K_4 ICH_GPIO56 B10 AE22
GLAN_DOCK#/GPIO56 INIT# H_INIT# 3
AG25
INTR H_INTR 3
+1.5V R382 24.9/F_4 B28 L3 R219 10K_4 +3V
B27 GLAN_COMPI RCIN#
GLAN_COMPO RCIN# 35
AF23
NMI H_NMI 3
HDA_BIT_CLK_R AF6 AF24
HDA_BIT_CLK SMI# H_SMI# 3
Internal pull-down HDA_SYNC_R AH4
HDA_SYNC AH27 R430 56_4
resistors that are AE7 STPCLK# H_STPCLK# 3 +1.05V
HDA_RST#_R
always enabled HDA_RST# AG26 H_THERMTRIP_R R421 54.9/F_4 H_THERMTRIP_RR R420 *0_4
THRMTRIP# PM_THRMTRIP# 3,6
AF4
29 ACZ_SDIN0 HDA_SDIN0
AG4 AG27 T22
4/21 Modify andy
AH3 HDA_SDIN1 TP8
IHDA
HDA_SDIN2 No use Thermal trip SB side still PU 56ohm.(Serial R use 0ohm)
AE5 HDA_SDIN2
HDA_SDIN3 AH11
Use Thermal trip can share PU for CPU and SB side(And Serial R use 54.9 ohm)
SATA4RXN SATA_RXN0 27 PU L<2"
C HDA_SDOUT_R AG5 AJ11 C
HDA_SDOUT SATA4RXP SATA_RXP0 27
AG12 SATA_TXN0_C C661 0.01u/16V_4
SATA4TXN SATA_TXN0 27
T23 AG7 AF12 SATA_TXP0_C C660 0.01u/16V_4
HDA_DOCK_EN#/GPIO33 SATA4TXP SATA_TXP0 27
T24
AE8
HDA_DOCK_RST#/GPIO34 AH9
AG8 SATA5RXN AJ9
27 SATA_LED# SATALED# SATA5RXP AE10 SATA HDD
AJ16 SATA5TXN AF10
27 SATA_RXN1 SATA0RXN SATA5TXP
AH16
SATA
27 SATA_RXP1 SATA0RXP
ODD (SATA) C659 0.01u/16V_4 SATA_TXN1_C AF17 AH18
27 SATA_TXN1 SATA0TXN SATA_CLKN CLK_PCIE_SATA# 2
C658 0.01u/16V_4 SATA_TXP1_C AG17 AJ18
27 SATA_TXP1 SATA0TXP SATA_CLKP CLK_PCIE_SATA 2
AH13 AJ7 SATA_RBIAS_PN
AJ13 SATA1RXN SATARBIAS# AH7
AG14 SATA1RXP SATARBIAS
AF14 SATA1TXN R170
SATA1TXP SATABIAS L<0.5"
ICH9MREV1.0 24.9/F_4
HD Audio R470 IV@33_4

RTC
HDA_BIT_CLK_HDMI 6
R471 IV@33_4
HDA_SDOUT_HDMI 6 Pjt: BCBAT54CZ04
HDA_BIT_CLK_R R477 33_4 Ons: BCBAT54CZ70
ACZ_BITCLK_AUDIO 29 +3VPCU +VCCRTC
HDA_SDOUT_R R478 33_4 20MIL
ACZ_SDOUT_AUDIO 29
24.000 MHz is output from the ICH9M. C668 C664 D28
B B
Weak integrated PD on the HDA_SDOUT pin. C671
*10P/50V_4 *10P/50V_4 R489 20K_6 SRTC_RST#
*10P/50V_4 VCCRTC_1
1
C667 G2
20MIL BAT54C
C675 1U/10V_4 *SHORT_PAD
2
R472 IV@33_4 R473 IV@33_4 R495 1U/10V_4
HDA_SYNC_HDMI 6 HDA_RST#_HDMI 6
HDA_SYNC_R R479 33_4 HDA_RST#_R R483 33_4 1K_4
ACZ_SYNC_AUDIO 29 ACZ_RST#_AUDIO 29
R497 20K_6 RTC_RST#
Weak integrated PD on the HDA_SYNC pins C672
1
C699 G3
*10P/50V_4
HDA_SDIN2 R166 IV@0_4 1 3 RTC_N01 R480 *16K_6 1U/10V_4 *SHORT_PAD
HDA_SDIN_HDMI 6 +5VPCU
VCCRTC_2
2
Q21 R481
20MIL
South Bridge Strap Pin (1/3) *MMBT3904 *68.1K/F_4
RTC_RST#
2
RTC_N03
3
Pin Name Strap description Sampled Configuration PU/PD
CN13
1 R482
0 = The Flash Descriptor Security will be overridden. 2 1 2
HDA_DOCK_EN/ Flash Descriptor Security This strap should only be enabled in manufacturing 35 RTC_EC
PWROK 1 = The security measures defined 2 *150K/F_6
GPIO33 Override Strap environments using an external pull-up resistor.
in the Flash Descriptor will be in effect RTC_CONN
Pitch: 1,25mm; Height: 1.95mm
Q22
1
A PCI Express Lane Reversal Change type 4/21 (ZQ7) DMN601K-7 A
SATALED# PWROK Internal PU
(Lanes 1-4)
ICH_TP3 HDA_SDOUT Description

TP3 XOR Chain Entrance
352-(&7=4
PWROK 14 ICH_TP3
ICH_TP3 R370 *1K_4
0 0 RSVD
0 1 Enter XOR Chain 4XDQWD&RPSXWHU,QF
XOR Chain Entrance /PCI Express*
HDA_SDOUT Port Config 1 bit 1(Port 1-4) PWROK 1 0 Normal opration(Default) HDA_SDOUT_R R440 *1K_4 +3V Size Document Number Rev
1A
1 1 Set PCIE port config bit 1
ICH9M HOST
5 4 3 2 1
5 4 3 2 1
ICH9M
N29
U23D
PERN1 DMI0RXN
V27
DMI_RXN0 6
13
Direct Media Interface

U23B N28 V26
PERP1 DMI0RXP DMI_RXP0 6
D11 F1 REQ0# T111 P27 U29
AD0 REQ0# PETN1 DMI0TXN DMI_TXN0 6
C8 G4 GNT0# P26 U28
D9 AD1 PCI GNT0# B6 REQ1#
T40 PETP1 DMI0TXP DMI_TXP0 6
AD2 REQ1#/GPIO50 T100
E12 A7 GNT1# L29 Y27
AD3 GNT1#/GPIO51 T107 PERN2 DMI1RXN DMI_RXN1 6
E9 F13 REQ2# T102 L28 Y26
AD4 REQ2#/GPIO52 PERP2 DMI1RXP DMI_RXP1 6
C9 F12 GNT2# T103 M27 W29
AD5 GNT2#/GPIO53 PETN2 DMI1TXN DMI_TXN1 6
E10 E6 REQ3# M26 W28
AD6 REQ3#/GPIO54 T104 PETP2 DMI1TXP DMI_TXP1 6
B7 F6 GNT3#
AD7 GNT3#/GPIO55 T41
D C7 J29 AB27 D
AD8 PERN3 DMI2RXN DMI_RXN2 6
C5 D8 J28 AB26
PCI-Express
AD9 C/BE0# PERP3 DMI2RXP DMI_RXP2 6
G11 B4 K27 AA29
AD10 C/BE1# PETN3 DMI2TXN DMI_TXN2 6
F8 D6 K26 AA28
AD11 C/BE2# PETP3 DMI2TXP DMI_TXP2 6
F11 A5
E7 AD12 C/BE3# G29 AD27
AD13 28 PCIE_RXN4 PERN4 DMI3RXN DMI_RXN3 6
A3 D3 IRDY# T113 G28 AD26
AD14 IRDY# 28 PCIE_RXP4 PERP4 DMI3RXP DMI_RXP3 6
D2 E3 WLAN C385 0.1U/10V_4 PCIE_TXN4_C H27 AC29
AD15 PAR 28 PCIE_TXN4 PETN4 DMI3TXN DMI_TXN3 6
F10 R1 PCIRST# C386 0.1U/10V_4 PCIE_TXP4_C H26 AC28
AD16 PCIRST# PCIRST# 28 28 PCIE_TXP4 PETP4 DMI3TXP DMI_TXP3 6
D5 C6 DEVSEL#
AD17 DEVSEL# T109
D10 E4 PERR# E29 T26
AD18 PERR# T114 PERN5 DMI_CLKN CLK_PCIE_ICH# 2
B3 C2 LOCK# T110 E28 T25
AD19 PLOCK# PERP5 DMI_CLKP CLK_PCIE_ICH 2
F7 J4 SERR# T120 F27
C3 AD20 SERR# A4 STOP# F26 PETN5 AF29
AD21 STOP# T105 PETP5 DMI_ZCOMP
F3 F5 TRDY# AF28 DMI_IRCOMP_R R409 24.9/F_4
AD22 TRDY# T117 DMI_IRCOMP +1.5V
F4 D7 FRAME# C29
AD23 FRAME# T101 31 GLAN_RXN PERN6/GLAN_RXN
C1 C28 AC5
AD24 31 GLAN_RXP PERP6/GLAN_RXP USBP0N USBP0- 28
G7 C14 PLT_RST# GLAN C401 0.1U/10V_4 GLAN_TXN_SB D27 AC4 EXT-USB
AD25 PLTRST# PLT_RST# 6 31 GLAN_TXN PETN6/GLAN_TXN USBP0P USBP0+ 28
H7 D4 C398 0.1U/10V_4 GLAN_TXP_SB D26 AD3
AD26 PCICLK PCLK_ICH 2 31 GLAN_TXP PETP6/GLAN_TXP USBP1N USBP1- 33
D1 R2 AD2 CardReader
G5 AD27 PME# D23 USBP1P AC1 USBP1+ 33
T48 SPI_CLK_R
AD28 SPI_CLK USBP2N USBP2- 28
H6 T50 SPI_CS0#_R D24 AC2 USBP2+ 28 EXT-USB
G1 AD29 SPI_CS1# F23 SPI_CS0# USBP2P AA5
AD30
PME# internal PU 18K~42K SPI_CS1#/GPIO58/CLGPIO6 USBP3N USBP3- 28
H3 AA4 Bluetooth 3.0
AD31 USBP3P USBP3+ 28
SPI_MOSI D25 AB2
SPI_MOSI USBP4N USBP4- 28
SPI
SPI_MISO E23 AB3 Wireless
INTA# J5
Interrupt I/F H4 INTE#
T51 SPI_MISO USBP4P AA1
USBP4+ 28
T116 PIRQA# PIRQE#/GPIO2 T121 USBP5N
T115 INTB# E1 K6 INTF# T123 USBOC#0 N4 AA2
INTC# J6 PIRQB# PIRQF#/GPIO3 F2 INTG# USBOC#1 N5 OC0#/GPIO59 USBP5P W5
T124 PIRQC# PIRQG#/GPIO4 T118 OC1#/GPIO40 USBP6N USBP6- 28
INTD# C4 G2 INTH# 4/22 add it USBOC#2 N6 W4 INT-USB
T106 PIRQD# PIRQH#/GPIO5 T119
USBOC#3 P6 OC2#/GPIO41 USB USBP6P Y3 USBP6+ 28
OC3#/GPIO42 USBP7N USBP7- 28
ICH9MREV1.0 USBOC#4 M1 Y2 Bluetooth 2.1
USBOC#5 N2 OC4#/GPIO43 USBP7P W1
USBP7+ 28 6/14 Modify
C
USBOC#6 M4 OC5#/GPIO29 USBP8N W2 C
28 USBOC#6 OC6#/GPIO30 USBP8P
USBOC#7 M3 V2
USBOC#8 N3 OC7#/GPIO31 USBP9N V3
USBOC#9 N1 OC8#/GPIO44 USBP9P U5
For EMI OC9#/GPIO45 USBP10N
USBOC#10 P5 U4
28 USBOC#10 OC10#/GPIO46 USBP10P
PCLK_ICH C579 *33p/50V_4 USBOC#11 P3 U1
OC11#/GPIO47 USBP11N USBP11- 25
U2 CAMERA
AG2 USBP11P USBP11+ 25
5/12 Add SB_USBBIAS
AG1 USBRBIAS
USBRBIAS#
4/26 add it
ICH9MREV1.0
R172
22.6/F_4
L<0.5",Avoid routing next to clock/high speed signals.
+3V
South Bridge Strap Pin (2/3)

C400
0.1U/10V_4
5
PCI Express Port 0 = Default

PLT_RST# 2 HDA_SYNC PWROK
+3V 4 Config 1 bit 0 (Port 1-4) 1 = Setting bit 0
RN16 PLTRST# 28,31,33,35
1
B LOCK# 6 5 B
INTD# 7 4 REQ2# U19 R354 PCI Express Port 0 = Setting bit 2
3
REQ3# 8 3 FRAME# GNT2# / GPIO53 PWROK

DEVSEL# 9 2 REQ1# TC7SH08FU 100K_4 Config 2 bit 2 (Port 5-6) 1 = Default
10 1 STOP#
+3V
8.2K_10P8R ESI Strap(Server Only) 0 = DMI for ESI-compatible
GNT1# / GPIO51 PWROK
1 = Default
+3V
RN18 RN19
INTF# 6 5 USBOC#0 6 5 +3V_S5 0 = "top-block swap" mode
INTC# 7 4 USBOC#6 7 4 USBOC#1 GNT3# / GPIO55 Top-Block Swap Override PWROK GNT3# R237 *1K_4
INTE# 8 3 USBOC#4 8 3 USBOC#5 1 = Default
SERR# 9 2 INTH# USBOC#7 9 2 USBOC#2
10 1 INTG# 10 1 USBOC#3
+3V +3V_S5
SPI_MOSI Integrated TPM Enable 0 = INT TPM disable(Default) SPI_MOSI
8.2K_10P8R CLPWROK R380 *10K_4 +3V_S5
10K_10P8R 1 = INT TPM enable
+3V
RN17 Boot Location
PCI_GNT#0 SPI_CS#1
PERR# 6 5 RN20 GNT0# Boot BIOS Selection 0 PWROK GNT0# R236 *1K_4
7 4 IRDY# USBOC#10 8 7
+3V_S5
REQ0# 8 3 INTB# USBOC#11 6 5 0 1 SPI
9 2 INTA# USBOC#8 4 3
+3V 10 1 TRDY# USBOC#9 2 1
SPI_CS1# / 1 0 PCI
8.2K_10P8R 10K_8P4R Boot BIOS Selection 1 CLPWROK SPI_CS1# R234 *1K_4
GPIO58 / CLGPIO6
1 1 LPC(Default)
A 5/11 Swap A
5/11 Swap
352-(&7=4
4XDQWD&RPSXWHU,QF
1A
ICH9M PCIE / PCI / USB
5 4 3 2 1
5 4 3 2 1
+3V_S5 4/20 Modify '$$6)LVVXHZKHQL$07LVQRWLPSOHPHQWHG 6$7$>[@*3SLQVLIXQXVHGUHTXLUH
14
,&+060%XVDQG60/LQNVKRXOGEHFRQQHFWHGWRJHWKHUWRVXSSRUWVODYHPRGH NWRNSXOOXSWR9FFBRU
R357 10K_4 SMB_CLK_ME
&RQQHFW60/,1.WR60%&/.DQG60/,1.WR60%'$7$$GG55IRUGHEXJXVH NWRNSXOOGRZQWRJURXQG
R356 10K_4 SMB_DATA_ME
U23C
R366 2.2K_4 PCLK_SMB PCLK_SMB G16 AH23 BOARD_ID2
2,16,28 PCLK_SMB SMBCLK SATA0GP/GPIO21
PDAT_SMB A13 AF19 PANEL_ID0 R181 10K_4
2,16,28 PDAT_SMB SMBDATA SATA1GP/GPIO19
R367 2.2K_4 PDAT_SMB ICH_GPIO60 E17 AE21 ICH_GPIO36 R446 10K_4
SATA
LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36
GPIO
SMB
SMB_CLK_ME C17 AD20 ICH_GPIO37 R408 10K_4
SMLINK0 SATA5GP/GPIO37 +3V
R225 10K_4 RI# 4/20 Modify SMB_DATA_ME B18
SMLINK1 H1 14M_ICH
CLK14 14M_ICH 2
R375 10K_4 ICH_GPIO60 RI# F19 AF3 CLKUSB_48 For EMI
Clocks
RI# CLK48 CLKUSB_48 2
CLKUSB_48
R224 10K_4 SYS_RST# R4 P1
D
T34
SYS_RST# G19 SUS_STAT#/LPCPD# SUSCLK ICH_SUSCLK 35 4/14 Modify 14M_ICH D
3 SYS_RST# SYS_RESET#
R376 10K_4 SMB_ALERT# C16
SLP_S3# SUSB# 6,35
M6 E16
6 PM_SYNC# PMSYNC#/GPIO0 SLP_S4# SUSC# 6,35
R223 10K_4 PCIE_WAKE# G17
SLP_S5# T36
SMB_ALERT# A17
R368 8.2K_4 PM_BATLOW# SMBALERT#/GPIO11 C10 C407 C325
S4_STATE#/GPIO26 T99
PM_STPPCI# A14 *10p/50V_4 *10p/50V_4
2 PM_STPPCI# STP_PCI#
R403 *10K_4 DNBSWON# PM_STPCPU# E19 G20 ICH_PWROK
SYS GPIO
2 PM_STPCPU# STP_CPU# PWROK
PWRBTN : 16 ms of internal debounce
R358 10K_4 ICH_GPIO12 logic on this pin and internal PU 24K CLKRUN# L4 M2
35 CLKRUN# CLKRUN# DPRSLPVR/GPIO16 PM_DPRSLPVR 6,39
Power MGT
R360 10K_4 ICH_GPIO13 PCIE_WAKE# E20 B13 PM_BATLOW#
28,31 PCIE_WAKE# WAKE# BATLOW#
M5 <Checklist ver0.8>
+3V 35 SERIRQ SERIRQ
THERM_ALERT# AJ23 R3 If integrated LAN is not used LAN_RST# tie it to GND.NC serial R from RSMRST#.
3 THERM_ALERT# THRM# PWRBTN# DNBSWON# 35
R218 8.2K_4 CLKRUN# VR_PWRGD_CLKEN D21 D20 PM_LAN_ENABLE_R R372 *0/short_4 If Intel LAN is used with Wake On LAN, tie LAN_RST# to RSMRST# and NC 0ohm.
VRMPWRGD LAN_RST#
R217 10K_4 SERIRQ T54 A20 D22 PM_RSMRST#_R R361 *0_4 PM_RSMRST#_R
TP12 RSMRST#
CL_PWROK must not assert after PWROK asserts for IAMT.
R445 8.2K_4 THERM_ALERT# D26 BAS316 KBSMI#_ICH AG19 R5 CL_PWROK to the NB and SB should be connected to existing PWROK inputs
35 KBSMI# AH21 GPIO1 CK_PWRGD CK_PWRGD 2
D27 BAS316 LID591#_ICH
R359 10K_4 EC_SCI#
25,35 LID591#
AG21 GPIO6 R6 on the NB and SB on a platform with no IAMT
T132 GPIO7 CLPWROK MPWROK 6,35
A21
35 EC_SCI# GPIO8
ICH_GPIO12 C12 B16
Stuff at GEN ICH_GPIO13 C21 LAN_PHY_PWR_CTRL/GPIO12 SLP_M# T53
R390 *10K_4 SATACLKREQ# BOARD_ID0
BOARD_ID1
AE18
K1
ENERGY_DETECT/GPIO13
GPIO17 CL_CLK0
F24
B19
CL_CLK0 6
CL VREF
GPIO18 CL_CLK1 T46 <Checklist ver0.8>
R444 *10K_4 MCH_ICH_SYNC# PANEL_ID1 AF8 VREF1 CRB connect to The ICH9M Controller
BOARD_ID3 AJ22 GPIO20 F22
SCLOCK/GPIO22 CL_DATA0 CL_DATA0 6 +3V_S5 Link 1 VREF circuit is
Controller Link
R439 10K_4 KBSMI#_ICH A9 C19
GPIO
T98 GPIO27 CL_DATA1 T49 Checklist connect to required only if Intel
D19
T45 GPIO28
R448 10K_4 LID591#_ICH SATACLKREQ# L1 C25 CL_VREF0_SB +3V(iAMT reserve) AMT is to be supported.
C 2 SATACLKREQ# SATACLKREQ#/GPIO35 CL_VREF0 C
CR_WAKE# AE19 A19 CL_VREF1_SB
R240 10K_4 PM_STPPCI# ICH_GPIO39 AG22 SLOAD/GPIO38 CL_VREF1
T129 SDATAOUT0/GPIO39
ICH_GPIO48 AF21 F21
T128 SDATAOUT1/GPIO48 CL_RST0# CL_RST#0 6
R221 10K_4 PM_STPCPU# DMI_TERM_SEL AH24 D18
T42 +3V +3V
A8 GPIO49 CL_RST1#
5/7 Modify GPIO57
GPIO57/CLGPIO5 A16 T52
+3V_S5 M7 MEM_LED/GPIO24 C18 ICH_GPIO10 R374 10K_4
29 PCSPK SPKR GPIO10/SUS_PWR_ACK +3V_S5
MCH_ICH_SYNC# AJ24 C11 ICH_GPIO14 R377 10K_4 R353 R256
6 MCH_ICH_SYNC# B21 MCH_SYNC# GPIO14/AC_PRESENT C20
R351 10K_4 TPM Physical ICH_TP3 ICH_GPIO9 R371 10K_4
12 ICH_TP3 TP3 WOL_EN/GPIO9
MISC
GPIO57 Presence for T130 AH20 *3.24K/F_6 3.24K/F_6
TP9
R352 *100/F_4
iTPM. T133 AJ20
TP10 =6'HIDXOWQRW
AJ21 CL_VREF1_SB CL_VREF0_SB
T131 TP11 VXSSRUW,$076RWKLV
ICH9MREV1.0 LQWHUIDFHIROORZ
R449 10K_4 CR_WAKE# &5%&KHFNOLVW38 R373 C584 R255 C436
RQO\
R222 10K_4 ICH_PWROK *453/F_4 *0.1U/10V_4 453/F_4 0.1U/10V_4
Add 4/19
ICH PWROK Resume RST M/B ID
+3V_S5
R369 *10K_4 EC_SCI# PM_RSMRST#_R 3 1 +3V +3V +3V +3V

RSMRST# 35
Q11
R362 MMBT3906
2
B R467 R466 R389 R469 B
+3V +3V_S5 10K_4 R248 4.7K_4 +3V_S5
'(/$<B95B3:5*22'QHHG38.WR9 *10K_4 *10K_4 *10K_4 *10K_4
2
R451 10K_4 PANEL_ID1 C582 *0.1U/10V_4 =638DWSRZHUVLGH D14
4/20 Modify BOARD_ID3 BOARD_ID2 BOARD_ID1 BOARD_ID0
R462 10K_4 ICH_GPIO39 3 BAV99
5
1
DELAY_VR_PWRGOOD 3,6,39
R447 10K_4 ICH_GPIO48 ICH_PWROK 4
2 PWROK_EC R468 R465 R385 R450
PWROK_EC 35
1
U16
3
R333 100K_4 ZD1 INTEL FAE (08/17) 10K_4 10K_4 10K_4 10K_4
2
TC7SH08FU D12
Follow CHECK LIST V1.5 3
"Add RSMRST# isolation (important!!! See
ww22 Santa Rosa MoW)"
BAV99
Default stuff for Teenah(Interposer) chipset
ZS2 Intel FAE suggestion to add for to protect
R238 RTC/CMOS data from corruption when system
1
2.2K_4
encounters an abnormal power down
sequence Board ID ID3 ID2 ID1 ID0
default 0 0 0 0
0 0 0 1
South Bridge Strap Pin (3/3) CLK Enable +3V
0 0 1 0
A
C439 0 0 1 1 A
*0.1U/10V_4
GPIO20 Reserved PWROK U18 0 1 0 0
1 5
2
39 VR_PWRGD_CK410#
0 = Default 3 4 VR_PWRGD_CLKEN
SPKR No Reboot PWROK
352-(&7=4
PCSPK R216 *1K_4 +3V
1 = No Reboot mode
NC7SZ04
4XDQWD&RPSXWHU,QF
R350
0 = for desktop applications 100K_4
DMI Termination 1 = for mobile applications
GPIO49 PWROK DMI_TERM_SEL R464 *1K_4 Size Document Number Rev
Voltage Internal PU ICH9M GPIO 1A

5 4 3 2 1
5 4 3 2 1
ICH9M
Power consumption reference to
Intel ICH9 Family EDS Rev 1.6
15
IV@ 2~3.456v 1.05V
U23E
3.6uA_G3 U23F 1634mA AA26 H5
EV@ +VCCRTC
A23
VCCRTC VCC1_05[01]
A15
B15
+1.05V
AA27
AA3
VSS[001]
VSS[002]
VSS[107]
VSS[108]
J23
J26
C592 C595 A6 VCC1_05[02] C15 C358 C350 AA6 VSS[003] VSS[109] J27
V5REF VCC1_05[03] D15 AB1 VSS[004] VSS[110] AC22
0.1U/10V_4 0.1U/10V_4 AE1 VCC1_05[04] E15 0.1U/10V_4 0.1U/10V_4 AA23 VSS[005] VSS[111] K28
V5REF_SUS VCC1_05[05] 1.5V VSS[006] VSS[112]
5V F15 AB28 K29
CHANGE TO 100OHM & 1UF
AA24 VCC1_05[06] L11 23mA AB29 VSS[007] VSS[113] L13

PER INTEL SUGGESTION:
D
2mA AA25 VCC1_5_B[01] VCC1_05[07] L12 AB4 VSS[008] VSS[114] L15 D
D24 2 1 CH751 SB_V5REF AB24 VCC1_5_B[02] VCC1_05[08] L14 +1.5V_ICH_VCCDMIPLL L46 1uh_6 AB5 VSS[009] VSS[115] L2
+3V VCC1_5_B[03] VCC1_05[09] +1.5V VSS[010] VSS[116]
AB25 L16 AC17 L26
C596 AC24 VCC1_5_B[04] VCC1_05[10] L17 C620 C612 AC26 VSS[011] VSS[117] L27
VCC1_5_B[05] VCC1_05[11] 500 mA, 20% VSS[012] VSS[118]
+5V R365 100_6 5V AC25 L18 AC27 L5
1U/10V_4 AD24 VCC1_5_B[06] VCC1_05[12] M11 0.01U/25V_4 10U/6.3V_8 AC3 VSS[013] VSS[119] L7
S0:2mA AD25 VCC1_5_B[07] VCC1_05[13] M18 AD1 VSS[014] VSS[120] M12
S3/4/5:1mA VCC1_5_B[08] VCC1_05[14] 1.05V VSS[015] VSS[121]
AE25 P11 AD10 M13
D25 2 1 CH751 +5VPCU_ICH_V5REF_SUS AE26 VCC1_5_B[09] VCC1_05[15] P18 50mA AD12 VSS[016] VSS[122] M14
+3V_S5 VCC1_5_B[10] VCC1_05[16] VSS[017] VSS[123]
AE27 T11 AD13 M15
C640 AE28 VCC1_5_B[11] VCC1_05[17] T18 +1.05V_ICH_DMI L34 NBQ160808T-100Y-N AD14 VSS[018] VSS[124] M16
VCC1_5_B[12] VCC1_05[18] +1.05V VSS[019] VSS[125]
R404 100_6 AE29 U11 AD17 M17
+5V_S5 VCC1_5_B[13] VCC1_05[19] VSS[020] VSS[126]
1U/10V_4 F25 U18 C340 C341 5 Ohms @ 100 MHz , 0.7A AD18 M23
CORE
G25 VCC1_5_B[14] VCC1_05[20] V11 AD21 VSS[021] VSS[127] M28
H24 VCC1_5_B[15] VCC1_05[21] V12 4.7U/6.3V_6 22U/6.3V_8 AD28 VSS[022] VSS[128] M29
1.5V H25 VCC1_5_B[16] VCC1_05[22] V14 AD29 VSS[023] VSS[129] N11
330 Ohms@ 100 MHz , 0805 VCC1_5_B[17] VCC1_05[23] VSS[024] VSS[130]
646mA J24 V16 +1.05V AD4 N12
L33 1 2 BLM21PG331SN1D +1.5V_B J25 VCC1_5_B[18] VCC1_05[24] V17 AD5 VSS[025] VSS[131] N13
+1.5V VCC1_5_B[19] VCC1_05[25] 1.05V VSS[026] VSS[132]
K24 V18 AD6 N14
K25 VCC1_5_B[20] VCC1_05[26] 2mA AD7 VSS[027] VSS[133] N15
+ C366 C378 C395 C364 L23 VCC1_5_B[21] R29 AD9 VSS[028] VSS[134] N16
L24 VCC1_5_B[22] VCCDMIPLL C373 C357 C337 AE12 VSS[029] VSS[135] N17
220U/6.3V_7343 22U/6.3V_8 22U/6.3V_8 2.2U/6.3V_6 L25 VCC1_5_B[23] W23 AE13 VSS[030] VSS[136] N18
M24 VCC1_5_B[24] VCC_DMI[1] Y23 0.1U/10V_4 0.1U/10V_4 4.7U/6.3V_6 AE14 VSS[031] VSS[137] N26
M25 VCC1_5_B[25] VCC_DMI[2] AE16 VSS[032] VSS[138] N27
N23 VCC1_5_B[26] AB23 AE17 VSS[033] VSS[139] P12
N24 VCC1_5_B[27] V_CPU_IO[1] AC23 AE2 VSS[034] VSS[140] P13
N25 VCC1_5_B[28] V_CPU_IO[2] AE20 VSS[035] VSS[141] P14
P24 VCC1_5_B[29] AG29 AE24 VSS[036] VSS[142] P15
VCC1_5_B[30] VCC3_3[01] +3V VSS[037] VSS[143]
P25 AE3 P16
VCC1_5_B[31] VSS[038] VSS[144]
VCCA3GP
R24 AJ6 C326 C310 C316 3.3V AE4 P17
R25 VCC1_5_B[32] VCC3_3[02] AE6 VSS[039] VSS[145] P2
R26 VCC1_5_B[33] AC10 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 308mA AE9 VSS[040] VSS[146] P23
R27 VCC1_5_B[34] VCC3_3[07] AF13 VSS[041] VSS[147] P28
T24 VCC1_5_B[35] AD19 AF16 VSS[042] VSS[148] P29
VCC1_5_B[36] VCC3_3[03] VSS[043] VSS[149]
T27
VCC1_5_B[37] VCC3_3[04]
AF20 ,PSDFW,&+09&&+'$DQG AF18
VSS[044] VSS[150]
P4
T28 AG24 AF22 P7
9&&686+'$VXSSO\99
VCCP_CORE
T29 VCC1_5_B[38] VCC3_3[05] AC20 AH26 VSS[045] VSS[151] R11
C C
U24 VCC1_5_B[39] VCC3_3[06] AF26 VSS[046] VSS[152] R12
U25 VCC1_5_B[40] B9 C411 C317 C383 AF27 VSS[047] VSS[153] R13
VCC1_5_B[41] VCC3_3[08] VSS[048] VSS[154]
V24
VCC1_5_B[42] VCC3_3[09]
F9 6XSSRUW,17+'0,+'$ AF5
VSS[049] VSS[155]
R14
V25 G3 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 AF7 R15
U23 VCC1_5_B[43] VCC3_3[10] G6 R458 EV@0_6 +3V 1.5V / 3.3V LQWHUIDFH7KHVHSRZHU AF9 VSS[050] VSS[156] R16
VCC1_5_B[44] VCC3_3[11] VSS[051] VSS[157]
W24
W25 VCC1_5_B[45] VCC3_3[12]
J2
J7 C656 R457 IV@0_6
11mA RQO\VXSSRUW9'HYLFH AG13
AG16 VSS[052] VSS[158]
R17
R18
+1.5V
PXVWWRPHHW
PCI
K23 VCC1_5_B[46] VCC3_3[13] K7 AG18 VSS[053] VSS[159] R28
1.5V Y24 VCC1_5_B[47] VCC3_3[14] 0.1U/10V_4 AG20 VSS[054] VSS[160] T12
47mA Y25 VCC1_5_B[48] AJ4 +3V_HDA_IO_ICH AG23 VSS[055] VSS[161] T13
VCC1_5_B[49] VCCHDA AG3 VSS[056] VSS[162] T14
L54 10uh_8 +1.5V_APLL_ICH AJ19 AJ3 +3V_VCCSUSHDA R459 EV@0_6 AG6 VSS[057] VSS[163] T15
+1.5V VCCSATAPLL VCCSUSHDA +3V_S5 NOTE: VSS[058] VSS[164]
AG9 T16
AC16 AC8
If (G)MCH's HD Audio signals are connected to ICH9M for AH12 VSS[059] VSS[165] T17
C662 C655 TP_VCCSUS1_05_ICH_1 T26 C657 R460 IV@12.1K_4
AD15 VCC1_5_A[01] VCCSUS1_05[1] F17 TP_VCCSUS1_05_ICH_2 iHDMI, VCCHDA and VCCSUSHDA on ICH9M should be AH14 VSS[060] VSS[166] T23
VCC1_5_A[02] VCCSUS1_05[2] T37 VSS[061] VSS[167]
10U/6.3V_8 1U/10V_4 AD16 0.1U/10V_4 R461 only on 1.5V. These power pins on ICH9M can be supplied AH17 B26
VCC1_5_A[03] VSS[062] VSS[168]
ARX
AE15 AD8 TP_VCCSUS1_5_ICH_1 T25 IV@10K_6 1.5V / 3.3V with 3.3V if and only if (G)MCH's HDA is not connected to AH19 U12
AF15 VCC1_5_A[04] VCCSUS1_5[1] AH2 VSS[063] VSS[169] U13
S0:11mA ICH9M. Consequently, only 1.5V audio/modem codecs can
AG15 VCC1_5_A[05] F18 VCCSUS1_5_INT_ICH AH22 VSS[064] VSS[170] U14
VCC1_5_A[06] VCCSUS1_5[2] S3/4/5:1mA VSS[065] VSS[171]
AH15 be used on the platform. AH25 U15
VCC1_5_A AJ15 VCC1_5_A[07] AH28 VSS[066] VSS[172] U16
C397 5/10 change R8382 value to 12.1K
1.5V C313 VCC1_5_A[08] A18 AH5 VSS[067] VSS[173] U17
AC11 VCCSUS3_3[01] D16 0.1U/10V_4 AH8 VSS[068] VSS[174] AD23
1342mA VCCSUS1_05 power by VCC1_05 in S0 / VCCSUS3_3 in S3/S4/S5
VCCPSUS
1U/10V_4 AD11 VCC1_5_A[09] VCCSUS3_3[02] D17 AJ12 VSS[069] VSS[175] U26

AE11 VCC1_5_A[10] VCCSUS3_3[03] E22 VCCSUS1_5 power by VCC1_5_A in S0 / VCCSUS3_3 in S3/S4/S5 AJ14 VSS[070] VSS[176] U27
VCC1_5_A[11] VCCSUS3_3[04] VSS[071] VSS[177]
ATX
AF11 AJ17 U3
AG10 VCC1_5_A[12] AJ8 VSS[072] VSS[178] V1
AG11 VCC1_5_A[13] AF1 B11 VSS[073] VSS[179] V13
VCC1_5_A[14] VCCSUS3_3[05] +3V_S5 VSS[074] VSS[180]
AH10 B14 V15
C331 AJ10 VCC1_5_A[15] T1 B17 VSS[075] VSS[181] V23
VCC1_5_A[16] VCCSUS3_3[06]
3.3V VSS[076] VSS[182]
T2 C343 C349 C352 B2 V28
AC9 VCCSUS3_3[07] T3
S0:212mA B20 VSS[077] VSS[183] V29
1U/10V_4
VCC1_5_A[17] VCCSUS3_3[08] T4 0.022U/16V_4 0.022U/16V_4 0.1U/10V_4 S3/4/5:53mA B23 VSS[078] VSS[184] V4
AC18 VCCSUS3_3[09] T5 B5 VSS[079] VSS[185] V5
AC19 VCC1_5_A[18] VCCSUS3_3[10] T6 B8 VSS[080] VSS[186] W26
VCC1_5_A[19] VCCSUS3_3[11] U6 C26 VSS[081] VSS[187] W27
AC21 VCCSUS3_3[12] U7 C27 VSS[082] VSS[188] W3
VCCPUSB
B VCC1_5_A[20] VCCSUS3_3[13] V6 E11 VSS[083] VSS[189] Y1 B

1.5V G10 VCCSUS3_3[14] V7 E14 VSS[084] VSS[190] Y28
11mA G9 VCC1_5_A[21] VCCSUS3_3[15] W6 E18 VSS[085] VSS[191] Y29
VCC1_5_A[22] VCCSUS3_3[16] W7 E2 VSS[086] VSS[192] Y4
AC12 VCCSUS3_3[17] Y6 E21 VSS[087] VSS[193] Y5
C315 AC13 VCC1_5_A[23] VCCSUS3_3[18] Y7 E24 VSS[088] VSS[194] AG28
AC14 VCC1_5_A[24] VCCSUS3_3[19] T7 E5 VSS[089] VSS[195] AH6
0.1U/10V_4 VCC1_5_A[25] VCCSUS3_3[20] E8 VSS[090] VSS[196] AF2
AJ5 G22 VCCCL1_05_INT_ICH F16 VSS[091] VSS[197] B25
VCCUSBPLL VCCCL1_05 F28 VSS[092] VSS[198]
AA7 G23 VCCCL1_5_INT_ICH C390 F29 VSS[093] A1
VCC1_5_A[26] VCCCL1_5 VCCCL1_05 power by VCC1_05_A in S0 VSS[094] VSS_NCTF[01]
USB CORE
AB6 G12 A2
C329 AB7 VCC1_5_A[27] A24 C388 C389 0.1U/10V_4 VCCCL1_5 power by VCC1_5_A in S0 G14 VSS[095] VSS_NCTF[02] A28
AC6 VCC1_5_A[28] VCCCL3_3[1] B24 G18 VSS[096] VSS_NCTF[03] A29
1.05V , Powered by VCC1_05 in S0 0.1U/10V_4 AC7 VCC1_5_A[29] VCCCL3_3[2] *1U/10V_4 *0.1U/10V_4 G21 VSS[097] VSS_NCTF[04] AH1
VCC1_5_A[30] G24 VSS[098] VSS_NCTF[05] AH29
A10 G26 VSS[099] VSS_NCTF[06] AJ1
3.3V VCCLAN1_05[1] 3.3V VSS[100] VSS_NCTF[07]
C583 0.1U/10V_4 VCCLAN1_05_INT_ICH A11 G27 AJ2
S0:19mA VCCLAN1_05[2] S0:19mA G8 VSS[101] VSS_NCTF[08] AJ28
S3/4/5:78mA A12 S3/4/5:73mA H2 VSS[102] VSS_NCTF[09] AJ29
B12 VCCLAN3_3[1] H23 VSS[103] VSS_NCTF[10] B1
+3V VCCLAN3_3[2] +3V VSS[104] VSS_NCTF[11]
H28 B29
C585 A27 H29 VSS[105] VSS_NCTF[12]
If use SB MAC for LAN function. VCCGLANPLL
If use SB MAC for LAN function. And VSS[106]
And support wake up need support wake up need connect to
GLAN POWER
0.1U/10V_4 D28 ICH9MREV1.0

connect to relation power. D29 VCCGLAN1_5[1] relation power.
E26 VCCGLAN1_5[2]
L45 1uh_6 +1.5V_ICH_GLANPLL_R E27 VCCGLAN1_5[3]
+1.5V VCCGLAN1_5[4]
1.5V 1.5V C597 A26
C600 VCCGLAN3_3
23mA 80mA 10U/6.3V_8 2.2U/6.3V_6 ICH9MREV1.0
MODIFY +1.5V_B
A follow ZR6 C372 A
3.3V 4.7U/6.3V_6
1mA
+3V
352-(&7=4
4XDQWD&RPSXWHU,QF
1A
ICH9 POWER
5 4 3 2 1
5 4 3 2 1
DDR3 (DDR) +3V
STD H=4.0 MM
LTK
QCI P/N
DGMK4000004 R307 R306

16
2
10K_4 10K_4
FOX DGMK4000117
3 1 SDA_DDR
2,14,28 PDAT_SMB
Q15
CN9A M_A_DQ[63:0] 8
D 8 M_A_A[14:0] D
M_A_A0 98 5 M_A_DQ0 +3V RHU002N06
M_A_A1 97 A0 DQ0 7 M_A_DQ1
M_A_A2 96 A1 DQ1 15 M_A_DQ2
M_A_A3 95 A2 DQ2 17 M_A_DQ3
A3 DQ3
2
M_A_A4 92 4 M_A_DQ4
M_A_A5 91 A4 DQ4 6 M_A_DQ5
M_A_A6 90 A5 DQ5 16 M_A_DQ6 3 1 SCL_DDR
A6 DQ6 2,14,28 PCLK_SMB
M_A_A7 86 18 M_A_DQ7
M_A_A8 89 A7 DQ7 21 M_A_DQ8 Q16
M_A_A9 85 A8 DQ8 23 M_A_DQ9
M_A_A10 107 A9 DQ9 33 M_A_DQ10 RHU002N06
M_A_A11 84 A10/AP DQ10 35 M_A_DQ11 +1.5V_SUS
M_A_A12 83 A11 DQ11 22 M_A_DQ12
M_A_A13 119 A12/BC# DQ12 24 M_A_DQ13
M_A_A14 80 A13 DQ13 34 M_A_DQ14
M_A_A15 78 A14 DQ14 36 M_A_DQ15 CN9B
PC2100 DDR3 SDRAM SO-DIMM

TP4 A15 DQ15 39 M_A_DQ16 75 44
109 DQ16 41 M_A_DQ17 76 VDD1 VSS16 48
8 M_A_BS0 BA0 DQ17 VDD2 VSS17
108 51 M_A_DQ18 81 49
79 53 M_A_DQ19 82 54
114 40 M_A_DQ20 87 55
6 M_CS#0 S0# DQ20 VDD5 VSS20
121 42 M_A_DQ21 88 60
101 50 M_A_DQ22 93 61
6 M_CLK0 CK0 DQ22 VDD7 VSS22
103 52 M_A_DQ23 94 65
6 M_CLK#0 CK0# DQ23 VDD8 VSS23
102 57 M_A_DQ24 99 66
104 59 M_A_DQ25 100 71
73 67 M_A_DQ26 105 72

6 M_CKE0 CKE0 DQ26 VDD11 VSS26
74 69 M_A_DQ27 106 127
115 56 M_A_DQ28 111 128
8 M_A_CAS# CAS# DQ28 VDD13 VSS28
C 110 58 M_A_DQ29 112 133 C
8 M_A_RAS# RAS# DQ29 VDD14 VSS29
113 68 M_A_DQ30 117 134
8 M_A_WE# W E# DQ30 VDD15 VSS30
R269 10K/F_4 DIMM0_SA0 197 70 M_A_DQ31 118 138
R268 10K/F_4 DIMM0_SA1 201 SA0 DQ31 129 M_A_DQ32 123 VDD16 VSS31 139
SCL_DDR 202 SA1 DQ32 131 M_A_DQ33 124 VDD17 VSS32 144
17 SCL_DDR SCL DQ33 VDD18 VSS33
SDA_DDR 200 141 M_A_DQ34 145
17 SDA_DDR SDA DQ34 VSS34
143 M_A_DQ35 199 150
DQ35 +3V VDDSPD VSS35
116 130 M_A_DQ36 151
6 M_ODT0 ODT0 DQ36 VSS36
120 132 M_A_DQ37 77 155
6 M_ODT1 ODT1 DQ37 NC1 VSS37
140 M_A_DQ38 122 156
8 M_A_DM[7:0] DQ38 NC2 VSS38
M_A_DM0 11 142 M_A_DQ39 125 161
M_A_DM1 28 DM0 DQ39 147 M_A_DQ40 NCTEST VSS39 162
DM1 DQ40 VSS40
(204P)
M_A_DM2 46 149 M_A_DQ41 198 167

DM2 DQ41 6 PM_EXTTS#0 EVENT# VSS41
M_A_DM3 63 157 M_A_DQ42 30 168
DM3 DQ42 6,17 DDR3_DRAMRST# RESET# VSS42
M_A_DM4 136 159 M_A_DQ43 172
M_A_DM5 153 DM4 DQ43 146 M_A_DQ44 VSS43 173
M_A_DM6 170 DM5 DQ44 148 M_A_DQ45 1 VSS44 178
DM6 DQ45 +SMDDR_VREF VREF_DQ VSS45
M_A_DM7 187 158 M_A_DQ46 126 179
DM7 DQ46 160 M_A_DQ47 VREF_CA VSS46 184
8 M_A_DQS[7:0] DQ47 VSS47
M_A_DQS0 12 163 M_A_DQ48 185
M_A_DQS1 29 DQS0 DQ48 165 M_A_DQ49 2 VSS48 189
M_A_DQS2 47 DQS1 DQ49 175 M_A_DQ50 3 VSS1 VSS49 190
DQS2 DQ50 VSS2 VSS50
(204P)
M_A_DQS3 64 177 M_A_DQ51 8 195
M_A_DQS4 137 DQS3 DQ51 164 M_A_DQ52 9 VSS3 VSS51 196
M_A_DQS5 154 DQS4 DQ52 166 M_A_DQ53 13 VSS4 VSS52
M_A_DQS6 171 DQS5 DQ53 174 M_A_DQ54 14 VSS5
M_A_DQS7 188 DQS6 DQ54 176 M_A_DQ55 19 VSS6
8 M_A_DQS#[7:0] DQS7 DQ55 VSS7
M_A_DQS#0 10 181 M_A_DQ56 20
M_A_DQS#1 27 DQS#0 DQ56 183 M_A_DQ57 25 VSS8
M_A_DQS#2 45 DQS#1 DQ57 191 M_A_DQ58 26 VSS9 203
B DQS#2 DQ58 VSS10 VTT1 +SMDDR_VTERM B
M_A_DQS#3 62 193 M_A_DQ59 31 204
M_A_DQS#4 135 DQS#3 DQ59 180 M_A_DQ60 32 VSS11 VTT2
M_A_DQS#5 152 DQS#4 DQ60 182 M_A_DQ61 37 VSS12 G1
M_A_DQS#6 169 DQS#5 DQ61 192 M_A_DQ62 38 VSS13 G1 G2
M_A_DQS#7 186 DQS#6 DQ62 194 M_A_DQ63 43 VSS14 G2
DQS#7 DQ63 VSS15
DDR3-DIMM0 DDR3-DIMM0
+1.5V_SUS +SMDDR_VREF
Place these Caps near So-Dimm0. 4/29 Modfiy type
5/13 Add C464 *470P/50V_4
R272 *0_6
+SMDDR_VTERM 17,40,42
C458 C475 C459 C460 C449 C457 C454 C461 C477 C451 C448 C67
+ C489 R271 *10K/F_4 +1.5V_SUS
10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 *0.1U/10V_4 0.1u/10V_4 *0.1U/10V_4 0.1u/10V_4 0.1u/10V_4 *22U/6.3V_8 R270 *10K/F_4
330U/2V_7343
+SMDDR_VREF +3V +SMDDR_VTERM

A
7/05 Modfiy_del C539. A
C462 C463 C455 C456 C536 C552 C533 C553 C556 C555
352-(&7=4
0.1u/10V_4 2.2U/6.3V_6 2.2U/6.3V_6 0.1u/10V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 *10U/6.3V_6 10U/6.3V_6
4XDQWD&RPSXWHU,QF
1A
DDR3 DIMM-0(H=5.2)
5 4 3 2 1
5 4 3 2 1
DDR3 (DDR) STD H=8.0 MM
LTK
FOX
QCI P/N
DGMK4000097
DGMK4000130
17
CN10A M_B_DQ[63:0] 8
D 8 M_B_A[14:0] D
M_B_A0 98 5 M_B_DQ0
M_B_A1 97 A0 DQ0 7 M_B_DQ1
M_B_A2 96 A1 DQ1 15 M_B_DQ2
M_B_A3 95 A2 DQ2 17 M_B_DQ3
M_B_A4 92 A3 DQ3 4 M_B_DQ4
M_B_A5 91 A4 DQ4 6 M_B_DQ5
M_B_A6 90 A5 DQ5 16 M_B_DQ6
M_B_A7 86 A6 DQ6 18 M_B_DQ7
M_B_A8 89 A7 DQ7 21 M_B_DQ8
M_B_A9 85 A8 DQ8 23 M_B_DQ9
M_B_A10 107 A9 DQ9 33 M_B_DQ10
M_B_A11 84 A10/AP DQ10 35 M_B_DQ11 +1.5V_SUS
M_B_A12 83 A11 DQ11 22 M_B_DQ12
M_B_A13 119 A12/BC# DQ12 24 M_B_DQ13
M_B_A14 80 A13 DQ13 34 M_B_DQ14
M_B_A15 78 A14 DQ14 36 M_B_DQ15 CN10B

TP3 A15 DQ15 39 M_B_DQ16 75 44
109 DQ16 41 M_B_DQ17 76 VDD1 VSS16 48
8 M_B_BS0 BA0 DQ17 VDD2 VSS17
108 51 M_B_DQ18 81 49
79 53 M_B_DQ19 82 54
114 40 M_B_DQ20 87 55
121 42 M_B_DQ21 88 60
101 50 M_B_DQ22 93 61
103 52 M_B_DQ23 94 65
102 57 M_B_DQ24 99 66
104 59 M_B_DQ25 100 71
73 67 M_B_DQ26 105 72

74 69 M_B_DQ27 106 127
115 56 M_B_DQ28 111 128
8 M_B_CAS# CAS# DQ28 VDD13 VSS28
C 110 58 M_B_DQ29 112 133 C
8 M_B_RAS# RAS# DQ29 VDD14 VSS29
113 68 M_B_DQ30 117 134
8 M_B_WE# W E# DQ30 VDD15 VSS30
R263 10K/F_4 DIMM1_SA0 197 70 M_B_DQ31 118 138
R262 10K/F_4 DIMM1_SA1 201 SA0 DQ31 129 M_B_DQ32 123 VDD16 VSS31 139
202 SA1 DQ32 131 M_B_DQ33 124 VDD17 VSS32 144
+3V 16 SCL_DDR SCL DQ33 VDD18 VSS33
200 141 M_B_DQ34 145
16 SDA_DDR SDA DQ34 VSS34
143 M_B_DQ35 199 150
DQ35 +3V VDDSPD VSS35
116 130 M_B_DQ36 151
6 M_ODT2 ODT0 DQ36 VSS36
120 132 M_B_DQ37 77 155
6 M_ODT3 ODT1 DQ37 NC1 VSS37
140 M_B_DQ38 122 156
8 M_B_DM[7:0] DQ38 NC2 VSS38
M_B_DM0 11 142 M_B_DQ39 125 161
M_B_DM1 28 DM0 DQ39 147 M_B_DQ40 NCTEST VSS39 162
DM1 DQ40 VSS40
(204P)
M_B_DM2 46 149 M_B_DQ41 198 167

DM2 DQ41 6 PM_EXTTS#1 EVENT# VSS41
M_B_DM3 63 157 M_B_DQ42 30 168
DM3 DQ42 6,16 DDR3_DRAMRST# RESET# VSS42
M_B_DM4 136 159 M_B_DQ43 172
M_B_DM5 153 DM4 DQ43 146 M_B_DQ44 VSS43 173
M_B_DM6 170 DM5 DQ44 148 M_B_DQ45 1 VSS44 178
DM6 DQ45 +SMDDR_VREF VREF_DQ VSS45
M_B_DM7 187 158 M_B_DQ46 126 179
DM7 DQ46 160 M_B_DQ47 VREF_CA VSS46 184
8 M_B_DQS[7:0] DQ47 VSS47
M_B_DQS0 12 163 M_B_DQ48 185
M_B_DQS1 29 DQS0 DQ48 165 M_B_DQ49 2 VSS48 189
M_B_DQS2 47 DQS1 DQ49 175 M_B_DQ50 3 VSS1 VSS49 190
DQS2 DQ50 VSS2 VSS50
(204P)
M_B_DQS3 64 177 M_B_DQ51 8 195
M_B_DQS4 137 DQS3 DQ51 164 M_B_DQ52 9 VSS3 VSS51 196
M_B_DQS5 154 DQS4 DQ52 166 M_B_DQ53 13 VSS4 VSS52
M_B_DQS6 171 DQS5 DQ53 174 M_B_DQ54 14 VSS5
M_B_DQS7 188 DQS6 DQ54 176 M_B_DQ55 19 VSS6
8 M_B_DQS#[7:0] DQS7 DQ55 VSS7
M_B_DQS#0 10 181 M_B_DQ56 20
M_B_DQS#1 27 DQS#0 DQ56 183 M_B_DQ57 25 VSS8
M_B_DQS#2 45 DQS#1 DQ57 191 M_B_DQ58 26 VSS9 203
B DQS#2 DQ58 VSS10 VTT1 +SMDDR_VTERM B
M_B_DQS#3 62 193 M_B_DQ59 31 204
M_B_DQS#4 135 DQS#3 DQ59 180 M_B_DQ60 32 VSS11 VTT2
M_B_DQS#5 152 DQS#4 DQ60 182 M_B_DQ61 37 VSS12 G1
M_B_DQS#6 169 DQS#5 DQ61 192 M_B_DQ62 38 VSS13 G1 G2
M_B_DQS#7 186 DQS#6 DQ62 194 M_B_DQ63 43 VSS14 G2
DQS#7 DQ63 VSS15
DDR3-DIMM1 DDR3-DIMM1
+1.5V_SUS
Place these Caps near So-Dimm1. 5/6 Modfiy
C483 C488 C476 C478 C482 C481 C486 C473 C487 C479 C474
+ C490
10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 *0.1U/10V_4 0.1u/10V_4 *0.1U/10V_4 0.1u/10V_4 0.1u/10V_4
330U/2V_7343
+SMDDR_VREF +3V +SMDDR_VTERM

A
7/05 Modfiy_del C538. A
C485 C484 C453 C452 C543 C547 C540 C537 C535 C534
352-(&7=4
0.1u/10V_4 2.2U/6.3V_6 2.2U/6.3V_6 0.1u/10V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 *10U/6.3V_6 10U/6.3V_6
4XDQWD&RPSXWHU,QF
1A
DDR3 DIMM-1(H=9.2)
5 4 3 2 1
5 4 3 2 1
GPU_1(VGA)
0518 SWAP PCIE for VGA side

U28A
Modfiy it 5/4 Reversal PICE
0518 SWAP PCIE for VGA side

7,26 PEG_TXP[0..15]
7,26 PEG_TXN[0..15]
7,26 PEG_RXP[0..15]
PEG_TXP[0..15]
PEG_TXN[0..15]
PEG_RXP[0..15]
18
5/18 add PEG_RXN[0..15]
7 PEG_RXN[0..15]
RN29 1 2 EV@0_4P2R PEG_TXP0_R AA38 Y33 CPEG_RXP0 C217 EV@0.1u/10V_4
7,26 PEG_TXP0 3 4 PCIE_RX0P PCIE_TX0P PEG_RXP0 7
PEG_TXN0_R Y37 Y32 CPEG_RXN0 C226 EV@0.1u/10V_4
D 7,26 PEG_TXN0 PCIE_RX0N PCIE_TX0N PEG_RXN0 7 D
RN30 1 2 EV@0_4P2R PEG_TXP1_R Y35 W33 CPEG_RXP1 C199 EV@0.1u/10V_4

7,26 PEG_TXP1 PCIE_RX1P PCIE_TX1P PEG_RXP1 7
3 4 PEG_TXN1_R W36 W32 CPEG_RXN1 C209 EV@0.1u/10V_4
7,26 PEG_TXN1 PCIE_RX1N PCIE_TX1N PEG_RXN1 7
Item Quanta P/N
RN31 1 2 EV@0_4P2R PEG_TXP2_R W38 U33 CPEG_RXP2 C187 EV@0.1u/10V_4
7,26 PEG_TXP2 3 4 PCIE_RX2P PCIE_TX2P PEG_RXP2 7
PEG_TXN2_R V37 U32 CPEG_RXN2 C197 EV@0.1u/10V_4 Park AJ077400T08
RN32 1 2 EV@0_4P2R PEG_TXP3_R V35 U30 CPEG_RXP3 C184 EV@0.1u/10V_4 Robson AJ007740T02
7,26 PEG_TXP3 3 4 PCIE_RX3P PCIE_TX3P PEG_RXP3 7,26
PEG_TXN3_R U36 U29 CPEG_RXN3 C179 EV@0.1u/10V_4
PEG_TXP4 U38 T33 CPEG_RXP4 C168 EV@0.1u/10V_4

7 PEG_TXP4 PCIE_RX4P PCIE_TX4P PEG_RXP4 7
PEG_TXN4 T37 T32 CPEG_RXN4 C163 EV@0.1u/10V_4
7 PEG_TXN4 PCIE_RX4N PCIE_TX4N PEG_RXN4 7
PCI EXPRESS INTERFACE

PEG_TXP5 T35 T30 CPEG_RXP5 C159 EV@0.1u/10V_4
7 PEG_TXP5 R36 PCIE_RX5P PCIE_TX5P T29 PEG_RXP5 7
PEG_TXN5 CPEG_RXN5 C150 EV@0.1u/10V_4
PEG_TXP6 R38 P33 CPEG_RXP6 C148 EV@0.1u/10V_4

PEG_TXN6 P37 P32 CPEG_RXN6 C141 EV@0.1u/10V_4
C 7 PEG_TXN6 PCIE_RX6N PCIE_TX6N PEG_RXN6 7 C
PEG_TXP7 P35 P30 CPEG_RXP7 C135 EV@0.1u/10V_4

7 PEG_TXP7 N36 PCIE_RX7P PCIE_TX7P P29 PEG_RXP7 7
PEG_TXP8 N38 N33 CPEG_RXP8 C123 EV@0.1u/10V_4

7 PEG_TXP8 M37 PCIE_RX8P PCIE_TX8P N32 PEG_RXP8 7
PEG_TXP9 M35 N30 CPEG_RXP9 C112 EV@0.1u/10V_4

PEG_TXN9 L36 N29 CPEG_RXN9 C109 EV@0.1u/10V_4
PEG_TXP10 L38 L33 CPEG_RXP10 C103 EV@0.1u/10V_4

7 PEG_TXP10 K37 PCIE_RX10P PCIE_TX10P L32 PEG_RXP10 7
PEG_TXP11 K35 L30 CPEG_RXP11 C97 EV@0.1u/10V_4

PEG_TXN11 J36 L29 CPEG_RXN11 C89 EV@0.1u/10V_4
PEG_TXP12 J38 K33 CPEG_RXP12 C80 EV@0.1u/10V_4

7 PEG_TXP12 H37 PCIE_RX12P PCIE_TX12P K32 PEG_RXP12 7
B PEG_TXN12 CPEG_RXN12 C83 EV@0.1u/10V_4 B
PEG_TXP13 H35 J33 CPEG_RXP13 C72 EV@0.1u/10V_4

7 PEG_TXP13 G36 PCIE_RX13P PCIE_TX13P J32 PEG_RXP13 7
PEG_TXP14 G38 K30 CPEG_RXP14 C62 EV@0.1u/10V_4

PEG_TXN14 F37 K29 CPEG_RXN14 C61 EV@0.1u/10V_4
PEG_TXP15 F35 H33 CPEG_RXP15 C71 EV@0.1u/10V_4

7 PEG_TXP15 E37 PCIE_RX15P PCIE_TX15P H32 PEG_RXP15 7
CLOCK
AB35
2 CLK_PCIE_VGA PCIE_REFCLKP
AA36
2 CLK_PCIE_VGA# PCIE_REFCLKN
For Broadway, Madison and Park CALIBRATION

AJ21 Y30 R91 EV@1.27K/F_4
the PWRGOOD ball must be conneccted to ground AK21 NC#1 PCIE_CALRP
A R112 EV@10K_4 AH16 NC#2 Y29 R90 EV@2K/F_4 A
PWRGOOD PCIE_CALRN +1V +1.0V
GPU_RST# AA30
T19 PERSTB For M97, Broadway, Madison and Park PCIE_VDDC is 1.0V Quanta Computer Inc.
EV@Madison/Park_M2
PROJECT : ZQ5
1A
Madison/Park M2-PCIE I/F
5 4 3 2 1
5 4 3 2 1
GPU_2(VGA)
U28B
AU24 HDMICLK+_C C692 EV@.1u/10V_4

U28G
LVDS CONTROL AK27

19
TXCAP_DPA3P HDMICLK+ 26 VARY_BL EV_LVDS_BRIGHT 25
AV23 HDMICLK-_C C691 EV@.1u/10V_4 AJ27
TXCAM_DPA3N HDMICLK- 26 DIGON EV_LVDS_VDDEN 25
AT25 HDMITX0P_C C677 EV@.1u/10V_4
TX0P_DPA2P AR24 HDMITX0P 26
MUTI GFX HDMITX0N_C C676 EV@.1u/10V_4
DPA TX0M_DPA2N HDMITX0N 26
AU26 HDMITX1P_C C694 EV@.1u/10V_4 AK35 C-test
TX1P_DPA1P AV25 HDMITX1P 26 TXCLK_UP_DPF3P AL36
HDMITX1N_C C693 EV@.1u/10V_4
TX1M_DPA1N HDMITX1N 26 TXCLK_UN_DPF3N
AR8 AT27 HDMITX2P_C C679 EV@.1u/10V_4 AJ38
DVPCNTL_MVP_0 TX2P_DPA0P HDMITX2P 26 TXOUT_U0P_DPF2P
AU8 AR26 HDMITX2N_C C678 EV@.1u/10V_4 AK37
D DVPCNTL_MVP_1 TX2M_DPA0N HDMITX2N 26 TXOUT_U0N_DPF2N D
AP8
NC on Park AW8
AR3
DVPCNTL_0
DVPCNTL_1 TXCBP_DPB3P
AR30
AT29
5/5 Add TXOUT_U1P_DPF1P
AH35
AJ36
AR1 DVPCNTL_2 TXCBM_DPB3N TXOUT_U1N_DPF1N
AU1 DVPCLK AV31 AG38
23 RAM_STRAP0 DVPDATA_0 TX3P_DPB2P TXOUT_U2P_DPF0P
AU3 AU30 AH37
GPU Power-on sequence 23 RAM_STRAP1
23 RAM_STRAP2
AW3
AP6
DVPDATA_1
DVPDATA_2
DPB TX3M_DPB2N
AR32
TXOUT_U2N_DPF0N
AF35
T144 AW5 DVPDATA_3 TX4P_DPB1P AT31 TXOUT_U3P AG36
1 => +3V_D AU5 DVPDATA_4
DVPDATA_5
TX4M_DPB1N TXOUT_U3N
AR6 AT33
2 => +VGPU_CORE 1.8V GPIO AW6
AU6
DVPDATA_6
DVPDATA_7
TX5P_DPB0P
TX5M_DPB0N
AU32 LVTMDP
DVPDATA_8
3 => +1V AT7
AV7 DVPDATA_9 TXCCP_DPC3P
AU14
AV13
T139 TXCLK_LP_DPE3P
AP34
AR34
EV_TXLCLKOUT+ 25
DVPDATA_10 TXCCM_DPC3N T135 TXCLK_LN_DPE3N EV_TXLCLKOUT- 25
AN7
4 => +1.5V_GPU AV9 DVPDATA_11
DVPDATA_12 TX0P_DPC2P
AT15
T136 TXOUT_L0P_DPE2P
AW37
EV_TXLOUT0+ 25
AT9 AR14 AU35
5 => +1.8V_GPU AR10 DVPDATA_13
DVPDATA_14
TX0M_DPC2N T140 TXOUT_L0N_DPE2N EV_TXLOUT0- 25
AW10 DPC AU16 AR37
T138 EV_TXLOUT1+ 25
6 => dGPU_PWROK AU10
AP10
DVPDATA_15
DVPDATA_16
TX1P_DPC1P
TX1M_DPC1N
AV15
T134
TXOUT_L1P_DPE1P
TXOUT_L1N_DPE1N
AU39
EV_TXLOUT1- 25
AV11 DVPDATA_17 AT17 AP35
AT11 DVPDATA_18 TX2P_DPC0P AR16 T141 TXOUT_L2P_DPE0P AR35 EV_TXLOUT2+ 25
DVPDATA_19 TX2M_DPC0N T145 TXOUT_L2N_DPE0N EV_TXLOUT2- 25
AR12
NC on Park AW12
AU12
DVPDATA_20
DVPDATA_21 TXCDP_DPD3P
AU20
AT19 TXOUT_L3P
AN36
AP37
AP12 DVPDATA_22 TXCDM_DPD3N TXOUT_L3N
+3V_D DVPDATA_23 AT21
5/6 modify
TX3P_DPD2P AR20
TX3M_DPD2N
Channel D N.C for Park-M2
DPD AU22 EV_LVDS_VDDEN R150 EV@10K_4
TX4P_DPD1P AV21 EV@Madison/Park_M2
R115 R118 TX4M_DPD1N EV_LVDS_BRIGHT R158 *EV@10K_4
EV@10K_4 EV@10K_4 I2C AT23
TX5P_DPD0P AR22 EV_LVDS_BLON R160 EV@10K_4
AK26 TX5M_DPD0N ramp remove short pad
AJ26 SCL
C C
SDA
AD39 EXT_CRT_RED
R EV_CRT_RED 25
GENERAL PURPOSE I/O AD37
AH20 RB
23 GPU_GPIO0 GPIO_0
AH18 AE36 EXT_CRT_GRN
23 GPU_GPIO1 AN16 GPIO_1 G AD35 EV_CRT_GRN 25
23 GPU_GPIO2 GPIO_2 GB
AH23
23 GPIO3_SMBDAT GPIO_3_SMBDATA
AJ23 AF37 EXT_CRT_BLU
23 GPIO4_SMBCLK AH17 GPIO_4_SMBCLK B AE38 EV_CRT_BLU 25
T13 GPIO_5_AC_BATT BB
1/21 ramp remove IO_VID0 AJ17 DAC1
AK17 GPIO_6 AC36 R505 R507 R509
25 EV_LVDS_BLON GPIO_7_BLON HSYNC EV_HSYNC 23,25
AJ13 AC38 EV@150/F_4 EV@150/F_4 EV@150/F_4
23 SOUT_GPIO8 GPIO_8_ROMSO VSYNC EV_VSYNC 23,25
AH15
23 SIN_GPIO9 AJ16 GPIO_9_ROMSI
+3V_D 23 SCLK_GPIO10 GPIO_10_ROMSCK
AK16 AB34 R95 EV@499/F_4
23 GPU_GPIO11 AL16 GPIO_11 RSET
23 GPU_GPIO12 GPIO_12
AM16 AD34 AVDD
23 GPU_GPIO13 GPIO_13 AVDD
AM14 AE34 +1.8V_GPU
T20 AM13 GPIO_14_HPD2 AVSSQ
3.3V GPIO R155 (1.8V@70mA AVDD)
41 GPU_VID1 GPIO_15_PWRCNTL_0
AK14 AC33 VDD1DI
T15 AG30 GPIO_16_SSIN VDD1DI AC34
*EV@10K_4 AVDD L20 EV@SBY100505T-121Y-N/300mA/120ohm_4
23 ALT#_GPIO17 GPIO_17_THERMAL_INT VSS1DI
AN14
T146
AM17 GPIO_18_HPD3 5/17 modify
AL13 GPIO_19_CTF AC30 C249 C259 C260
+3V_D 41 GPU_VID2 GPIO_20_PWRCNTL_1 R2
AJ14 AC31 R101 EV@0_4 EV@0.1u/10V_4 EV@1u/6.3V_4 EV@10u/6.3V_6
T10 AK13 GPIO_21_BB_EN R2B
R151
23 SCS#_GPIO22 GPIO_22_ROMCSB
AN13 AD30
EV@10K_4 R132 *EV@10K_4 GPIO24_TRSTB AM23 GPIO_23_CLKREQB G2 AD31 R97 EV@0_4
JTAG_TRSTB G2B (1.8V@100mA VDD1DI)
R154 R133 *EV@10K_4 AN23
+3V_D T18 JTAG_TDI
27M_CLK AK23 AF30 VDD1DI L15 EV@SBY100505T-121Y-N/300mA/120ohm_4
*EV@10K/F_4 R126 *EV@10K_4 AL24 JTAG_TCK B2 AF31 R107 EV@0_4
+3V_D JTAG_TMS B2B
AM24 SP@
T17 JTAG_TDO
D3D AJ19 DAC2 will be NC on future ASIC C235 C241 C247
2 PEG_CLKREQ# AK19 GENERICA AC32 EV@0.1u/10V_4 EV@1u/6.3V_4 EV@10u/6.3V_6 Seymour no stuff
AJ20 GENERICB C AD32
GENERICC Y 5/7
R153 AK20 AF32
AJ24 GENERICD COMP 5/5 Modify
B
*EV@10K/F_4 AH26 GENERICE_HPD4 DAC2 B
AH24 GENERICF AD29
GENERICG H2SYNC H2SYNC 23 5/5 add for CRT issue
AC29
V2SYNC V2SYNC 23
26 HDMI_HP_EV
AK24
+1.8V_GPU HPD1 AG31 VDD1DI C251 C242
VDD2DI AG32 R119 EV@0_4
VSS2DI
SP@ SP@ (3.3V@130mA A2VDD) *EV@10U/6.3V_8 *EV@10U/6.3V_8
R488 *EV@0_4 XTALI_27M R144 AG33 A2VDD R517 EV@0_4 +3V_D

2 27M_NONSS A2VDD
R487 *EV@0_4 27M_CLK EV@499/F_4
AD33 A2VDDQ
5/6 Modify VREFG AH13 A2VDDQ C225
VREFG AF33 EV@0.1u/10V_4
C256 A2VSSQ
R135
EV@249/F_4 EV@0.1u/10V_4 AA29 R103 EV@715/F_4
R2SET
Seymour no stuff
+1.8V(75mA) SP@ 5/7
L26 EV@SBY100505T-121Y-N/300mA/120ohm_4 DPLL_PVDD DDC/AUX AM26 Seymour no stuff
+1.8V_GPU DDC1CLK MXM_DDCCK_C 26
PLL/CLOCK AN26 SP@ 5/7
C294 C286 C295 DPLL_PVDD AM32
AN32 DPLL_PVDD
DDC1DATA
AM27
MXM_DDCDAT_C 26
HDMI
(1.8V@2mA A2VDDQ) +1.8V_GPU
EV@10u/6.3V_6 EV@1u/6.3V_4 EV@0.1u/10V_4 DPLL_PVSS AUX1P AL27
AUX1N
DPLL_VDDC AN31 AM19 A2VDDQ L59 EV@SBY100505T-121Y-N/300mA/120ohm_4
C688 EV@27p/50V_4 DPLL_VDDC DDC2CLK AL19
DDC2DATA
+1.0V(125mA)
2
XTALI_27M AV33 AN20 C710 C711

L21 EV@SBY100505T-121Y-N/300mA/120ohm_4 DPLL_VDDC Y4 R499 XTALO_27M AU34 XTALIN AUX2P AM20 EV@0.1u/10V_4 EV@1u/6.3V_4
+1V XTALOUT AUX2N
EV@27MHZ EV@1M/F_4
C267 C258 C253 AL30 T14
1
DDCCLK_AUX3P AM30
DDCDATA_AUX3N T16
EV@10u/6.3V_6 EV@1u/6.3V_4 EV@0.1u/10V_4 C689 EV@27p/50V_4
AL29
AF29 DDCCLK_AUX4P AM29
A
23
23
GPU_D+
GPU_D-
AG29 DPLUS
DMINUS
THERMAL DDCDATA_AUX4N
AN21
DDC AUX4 NC for Park_M2 A
+1.8V(5mA) DDCCLK_AUX5P EV_LVDS_DDCCLK 25
AM21
+1.8V_GPU L16 EV@SBY100505T-121Y-N/300mA/120ohm_4 TS_VDD
T11
AK32
AJ32 TS_FDO
DDCDATA_AUX5N
AJ30
EV_LVDS_DDCDAT 25 LVDS
TS_VDD
TSVDD DDC6CLK EV_CRTDCLK 25
C261 C243 AJ33 AJ31
TSVSS DDC6DATA
AK30
EV_CRTDDAT 25 CRT
EV@10u/6.3V_6 EV@0.1u/10V_4
NC_DDCCLK_AUX7P AK29
NC_DDCDATA_AUX7N DDC AUX7 NC for Park_M2
Quanta Computer Inc.
EV@Madison/Park_M2
PROJECT : ZQ5
1A
Madison/Park M2-HOST I/F
5 4 3 2 1
5 4 3 2 1
GPU_3(VGA)
Park M2-channel B used(S3 package use Channel A) 20
VMB_DQ[63..0]
24 VMB_DQ[63..0]
VMB_DM[7..0]
24 VMB_DM[7..0]
U28C U28D
DDR2 DDR2 VMB_RDQS[7..0] DDR2 DDR2
GDDR3/GDDR5 GDDR5/GDDR3 24 VMB_RDQS[7..0] GDDR3/GDDR5 GDDR5/GDDR3
DDR3 DDR3 VMB_WDQS[7..0] DDR3 DDR3
C37 G24 24 VMB_WDQS[7..0] C5 P8
VMB_DQ0 VMB_MA0
C35 DQA0_0/DQA_0 MAA0_0/MAA_0 J23 VMB_DQ1 C3 DQB0_0/DQB_0 MAB0_0/MAB_0 T9 VMB_MA1
MEMORY INTERFACE A
D
A35 DQA0_1/DQA_1 MAA0_1/MAA_1 H24 VMB_MA[13..0] VMB_DQ2 E3 DQB0_1/DQB_1 MAB0_1/MAB_1 P9 VMB_MA2 D
MEMORY INTERFACE B
E34 DQA0_2/DQA_2 MAA0_2/MAA_2 J24 24 VMB_MA[13..0] E1 DQB0_2/DQB_2 MAB0_2/MAB_2 N7
VMB_DQ3 VMB_MA3
G32 DQA0_3/DQA_3 MAA0_3/MAA_3 H26 VMB_DQ4 F1 DQB0_3/DQB_3 MAB0_3/MAB_3 N8 VMB_MA4
D33 DQA0_4/DQA_4 MAA0_4/MAA_4 J26 VMB_BA0 VMB_DQ5 F3 DQB0_4/DQB_4 MAB0_4/MAB_4 N9 VMB_MA5
DQA0_5/DQA_5 MAA0_5/MAA_5 24 VMB_BA0 DQB0_5/DQB_5 MAB0_5/MAB_5
F32 H21 VMB_BA1 VMB_DQ6 F5 U9 VMB_MA6
DQA0_6/DQA_6 MAA0_6/MAA_6 24 VMB_BA1 DQB0_6/DQB_6 MAB0_6/MAB_6
E32 G21 VMB_BA2 VMB_DQ7 G4 U8 VMB_MA7
D31 DQA0_7/DQA_7 MAA0_7/MAA_7 H19 24 VMB_BA2 H5 DQB0_7/DQB_7 MAB0_7/MAB_7 Y9
VMB_DQ8 VMB_MA8
F30 DQA0_8/DQA_8 MAA1_0/MAA_8 H20 VMB_DQ9 H6 DQB0_8/DQB_8 MAB1_0/MAB_8 W9 VMB_MA9
C30 DQA0_9/DQA_9 MAA1_1/MAA_9 L13 VMB_DQ10 J4 DQB0_9/DQB_9 MAB1_1/MAB_9 AC8 VMB_MA10
A30 DQA0_10/DQA_10 MAA1_2/MAA_10 G16 VMB_DQ11 K6 DQB0_10/DQB_10 MAB1_2/MAB_10 AC9 VMB_MA11
F28 DQA0_11/DQA_11 MAA1_3/MAA_11 J16 VMB_DQ12 K5 DQB0_11/DQB_11 MAB1_3/MAB_11 AA7 VMB_MA12
C28 DQA0_12/DQA_12 MAA1_4/MAA_12 H16 VMB_DQ13 L4 DQB0_12/DQB_12 MAB1_4/MAB_12 AA8 VMB_BA2
A28 DQA0_13/DQA_13 MAA1_5/MAA_13_BA2 J17 VMB_DQ14 M6 DQB0_13/DQB_13 MAB1_5/BA2 Y8 VMB_BA0
E28 DQA0_14/DQA_14 MAA1_6/MAA_14_BA0 H17 VMB_DQ15 M1 DQB0_14/DQB_14 MAB1_6/BA0 AA9 VMB_BA1
D27 DQA0_15/DQA_15 MAA1_7/MAA_A15_BA1 VMB_DQ16 M3 DQB0_15/DQB_15 MAB1_7/BA1
F26 DQA0_16/DQA_16 A32 VMB_DQ17 M5 DQB0_16/DQB_16 H3 VMB_DM0
C26 DQA0_17/DQA_17 WCKA0_0/DQMA_0 C32 VMB_DQ18 N4 DQB0_17/DQB_17 WCKB0_0/DQMB_0 H1 VMB_DM1
A26 DQA0_18/DQA_18 WCKA0B_0/DQMA_1 D23 VMB_DQ19 P6 DQB0_18/DQB_18 WCKB0B_0/DQMB_1 T3 VMB_DM2
F24 DQA0_19/DQA_19 WCKA0_1/DQMA_2 E22 VMB_DQ20 P5 DQB0_19/DQB_19 WCKB0_1/DQMB_2 T5 VMB_DM3
C24 DQA0_20/DQA_20 WCKA0B_1/DQMA_3 C14 VMB_DQ21 R4 DQB0_20/DQB_20 WCKB0B_1/DQMB_3 AE4 VMB_DM4
A24 DQA0_21/DQA_21 WCKA1_0/DQMA_4 A14 VMB_DQ22 T6 DQB0_21/DQB_21 WCKB1_0/DQMB_4 AF5 VMB_DM5
E24 DQA0_22/DQA_22 WCKA1B_0/DQMA_5 E10 VMB_DQ23 T1 DQB0_22/DQB_22 WCKB1B_0/DQMB_5 AK6 VMB_DM6
C22 DQA0_23/DQA_23 WCKA1_1/DQMA_6 D9 VMB_DQ24 U4 DQB0_23/DQB_23 WCKB1_1/DQMB_6 AK5 VMB_DM7
A22 DQA0_24/DQA_24 WCKA1B_1/DQMA_7 VMB_DQ25 V6 DQB0_24/DQB_24 WCKB1B_1/DQMB_7
F22 DQA0_25/DQA_25 GDDR5/DDR2/GDDR3 C34 VMB_DQ26 V1 DQB0_25/DQB_25 GDDR5/DDR2/GDDR3 F6 VMB_RDQS0
D21 DQA0_26/DQA_26 EDCA0_0/QSA_0/RDQSA_0 D29 VMB_DQ27 V3 DQB0_26/DQB_26 EDCB0_0/QSB_0/RDQSB_0 K3 VMB_RDQS1
+1.5V_GPU A20 DQA0_27/DQA_27 EDCA0_1/QSA_1/RDQSA_1 D25 VMB_DQ28 Y6 DQB0_27/DQB_27 EDCB0_1/QSB_1/RDQSB_1 P3 VMB_RDQS2
F20 DQA0_28/DQA_28 EDCA0_2/QSA_2/RDQSA_2 E20 VMB_DQ29 Y1 DQB0_28/DQB_28 EDCB0_2/QSB_2/RDQSB_2 V5 VMB_RDQS3
DQA0_29/DQA_29 EDCA0_3/QSA_3/RDQSA_3 DQB0_29/DQB_29 EDCB0_3/QSB_3/RDQSB_3 QSB[7..0]
D19 E16 VMB_DQ30 Y3 AB5 VMB_RDQS4
E18 DQA0_30/DQA_30 EDCA1_0/QSA_4/RDQSA_4 E12 VMB_DQ31 Y5 DQB0_30/DQB_30 EDCB1_0/QSB_4/RDQSB_4 AH1 VMB_RDQS5
C18 DQA0_31/DQA_31 EDCA1_1/QSA_5/RDQSA_5 J10 VMB_DQ32 AA4 DQB0_31/DQB_31 EDCB1_1/QSB_5/RDQSB_5 AJ9 VMB_RDQS6
R58 A18 DQA1_0/DQA_32 EDCA1_2/QSA_6/RDQSA_6 D7 VMB_DQ33 AB6 DQB1_0/DQB_32 EDCB1_2/QSB_6/RDQSB_6 AM5 VMB_RDQS7
EV@40.2/F_4 F18 DQA1_1/DQA_33 EDCA1_3/QSA_7/RDQSA_7 VMB_DQ34 AB1 DQB1_1/DQB_33 EDCB1_3/QSB_7/RDQSB_7
D17 DQA1_2/DQA_34 A34 VMB_DQ35 AB3 DQB1_2/DQB_34 G7 VMB_WDQS0
MVREFDA A16 DQA1_3/DQA_35 DDBIA0_0/QSA_0B/WDQSA_0 E30 VMB_DQ36 AD6 DQB1_3/DQB_35 DDBIB0_0/QSB_0B/WDQSB_0 K1 VMB_WDQS1
F16 DQA1_4/DQA_36 DDBIA0_1/QSA_1B/WDQSA_1 E26 VMB_DQ37 AD1 DQB1_4/DQB_36 DDBIB0_1/QSB_1B/WDQSB_1 P1 VMB_WDQS2
D15 DQA1_5/DQA_37 DDBIA0_2/QSA_2B/WDQSA_2 C20 VMB_DQ38 AD3 DQB1_5/DQB_37 DDBIB0_2/QSB_2B/WDQSB_2 W4 VMB_WDQS3
DQA1_6/DQA_38 DDBIA0_3/QSA_3B/WDQSA_3 DQB1_6/DQB_38 DDBIB0_3/QSB_3B/WDQSB_3 QSB#[7..0]
C C84 E14 C16 VMB_DQ39 AD5 AC4 VMB_WDQS4 C
R59 EV@0.1u/10V_4 F14 DQA1_7/DQA_39 DDBIA1_0/QSA_4B/WDQSA_4 C12 VMB_DQ40 AF1 DQB1_7/DQB_39 DDBIB1_0/QSB_4B/WDQSB_4 AH3 VMB_WDQS5
EV@100/F_4 D13 DQA1_8/DQA_40 DDBIA1_1/QSA_5B/WDQSA_5 J11 VMB_DQ41 AF3 DQB1_8/DQB_40 DDBIB1_1/QSB_5B/WDQSB_5 AJ8 VMB_WDQS6
F12 DQA1_9/DQA_41 DDBIA1_2/QSA_6B/WDQSA_6 F8 VMB_DQ42 AF6 DQB1_9/DQB_41 DDBIB1_2/QSB_6B/WDQSB_6 AM3 VMB_WDQS7
A12 DQA1_10/DQA_42 DDBIA1_3/QSA_7B/WDQSA_7 VMB_DQ43 AG4 DQB1_10/DQB_42 DDBIB1_3/QSB_7B/WDQSB_7
D11 DQA1_11/DQA_43 J21 VMB_DQ44 AH5 DQB1_11/DQB_43 T7
F10 DQA1_12/DQA_44 ADBIA0/ODTA0 G19 AH6 DQB1_12/DQB_44 ADBIB0/ODTB0 W7 VMB_ODT0 24
VMB_DQ45
DQA1_13/DQA_45 ADBIA1/ODTA1 DQB1_13/DQB_45 ADBIB1/ODTB1 VMB_ODT1 24
A10 VMB_DQ46 AJ4
+1.5V_GPU C10 DQA1_14/DQA_46 H27 VMB_DQ47 AK3 DQB1_14/DQB_46 L9 VMB_CLKP0
G13 DQA1_15/DQA_47 CLKA0 G27 AF8 DQB1_15/DQB_47 CLKB0 L8 VMB_CLKP0 24
VMB_DQ48 VMB_CLKN0
DQA1_16/DQA_48 CLKA0B DQB1_16/DQB_48 CLKB0B VMB_CLKN0 24
H13 VMB_DQ49 AF9
J13 DQA1_17/DQA_49 J14 VMB_DQ50 AG8 DQB1_17/DQB_49 AD8 VMB_CLKP1
DQA1_18/DQA_50 CLKA1 DQB1_18/DQB_50 CLKB1 VMB_CLKP1 24
H11 H14 VMB_DQ51 AG7 AD7 VMB_CLKN1
DQA1_19/DQA_51 CLKA1B DQB1_19/DQB_51 CLKB1B VMB_CLKN1 24
R62 G10 VMB_DQ52 AK9
EV@40.2/F_4 G8 DQA1_20/DQA_52 K23 VMB_DQ53 AL7 DQB1_20/DQB_52 T10 VMB_RAS0#
DQA1_21/DQA_53 RASA0B DQB1_21/DQB_53 RASB0B VMB_RAS0# 24
K9 K19 VMB_DQ54 AM8 Y10 VMB_RAS1#
K10 DQA1_22/DQA_54 RASA1B AM7 DQB1_22/DQB_54 RASB1B VMB_RAS1# 24
MVREFSA VMB_DQ55
G9 DQA1_23/DQA_55 K20 VMB_DQ56 AK1 DQB1_23/DQB_55 W10 VMB_CAS0#
DQA1_24/DQA_56 CASA0B DQB1_24/DQB_56 CASB0B VMB_CAS0# 24
A8 K17 VMB_DQ57 AL4 AA10 VMB_CAS1#
C8 DQA1_25/DQA_57 CASA1B AM6 DQB1_25/DQB_57 CASB1B VMB_CAS1# 24
C88 +1.5V_GPU VMB_DQ58
R60 EV@0.1u/10V_4 E8 DQA1_26/DQA_58 K24 VMB_DQ59 AM1 DQB1_26/DQB_58 P10 VMB_CS0#
A6 DQA1_27/DQA_59 CSA0B_0 K27 AN4 DQB1_27/DQB_59 CSB0B_0 L10 VMB_CS0# 24
EV@100/F_4 VMB_DQ60
C6 DQA1_28/DQA_60 CSA0B_1 VMB_DQ61 AP3 DQB1_28/DQB_60 CSB0B_1
E6 DQA1_29/DQA_61 M13 VMB_DQ62 AP1 DQB1_29/DQB_61 AD10 VMB_CS1#
A5 DQA1_30/DQA_62 CSA1B_0 K16 AP5 DQB1_30/DQB_62 CSB1B_0 AC10 VMB_CS1# 24
R102 VMB_DQ63
DQA1_31/DQA_63 CSA1B_1 EV@40.2/F_4 DQB1_31/DQB_63 CSB1B_1
Used for Park-M2
MVREFDA L18 K21 U10 VMB_CKE0
MVREFDA CKEA0 CKEB0 VMB_CKE0 24
R68 *EV@MD@243/F_4 MVREFSA L20 J20 MVREFDB Y12 AA11 VMB_CKE1
MVREFSA CKEA1 MVREFDB CKEB1 VMB_CKE1 24
MVREFSB AA12
R70 EV@PK@243/F_4 L27 K26 MVREFSB N10 VMB_WE0#
MEM_CALRN0 WEA0B WEB0B VMB_WE0# 24
N12 L15 C198 D3D AB11 VMB_WE1#
AG12 MEM_CALRN1 WEA1B WEB1B VMB_WE1# 24
+1.5V_GPU R110 *EV@MD@243/F_4 R96 EV@0.1u/10V_4
MEM_CALRN2 EV@100/F_4 R120 *EV@10K_4
+3V_D
R64 EV@PK@243/F_4 M12 H23 R100 EV@10K_4 AD28 T8 VMB_MA13
GDDR5
GDDR5
M27 MEM_CALRP1 MAA0_8 J19 TESTEN MAB0_8 W8
R69 *EV@MD@243/F_4 AH12 MEM_CALRP0 MAA1_8 AK10 MAB1_8
R111 *EV@MD@243/F_4 MEM_CALRP2 AL10 CLKTESTA AH11 R148 EV@10/F_4 R149 EV@51_4
CLKTESTB DRAM_RST MEM_RST# 24
B B
Note by AN_M96_C1 +1.5V_GPU
AL31 R114 R124
RSVD *EV@0_4 *EV@0_4 R140 C282
Used for Madison-M2
EV@120p/50V_4
EV@4.99K/F_4
EV@Madison/Park_M2 R106 EV@Madison/Park_M2
EV@40.2/F_4
Place all these components very close to GPU (Within

C223 25mm) and keep all component close to each Other (within
R104 EV@0.1u/10V_4
EV@100/F_4 5mm)
5/17 Modify
A A

PROJECT : ZQ5
1A
Madison/Park M2-MEM I/F
5 4 3 2 1
5 4 3 2 1
GPU_4(VGA)
U28F
21
U28E
For DDR3, MVDDQ = 1.5V (3A)
+1.5V_GPU MEM I/O +1.8V_GPU
PCIE (1.8V@400mA PCIE_VDDR) AB39 A3
AC7 AA31 PCIE_VDDR L61 EV@HCB1608KF-181T15/1.5A/180ohm_6 E39 PCIE_VSS#1 GND#1 A37
AD11 VDDR1#1 PCIE_VDDR#1 AA32 F34 PCIE_VSS#2 GND#2 AA16
AF7 VDDR1#2 PCIE_VDDR#2 AA33 F39 PCIE_VSS#3 GND#3 AA18
C100 C118 C93 C96 C188 AG10 VDDR1#3 PCIE_VDDR#3 AA34 C206 C207 C180 C173 C721 C186 C720 C213 G33 PCIE_VSS#4 GND#4 AA2
EV@10u/6.3V_6 EV@10u/6.3V_6 EV@10u/6.3V_6 AJ7 VDDR1#4 PCIE_VDDR#4 V28 EV@0.1u/10V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 G34 PCIE_VSS#5 GND#5 AA21
EV@10u/6.3V_6 EV@10u/6.3V_6 AK8 VDDR1#5 PCIE_VDDR#5 W29 EV@0.1u/10V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@10u/6.3V_6 H31 PCIE_VSS#6 GND#6 AA23
D
AL9 VDDR1#6 PCIE_VDDR#6 W30 H34 PCIE_VSS#7 GND#7 AA26 D
G11 VDDR1#7 PCIE_VDDR#7 Y31 H39 PCIE_VSS#8 GND#8 AA28
G14 VDDR1#8 PCIE_VDDR#8 J31 PCIE_VSS#9 GND#9 AA6
G17 VDDR1#9 J34 PCIE_VSS#10 GND#10 AB12
G20 VDDR1#10 G30 +1V K31 PCIE_VSS#11 GND#11 AB15
C124 C208 C195 C108 C185 C85 G23 VDDR1#11 PCIE_VDDC#1 G31 K34 PCIE_VSS#12 GND#12 AB17
VDDR1#12 PCIE_VDDC#2 (1.0V@1.1A PCIE_VDDC) PCIE_VSS#13 GND#13
EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 G26 H29 K39 AB20
EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 G29 VDDR1#13 PCIE_VDDC#3 H30 L31 PCIE_VSS#14 GND#14 AB22
H10 VDDR1#14 PCIE_VDDC#4 J29 L34 PCIE_VSS#15 GND#15 AB24
J7 VDDR1#15 PCIE_VDDC#5 J30 C152 C142 C92 C107 C162 C120 C146 C102 M34 PCIE_VSS#16 GND#16 AB27
J9 VDDR1#16 PCIE_VDDC#6 L28 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 M39 PCIE_VSS#17 GND#17 AC11
K11 VDDR1#17 PCIE_VDDC#7 M28 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@10u/6.3V_6 N31 PCIE_VSS#18 GND#18 AC13
K13 VDDR1#18 PCIE_VDDC#8 N28 N34 PCIE_VSS#19 GND#19 AC16
K8 VDDR1#19 PCIE_VDDC#9 R28 P31 PCIE_VSS#20 GND#20 AC18
C101 C113 C90 C169 C98 C122 L12 VDDR1#20 PCIE_VDDC#10 T28 P34 PCIE_VSS#21 GND#21 AC2
EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 L16 VDDR1#21 PCIE_VDDC#11 U28 P39 PCIE_VSS#22 GND#22 AC21
EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 L21 VDDR1#22 PCIE_VDDC#12 +VGPU_CORE R34 PCIE_VSS#23 GND#23 AC23
L23 VDDR1#23 T31 PCIE_VSS#24 GND#24 AC26
VDDR1#24 (30A or more) PCIE_VSS#25 GND#25
L26 AA15 T34 AC28
L7 VDDR1#25 CORE VDDC#1 AA17 T39 PCIE_VSS#26 GND#26 AC6
M11 VDDR1#26 VDDC#2 AA20 U31 PCIE_VSS#27 GND#27 AD15
N11 VDDR1#27 VDDC#3 AA22 C157 C160 C181 C182 C158 C221 C210 C155 C156 C204 U34 PCIE_VSS#28 GND#28 AD17
C91 C139 C125 C164 C106 P7 VDDR1#28 VDDC#4 AA24 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 V34 PCIE_VSS#29 GND#29 AD20
EV@1u/6.3V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 R11 VDDR1#29 VDDC#5 AA27 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 V39 PCIE_VSS#30 GND#30 AD22
EV@0.1u/10V_4 EV@0.1u/10V_4 U11 VDDR1#30 VDDC#6 AB16 W31 PCIE_VSS#31 GND#31 AD24
U7 VDDR1#31 VDDC#7 AB18 W34 PCIE_VSS#32 GND#32 AD27
Y11 VDDR1#32 VDDC#8 AB21 Y34 PCIE_VSS#33 GND#33 AD9
Y7 VDDR1#33 VDDC#9 AB23 Y39 PCIE_VSS#34 GND#34 AE2
VDDR1#34 VDDC#10 AB26 PCIE_VSS#35 GND#35 AE6
VDDC#11 AB28 GND#36 AF10
VDDC#12 AC17 C238 C239 C212 C189 C246 C229 C216 C166 C215 C230 GND#37 AF16
VDDC#13 AC20 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 GND#38 AF18
LEVEL VDDC#14 AC22 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 GND#39 AF21
(1.8V@110mA VDD_CT) TRANSLATION VDDC#15
VDDC#16
AC24 GND GND#40
GND#41
AG17
POWER
L56 EV@SBY100505T-121Y-N/300mA/120ohm_4 VDDC_CT AF26 AC27 F15 AG2
+1.8V_GPU VDD_CT#1 VDDC#17 GND#100 GND#42
AF27 AD18 F17 AG20
AG26 VDD_CT#2 VDDC#18 AD21 F19 GND#101 GND#43 AG22
C C670 C233 C220 AG27 VDD_CT#3 VDDC#19 AD23 F21 GND#102 GND#44 AG6 C
EV@10u/6.3V_6 EV@0.1u/10V_4 VDD_CT#4 VDDC#20 AD26 F23 GND#103 GND#45 AG9
VDDC#21 GND#104 GND#46 PowerXpress control signal for Madsion and Park only
EV@1u/6.3V_4 AF17 C200 C224 C193 C236 C214 C192 C165 C196 C178 C161 F25 AH21
VDDC#22 GND#105 GND#47 If not used, can be disconnected.
(3.3V@60mA)) I/O AF20 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 F27 AJ10
AF23 VDDC#23 AF22 F29 GND#106 GND#48 AJ11 PX_EN = LOW, turn on
+3V_D EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4
AF24 VDDR3#1 VDDC#24 AG16 F31 GND#107 GND#49 AJ2 PX_EN = HIGH, turn off
AG23 VDDR3#2 VDDC#25 AG18 F33 GND#108 GND#50 AJ28 PX_EN is used to turn ON/OFF some
C245 C237 C234 C240 AG24 VDDR3#3 VDDC#26 AG21 F7 GND#109 GND#51 AJ6 regulators for PowerXpress mode. An
EV@10u/6.3V_6 EV@1u/6.3V_4 VDDR3#4 VDDC#27 AH22 F9 GND#110 GND#52 AK11 output high ‘3.3V’ will turn the regulators
EV@1u/6.3V_4 EV@1u/6.3V_4 VDDC#28 AH27 G2 GND#111 GND#53 AK31 OFF. An output low ‘0V’ will turn the
AF13 VDDC#29 AH28 C191 C171 C190 C170 C143 C172 G6 GND#112 GND#54 AK7 regulators ON. PX_EN outputs low (0V)
AF15 VDDR4#4 VDDC#30 M26 EV@10u/6.3V_6 EV@10u/6.3V_6 EV@10u/6.3V_6 H9 GND#113 GND#55 AL11
VDDR4#5 VDDC#31 GND#114 GND#56 by default.
AG13 N24 EV@10u/6.3V_6 EV@10u/6.3V_6 EV@10u/6.3V_6 J2 AL14 If this signal is unused, it can be NC (not
L19 EV@SBY100505T-121Y-N/300mA/120ohm_4 VDDR4 AG15 VDDR4#7 VDDC#32 N27 J27 GND#115 GND#57 AL17
+1.8V_GPU VDDR4#8 VDDC#33 GND#116 GND#58 connected) or connected to ground.
R18 J6 AL2
VDDC#34 R21 J8 GND#117 GND#59 AL20
VDDC#35 BIF_VDDC should be connected to VDDC if BACO feature not used. GND#118 GND#60
C255 C262 AD12 R23 K14 AL21 R145 *EV@0_4
EV@1u/6.3V_4 AF11 VDDR4#1 VDDC#36 R26 For BACO, refer to the databook K7 GND#119 GND#61 AL23
+3V_D
EV@0.1u/10V_4 AF12 VDDR4#2 VDDC#37 T17 L11 GND#120 GND#62 AL26
AG11 VDDR4#3 VDDC#38 T20 L17 GND#121 GND#63 AL32 R139
VDDR4#6 VDDC#39 T22 L2 GND#122 GND#64 AL6 *EV@0_4
VDDC#40 T24 PIN different between Broadway and Madison L22 GND#123 GND#65 AL8
VDDC#41 T27 L24 GND#124 GND#66 AM11
VDDC#42 U16 L6 GND#125 GND#67 AM31
M20 VDDC#43 U18 Pin Broadway Madison 5/14 modify M17 GND#126 GND#68 AM9
T6 M21 NC_VDDRHA VDDC#44 U21 M22 GND#127 GND#69 AN11 Pin AL21 to Ground for Broadway
T5 NC_VSSRHA VDDC#45 U23 M24 GND#128 GND#70 AN2
VDDC#46
N27 VDDC BIF_VDDC GND#129 GND#71
U26 +VGPU_IO +VGPU_CORE N16 AN30
V12 VDDC#47 V17 N18 GND#130 GND#72 AN6
T8 U12 NC_VDDRHB VDDC#48 V20 N2 GND#131 GND#73 AN8
T7 NC_VSSRHB VDDC#49
AL31 TS_A NC_TS_A GND#132 GND#74
V22 N21 AP11
VDDC#50 V24 L12 N23 GND#133 GND#75 AP7
VDDC#51 V27 N26 GND#134 GND#76 AP9
VDDC#52
AL21 GND PX_EN EV@TI201209G121_8_3A
GND#135 GND#77
Y16 L10 N6 AR5
PLL VDDC#53 Y18 EV@TI201209G121_8_3A R15 GND#136 GND#78 AW34
(1.8V@40mA PCIE_PVDD) VDDC#54 GND#137 GND#79
L60 EV@SBY100505T-121Y-N/300mA/120ohm_4 PCIE_PVDD AB37 Y21 R17 B11
+1.8V_GPU PCIE_PVDD VDDC#55 GND#138 GND#80
Y23 R2 B13
MPV18 H7 VDDC#56 Y26 R20 GND#139 GND#81 B15
B
C719 C723 C722 H8 MPV18#1 VDDC#57 Y28 R22 GND#140 GND#82 B17 B
EV@10u/6.3V_6 EV@0.1u/10V_4 MPV18#2 VDDC#58 R24 GND#141 GND#83 B19

EV@1u/6.3V_4 +VGPU_IO R27 GND#142 GND#84 B21
SPV18 AM10 R6 GND#143 GND#85 B23
SPV18 (DDR3 1.12V@4A VDDCI) or more GND#144 GND#86
(1.8V@150mA MPV18) AA13 T11 B25
L13 EV@SBY100505T-121Y-N/300mA/120ohm_4 SPV10 AN9 VDDCI#1 AB13 T13 GND#145 GND#87 B27
+1.8V_GPU SPV10 VDDCI#2 GND#146 GND#88
AC12 T16 B29
AN10 VDDCI#3 AC15 C144 C183 C127 C138 C205 C119 C110 C153 C133 C140 T18 GND#147 GND#89 B31
C87 C105 C94 SPVSS VDDCI#4 AD13 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 T21 GND#148 GND#90 B33
EV@10u/6.3V_6 EV@0.1u/10V_4 VDDCI#5 AD16 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 T23 GND#149 GND#91 B7
EV@1u/6.3V_4 VDDCI#6 M15 T26 GND#150 GND#92 B9
VDDCI#7 M16 U15 GND#151 GND#93 C1
VOLTAGE VDDCI#8 M18 U17 GND#153 GND#94 C39
SENESE VDDCI#9 M23 U2 GND#154 GND#95 E35
(1.8V@75mA SPV18) VDDCI#10 GND#155 GND#96
L24 EV@SBY100505T-121Y-N/300mA/120ohm_4 N13 +3V U20 E5
+1.8V_GPU VDDCI#11 GND#156 GND#97
AF28 N15 U22 F11
T21 FB_VDDC VDDCI#12 GND#157 GND#98
N17 C218 C130 C117 U24 F13
C278 C264 VDDCI#13 N20 EV@10u/6.3V_6 EV@10u/6.3V_6 U27 GND#158 GND#99
VDDCI#14 GND#159
1
EV@10u/6.3V_6 AG28 N22 EV@10u/6.3V_6 U6
T9 FB_VDDCI
EV@0.1u/10V_4 ISOLATED VDDCI#15 R12 V11 GND#160
CORE I/O VDDCI#16 R13 R162 V16 GND#161
AH29 VDDCI#17 R16 2 *EV@0_6 V18 GND#163
T12 FB_GND VDDCI#18 GND#164
120 ohm/300mA
(1.0V@120mA SPV10) T12 V21
L57 EV@SBY100505T-121Y-N/300mA/120ohm_4 VDDCI#19 T15 V23 GND#165
+1V VDDCI#20
VDDCI#21
V15
Y13
EV@AO3413
Q5
0.5A
+3V_D_EXT 23,41 V26
W2
GND#166
GND#167
GPU Power-on sequence
3
C695 C690 VDDCI#22 W6 GND#168
EV@10u/6.3V_6
+3V_D_EXT
Y15 GND#169
GND#170
1 => +3V_D
EV@0.1u/10V_4 VDDC_SENSE/VSS_SENSE and EV@Madison/Park_M2 C306 C304 C305 Y17
VDDCI_SENSE/VSS_SENSE route as differetial pair
EV@10u/6.3V_6 EV@0.1u/10V_4
Spec: 0.15A
Rating: 3A
Y20
Y22
GND#171
GND#172 A39
2 => +VGPU_CORE
GND#173 VSS_MECH#1
+3V
EV@1u/6.3V_4 Y24
Y27 GND#174 VSS_MECH#2
AW1
AW39
3 => +1V
GPU all PWROK U13 GND#175 VSS_MECH#3
V13 GND#152
GND#162
4 => +1.5V_GPU
+3V +3V
R490 EV@Madison/Park_M2 5 => +1.8V_GPU
A EV@10K_4 R161 A
*EV@0_6 6 => dGPU_PWROK
1
R163
GPU +3V power EV@4.7K_4
dGPU_PWROK 35 B-test
R474 R157
3
EV@10K_4 Fine-tune Power-on sequence 2 *EV@0_6

3
2 Q20 EV@AO3413 0.5A

EV@2N7002K Q6
3
3
R164 *EV@0_4 2 Q7
2
35,38,40,42 MAINON
EV@DTC144EUA
+3V_D
+1.8V_GPU Q19 R165 EV@0_4 C669 C673 C674 Spec: 0.15A
1
35,41,43 VGPU_ON
EV@DTC144EUA C307 Rating: 3A PROJECT :ZQ5
1
C3C *EV@1u/6.3V_4 EV@10u/6.3V_6 EV@0.1u/10V_4

EV@1u/6.3V_4 Size Document Number Rev
1
1A
Modfiy it 5/4 Madison/Park M2 (PWR/GND)
5 4 3 2 1
5 4 3 2 1
GPU_5(VGA)
DPC_VDD18 AP20
AP21
U28H
DP C/D POWER
DPC_VDD18#1
DP A/B POWER
DPA_VDD18#1
AN24
AP24
DPA_VDD18
22
DPC_VDD18#2 DPA_VDD18#2
D +1V D
DPC_VDD10 AP13 AP31 DPA_VDD10 (1.0V@110mA DPA_VDD10)
AT13 DPC_VDD10#1 DPA_VDD10#1 AP32 DPA_VDD10 L22 EV@SBY100505T-121Y-N/300mA/120ohm_4
DPC_VDD10#2 DPA_VDD10#2
AN17 AN27 C271 C252 C257

+1.8V_GPU AP16 DPC_VSSR#1 DPA_VSSR#1 AP27 EV@10u/6.3V_6 EV@0.1u/10V_4
AP17 DPC_VSSR#2 DPA_VSSR#2 AP28 EV@1u/6.3V_4
(1.8V@130mA DPA_VDD18) DPC_VSSR#3 DPA_VSSR#3
AW14 AW24
L28 EV@SBY100505T-121Y-N/300mA/120ohm_4 DPA_VDD18 AW16 DPC_VSSR#4 DPA_VSSR#4 AW26
DPC_VSSR#5 DPA_VSSR#5
(1.0V@110mA DPC_VDD10)
C292 C285 C279 DPC_VDD10 L23 EV@SBY100505T-121Y-N/300mA/120ohm_4
EV@10u/6.3V_6 EV@0.1u/10V_4 DPC_VDD18 AP22 AP25 DPA_VDD18
EV@1u/10V_6 AP23 DPD_VDD18#1 DPB_VDD18#1 AP26
DPD_VDD18#2 DPB_VDD18#2 C276 C269 C263
EV@10u/6.3V_6 EV@0.1u/10V_4
EV@1u/6.3V_4
(1.8V@130mA DPC_VDD18) DPC_VDD10 AP14 AN33 DPA_VDD10
AP15 DPD_VDD10#1 DPB_VDD10#1 AP33
L29 EV@SBY100505T-121Y-N/300mA/120ohm_4 DPC_VDD18 DPD_VDD10#2 DPB_VDD10#2
C287 C288 C272 AN19 AN29

C DPD_VSSR#1 DPB_VSSR#1 C
EV@10u/6.3V_6 EV@0.1u/10V_4 AP18 AP29
EV@1u/10V_6 AP19 DPD_VSSR#2 DPB_VSSR#2 AP30
AW20 DPD_VSSR#3 DPB_VSSR#3 AW30
AW22 DPD_VSSR#4 DPB_VSSR#4 AW32
DPD_VSSR#5 DPB_VSSR#5
R494 EV@150/F_4 DPCD_CALR AW18 AW28 DPAB_CALR R498 EV@150/F_4 +1.8V_GPU

DPCD_CALR DPAB_CALR
(1.8V@20mA DPA_PVDD)
DPA_PVDD L27 EV@SBY100505T-121Y-N/300mA/120ohm_4
DP E/F POWER DP PLL POWER
AH34 AU28
DPE_VDD18 AJ34 DPE_VDD18#1 DPA_PVDD AV27 C280 C265 C266
DPE_VDD18#2 DPA_PVSS EV@10u/6.3V_6 EV@0.1u/10V_4
EV@1u/6.3V_4
+1.8V_GPU
AL33 AV29 DPB_PVDD (1.8V@20mA DPB_PVDD)
DPE_VDD10 AM33 DPE_VDD10#1 DPB_PVDD AR28 L30 EV@SBY100505T-121Y-N/300mA/120ohm_4
+1.8V_GPU DPE_VDD10#2 DPB_PVSS
(1.8V@400mA DPE/F_VDD18)
L14 EV@HCB1608KF-181T15/1.5A/180ohm_6 DPE_VDD18 C297 C283 C290
AN34 AU18 EV@10u/6.3V_6 EV@0.1u/10V_4
AP39 DPE_VSSR#1 DPC_PVDD AV17 EV@1u/6.3V_4
C228 C227 C232 AR39 DPE_VSSR#2 DPC_PVSS +1.8V_GPU
B B
EV@0.1u/10V_4 EV@10u/6.3V_6 AU37 DPE_VSSR#3 DPC_PVDD
DPE_VSSR#4 (1.8V@20mA DPC_PVDD)
EV@1u/6.3V_4 AW35 L58 EV@SBY100505T-121Y-N/300mA/120ohm_4
DPE_VSSR#5 AV19
DPD_PVDD AR18
DPD_PVSS C680 C687 C697
AF34 EV@10u/6.3V_6 EV@0.1u/10V_4
DPE_VDD18 AG34 DPF_VDD18#1 EV@1u/6.3V_4
+1V DPF_VDD18#2 AM37 +1.8V_GPU
(1.0V@400mA DPE/F_VDD10) DPE_PVDD
180 ohm/1.5A AN38 DPD_PVDD (1.8V@20mA DPD_PVDD)
L18 EV@HCB1608KF-181T15/1.5A/180ohm_6 DPE_VDD10 DPE_PVSS L31 EV@SBY100505T-121Y-N/300mA/120ohm_4
AK33
DPE_VDD10 AK34 DPF_VDD10#1
C248 C244 C273 DPF_VDD10#2 AL38 C303 C293 C299
EV@0.1u/10V_4 EV@10u/6.3V_6 NC_DPF_PVDD AM35 EV@10u/6.3V_6 EV@0.1u/10V_4
EV@1u/6.3V_4 NC_DPF_PVSS EV@1u/6.3V_4 +1.8V_GPU
AF39
AH39 DPF_VSSR#1
DPF_VSSR#2 (1.8V@40mA DPE/F_PVDD)
AK39 DPE_PVDD L25 EV@SBY100505T-121Y-N/300mA/120ohm_4
AL34 DPF_VSSR#3
AM34 DPF_VSSR#4
DPF_VSSR#5 C298 C291 C275
EV@10u/6.3V_6 EV@0.1u/10V_4
EV@1u/6.3V_4
A R503 EV@150/F_4 DPEF_CALR AM39 A
DPEF_CALR
EV@Madison/Park_M2
PROJECT : ZQ5
1A
Madison/Park M2 (DP_PWR/GND)
5 4 3 2 1
5 4 3 2 1
PIN STRAPS(VGA) +3V_D
19
19
GPU_GPIO0
GPU_GPIO1
19 GPIO3_SMBDAT
R128
R127
R122
*EV@10K_4
*EV@10K_4
*EV@10K_4
ROM Table
CONFIGURATION STRAPS
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET
23
R123 *EV@10K_4 STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS DEFAULT REMARK
19 GPIO4_SMBCLK
Size of the primary
CONFIG[2:0]
D
SCS#_GPIO22 R475 *EV@10K_4 memory apertures TX_PWRS_ENB GPIO0 0 = 50% TX OUTPUT SWING
1 = FULL TX OUTPUT SWING
0 D
R129 *EV@10K_4 000 TX_DEEMPH_EN GPIO1 PCIE TRANSMITTER DE-EMPHASIS ENABLED 0

19 GPU_GPIO13 128 MB 0 = TX DE-EMPHASIS DISABLED
R138 *EV@10K_4 1 = TX DE-EMPHASIS ENABLED
19 GPU_GPIO12
001 ENABLE EXTERNAL BIOS ROM
R136 EV@10K_4
256 MB BIOS_ROM_EN GPIO_22_ROMCSB 0 = DISABLE
19 GPU_GPIO11 5/17 Modify 1
1 = ENABLE
64 MB 010
R134 *EV@10K_4 ROMIDCFG(2:0) GPIO[13:11] Primary Memory Aperture size requested at PCI Configuration 001 table 3-35
19 GPU_GPIO2
32 MB 011
R512 EV@10K_4
19,25 EV_HSYNC
BIF_GEN2_EN_A GPIO2 0 = PCIE DEVICE AS 2.5GT/S CAPABLE 0
R518 EV@10K_4 1 = PCIE DEVICE AS 5GT/S CAPABLE
19,25 EV_VSYNC
GPIO_8_ROMSO GPIO8
SIN_GPIO9 R476 *EV@10K_4 H2SYNC H2SYNC Reserved Only 0
ROM Table GPIO_21_BB_EN GPIO21
R156 *EV@10K_4
19 V2SYNC
EXT_HSYNC EXT_VSYNC AUD[1:0]
19 H2SYNC
R159 *EV@10K_4
5/5 Modify Discription AUD[1] HSYNC 00: NO AUDIO FUNCTION.
01: AUDIO FOR DISPLAYPORT AND HDMI IF
No Audio AUD[0] VSYNC ADAPTER IS DETECTED. 11 See Audio table
SCS#_GPIO22 R121 *EV@10K_4

0 0 10: AUDIO FOR DISPLAYPORT ONLY.
11: AUDIO FOR BOTH DISPLAYPORT AND HDMI.

GPU_GPIO13 R125 *EV@10K_4 0 1 Any one by dectec
GPU_GPIO12 R137 *EV@10K_4 GPIO_9_ROMSI GPIO9 0 = VGA controller capacity enable 0
C 5/17 Add 1 0 DP only C
GPU_GPIO11 R131 *EV@10K_4
VIP_DEVICE_STRAP_ENA V2SYNC 0 = DRIVER would ignore the value sample on VHAD_0 during RESET. 0
1 1 Both DP & HDMI
EEPROM(VGA) DDR3 Memory Aperture size(GPU)
U25
SIN_GPIO9 5 2 SOUT_GPIO8
DDR3 Memory Aperture size
19 SIN_GPIO9 D Q SOUT_GPIO8 19
6 RAM_STRAP2 RAM_STRAP1 RAM_STRAP0
19 SCLK_GPIO10 C
SCS#_GPIO22 1
Vendor Vendor P/N STN B/S P/N
19 SCS#_GPIO22 S DVPDATA_2 DVPDATA_1 DVPDATA_0
+3V_D_EXT 7
HOLD
B-test R441 *EV@10K_4 3
W
1 1 0
8 4 Hynix AKD5LZGTW04
R438 VCC VSS
H5TQ1G63BFR-12C
*EV@10K_4
C665
*EV@M25P10-AVMN6P (64M*16) 1 0 0
*EV@0.1u/10V_4
B 1 0 1 B
Thermal Sensor(VGA) AKD5LGGT506

K4W1G1646E-HC12
Vendor P/N Samsung (64M*16) 0 0 0
WINDBOND AL83L771K01
K4W2G1646B-HC12 AKD5MGGT500
5/6 modify GMT AL000780000 USD0.16
(128M*16)
0 0 1
+3V_D_EXT B-test
+3V_D_EXT
R418 R419 C641 EV@0.1u/10V_4

EV@10K_4 EV@10K_4
U24 +1.8V_GPU
35 VGA_CLK 8 1
SCLK VCC GPU_D+ 19
R485 *EV@10K_4
7 2 19 RAM_STRAP2
C645
A
35 VGA_DATA SDA DXP R492 EV@10K_4 RAM_STRAP2 SET DDR3 Vendor A
6 3 EV@2200p/50V_4
19 ALT#_GPIO17 ALERT# DXN
GPU_D- 19
RAM_STRAP[1:0] SET SIZE.
4 5
35 VGA_THERM# OVERT# GND R486 *EV@10K_4
19 RAM_STRAP1
B-test EV@G780P81U(MSOP-8) R493 EV@10K_4
$''5(66+ Quanta Computer Inc.
R484 *EV@10K_4
PROJECT :ZQ5
R491 EV@10K_4 Size Document Number Rev
19 RAM_STRAP0
1A
Strip/Thermal
5 4 3 2 1
5 4 3 2 1
20 VMB_DQ[63..0]
20 VMB_DM[7..0]
20 VMB_RDQS[7..0]
VMB_DQ[63..0]
VMB_DM[7..0]
VMB_RDQS[7..0] QSA[7..0]
CHANNEL B: 512MB DDR3 (16*64M*4pcs)
24
VMB_WDQS[7..0] QSA#[7..0]
20 VMB_WDQS[7..0]
U4 U30 U27 U7
VREFC_VMB1 M8 E3 VMB_DQ4 VREFC_VMB2 M8 E3 VMB_DQ19 VREFC_VMB3 M8 E3 VMB_DQ36 VREFC_VMB4 M8 E3 VMB_DQ52

VREFD_VMB1 H1 VREFCA DQL0 F7 VMB_DQ3 VREFD_VMB2 H1 VREFCA DQL0 F7 VMB_DQ21 VREFD_VMB3 H1 VREFCA DQL0 F7 VMB_DQ39 VREFD_VMB4 H1 VREFCA DQL0 F7 VMB_DQ50
VREFDQ DQL1 F2 VMB_DQ5 VREFDQ DQL1 F2 VMB_DQ17 VREFDQ DQL1 F2 VMB_DQ33 VREFDQ DQL1 F2 VMB_DQ55
VMB_MA0 N3 DQL2 F8 VMB_DQ0 VMB_MA0 N3 DQL2 F8 VMB_DQ18 VMB_MA0 N3 DQL2 F8 VMB_DQ35 VMB_MA0 N3 DQL2 F8 VMB_DQ49
20
20
20
VMB_MA0
VMB_MA1
VMB_MA2
VMB_MA1
VMB_MA2
VMB_MA3
P7
P3
N2
A0
A1
A2
DQL3
DQL4
DQL5
H3
H8
G2
VMB_DQ6
VMB_DQ1
VMB_DQ7
0 VMB_MA1
VMB_MA2
VMB_MA3
P7
P3
N2
A0
A1
A2
DQL3
DQL4
DQL5
H3
H8
G2
VMB_DQ20
VMB_DQ22
VMB_DQ16
2 VMB_MA1
VMB_MA2
VMB_MA3
P7
P3
N2
A0
A1
A2
DQL3
DQL4
DQL5
H3
H8
G2
VMB_DQ37
VMB_DQ32
VMB_DQ38
4 VMB_MA1
VMB_MA2
VMB_MA3
P7
P3
N2
A0
A1
A2
DQL3
DQL4
DQL5
H3
H8
G2
VMB_DQ53
VMB_DQ48
VMB_DQ54
6
D 20 VMB_MA3 A3 DQL6 A3 DQL6 A3 DQL6 A3 DQL6 D
VMB_MA4 P8 H7 VMB_DQ2 VMB_MA4 P8 H7 VMB_DQ23 VMB_MA4 P8 H7 VMB_DQ34 VMB_MA4 P8 H7 VMB_DQ51
20 VMB_MA4 P2 A4 DQL7 P2 A4 DQL7 P2 A4 DQL7 P2 A4 DQL7
VMB_MA5 VMB_MA5 VMB_MA5 VMB_MA5
20 VMB_MA5 A5 A5 A5 A5
VMB_MA6 R8 VMB_MA6 R8 VMB_MA6 R8 VMB_MA6 R8
20 VMB_MA6 R2 A6 D7 R2 A6 D7 R2 A6 D7 R2 A6 D7
VMB_MA7 VMB_DQ26 VMB_MA7 VMB_DQ15 VMB_MA7 VMB_DQ62 VMB_MA7 VMB_DQ40
20 VMB_MA7 A7 DQU0 A7 DQU0 A7 DQU0 A7 DQU0
VMB_MA8 T8 C3 VMB_DQ27 VMB_MA8 T8 C3 VMB_DQ11 VMB_MA8 T8 C3 VMB_DQ58 VMB_MA8 T8 C3 VMB_DQ47
VMB_MA9 R3 C8 VMB_DQ28 VMB_MA9 R3 C8 VMB_DQ14 VMB_MA9 R3 C8 VMB_DQ63 VMB_MA9 R3 C8 VMB_DQ42
20
20
20
VMB_MA9
VMB_MA10
VMB_MA11
VMB_MA10
VMB_MA11
VMB_MA12
L7
R7
N7
A9
A10/AP
A11
DQU2
DQU3
DQU4
C2
A7
A2
VMB_DQ31
VMB_DQ24
VMB_DQ29
3 VMB_MA10
VMB_MA11
VMB_MA12
L7
R7
N7
A9
A10/AP
A11
DQU2
DQU3
DQU4
C2
A7
A2
VMB_DQ10
VMB_DQ12
VMB_DQ9
1 VMB_MA10
VMB_MA11
VMB_MA12
L7
R7
N7
A9
A10/AP
A11
DQU2
DQU3
DQU4
C2
A7
A2
VMB_DQ56
VMB_DQ61
VMB_DQ57
7 VMB_MA10
VMB_MA11
VMB_MA12
L7
R7
N7
A9
A10/AP
A11
DQU2
DQU3
DQU4
C2
A7
A2
VMB_DQ46
VMB_DQ43
VMB_DQ45
5
20 VMB_MA12 A12/BC DQU5 A12/BC DQU5 A12/BC DQU5 A12/BC DQU5
VMB_MA13 T3 B8 VMB_DQ25 VMB_MA13 T3 B8 VMB_DQ13 VMB_MA13 T3 B8 VMB_DQ60 VMB_MA13 T3 B8 VMB_DQ41
T7 A3 VMB_DQ30 T7 A3 VMB_DQ8 T7 A3 VMB_DQ59 T7 A3 VMB_DQ44
M7 A14 DQU7 M7 A14 DQU7 M7 A14 DQU7 M7 A14 DQU7
A15 +1.5V_GPU A15 +1.5V_GPU A15 +1.5V_GPU A15 +1.5V_GPU
VMB_BA0 M2 B2 VMB_BA0 M2 B2 VMB_BA0 M2 B2 VMB_BA0 M2 B2

20 VMB_BA0 BA0 VDD#B2 BA0 VDD#B2 BA0 VDD#B2 BA0 VDD#B2
VMB_BA1 N8 D9 VMB_BA1 N8 D9 VMB_BA1 N8 D9 VMB_BA1 N8 D9
20 VMB_BA1 M3 BA1 VDD#D9 G7 M3 BA1 VDD#D9 G7 M3 BA1 VDD#D9 G7 M3 BA1 VDD#D9 G7
VMB_BA2 VMB_BA2 VMB_BA2 VMB_BA2
20 VMB_BA2 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7
K2 K2 K2 K2
VDD#K2 K8 VDD#K2 K8 VDD#K2 K8 VDD#K2 K8
VDD#K8 N1 VDD#K8 N1 VDD#K8 N1 VDD#K8 N1
VMB_CLK0 J7 VDD#N1 N9 VMB_CLK0 J7 VDD#N1 N9 VMB_CLK1 J7 VDD#N1 N9 VMB_CLK1 J7 VDD#N1 N9
20 VMB_CLKP0 K7 CK VDD#N9 R1 K7 CK VDD#N9 R1 20 VMB_CLKP1 K7 CK VDD#N9 R1 K7 CK VDD#N9 R1
VMB_CLK0# VMB_CLK0# VMB_CLK1# VMB_CLK1#
20 VMB_CLKN0 CK VDD#R1 CK VDD#R1 20 VMB_CLKN1 CK VDD#R1 CK VDD#R1
VMB_CKE0 K9 R9 VMB_CKE0 K9 R9 VMB_CKE1 K9 R9 VMB_CKE1 K9 R9
20 VMB_CKE0 CKE VDD#R9 CKE VDD#R9 20 VMB_CKE1 CKE VDD#R9 CKE VDD#R9
+1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU
VMB_ODT0 K1 A1 VMB_ODT0 K1 A1 VMB_ODT1 K1 A1 VMB_ODT1 K1 A1

20 VMB_ODT0 L2 ODT VDDQ#A1 A8 L2 ODT VDDQ#A1 A8 20 VMB_ODT1 L2 ODT VDDQ#A1 A8 L2 ODT VDDQ#A1 A8
VMB_CS0# VMB_CS0# VMB_CS1# VMB_CS1#
20 VMB_CS0# CS VDDQ#A8 CS VDDQ#A8 20 VMB_CS1# CS VDDQ#A8 CS VDDQ#A8
VMB_RAS0# J3 C1 VMB_RAS0# J3 C1 VMB_RAS1# J3 C1 VMB_RAS1# J3 C1
20 VMB_RAS0# K3 RAS VDDQ#C1 C9 K3 RAS VDDQ#C1 C9 20 VMB_RAS1# K3 RAS VDDQ#C1 C9 K3 RAS VDDQ#C1 C9
VMB_CAS0# VMB_CAS0# VMB_CAS1# VMB_CAS1#
20 VMB_CAS0# CAS VDDQ#C9 CAS VDDQ#C9 20 VMB_CAS1# CAS VDDQ#C9 CAS VDDQ#C9
VMB_WE0# L3 D2 VMB_WE0# L3 D2 VMB_WE1# L3 D2 VMB_WE1# L3 D2
20 VMB_WE0# WE VDDQ#D2 WE VDDQ#D2 20 VMB_WE1# WE VDDQ#D2 WE VDDQ#D2
E9 E9 E9 E9
VDDQ#E9 F1 VDDQ#E9 F1 VDDQ#E9 F1 VDDQ#E9 F1
VMB_RDQS0 F3 VDDQ#F1 H2 VMB_RDQS2 F3 VDDQ#F1 H2 VMB_RDQS4 F3 VDDQ#F1 H2 VMB_RDQS6 F3 VDDQ#F1 H2
VMB_RDQS3 C7 DQSL VDDQ#H2 H9 VMB_RDQS1 C7 DQSL VDDQ#H2 H9 VMB_RDQS7 C7 DQSL VDDQ#H2 H9 VMB_RDQS5 C7 DQSL VDDQ#H2 H9
DQSU VDDQ#H9 DQSU VDDQ#H9 DQSU VDDQ#H9 DQSU VDDQ#H9
VMB_DM0 E7 A9 VMB_DM2 E7 A9 VMB_DM4 E7 A9 VMB_DM6 E7 A9

VMB_DM3 D3 DML VSS#A9 B3 VMB_DM1 D3 DML VSS#A9 B3 VMB_DM7 D3 DML VSS#A9 B3 VMB_DM5 D3 DML VSS#A9 B3
C C
DMU VSS#B3 E1 DMU VSS#B3 E1 DMU VSS#B3 E1 DMU VSS#B3 E1
VSS#E1 G8 VSS#E1 G8 VSS#E1 G8 VSS#E1 G8
VMB_WDQS0 G3 VSS#G8 J2 VMB_WDQS2 G3 VSS#G8 J2 VMB_WDQS4 G3 VSS#G8 J2 VMB_WDQS6 G3 VSS#G8 J2
VMB_WDQS3 B7 DQSL VSS#J2 J8 VMB_WDQS1 B7 DQSL VSS#J2 J8 VMB_WDQS7 B7 DQSL VSS#J2 J8 VMB_WDQS5 B7 DQSL VSS#J2 J8
DQSU VSS#J8 M1 DQSU VSS#J8 M1 DQSU VSS#J8 M1 DQSU VSS#J8 M1
VSS#M1 M9 VSS#M1 M9 VSS#M1 M9 VSS#M1 M9
VSS#M9 P1 VSS#M9 P1 VSS#M9 P1 VSS#M9 P1
MEM_RST# T2 VSS#P1 P9 MEM_RST# T2 VSS#P1 P9 MEM_RST# T2 VSS#P1 P9 MEM_RST# T2 VSS#P1 P9
20 MEM_RST# RESET VSS#P9 T1 RESET VSS#P9 T1 RESET VSS#P9 T1 RESET VSS#P9 T1
VMB_ZQ1 L8 VSS#T1 T9 VMB_ZQ2 L8 VSS#T1 T9 VMB_ZQ3 L8 VSS#T1 T9 VMB_ZQ4 L8 VSS#T1 T9
ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9
B1 B1 B1 B1
VSSQ#B1 B9 VSSQ#B1 B9 VSSQ#B1 B9 VSSQ#B1 B9
R73 VSSQ#B9 D1 R524 VSSQ#B9 D1 R506 VSSQ#B9 D1 R93 VSSQ#B9 D1
VSSQ#D1 D8 VSSQ#D1 D8 VSSQ#D1 D8 VSSQ#D1 D8
EV@240/F_4 VSSQ#D8 EV@240/F_4 VSSQ#D8 EV@240/F_4 VSSQ#D8 EV@240/F_4 VSSQ#D8
E2 E2 E2 E2
J1 VSSQ#E2 E8 J1 VSSQ#E2 E8 J1 VSSQ#E2 E8 J1 VSSQ#E2 E8
L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9
J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1
L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9
NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9
100-BALL 100-BALL 100-BALL 100-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
SP@VRAM_DDR3 SP@VRAM_DDR3 SP@VRAM_DDR3 SP@VRAM_DDR3
BOT Down TOP Down TOP Up BOT Up
Group-B0 VREF Group-B1 VREF

+1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU
B B
R76 R67 R523 R528 R516 R521 R105 R142

EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4
VREFC_VMB1 VREFD_VMB1 VREFC_VMB2 VREFD_VMB2 VREFC_VMB3 VREFD_VMB3 VREFC_VMB4 VREFD_VMB4
R75 C136 R63 C104 R525 C731 R529 C742 R511 C709 R522 C726 R109 C219 R141 C281
EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4
EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4
Group-B0 decoupling CAP Group-B1 decoupling CAP MEM_B1 CLK

MEM_B0 CLK
+1.5V_GPU +1.5V_GPU
VMB_CLK1
VMB_CLK0 VMB_CLK1#
C733 C95 C751 C748 C57 C151 C301 C752 C203 C698 C70 C211 C78 C137 C708 C707
VMB_CLK0# EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4
EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 R108 R113
EV@56.2/F_4
R66 R65 EV@56.2/F_4
EV@56.2/F_4 +1.5V_GPU +1.5V_GPU
EV@56.2/F_4
A C222 A
C728 C194 C58 C750 C718 C63 C56 C300 C746 C696 C684 C296 C716 C717 C268 C744 EV@0.01u/16V_4
C116 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4
EV@0.01u/16V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4
+1.5V_GPU +1.5V_GPU

C729 C60 C82 C743 C749 C289 C134 C745 C685 C683
EV@10u/6.3V_6 EV@10u/6.3V_6 EV@10u/6.3V_6 EV@10u/6.3V_6 EV@10u/6.3V_6 EV@10u/6.3V_6
EV@10u/6.3V_6 EV@10u/6.3V_6 EV@10u/6.3V_6 EV@10u/6.3V_6 PROJECT : ZQ5
1A
MEMORY 2 channel B
5 4 3 2 1
1 2 3 4 5 6 7 8
CRT Switch
IV@ --> iGPU only
EV@ --> dGPU only
CRT
12/29 Modify
F2
C791
updatefootprint 4/19 ZQ2
.1u/10V_4 25
1 2 +5V_CRT CRTVDD5
16
+5V
D33 SSM22LLPT CN20
SMD1206P110TFT CRT
6
VGA_RED L3 BK1608LL680_6 CRT_R1 1 11 CRT_11 T1
7
INT_CRT_RED R424 IV@0_4 VGA_RED VGA_GRN L2 BK1608LL680_6 CRT_G1 2 12 DDCDAT_1
7 INT_CRT_RED 8
INT_CRT_GRN R422 IV@0_4 VGA_GRN
7 INT_CRT_GRN 3 13
INT_CRT_BLU R423 IV@0_4 VGA_BLU VGA_BLU L1 BK1608LL680_6 CRT_B1 CRTHSYNC
iGPU 7
7
7
INT_CRT_BLU
INT_VSYNC
INT_HSYNC
INT_VSYNC
INT_HSYNC
R434
R435
IV@0_4
IV@0_4
VSYNC
HSYNC REV:B 9
4 14 CRTVSYNC
INT_CRT_DDCDAT R427 IV@0_4 CRTDDATA R4 R3 R2 C7 C6 C5 C1 C2 C3 10
A
only 7 INT_CRT_DDCDAT
INT_CRT_DDCCLK R428 IV@0_4 CRTDCLK 6/14 5 15 DDCCLK_1
A
7 INT_CRT_DDCCLK
150/F_4 150/F_4 150/F_4 5p/50V_4 5p/50V_4 5p/50V_4 5p/50V_4 5p/50V_4 5p/50V_4
17
R553 10K_4 +3V
D32 BAS316 CRT_SEN#
4/16 35 CRT_SENSE#
EV_CRT_RED R433 EV@0_4 VGA_RED R1 *0_4 4/14 Modify
19 EV_CRT_RED
EV_CRT_GRN R431 EV@0_4 VGA_GRN C4 2.2u/6.3V_6
dGPU 19
19
19,23
EV_CRT_GRN
EV_CRT_BLU
EV_VSYNC
EV_CRT_BLU
EV_VSYNC
R432
R455
EV@0_4
EV@0_4
VGA_BLU
VSYNC
+3V
EV_HSYNC R456 EV@0_4 HSYNC
only 19,23
19
EV_HSYNC
EV_CRTDDAT
EV_CRTDDAT
EV_CRTDCLK
R436
R437
EV@0_4
EV@0_4
CRTDDATA
CRTDCLK
C8
CRTVDD5 1
U33
16 CRT_VSYNC2 R11 15_4 CRTVSYNC C779 *.1u/10V_4 CRTVDD5
19 EV_CRTDCLK VCC_SYNC SYNC_OUT2 14
.1u/10V_4 CRT_HSYNC2 R14 15_4 CRTHSYNC
7 SYNC_OUT1 C11 *10p/50V_4 CRTVSYNC
CRT_BYP 8 VCC_DDC
C786 0.22u/25V_6 BYP 15 VSYNC CRTVDD5 C15 *10p/50V_4 CRTHSYNC
2 SYNC_IN2 13 HSYNC REV:B +3V
+3V VCC_VIDEO SYNC_IN1 C774 10p/50V_4 DDCCLK_1
C9 6/14 R545 R547
CRT_R1 3 10 CRTDCLK R21 2.7K_4 C777 10p/50V_4 DDCDAT_1
.1u/10V_4 CRT_G1 4 VIDEO_1 DDC_IN1 11 CRTDDATA R22 2.7K_4 2.7K_4 2.7K_4
CRT_B1 5 VIDEO_2 DDC_IN2
VIDEO_3 9 DDCCLK_1
6 DDC_OUT1 12 DDCDAT_1
GND DDC_OUT2
CM2009-02QR
LCD_ON (LCD Power)

B
LVDS iGPU only 5/11 Swap net +3V INVCC0 Stuff R713 on 2 CH. B
+3V +5V
Stuff R712 on 1 CH.
INT_TXLCLKOUT- RN24 3 4 IV@0_4P2R TXLCLKOUT- C725 C724 C121 C167 R147 R152
7 INT_TXLCLKOUT- 1 2
INT_TXLCLKOUT+ TXLCLKOUT+ 4/20 Modify
7 INT_TXLCLKOUT+ 1 2
INT_TXLOUT0- RN21 IV@0_4P2R TXLOUT0- .1u/10V_4 1000p/50V_4 4.7u/25V_8 1000p/50V_4
7 INT_TXLOUT0- 3 4
INT_TXLOUT0+ TXLOUT0+ 0_6 *0_1206 U8
7 INT_TXLOUT0+ 1 2
INT_TXLOUT1- RN22 IV@0_4P2R TXLOUT1-
7 INT_TXLOUT1- 3 4 6 1
INT_TXLOUT1+ TXLOUT1+ LCDVCC
7 INT_TXLOUT1+ 1 2 IN OUT
INT_TXLOUT2- RN23 IV@0_4P2R TXLOUT2-
7 INT_TXLOUT2- 3 4 4 2
INT_TXLOUT2+ TXLOUT2+ LCDVCC_R
7 INT_TXLOUT2+ 1 2 IN GND
INT_LVDS_EDIDDATA RN7 IV@0_4P2R LCD_EDIDDATA C254 C174 C201 C202 C175
7 INT_LVDS_EDIDDATA 3 4 3 5
INT_LVDS_EDIDCLK LCD_EDIDCLK R98 *0_8 LCDVCC C302 LVDS_VDDEN
7 INT_LVDS_EDIDCLK ON/OFF GND *.1u/10V_4 *2.2u/10V_8 .1u/10V_4 0.01U/25V_4 22u/6.3V_8
5/6 Modify 1U/6.3V_4
C231 C250 AAT4280-4
4/29 Modify it R130
*1000p/50V_4 *1000p/50V_4
100K_4
5/5 Add Item QCI P/N
AAT AL004280001
dGPU only 5/11 Swap net R117 EV@0_4
19 EV_LVDS_VDDEN
CN14
INVCC0 1 R116 IV@0_4 LVDS_VDDEN GMT AL005243001
1 2 +3V 2 1 7 INT_LVDS_DIGON
EV_TXLCLKOUT- RN28 EV@0_4P2R TXLCLKOUT-
19 EV_TXLCLKOUT- 3 4 3 2
EV_TXLCLKOUT+ TXLCLKOUT+ LCDVCC_L
19 EV_TXLCLKOUT+ 3 4 4 3
EV_TXLOUT0- RN25 EV@0_4P2R TXLOUT0-
19 EV_TXLOUT0- 1 2 5 4
EV_TXLOUT0+ TXLOUT0+
19 EV_TXLOUT0+ 3 4 6 5
EV_TXLOUT1- RN26 EV@0_4P2R TXLOUT1-
19 EV_TXLOUT1- 1 2 7 6
EV_TXLOUT1+ TXLOUT1+ R515 2.2K_4 LCD_EDIDCLK
19
19
EV_TXLOUT1+
EV_TXLOUT2-
EV_TXLOUT2-
EV_TXLOUT2+
RN27 3
1
4
2
EV@0_4P2R TXLOUT2-
TXLOUT2+
R510 2.2K_4 LCD_EDIDDATA 8
9
7
8
Backlight Control
19 EV_TXLOUT2+ 3 4 10 9
EV_LVDS_DDCDAT RN6 EV@0_4P2R LCD_EDIDDATA TXLOUT0-
19 EV_LVDS_DDCDAT 1 2 11 10
EV_LVDS_DDCCLK LCD_EDIDCLK TXLOUT0+
19 EV_LVDS_DDCCLK 12 11
TXLOUT1- 13 12
4/29 Modify it TXLOUT1+ 14 13
15 14
C 15 C
TXLOUT2- 16
TXLOUT2+ 17 16
18 17
TXLCLKOUT- 19 18
TXLCLKOUT+ 20 19
21 20 +3V
USBP11-_R 22 21
USBP11+_R 23 22 34
24 23 34
25 24
CCD_PWR 26 25 33
Brightness 27
28
26
27
33
32
32 R191
LVDS_BRIGHT L55 LVDS_BRIGHT_R 29 28 31 R167 10K_4

VIN BL_ON 30 29 31 BL_ON D10 2 1 BAS316
2A 30 LID591# 14,35
R454 *EV@0_4 LVDS_BRIGHT SBY100505T-121Y-N 10K_4
19 EV_LVDS_BRIGHT
3
R72 *0_8 INVCC0 LVDS
R453 IV@0_4 R71 *0_8
7 L_BKLT_CTRL
3
R452 EV@0_4 C115 C177 BL# 2
35 CONTRAST 5/21 change Connector 2
EC_FPBACK# 35
3
*1000p/50V_4 *1000p/50V_4 Q9
2N7002D Q10
DTC144EU
1
LVDS_BLON 2
R168 Q8
2N7002D
100K_4
CCD
1
R146 *0_8 CCD_PWR
+3V
C274 C700
5/6 Modfiy
Lid Switch (HSR) *1000p/50V_4 *1000p/50V_4
+3VPCU
+3VPCU
C342 1u/10V_4 Close to USB
D R193 R174 EV@0_4 D
19 EV_LVDS_BLON
1
RN8 0_4P2R
*470K_4 3 4 USBP11-_R R177 IV@0_4 LVDS_BLON
LID591# 2 13 USBP11- 1 2 USBP11+_R 7 INT_LVDS_BLON
HE1
13 USBP11+
PT3661-BB
SOT23_123-2_8-1_9 L17
4 3
3
1 4 3 2
PT3661-BB (PLC) : AL003661003 1 2
ME268-002 (FCE) : AL000268000
*DLW21HN900SQ2L
5/24 Modify it
4/22 add it 352-(&7=4
4XDQWD&RPSXWHU,QF
1A
CRT/LVDS/CAMERA/LID
1 2 3 4 5 6 7 8
5 4 3 2 1
26
HDMI_MB_HP
iGPU HDMI LEVEL SHIFTER MB_HDMI_DDCDATA +3V
MB_HDMI_DDCCLK
IV@ --> iGPU only +3V R26 *IV@4.7K_4 HDMI_HPD_EC#
EV@ --> dGPU only DDCBUF_EN OE# control for +3V

CFG R542 To dGPU HPD
+3V +3V power saving EV@10K_4
REV:B Active Buffer
6/15 R15
HDMI_HP_EV 19
3
U1 10K_4
4/20 Modify
36
35
34
33
32
31
30
29
28
27
26
25
REV:B
HPD_SINK
SDA_SINK
SCL_SINK
GND
VCC
DDC_EN
GND
GND
VCC
CCT2
CCT1
OE#
HDMI_HPD_EC# 2
D
+3V from MCH 4/20 6/15 35 HDMI_HPD_EC# D
3
37 24 Q28
HDMITX0_P 38 GND GND 23 MB_HDMITX0P EV@2N7002D
HDMITX0_N 39 IN_D1- OUT_D1- 22 MB_HDMITX0N
1
C771 C26 C27 C16 C19 40 IN_D1+ OUT_D1+ 21 HDMI_MB_HP 2
+3V VCC VCC +3V
HDMITX2_P 41 20 MB_HDMITX2P
IV@2.2u/6.3V_6 IV@.1u/10V_4 IV@.1u/10V_4 IV@.1u/10V_4 IV@.1u/10V_4 HDMITX2_N 42 IN_D2- OUT_D2- 19 MB_HDMITX2N
43 IN_D2+ OUT_D2+ 18 Q29
HDMITX1_P 44 GND GND 17 MB_HDMITX1P 2N7002D
1
HDMITX1_N 45 IN_D3- OUT_D3- 16 MB_HDMITX1N
IN_D3+ OUT_D3+ +5V
close to pin2/11/15/21/26/33/40/46 +3V 46 15 +3V R550 *10K_4
+3V HDMICLK_P 47 VCC VCC 14 MB_HDMICLK+
HDMICLK_N 48 IN_D4- OUT_D4- 13 MB_HDMICLK-
49 IN_D4+ OUT_D4+
HPDEN
HPD_S
SDA_S
SCL_S
GND
REXT
TRIM
SDVO I2C Control
GND
GND
GND
VCC
VCC
C780 C42 C43
NC
IV@PS8101T
IV@.1u/10V_4 IV@.1u/10V_4 IV@.1u/10V_4
1
2
3
4
5
6
7
8
9
10
11
12
5/7 Modify part number
For PS8101T +3V
LS_REXT
PC0
PC1 +3V MB_HDMITX2P
+3V from MCH
R7 *IV@100/F_4
R27 IV@4.7K_4 PC0 R25 SP@499/F_4
R28 *IV@4.7K_4 Control by pin4 HPDEN_R MB_HDMITX2N
C R24 SP@4.7K_4 PC1 MB_HDMITX1P C

HDMI_HP_IV# R23 IV@0_4 INT_HDMI_HPD
R32 SP@4.7K_4 DDCBUF_EN R6 *IV@100/F_4 +5V D29 2 1
RB501V-40
R30 *IV@4.7K_4
MB_HDMITX1N
R34 *IV@4.7K_4 CFG
6 SDVO_CTRLDATA
SDVO_CTRLDATA R19 IV@0_4 HDMI_DDCDATA_SW CSP@ HDMI SDVO I2C
For IV: 2.2K ohm
R536
R42 *IV@4.7K_4 MB_HDMITX0P 2.2K_4
6 SDVO_CTRLCLK
SDVO_CTRLCLK R20 IV@0_4 HDMI_DDCCLK_SW 5/24 Add it For ES:4.7K ohm
R8 *IV@100/F_4 Q23
EV@BSN20
MB_HDMITX0N
Equalization Control 1 3 MXM_DDCCK R535 EV@0_4 MB_HDMI_DDCCLK R548 *SHORT_6 HDMI_DDCCLK_MB
19 MXM_DDCCK_C
PC0 internal PD 5/7 Add +3V MB_HDMICLK+
PC1 PC0 PC1 internal PD
PIN4 PIN3 EQ Control R5 *IV@100/F_4 R568 +5V D30 2 1
RB501V-40 C787
2
DDCBUF_EN internal PD HP-detect for EV@10K_4
L L 8dB R532 MB_HDMICLK- *.1u/10V_4
L H 4dB
CFG
DDC_EN
internal PD
internal PU
PS8101 only *IV@20K/F_6 +3V
CSP@ HDMI SDVO I2C
For IV: 2.2K ohm
R537
H L 12dB 2.2K_4
H H 0dB HDMI_HP_IV# R92 *short0402 PEG_RXP3 PEG_RXP3 7,18 R569 For ES:4.7K ohm
2
EV@10K_4
3
Item QCI P/N

SP@SN75DP139 1 3 MXM_DDCDAT R538 EV@0_4 MB_HDMI_DDCDATA R549 *SHORT_6 HDMI_DDCDATA_MB
19 MXM_DDCDAT_C
1.Pin34 HPDINV for 8101T Stuff R32 INT_HDMI_HPD 2 R533 PS8101TQFN48GTR AL008101001 Q24
2.Stuff R24 *IV@7.5K/F_4 EV@BSN20 C788
3.R25 change 3.9K (CS23902FB14) Q26
*IV@DMN601K-7 PS8101QFN48GTR AL008101000 *.1u/10V_4
1
SN75DP139RGZR AL000139000
B B
GPU Switchable Graphic HDMI source HDMI connector updatefootprint 4/19 ZQ2
Close to HDMI connector
From Discrete 6/15 Swap CN21 1/11 Add C928 by EMI.
20
RN36 1 2 EV@0_4P2R MB_HDMITX0N MB_HDMITX2P 1 SHELL1 22
19 HDMITX0N D2+ SHELL3 +3V
3 4 MB_HDMITX0P 2
19 HDMITX0P D2 Shield
MB_HDMITX2N 3
RN34 1 2 EV@0_4P2R MB_HDMITX1N MB_HDMITX1P 4 D2-
19 HDMITX1N D1+
3 4 MB_HDMITX1P 5
To Discrete 19 HDMITX1P
MB_HDMITX1N 6 D1 Shield
D1-
RN35 1 2 EV@0_4P2R MB_HDMITX2N MB_HDMITX0P 7 C781
19 HDMITX2N D0+
3 4 MB_HDMITX2P 8 2200p/50V_4
19 HDMITX2P D0 Shield
MB_HDMITX0N 9
RN33 1 2 EV@0_4P2R MB_HDMICLK- MB_HDMICLK+ 10 D0-
19 HDMICLK- CK+
3 4 MB_HDMICLK+ 11
19 HDMICLK+ 12/29 Modify MB_HDMICLK- 12 CK Shield
13 CK-
R563 EV@499/F_4 MB_HDMITX0N +5V 14 CE Remote
R564 EV@499/F_4 MB_HDMITX0P From GMCH (iHDMI) HDMI_DDCCLK_MB 15 NC
DDC CLK
R560 EV@499/F_4 MB_HDMITX1P PEG_TXP2 RN5 1 2 IV@0_4P2R HDMITX0_P F1 HDMI_DDCDATA_MB 16
7,18 PEG_TXP2 DDC DATA
R559 EV@499/F_4 MB_HDMITX1N PEG_TXN2 3 4 HDMITX0_N 17
7,18 PEG_TXN2 GND
R562 EV@499/F_4 MB_HDMITX2N 1 2 +5V_HDMI_D D1 SSM22LLPT +5V_HDMI 18
R561 EV@499/F_4 MB_HDMITX2P PEG_TXP1 RN3 1 2 IV@0_4P2R HDMITX1_P HP_DET 19 +5V 23
7,18 PEG_TXP1 HP DET
SHELL4
R557 EV@499/F_4 MB_HDMICLK- PEG_TXN1 3 4 HDMITX1_N SMD1206P110TFT 21
7,18 PEG_TXN1 SHELL2
R558 EV@499/F_4 MB_HDMICLK+
PEG_TXP0 RN4 1 2 IV@0_4P2R HDMITX2_P QJ1119C-NK01-8F
A 7,18 PEG_TXP0 A
3
PEG_TXN0 3 4 HDMITX2_N HDMI_MB_HP R565 *SHORT_4

7,18 PEG_TXN0
Q1 PEG_TXP3 RN2 1 2 IV@0_4P2R HDMICLK_P
7,18 PEG_TXP3
+5V 2 PEG_TXN3 3 4 HDMICLK_N R556
7,18 PEG_TXN3
100K_4
352-(&7=4
R10 EV@2N7002D 5/11 Swap
EV@100K_4
4/29 Modify
1
Close to NB couple cap & PCIE RESARRAY 4XDQWD&RPSXWHU,QF

1A
HDMI (PS8101)
5 4 3 2 1
5 4 3 2 1
SATA HDD(HDD) SATA ODD(ODD)

CN6
GND23
GND1
RXP
23
1
2
3
SATA_TXP0 12
27
RXN SATA_TXN0 12
4
GND2 5 SATA_RXN0_C C508 0.01u/16V_4
TXN SATA_RXN0 12
D 6 SATA_RXP0_C C513 0.01u/16V_4 SATA_RXP0 12 CN5 D
TXP 7 14
GND3 GND14
1
8 GND1 2
3.3V RXP SATA_TXP1 12
9 5/11 Modify 3
3.3V RXN SATA_TXN1 12
10 4
3.3V 11 GND2 5 SATA_RXN1_C C529 0.01u/16V_4
GND For ESD TXN SATA_RXN1 12 5/5 Modify
12 U13 6 SATA_RXP1_C C525 0.01u/16V_4 SATA_RXP1 12
GND 13 *CM1293A-04SO TXP 7
GND 14 SATA_TXN0 1 6 SATA_RXN0_C GND3 Power/Suspend: Green/Amber
5V
5V
15
16 2
CH1 CH4
5 8 SATA_DP R305 *1K_4
LED(UIF) LED1
5V 17
+5V VN VP +5V DP 9 R212 330_4 4 1
Power LED
GND 18 120mil SATA_TXP0 3 4 SATA_RXP0_C +5V 10
+5V
For ESD
35 SUSLED#
RSVD CH2 CH3 +5V +3V_S5
19 11 U14 R215 330_4 3 2
GND RSVD 35 PWRLED#
20 12 *CM1293A-04SO
12V 21 GND 13 SATA_RXP1_C 1 6 SATA_TXP1 LED_A/B
12V +3V GND CH1 CH4 4/22 modify
22
12V C499 C354 C314 15 2 5
24 GND15 VN VP +5V
R220 330_4 4
LED2
1
Battery LED
GND24 35 BATLED1#
*4.7u/6.3V_6 *4.7u/6.3V_6 *0.1u/16V_4 C18534-11305-L SATA_RXN1_C 3 4 SATA_TXN1
CH2 CH3 +3VPCU
SATA_HDD R232 330_4 3 2
35 BATLED0#
R226 *1M_6
C 5/4 change footprint (ZQ2) LED_A/B
C
+5V +5V
120mil R229 *1M_6
4/28 Add WiFi LED
+
+
C506 C514 C512 C511 C510 C509 C526 C527 C528 C524 C523 C522 28 WLAN_LED# D15 AMBER R249 182/F_4 4/29 change to amber
4.7u/6.3V_6 0.1u/16V_4 0.1u/16V_4 0.01u/16V_4 0.01u/16V_4 10u/6.3V_8 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4
4/28 DEL CAPS and NUM LED
EV@100u/6.3V_3528 EV@100u/6.3V_3528 +3V
+3V SATA_LED#_R D13 Bule R246 182/F_4

5/12 UMA no stuff R243 U9
5/12 UMA no stuff DEL D2 4/29
TC7SH08FU
5
10K_4 1 D8 Bule R61 182/F_4

4 SATA_LED#_R D1 Power LED near PW SW
2
12 SATA_LED#
3
Modify it 4/26
R244 *0_4
B B
FAN(THM) TP CONN 25mil
R302 4.7K_4 R301 0_6 TP_VCC
+5V +5V
R304 4.7K_4 C515 0.1u/16V_4 CN4
1
2
+3V L40 BK1608LL121_6_150mA TPDATA_R 3
35 TPDATA
L41 BK1608LL121_6_150mA TPCLK_R 4
35 TPCLK
5
C518 C520 6
R399 TP_RIGHT# 7
10K_4 10p/50V_4 10p/50V_4 8
+5V 9
10 13
35 FANSIG
R405 *0805 11 14
TP_LEFT# D11 1 2 *Uclamp0511P_4_ESD TP_LEFT# 12
U22
30 MIL CN12
C630 2.2u/6.3V_6 2 3 TH_FAN_POWER Aces88501-120N
VIN VO 5 1 TP_RIGHT# D16 1 2 *Uclamp0511P_4_ESD
1 GND 6 2 4
3 THER_OVERT# FON# GND 3 5
7 C633 C636 C628
PWM_FAN1 R402 0_4 4 GND 8 0.01u/16V_4 SW3 SW2
35 PWM_FAN1 FAN
VSET GND 22u/6.3V_8 1000p/50V_4
A
G991 TP_RIGHT# 3 2 TP_LEFT# 3 2 4/30 update footprint ZQ9 A
1 4 1 4
5 5
352-(&7=4
change footpirnt as SA6 6 6
FANPWR = 1.6*VSET 4/23
4XDQWD&RPSXWHU,QF
MISAKI_SW_H1.5 MISAKI_SW_H1.5

1A
HDD/ODD/LED/SW/TP/FAN/MMB
5 4 3 2 1
1 2 3 4 5 6 7 8
28
R275 *0_6
Bluetooth
MINI-CARD(MPC) 4/21 change footprint andy(ZYD) H=7.0
(BTM-3.0)
+3V
1 3 BT_POWER
PLO
+3VSUS
Q14 AO3413 C480
+1.5V +3V
2
CN15 4.7u/6.3V_6
51 52 R276 *short0402
49 Reserved +3.3V 50 35 BT_POWERON# CON5_BT_L
47 Reserved GND 48
13 PCIRST# Reserved +1.5V Close to USB
45 46 5
2 PCLK_DEBUG 43 Reserved LED_WPAN# 44 WLAN_LED# 4 5
RN11 0_4P2R
+3V_MINI_R_A 41 Reserved LED_WLAN# 42 WLAN_LED# 27 3 4 USBP3+_R 3 4
+3V R94 *0_6
39 Reserved LED_WWAN# 40 13 USBP3+ 1 2 2 3 7
TV use +3V USBP3-_R
A 37 Reserved GND 38 13 USBP3- 1 2 7 6 A
C176 *0.1u/16V_4 T85 BT_LED
35 Reserved USB_D+ 36 USBP4+ 13 1 6
L35
33 GND USB_D- 34 USBP4- 13 4 3
13 PCIE_TXP4 31 PETp0 GND 32 MINI_SMDATA 1 4 3 2 CN8
C532
13 PCIE_TXN4 29 PETn0 SMB_DATA 30 1 2
MINI_SMCLK *0.01u/16V_4
27 GND SMB_CLK 28 *DLW21HN900SQ2L
25 GND +1.5V 26
13 PCIE_RXP4 23 PERp0 GND 24
13 PCIE_RXN4 21 PERn0 +3.3Vaux 22
5/22 SWAP net Modify follow ZQ1 5/5
19 GND PERST# 20 PLTRST# 13,31,33,35
RF_EN
17 Reserved Reserved 18 RF_EN 35
Reserved GND
15 16 R572 *0_6
13 GND Reserved 14 LFRAME# 12,35 Bluetooth +3V
2 CLK_PCIE_MINI1 REFCLK+ Reserved LAD3 12,35
2 CLK_PCIE_MINI1#
11
9 REFCLK- Reserved
12
10 LAD2 12,35 (BTM-2.1) 1 3 BT_POWER_1
PLO
2 MINI_CLKREQ# 7 GND Reserved 8 LAD1 12,35 +3VSUS
+5V_TV-CARD 5 CLKREQ# Reserved 6 LAD0 12,35
R520 *0_6 +5V_TV-CARD_R_A Q30 AO3413 C792
R519 *0_6 +5V_TV-CARD_R_B 3 Reserved +1.5V 4
TV use +5V
2
1 Reserved GND 2 4.7u/6.3V_6
53 WAKE# +3.3V 54 BT_POWERON# R573 *short0402
PCIE_WAKE_WL_R_# PAD53 PAD54 CON5_BT_L
MINICARD_A Close to USB
5
4 5
RN37 1 2 0_4P2R USBP7+_R 3 4
C147 R89 For EMI 13 USBP7+ 3 4 USBP7-_R 2 3 7
PCLK_DEBUG 13 USBP7- BT_LED_1 1 2 7 6
T151
+3VSUS L69 1 6
1 2
*10p/50V_4 *22_4 4 1 2 3 C793 CN22
R99 4 3 *0.01u/16V_4
2
B *DLW21HN900SQ2L B
Q4 4.7K_4
*DTC144EUA Modify 6/15

3 1 PCIE_WAKE_WL_R_# R81
14,31 PCIE_WAKE# REV:B
+3V
10K_4
2
3 1 MINI_SMDATA EXT. USB(USB) +5VPCU
2,14,16 PDAT_SMB
+5V
P$PLO +1.5V Q3
DMN601K-7
PLO CN7
R508 *0_6 +5V_TV-CARD C531 10u/10V_8
R80 *0_4 16 18
C712 C715 C149 C736 C737 C530 1u/10V_4 15 17
R79 14
*4.7u/6.3V_6 *0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 4.7u/6.3V_6 13
+3V 12
4/22 add it 13 USBOC#6 11
2
10K_4
10
3 1 MINI_SMCLK USBP2-_R 9
2,14,16 PCLK_SMB USBP2+_R 8
Q2
DMN601K-7 7
6
R78 *0_4 USBP0-_R 5
+3V USBP0+_R 4
3
2
35 USBON# 1
C738 C131 C740 C739 C735 C741 C145 USB_DBFFCCONN
C 4.7u/6.3V_6 4.7u/6.3V_6 *4.7u/6.3V_6 *4.7u/6.3V_6 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 C
5/11 update footprint
Close to USB 5/22 SWAP net

RN13 0_4P2R
USBP2- 3 4 USBP2-_R
13 USBP2- USBP2+ 1 2 USBP2+_R
13 USBP2+
L39
PLO 4
1 4 3
3
2
INT. USB(USB) updatefootprint 4/19 ZQ2 1 2
USBPWRP1 L5 USBPWR1 *DLW21HN900SQ2L
Close to USB TI201209G121_8_3A
CN18 + C775
RN1 0_4P2R 1 8
3 4 USBP6-_R 2 1 8 7 100U/25V_6.3X5.8
13 USBP6- 1 2 3 2 7 6
USBP6+_R C10 + C21 Close to USB
13 USBP6+ 4 3 6 5 C18
L4 4 5 470p/50V_4 *470p/50V_4 RN12 0_4P2R
4 3 USB_MB *100u/6.3V_3528 USBP0- 1 2 USBP0-_R
1 4 3 2 13 USBP0- 3 4
USBP0+ USBP0+_R
1 2 13 USBP0+
*DLW21HN900SQ2L L38
1 2
Item QCI P/N 4 1 2 3
5/22 SWAP net 4 3
*DLW21HN900SQ2L
D D
GMT AL000547000 4/29 Modify it
C17 10u/10V_8
+5VPCU U2
G547F2P81U
PLO ROH AL008015K00
2 8 USBPWR1
C25 1u/10V_4 3 IN1 OUT3 7
IN2 OUT2 6 USBP6+ D4 2 1 *PESD5V0U1BL
OUT1
352-(&7=4
USBON# 4
1 EN# USBP6- D3 2 1 *PESD5V0U1BL
GND
4XDQWD&RPSXWHU,QF
9 5 USBOC#10 R17 *6.34K/F_4
GND-C OC#

13 USBOC#10
Add it 4/26 1A
MINI/USB/BT/HOLE
1 2 3 4 5 6 7 8
5 4 3 2 1
Codec(ADO)
HP 30
30
30
HP-R
HP-L
HPOUT_JD
R50
SENSEB
5.1K/F_4
MUTE(AMP)
5/11 Modfiy it
+5VA
C111 C128 C129

C86
29
0.1u/10V_4 0.1u/10V_4
0.1u/10V_4 4.7U/6.3V_6
INSPKR+ R530 36K/F_6
ADOGND
REV:B
11
13
MIC1-VREFO 30
6
U5
ADOGND 6/11 Modify
VCC
VCC
NC
NC
D FRONT-L= (L+R)/2 Place next to pin 27 MONO-OUT C747 0.47u/10V_6 15 D
LIN-
5/11 Del FRONT-R FRONT-L C68 *0.47u/10V_6 FRONT-R-1 R55 33K/F_6 FRONT-R-2 7 5 C81 4.7U/6.3V_6 ADOGND
RIN- BYPASS
Speaker C55 C52 C50 C48 16 12
ADOGND LIN+ RVO1 INSPKR+ 30
FRONT-L
+ +
0.1u/10V_4 10u/6.3V_6 +5VA C69 0.47u/10V_6 FRONT-R+1 R56 33K/F_6 FRONT-R+2 8 9
THERMALPAD
ADOGND RIN+ RVO2 INSPKR- 30
2.2u/6.3V_6 2.2u/6.3V_6
Place next to pin 25 1
LVO1
14 4
SHDN#
VSS
VSS
C44 C41 LVO2
36
35
34
33
32
31
30
29
28
27
26
25
U3 INSPKR- R57 36K/F_6
5/10 Add G1453L
FRONT-L
Sense B
HPOUT-L
CPVEE
CBP
MIC1-VREFO
AVSS1
AVDD1
FRONT-R
HPOUT-R
CBN
VREF
17
10
0.1u/10V_4 10u/6.3V_6 +5V_S5 R85 *100K_4
REV:B R86 *0_4

MONO-OUT 37 24
MONO-OUT LINE1-R T3
ADOGND
6/11 Modify +5V_S5 ADOGND
+5VA 38 23
AVDD2 LINE1-L T2
39 22 MIC1-R
SURR-L MIC1-R MIC1-R 30 U6
5
1
C74 C76
10u/6.3V_6 0.1u/10V_4
ADOGND R53 20K/F_4 40
JDREF MIC1-L
21 MIC1-L
MIC1-L 30
MIC 35 AMP_MUTE#
EAPD# 2
4 R84 0_4
HP_MUTE# 30
41 20 TC7SH08FU C154
3
SURR-R LINE2-VREFO
42 19 MIC2-VREFO R87 *0_4 *4.7u/10V_6
ADOGND
Place next to pin 38
ADOGND
43
AVSS2
ALC272X<LQFP-48> MIC2-VREFO
18
Vender QCI P/N
ANALOG T4 NC LINE1-VREFO
44 17 MIC2_INT_R C40 1U-16V_6 MIC2_INTL1_R R41 1K_4 MIC2_INTL1 GMT AL001453000
DMIC-CLK3/4 MIC2-R
C DIGITAL C
45 16 MIC2_INT_L C39 1U-16V_6
SPDIFO2 MIC2-L
GMT AL001465000
46 15
DMIC-CLK1/2 LINE2-R
Split by DGND 47 14
EAPD
DMIC-1/2/GPIO0
DMIC-3/4/GPIO1
LINE2-L
48 13 SENSEA R39 20K/F_4 MIC1_JD
SDATA-OUT
SPDIFO1 Sense A MIC1_JD 30

EAPD#
SDATA-IN
DVDD-IO
PCBEEP
RESET#
BIT-CLK
DVDD1
DVSS1
DVSS2
SYNC
Split by DGND
ANALOG
1
10
11
12
DIGITAL
1.6Vrms
+3V
PCBEEP C38 1u/10V_6 BEEP_1 R43 47K/F_4
PCSPK 14
C75 C64 C32 R40 REV:B
4.7K_4 6/11
10u/6.3V_6 0.1u/10V_4 100p/50V_4
R570 IV@0_6 +1.5V

Place next to pin 1
R47 EV@0_6 +3V
C54 C53
ACZ_RST#_AUDIO 12
B 0.1u/10V_4 10u/6.3V_6 B
C49
ACZ_SYNC_AUDIO 12
C51 *22p/50V_4 *100p/50V_4
4/29 Add it Place next to pin 9

ACZ_SDIN0_R R49 22_4
ACZ_SDIN0 12
ACZ_SDOUT_AUDIO 12
ACZ_BITCLK_AUDIO 12
C59 22p/50V_4
5/6 modify
Power (ADO) INT MIC 5/7 update the footprint name

DIGITAL ANALOG
+5V L62 UPB201209T-310Y-N/6A/31ohm_8 R31 *0_6 CN1 R77
+5VA R54 *0_6 1 MIC2_INTL1 MIC2-VREFO
U29 R74 *0_6 1 2
3 4 R88 *0_6 2 C132 2.2K_4
IN OUT R534 *0_6
2 R16 *0_6 INT_MIC *22P_4
GND R82 0_6
A A
1 5 R527 *29.4K/F_4 R531 0_6
SHDN SET C13 *1000p/50V_4 5/26 update Mic Partnumber
*G923-330T1UF C34 *1000p/50V_4
R526 + C734 C732 ADOGND
*10K/F_4
10u/10V_3216 0.1u/10V_4
C730 C727 ADOGND C73 0.1u/10V_4
352-(&7=4
+ R83 **0_4
Tied at one point only under
4XDQWD&RPSXWHU,QF
0.1u/10V_4 10u/10V_3216
the codec or near the codec
ADOGND ADOGND
ADOGND cap place close to MIC-connector 1A
C730, C787 close U37 pin3 and L65
REALTEK ALC663&888/MDC
5 4 3 2 1
5 4 3 2 1
30
MIC D2 BAS316
4/21
change footprint (ZQ2)
D5 BAS316
29 MIC1-VREFO
Internal Speaker
Normal OPEN Jack
R29 R543
4.7K/F_4 4.7K/F_4
PINK
1 CN17 7 SPEAKER-CONN
D C30 4.7u/6.3V_6 MIC1_L2 R33 1K/F_4 MIC1_L3 L7 MIC1_L 2 D
29 MIC1-L
BLM15AG121SS1/0.5A/120ohm_4 6 29 INSPKR- R387 0_6 R_SPK-_1 2
C768 4.7u/6.3V_6 MIC1_R2 R541 1K/F_4 MIC1_R3 L67 MIC1_R 3 R386 0_6 R_SPK+_1 1 2
29 MIC1-R 29 INSPKR+ 1
BLM15AG121SS1/0.5A/120ohm_4 MIC1_JD 4
29 MIC1_JD 8 CN11
5
JAS7331-P30H9-7F
C776 C33 C607 C608
Max. 100mVrms input for Mic-IN 470p/50V_4 470p/50V_4
5/5 Modify
*0.22u/25V_6 *0.22u/25V_6
Modify it 5/4
MIC1_JD ADOGND
1
ADOGND
D31
*VPORT_6
ADOGND
C C
29 HP_MUTE#
HP/SPDIF
2
2N7002K Q25
29 HP-L 3 1 HP-L-2
1 CN16 7
HP-L-2 R51 56/F_4 HPL-1 L11 BLM15AG121SS1/0.5A/120ohm_4 HPL_SYS 2
HP-R-2 R45 56/F_4 HPR-1 L9 BLM15AG121SS1/0.5A/120ohm_4 6
HPR_SYS 3 R48 *0_6
29 HPOUT_JD HPOUT_JD 4
R44 R52 C45 C65 8
5
*1K_4 *1K_4 2200p/50V_4 2200p/50V_4 JAS7331-P30H9-7F HP_MUTE#
2
2N7002K Q27
ADOGND 3 1 HP-R-2
29 HP-R
B ADOGND Normal OPEN Jack B
4/29 Modify R46 *0_6
6/18 change it andy

REV:B
HPOUT_JD
1
D6
A *VPORT_6 A
2
ADOGND 352-(&7=4
4XDQWD&RPSXWHU,QF
1A
AMP /AUDIO JACK CONN
5 4 3 2 1
5 4 3 2 1
Giga-LAN BCM57780
+3V_S5
31
U32
15mil
+3V_S5 42 25 BIASVDD L65 BLM18AG601SN1D_6
VDDO BIASVDDH C764 0.1u/10V_4_X7R
6
VAUX_12 VDDC
15 14 XTALVDD L64 BLM18AG601SN1D_6
D 41 VDDC XTALVDDH C761 0.1u/10V_4_X7R D
L6 VDDC
15mil AVDDL 27 30 AVDDH L68 BLM18AG601SN1D_6
VAUX_12 AVDDL AVDDH
C22 4.7U/6.3V_6 33
BLM18AG601SN1D_6 C28 0.1u/10V_4_X7R 39 AVDDL
AVDDL
BCM57780
7mm X 7mm AVDDH
36 C784 0.1u/10V_4_X7R
48-Pin QFN C24 0.1u/10V_4_X7R

L63
15mil GPHY_PLLVDD 24 37
GPHY_PLLVDDL TRD3_N LAN_TRD3N 32
C760 4.7U/6.3V_6 38
TRD3_P LAN_TRD3P 32
BLM18AG601SN1D_6 C763 0.1u/10V_4_X7R
35
TRD2_N LAN_TRD2N 32
L8 34
15mil PCIE_PLLVDD 18 TRD2_P LAN_TRD2P 32
PCIE_PLLVDDL 31
TRD1_N 32 LAN_TRD1N 32
BLM18AG601SN1D_6 C36 4.7U/6.3V_6
TRD1_P LAN_TRD1P 32
C37 0.1u/10V_4_X7R 21
PCIE_PLLVDDL 29
TRD0_N LAN_TRD0N 32
28
TRD0_P LAN_TRD0P 32
48 LAN_LINKLED#
LINKLED# 47 LAN_LINKLED# 32
SPD100LED# 46
SPD1000LED# 45 LAN_ACTLED#
TRAFFICLED# LAN_ACTLED# 32
C762 0.1u/10V_4_X7R PCIE_RXP1_LAN_R 17
13 GLAN_RXP PCIE_TXDP
C759 0.1u/10V_4_X7R PCIE_RXN1_LAN_R 16
13 GLAN_RXN 22 PCIE_TXDN 5
13 GLAN_TXP 23 PCIE_RXDP MODE
13 GLAN_TXN 4 PCIE_RXDN
C 14,28 PCIE_WAKE# WAKE# C
2
13,28,33,35 PLTRST# 20 PERST#
2 CLK_PCIE_LAN 19 PCIE_REFCLK_P
2 CLK_PCIE_LAN# PCIE_REFCLK_N
44 BCM_EEC
EECLK
43 BCM_EED
R13 1K/F_4 VMA_PRES 40 EEDATA VAUX_12
+3V VMAIN_PRSNT
R551 4.7K_4 LOW_PWR 1
LOW_PWR
11 L66 4.7uh
SR_LX 8
Don't route under Choke.
5/19 Modify SR_VFB
C757 27p/50V_4 R539 200_4 XTALO 13
XTALI 12 XTALO 10 +3V_S5
1
XTALI SR_VDDP 9
RDAC 26 SR_VDD
1.2H Y6 R540 1.24K/F_4
RDAC
C12 C20 C46 C47
25MHz 10u/6.3V_6
4.7U/6.3V_6 0.1u/10V_4_X7R 0.1u/10V_4_X7R
2
C758 27p/50V_4
R544 *4.7K_4 3 7
+3V_S5 CLK_REQ# NC
R546 0_4 BCM_CLKREQ#

2 LAN_CLKREQ#
GND
BCM57780
49
B B
LAN POWER EEPROM

+3V_S5
REV:B
6/11
+3V_S5 VAUX_12 20mil
R567 R566
*1K_4 1K_4
C785 4.7U/6.3V_6 C31 4.7U/6.3V_6 U34
BCM_EED 5 1
C766 0.1u/10V_4_X7R C35 0.1u/10V_4_X7R BCM_EEC 6 SDA A0 2
SCL A1 3
C23 0.1u/10V_4_X7R 7 A2
R555 R554 WP
C769 0.1u/10V_4_X7R 1K_4 *1K_4 4 8 +3V_S5
GND VCC
*AT24C02 C790
0.1u/10V_4_X7R
A A
EEPROM Strapping
EEPROM Type EECLK EEDATA
24LC02 1 1
352-(&7=4
Internal 1 0 4XDQWD&RPSXWHU,QF
1A
GLAN BCM57780
5 4 3 2 1
1 2 3 4 5 6 7 8
32
4/27 modify it
TRANSFORMER U31
1 24
LAN_TRD0P 2 TCT1 MCT1 23 X-TX0P
31 LAN_TRD0P TD1+ MX1+
LAN_TRD0N 3 22 X-TX0N
31 LAN_TRD0N TD1- MX1-
C753 C754
4 21
0.1u/10V_4_X7R 0.1u/10V_4_X7R LAN_TRD1P 5 TCT2 MCT2 20 X-TX1P
A 31 LAN_TRD1N TD2- MX2- A
7 18
LAN_TRD2P 8 TCT3 MCT3 17 X-TX2P
C755 C756
10 15
0.1u/10V_4_X7R 0.1u/10V_4_X7R LAN_TRD3P 11 TCT4 MCT4 14 X-TX3P
TRANSFORMER
R35 R36 R37 R38

75/F_8 75/F_8 75/F_8 75/F_8
4/21 change Part number

DB0Z06LAN00 (follow Z08)
C29
1500p/3KV_18
B B
RJ45 Conn For EMI
LAN_TRD0P C765 *10p/50V_4
LAN_TRD0N C767 *10p/50V_4
CN19 LAN_TRD1P C772 *10p/50V_4

LAN_ACTLED# 9
31 LAN_ACTLED# YELLOW_N
C +3V_S5 R18 220_8 LAN_ACT_LED_PWR 10 LAN_TRD1N C770 *10p/50V_4 C
YELLOW_P
14 R9 *0_6 LAN_TRD2P C773 *10p/50V_4
X-TX0P 1 GND2 13 R12 *0_6
X-TX0N 2 0+ GND1 LAN_TRD2N C778 *10p/50V_4
X-TX1P 3 0-
X-TX2P 4 1+ LAN_TRD3P C782 *10p/50V_4
X-TX2N 5 2+
X-TX1N 6 2- LAN_TRD3N C783 *10p/50V_4
X-TX3P 7 1-
X-TX3N 8 3+
3-
LAN_LINKLED# 11
31 LAN_LINKLED# GREEN_N
+3V_S5 R552 220_8 LAN_LNK_LED_PWR 12
GREEN_P
RJ45
LAN_ACTLED#
LAN_LINKLED#
D D
C14 C789
352-(&7=4
*0.1u//50V_8 *0.1u//50V_8
4XDQWD&RPSXWHU,QF
1A
LAN Transformer and RJ45
1 2 3 4 5 6 7 8
A B C D E
CARD READER Controller 2 IN 1 CARD READER (SD/MMC) SD_WP
SD_CD#
33
11
12
4
CN2
SW COM
CD/SW
WP/SW
SD_DAT1 10
SD_DAT0 9 DATA1
8 DATA0
4 SD_CLK 7 VSS2 4
6 CLK
VCC_XD VDD
5
SD_CMD 3 VSS1
CMD
GND1
SD_DAT3 2
GND
SD_DAT2 1 DATA3
5/10 modify DATA2
SD-CARD
13
14
5/10 Del R40001
VCC_XD
C284 C277
Clock input selection 4.7u/10V_6 0.1u/16V_4

'1' for 48MHz input [Default,Internal PU]
'0' for 12MHz input Main DFHS11FR011
C743 close PIN46, 47 Close to CN14 pin 14 & pin23
+1.8V_VDD
C708 close PIN48, 47 Second DFHS11FR033 4.7u CAP close to pin23
+3V_VDD T137
R496 *0_4 XTALSEL C681 C682 T143 5/10 change Card Redaer conn
0.1u/16V_4 0.1u/16V_4 footpirnt sdcard-sdsn09-08-xa-11p-smt
3 3
XTALSEL
CRMD_N
DATA1
DATA0
CTRL1
CTRL3
NBMD
8/14 ZH7 remove R136, R591 and C775 5/10 Modify
R500 *100K_4
48
47
46
45
44
43
42
41
40
39
38
37
+3V_VDD U26
R501 0_4
13,28,31,35 PLTRST#
CTRL0, CRTL 1 trace length shorter ,
GND
VDD
NBMD
VDDHM
TRIST
XTALSEL
CTRL1
CTRL3
DATA1
DATA0
DATA7
DATA6
C686 *0.47u/10V_6 and surround with GND. DATA0 SD_DAT0
+3V R514 0_6 +3V_VDD

C701 1 36 CTRL0 DATA1 SD_DAT1
2 GPON7 CTRL0 35
2 CLK_Card48 EXT48IN DATA5
4.7u/10V_6 3 34 CTRL2
R502 330_4 4 RSTN CTRL2 33 GPI4 DATA2 SD_DAT2
5 REXT GPI4 32 T142
6 VD33P DATA4 31 DATA3
13 USBP1+ DP DATA3
7 AU6437-GBL 30 DATA2 DATA3 SD_DAT3
13 USBP1- DM DATA2
8 29
C702 C704 XI 9 VS33P XDWPN 28 GPI2
XO 10 XI GPI2 27 T147
*5p/50V_4 *5p/50V_4 11 XO XDCEN 26 EEPDATA
+1.8V_VDD VDD EEPDATA
12 25 GPI1 T148
8/14 C707 close PIN11, 12 VDD GPI1 T149
Close to connector
SDWPEN
AGND5V
EEPCLK
CF_V33
VDDHM
XDCDN
VCC33
CTRL4
GND
VDD
V18
V33
2 2
13
14
15
16
17
18
19
20
21
22
23
24
crystal trace width needs at least 10 mils. 8/14 pin13 output 20mils
EEPCLK T150
C705
VCC_XD
C703 *18p/50V_4 XI CTRL0 R143 SD_CLK

4.7u/10V_6 BLM15AG121SS1/0.5A/120ohm_4
Y5 R504 CTRL1 SD_WP C270

*12MHz *270K_4 *10p/50V_4
*0_4 R513
VCC_XD
C706 *18p/50V_4 XO CTRL2 SD_CMD

SD write protect
+1.8V_VDD 1:decided by SDWP[Default]
4/20 Modify 0:letting SD always CTRL3 SD_CD#
+3V_VDD +3V_VDD write-able
C713 C714
4.7u/10V_6 0.1u/16V_4
1 1
352-(&7=4
4XDQWD&RPSXWHU,QF
1A
AU6433 CardReader
A B C D E
5 4 3 2 1
(OTH)
HOLE10
*H-C315D118P2
HOLE4
*H-C315D118P2
HOLE13
*H-C315D118P2
34
1
D D
HOLE12 HOLE16 HOLE8 HOLE17 HOLE9 HOLE6 HOLE7

H-C256D161P2 H-C256D161P2 H-C256D161P2 H-C197D87P2 *H-TC205BC276D146P2 *H-TC205BC276D146P2 *H-TC205BC276D146P2
1
5/21 Modify HOLE15 HOLE5
HG-C315D154P2 *HG-C315D110P2
7 6 7 6
5/25 Modify
8 5 8 5
9 4 9 4
1
2
3
1
2
3
HOLE19 HOLE1 HOLE21 HOLE3 HOLE11 HOLE2
HOLE20 *HG-C315D118P2 *HG-C315D118P2 *HG-C315D118P2 *HG-C315D118P2 *HG-C315D118P2 *HG-C315D118P2
C 5/21 Modify *H-C315I178D118P2 7 6 7 6 7 6 7 6 7 6 7 6 C
8 5 8 5 8 5 8 5 8 5 8 5
9 4 9 4 9 4 9 4 9 4 9 4
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
7/08 Modify for ESD issue.
HOLE14 7/08 Add for ME.
*H-C1417D1417N HOLE18
HOLE22 *H-C315I178D118P2
*h-o94x134d94x134n
1
1
B B
+3V_S5 +1.5V_SUS +1.05V +VGPU_CORE
C427 C503 C368 C77
*0.1u/10V_4 *1000p/50V_4 *1000p/50V_4 *1000p/50V_4
For EMI(EMI)
A A
352-(&7=4
4XDQWD&RPSXWHU,QF
1A
MINI/USB/BT/HOLE
5 4 3 2 1
5 4 3 2 1
EC(KBC)
+3VPCU
30mil
L37 BK1608HS220_6_1A
Modify on 9/15
E775AGND
C502
0.1u/16V_4
+A3VPCU
C501
4.7u/10V_6
+3V
I/O ADDRESS SETTING 35
D23 C516 C521
R293 2.2_6 +3VPCU_EC 0.03A(30mils)
BAS316 4.7u_6 0.1u/16V_4
C500 C505 C519 C498 C504 C497 Modify to 1000P on 9/17
115
102
U12 No stuff 1000P on 4/29
19
46
76
88
4
PCLK_591 4.7u_6 0.1u/16V_4 *0.1u/16V_4 0.1u/16V_4 *0.1u/16V_4 0.1u/16V_4
AVCC
VDD
VCC1
VCC2
VCC3
VCC4
VCC5
E775AGND C495 *1000P_4 ICMNT SHBM=0: Enable shared memory with host BIOS
D D
R300 C496 0.01u/16V_4
LFRAME# 3 97
12,28 LFRAME# LFRAME GPI90/AD0 TEMP_MBAT 36
*22_4 LAD0 126 98 WL_SW T62
12,28 LAD0 LAD0 GPI91/AD1
LAD1 127 99 TPD_TRIP T63
12,28 LAD1 LAD1 GPI92/AD2
LAD2 128 A/D 100
12,28 LAD2 LAD2 GPI93/AD3 ICMNT 36
LAD3 1 108 DIGVOL_UP T65 SHBM SHBM_R R289 10K_4
12,28 LAD3 LAD3 GPIO05/AD4
C507 PCLK_591 2 96 DIGVOL_DN T61 Change Pin 98 to WL_SW
2 PCLK_591 LCLK GPIO04/AD5
*10p/50V_4 Pin99 for SML1ALERT#
8 on 9/10 1/13 Comfirm by vendor mail :
14 CLKRUN# GPIO11/CLKRUN 101 POWER_SAVE T81 Disabled ('1') if using FWH device on LPC.
121 GPI94/DA0 105
12 GATEA20 GA20 GPI95/DA1 PWM_FAN1 27 Enabled ('0') if using SPI flash for both system BIOS and EC firmware
D/A 106 TP_LED# T64
+3VPCU 122 GPI96/DA2 107 TP_SW#
12 RCIN# KBRST GPI97/DA3 T67
RP1 10K_10P8R 4/22 add
10 1 MX3 29 LPC
14 EC_SCI# ECSCI/GPIO54
MX4 9 2 MX2 64
GPIO01/TB2 ACIN 36
MX5 8 3 MX1 EC_FPBACK# 6 95 NBSWON#
25 EC_FPBACK# GPIO24/LDRQ GPIO03/AD6
MX6 7 4 MX0 93 +3VPCU
MX7 6 5
25 CRT_SENSE#
CRT_SENSE# 124
GPIO10/LPCPD
GPIO06
GPIO07/AD7
94
119
LID591# 14,25
SUSB# 6,14
SM BUS PU MBCLK R281 4.7K_4
GPIO23/SCL3 VGA_CLK 23
PLTRST# 7 109 ACPRN_ACLED T70 Del ACPRN on 9/18 Change pull-up resistor (R148 MBDATA R286 4.7K_4
13,28,31,33 PLTRST# LREST GPIO30/CIRTX2 /R154) from 10K to 4.7Kohm
+3VPCU 120
GPIO31/SDA3 VGA_DATA 23
USBON# 123 65
28 USBON# GPIO67/PWUREQ GPIO32/D_PWM BATLED0# 27
66
GPIO33/H_PWM BATLED1# 27
IRQ_SERIRQ 125 15 +3V
14 SERIRQ SERIRQ GPIO36/TB3 VR_ON 39
16 4/20 Modify
CN3 GPIO40/F_PWM SUSLED# 27
9 17 VGPU_ON
14 KBSMI# GPIO65/SMI GPIO42/TCK VGPU_ON 21,41,43
28 1 MY0 GPIO 20 2ND_MBCLK R285 4.7K_4
28 1 GPIO43/TMS AMP_MUTE# 29
27 2 MY1 21 3G_SW T77
4/21 add 2ND_MBDATA R280 4.7K_4
27 2 3 MY2 MX0 54 GPIO44/TDI 22 CPUFAN#
3 4 MY3 MX1 55 KBSIN0 GPIO45/E_PWM 23 3G_WKAE_1
T73 4/22 DEL PWM
4 KBSIN1 GPIO46/CIRRXM/TRST T75
5 MY4 MX2 56 24 VIN_ON T71 Del VIN_ON on 4/19
5 6 MY5 MX3 57 KBSIN2 GPO47/SCL4 25
C 6 KBSIN3 GPIO50/TDO D/C# 36 C
7 MY6 MX4 58 26 +3V
7 KBSIN4 GPIO51/TA3 S5_ON 37,44
8 MY7 MX5 59 27
8 KBSIN5 GPIO52/CIRTX2/RDY HDMI_HPD_EC# 26
9 MY8 MX6 60 28 EC_ODD_EN T74
9 10 MY9 MX7 61 KBSIN6 GPIO53/SDA4 91 VGA_CLK R297 2.2K_4
10 KBSIN7 GPIO81 DNBSWON# 14
11 MY10 110 T69 VGA_DATA R299 2.2K_4
11 12 MY11 MY0 53 GPO82/TRIS 112 RF_LED_EN#
12 KBSOUT0/JENK GPO84/BADDR0 T66
13 MY12 MY1 52 80 3G_WKAE_2 T58
Modify on 4/19
13 14 MY13 MY2 51 KBSOUT1/TCK GPIO41
14 KBSOUT2/TMS
Del DP_HPD_EC#
15 MY14 MY3 50 R303 100K_4
15 16 MY15 MY4 49 KBSOUT3/TDI 31 RTC_EC
16 17 MY16 MY5 48 KBSOUT4/JEN0 KB GPIO56/TA1 117
RTC_EC 12
17 KBSOUT5/TDO GPIO20/TA2 SUSON 40,42
18 MY17 MY6 47 63
18 KBSOUT6/RDY GPIO14/TB1 FANSIG 27
19 MX7 MY7 43
19 20 MX6 MY8 42 KBSOUT7 32
20 21 MX5 MY9 41 KBSOUT8 TIMER GPIO15/A_PWM 118 NUMLED#
CONTRAST 25
21 KBSOUT9 GPIO21/B_PWM T80
22 MX4 MY10 40 62
22 KBSOUT10 GPIO13/C_PWM PWRLED# 27
23 MX3 MY11 39 81 CAPSLED#
23
24
24
25
MX2
MX1
MY12
MY13
38
37
KBSOUT11
KBSOUT12/GPIO64
GPIO66/G_PWM T57
4/28 Modfiy it SPI FLASH +3VPCU
25 26 MX0 MY14 36 KBSOUT13/GPIO63 84 ODD_EJ U11

26 KBSOUT14/GPIO62 GPIO77/SPI_DI T60
MY15 35 SPI 83 SHBM_R SPI_SDI_uR R291 22_4 SPI_SDI_uR_R 2 8
FFC_26P_KB MY16 34 KBSOUT15/GPIO61/XOR_OUT GPO76/SPI_DO/SHBM 82 Back_SW SO VDD
GPIO60/KBSOUT16 GPIO75/SPI_SCK T59
MY17 33 R294 100K_4 SPI_SDO_uR 5 7 C492
5/12 add GND pin GPIO57/KBSOUT17 SI HOLD
75 RSMRST#_uR R288 *Short_4 SPI_SDI_uR pull-down 100Kohm at B-test SPI_SCK_uR 6 3 0.1u/16V_4
GPIO72/IRRX1/SIN2 RSMRST# 14 SCK WP
MBCLK 70 73
36 MBCLK GPIO17/SCL1 GPIO70/IRRX2_IRSL0 SUSC# 6,14
MBDATA 69 74 PWROK_EC_uR R287 *Short_4 +3VPCU R292 10K_4 SPI_CS0#_uR 1 4
36 MBDATA GPIO22/SDA1 GPIO71/IRTX/SOUT2 PWROK_EC 14 CE VSS
2ND_MBCLK 67 SMB IR 113
3 2ND_MBCLK GPIO73/SCL2 GPIO87/CIRRXM/SIN_CR RF_EN 28
2ND_MBDATA 68 14 CIRR_X2 T76 W25X16AVSSIG
3 2ND_MBDATA GPIO74/SDA2 GPIO34/CIRRXL
5/11 Swap Modfiy 4/19 114 HWPG
GPIO16/CIRTX 111 P_SAVE_LED#
GPO83/SOUT_CR/BADDR1 T68
TPCLK 72
27 TPCLK GPIO37/PSCLK1
CP2 TPDATA 71 1/13 Comfirm by vendor mail : At 11/24 add
27 TPDATA GPIO35/PSDAT1
B 1 2 MY10 T78 PCH_ACIN 10 86 SPI_SDI_uR If the Southbridge enables 'Long Wait Abort' by Winbond W25X16AVSSIG AKE38FP0N01 B
3 4 MY11 11 GPIO26/PSCLK2 F_SDI 87 SPI_SDO_uR_R R283 22_4 SPI_SDO_uR MXIC MX25L1605DM2I-12G AKE38FP0Z00
5 6 MY12
28 BT_POWERON#
12 GPIO27PSDAT2 PS/2 F_SDO 90 SPI_CS0#_uR default, the flash device should be 50MHz (or faster) AMIC A25L016M-F AKE38ZN0800
7 8 MY13
21,38,40,42 MAINON
VGA_THERM# 13 GPIO25/PSCLK3 FIU F_CS0 92 SPI_SCK_uR_R R284 22_4 SPI_SCK_uR
23 VGA_THERM# GPIO12/PSDAT3 F_SCK
*220PX4
14 ICH_SUSCLK R279 0_6 E775_32KX1 77 30 ECDB_CLOCK T72
CP3 32KX1/32KCLKIN GPIO55/CLKOUT
1 2 MY8 85 VCC_POR# R282 47K/F_4 +3VPCU
3 4 MY9 VCC_POR +3V
VCORF
AGND
GND1
GND2
GND3
GND4
GND5
GND6
5 6 R277 *20M_6 E775_32KX2 79 104 VREF_uR R290 *Short_4 +A3VPCU

7 8 32KX2 VREF
*220PX4
R278 WPCE781
HWPG R298
5
18
45
78
89
116
103
VCORF_uR 44
CP5
1 2 MY4 Y1 *33K/F_4 SM BUS ARRANGEMENT TABLE 10K_4
3 4 MY5 1 4 D22 BAS316 HWPG
42 HWPG_1.8V
5 6 MY6 L36 SM Bus 1 Battery
7 8 MY7 D21 BAS316
38 HWPG_1.05V
*220PX4 R295
C493 *32.768KHz C494 BK1608HS220_6_1A C517 SM Bus 2 PCH D20 BAS316 *Short_4
6,40 HWPG_1.5V
CP7 *15p_4 *15p_4
1 2 MX0 1u_4 D19 BAS316
37 SYS_HWPG
3 4 MX1 E775AGND SM Bus 3 VGA Thermal MPWROK 6,14
5 6 MX2 D17 EV@BAS316
43 PG_1.5V_EN
7 8 MX3
*220PX4 E775AGND SM Bus 4 Add D18 EV@BAS316
21 dGPU_PWROK
CP6
1 2 MX4
3 4 MX5
5 6 MX6
7 8 MX7
A
*220PX4 POWER-ON Switch POWER-ON PAD(UIF) POWER-Smart Key(UIF) INTERNAL KEYBOARD STRIP SET A
CP4 +3VPCU
1 2 MY0 SW1
3 4 MY1 MISAKI_SW_H1.5 MY0 R296 10K_4
5 6 MY2
7 8 MY3 NBSWON# 1 2
*220PX4 3 4
2
5 DEL it 5/5
352-(&7=4
CP1 D7 6
G1
1 2 MY14 *VPORT_6
4XDQWD&RPSXWHU,QF
3 4 MY15 NBSWON# 1 2
5 6 MY16
1
7 8 MY17
*220PX4 *SHORT_PAD Size Document Number Rev
1A
WPCE81 & FLASH
5 4 3 2 1
5 4 3 2 1
SP@POWER_JACK
dcjk-2dc2003-000111-3p-v
PJ2
1
2
3
VA
EMI Add 4/26
PL12
HI0805R800R-00_8
VA1 PD10
SBR1045SP5-13
1
2
3 VA2 3
PQ56
FDD6685
4 1
PR16
0.01_3720
2
Close to PR9002 VIN PQ39
FDD6685
3
36
4
1
PC165 PC12 PR19 PR20 PR21 PC5 PC6 PR40
7
6
5
4
PC168 PC158 PL13 0.1u/50V_6 0.1u/50V_6 220K_4 SHORT_PAD_4 SHORT_PAD_4 0.1u/50V_6 2200p/50V_6 33K/F_4
HI0805R800R-00_8 PD11 Add 5/14
SMAJ20A
2
D 2200p/50V_6 *47u/25V_6.3*6 CSIN_1 D
PC166
0.1u/50V_6 1 6 CSIP_1
PD1 PR39
SW1010CPT PR17 2 5 10K_4
D/C# 35
220K_4
3 4 PR14
3
*0/short_4
Modfiy 4/28 andy PQ5
ZH9 CSIN_1
IMD2AT108
2
PQ15
Item Color QCI P/N CSIP_1 EMI Add 4/22 DMN601K-7
1
VIN
65W Yellow DFPJ06MR012
PC90
PR67 PR72 1u/16V_6
90W Blue DFPJ06MR013 10/F_4 10/F_4
PC101
0.1u/50V_6 PR92
4.7_6 PC85
1u/16V_6 PC79 PC74
27 CSIN
28 CSIP
ISL88731_VDDP
5
6
7
8
PC64 *10u/25V_1206
10u/25V_1206 *10u/25V_1206
33
32
31
30
26
21
C C
1
+3VPCU PD6 PC65
*RB500V-40 4 2200p/50V_6
CSSP
VDDP
NC
GND
GND
GND
GND
CSSN
VCC
PC100 PR124 PC58
0.1u/50V_6 2.7_6 0.1u/50V_8
+3VPCU 11 25 88731B_2 88731B_1 PQ25 0.01_3720
VDDSMB BOOT AO4468 PR160
PL4
3
2
1
35 MBDATA 9 24 ISL88731_UGATE 6.8uH
PR131 SDA UGATE 1 2 BAT-V
100K_4
5
6
7
8
35 MBCLK 10 23 ISL88731_PHASE
SCL PHASE
13 20 ISL88731_LGATE 4 PR81
35 ACIN ACOK LGATE *4.7_6
PR78 PC88 19
49.9/F_6 0.1u/50V_6 PGND PQ26
DCIN 22 AO4468 CSOP_1
DCIN PR87 PC27 PC119
3
2
1
PR149 10/F_4 PC59 BAT-V 2200p/50V_6 10u/25V_1206
82.5K/F_4 PU3 18 CSOP CSOP_1 *680p/50V_6 PC124
PC18 88731ACSET 2 ISL88731A CSOP 10u/25V_1206
0.1u/50V_6 ACIN PC86
2 1 0.1u/50V_6
3
PC17 PR150 VREF 17 CSON BAT-V
Modify 6/18
B 4/21 100p/50V_6 PL1 22K/F_4 CSON B
change footprint (ZQ3) HI0805R800R-00_8 4

ICOMP 16
PR86
10/F_4
MBAT+ BAT-V NC
C114F3-108A1-L_Batt_Conn 5 PR125
PL2 NC *0/short_4
HI0805R800R-00_8 15 BAT-V
10 1 PR27 6 VBF
2 100_4 VCOMP 29 PR174
3 TEMP_MBAT GND 100_4
GND
4 TEMP_MBAT 35
ICM
NC
NC
5
6 PR28 PR142
7
14
12
7 100K_4 2.21K/F_4
9 8
+3VPCU
PJ1
PC20 PC19
47p/50V_6 47p/50V_6 PC110
0.01u/50V_6
ISL88731 thermal pad
ICMNT
tie to Pin12
ICMNT 35
PR26
*0/short_4 PR30 PR29
100_4 100_4 PC106 PC105 PC104
*1u/16V_6 0.01u/50V_6 *0.01u/50V_6
MBCLK
A MBDATA A
PU6
CM1293A-04SO
1 6 MBDATA
CH1 CH4
2
VN VP
5
+3VPCU
Modfiy 4/19 andy 352-(&7=4
TEMP_MBAT 3
CH2 CH3
4 MBCLK 4XDQWD&RPSXWHU,QF
Add ESD diode base on EC FAE suggestion 1A
Charger(ISL88731A)
5 4 3 2 1
5 4 3 2 1
SUSD
37
SUSD 42
MAIND
MAIND 40,42
VL
3,44 SYS_SHDN#
PR169
*0/short_4
1
D VIN VIN D
PR156
39K/F_4 VL
2
PC122
2
+ 3V5V_EN 4.7u/10V_8
PR157 PC52 PC53
*0/short_4 2.2n/50V_4 10u/25V_1206
1
PC94 PR153 OCP:9A
100u/25V_6X7.7 PR168 PR143 *0/short_4
1
*0/short_4 *0/short_4
PC111 PR148
7A
PC26 PC127 PC25 PR158 PC117 1u/16V_6 *0_4 +3VPCU
2
5V_EN
3V_EN
2.2n/50V_6 *10u/25V_1206 10u/25V_1206 390K_4 0.1u/50V_6
OCP:7A
5
6
7
8
PC116
2
0.01u/16V_4 PC109
5.4A 0.1u/50V_6
1
+5VPCU 8206_ONLDO REF 4
1
3V_DH
8
7
6
5
PR151 PQ21 Change footprint 5/14
PR159 *0_6 AO4468
8
7
6
5
4
3
2
1
4 5V_DH 150K_4
PL3
LDOREFIN
LDO
VIN
NC
ONLDO
VCC
TON
REF
3
2
1
2.2uH_7X7X3
PQ14 +3VPCU
Change footprint 5/14 AO4468 PR57
Modify 6/18 3V_LX
5
6
7
8
+5VPCU 9 32 REFIN2 220K/F_4
PL8 10 BYP REFIN2 31 1 2
1
2
3
2.2uH_7X7X3 11 OUT1 ILIM2 30 PR91
C C
+5VPCU 5V_LX 1 2 12 FB1 PU4 OUT2 29 SKIP 4 PD5 *4.7_6
ILIM1 SKIP#
2
PR43 DDPWRGD_R 13 RT8206B 28 DDPWRGD_R *SX34
PGOOD1 PGOOD2
8
7
6
5
169K/F_4 5V_EN 14 27 3V_EN PR140 +
PR167 15 EN1 EN2 26 PC63
DH1 DH2 *0_4
*0_4 PR175 16 25 *680p/50V_6 PC95 PC84
*4.7_6 4 5V_DL 37 LX1 LX2 0.1u/50V_6 330u/6.3V_6X5.7
Modify 6/18
1
+ PD2 36 PAD
3
2
1
PAD
PGND
PVCC
*SX34 PQ22
BST1
BST2
GND
PAD
PAD
PAD
DL1
DL2
PC21 PC121 PC108 AO4710
NC
0.1u/50V_6 PC128 0.1u/50V_6 0.1u/50V_6 1 2
*680p/50V_6 PQ13 PR152 PR146 *0/short_4
35
34
33
17
18
19
20
21
22
23
24
PC23 AO4710 PR164 1/F_6 +3VPCU_OUT 1 2
1
2
3
*10u/25V_1206 PR44 1/F_6 1 2 PR147 *0_4

*0/short_4 1 2 3V_DL
2
PC134 PR46 VL SKIP 1 2 REF PR141
330u/6.3V_6X5.7 +5VPCU_FB *0_6 *0_4
PC43 PR170 PR55
2 0.1u/50V_6 PC112 *0/short_6 *0_4
1
PD3 1u/16V_6 1 2
CHN217 3
PR56
1 *0/short_4 +3VPCU
PC48 PR50
0.1u/50V_6 *0/short_6
2
PD4
OCP:7A CHN217 3 OCP:9A PR144
B B
L(ripple current) PC42 L(ripple current) *100K/F_4
1 0.1u/50V_6
=(9-5)*5/(2.2u*0.4M*9) =(9-3.3)*3.3/(2.2u*0.5M*9)=1.9A
~2.525A +15V_ALWP 1 2 Iocp=9-(1.9/2)=8.05A
+15V
DDPWRGD_R
Vth=8.05A*14.2mOhm=0.11431V SYS_HWPG 35
1
Iocp=7-(2.525/2)=5.74A PR80 PR77
22_8 *200K/F_4 PR47 R(Ilim)=(114.31mV*10)/5uA=228.62K PR145
Vth=5.74A*14.2mOhm=0.08147V PC51 *39K/F_4 *0/short_4
R(Ilim)=(81.47mV*10)/5uA=163K 0.1u/50V_6 I_peak(choke)=11.479A
2
I_peak(choke)=11.187A
+3VPCU +3VPCU
VIN +3V_S5 +5V_S5 +15V VIN +5VPCU +5VPCU +3VPCU
Modfiy 4/19 andy
5
6
7
8
3
PR34 PR36 PR35 PR32 PR31
1M_6 22_8 22_8 1M_6 *1M_6
3
5
6
7
8
5
6
7
8
S5D 4
SUSD 2
S5D 2 MAIND 4 MAIND 4 PQ24

AO4468 PQ23
3
AO3404
0.21A
1
A PQ8 PQ42 PQ28 A
3
2
1
2 AO3404 AO4468 AO4468
35,44 S5_ON +3VSUS
1
2 2 2
+3V_S5 2.8A
3
2
1
3
2
1
PR33 PQ10 PQ11

1
PQ7 1M_6 DMN601K-7 DMN601K-7
352-(&7=4
DTC144EU PQ9 PC22
+5V_S5
1
DMN601K-7 *2.2n/50V_4
0.002A
+5V +3V
4XDQWD&RPSXWHU,QF
2.4A 4.01A Size Document Number Rev
1A
SYSTEM 5V/3V (RT8206)
5 4 3 2 1
5 4 3 2 1
[PWM]
38
VIN
D +5V_S5 D
OCP:20A
16A
PR161 +1.05V
10_6
5
PR172 PD7
2.2/F_6 RB500V-40
PR42
1M/F_4 PC113 4
4.7u/6.3V_6
PC129 PC130 PC24
1
2
3
PU5 PR171 PQ40 2.2n/50V_4 10u/25V_1206 10u/25V_1206
PR38 UP6111AQDD PC125 AOL1448
*0/short_4 0.1u/50V_6
15 13
21,35,40,42 MAINON EN/DEM BOOT *0/short_6
+3V 16 12 UGATE-1.05V PL9
PC120 TON UGATE 1uH
*0.1u/50V_6 1 11 PHASE-1.05V
VOUT PHASE
PR162 2 10 PR37
VDD OC
5
C *10K/F_4 3.9K/F_4 C
3 9 PC126
FB VDDP 1u/16V_6
4 8 LGATE-1.05V 4 PR177 +
35 HWPG_1.05V PGOOD LGATE *4.7_6
6 7
1
2
3
GND PGND PQ41
5 17 AOL1718 PC133
NC TPAD *680p/50V_6
14
NC
PC114 PC118 PC135 PC137 PC136
1u/16V_6 *1000p/50V_6 560u/2.5V *10u/10V_8 0.1u/50V_6
PR48
B 4.02K/F_4 PC115 B
R1 *33p/50V_6
1.05V_FB
PR49
10K/F_4
R2
07/06 modify to short-pad.
PR217
*0/short_6
TON=3.85p*RTON*Vout/(Vin-0.5) L(ripple current)

Frequency=Vout/(Vin*TON) =(19-1.05)*1.05/(1u*272k*19)
A
TON=3.85p*1M*1/(Vin-0.5) ~3.647A PR154
*0/short_6
A
Frequency=1/(0.0036767)=272K RILIM=4.3mohm*20-1.823/20uA=3.907Kohm 352-(&7=4

I(choke)peak=23.647A 4XDQWD&RPSXWHU,QF
1A
+1.05V (UP6111A)
5 4 3 2 1
5 4 3 2 1
PR98
*0_4
PR94
*0_4
PR123
*0_4
+3VPCU
PR126
*0_4
PR97
*0_4
PR93
*0_4
PR89
*0_4
+3VPCU
DELAY_VR_PWRGOOD 3,6,14
T82 T79
39
VIN VIN
H_VID6 H_VID5 H_VID4 H_VID3 H_VID2 H_VID1 H_VID0
+
PC38 PC47 PC41 PC37 PC102
2200p/50V_6 10u/25V_1206 10u/25V_1206 0.1u/50V_6 100u/25V_6X7.7
D D
5
07/06 modify to short-pad.
6266A_UG1 4 PQ34
Modify 6/18 36A
PR218 AOL1448 REV:B VCC_CORE
*0/short_8 VIN +3V
1
2
3
PL6
PR112 0.36uH
*0/short_8 6266A_PH1
PR127 PR119 PR102
5
10/F_6 10_4 1.91K/F_4
+5V_S5 PR52
*2.2_6 + +
6266A_LG1 4 PC131 PC132
330u/2V_7343 330u/2V_7343
PR113 PC87 PC76
1
2
3
4.99K/F_6 PR84 0.1u/50V_6 0.1u/50V_6 PQ37 PC36
PWR_MON PGD_IN 10/F_6 AOL1718 *2200p/50V_6
PC69
0.1u/50V_6
22
20
48
1
PR70 PR75
PC89 *0/short_6 *0/short_6
VCC
VIN
PGOOD
3V3
1u/25V_8
PR138 3.65K/F_6
21 VSUM
GND 35
Close to Phase 1 Inductor UGATE1
49 PR65 10K/F_6
GND_T 36
3 PSI# PSI# BOOT1
Throttling temp. PR136 PR135 1/F_6
PR107 2.2_6 PC97
10K/F_6 105 degree C 0.22u/25V_8
C VR_ON 34 PR134 *0_6 C
PR103 *0/short_4 PSI#_1 2 PHASE1 ISEN2
PSI# 32 T84 T83
PR111 PR108 *0_4 PGD_IN 3 LGATE1
*10K/F_4 PGD_IN 33
PR110 147K/F_6 4 PGND1
+3V_S5 RBIAS 24 ISEN1
5 ISEN1 VIN
3 H_PROCHOT# VR_TT# VIN
PR173 PR109
470K_4NTC 4.02K/F_4 6 +5V_S5 PC54
NTC 31 0.22u/25V_6 +
PC66 VSOFT 7 PVCC PC45 PC107 PC39 PC103
0.01u/16V_4 PC67 SOFT PC98 2200p/50V_6 10u/25V_1206 10u/25V_1206 0.1u/50V_6 PC96
0.022u/50V_6 4.7u/10V_8 100u/25V_6X7.7
Panasonic H_VID0 37
VID0
5
4 H_VID0
ERT-J0EV474J H_VID1 38 PU2 27
4 H_VID1 VID1 UGATE2
ISL6266A
H_VID2 39 26 6266A_UG2 4 PQ35
Modify 6/18
4 H_VID2 VID2 BOOT2
H_VID3 40
AOL1448 REV:B
PR137
4 H_VID3
1
2
3
VID3 2.2_6 PC99 PL7
H_VID4 41 0.22u/25V_8 0.36uH
4 H_VID4 VID4 28 6266A_PH2
H_VID5 42 PHASE2
4 H_VID5 VID5 30
LGATE2
5
H_VID6 43
4 H_VID6 VID6 29
PR121 PR51
*0/short_4 VR_ON 44 PGND2 *2.2_6 + + +
35 VR_ON VR_ON
PR99 23 ISEN2 6266A_LG2 4 PC31 PC29 PC30
499/F_4 DPRSLPVR 45 ISEN2 *330u/2V_7343 *330u/2V_7343 *330u/2V_7343
6,14 PM_DPRSLPVR DPRSLPVR
1
2
3
PR104 *0/short_4 ICH_DPRSTP#_R 46 PC93 PQ38 PC35
3,6,12 ICH_DPRSTP# DPRSTP# 25 0.22u/25V_6 AOL1718 *2200p/50V_6
PR120 *0/short_4 CLKEN# 47 NC
14 VR_PWRGD_CK410# CLK_EN# PR82 PR85
B *0/short_6 *0/short_6 B
8 PC70 PR114
PR117 OCSET 1000p/50V_4 13.3K/F_4
1K/F_4 13
VDIFF
19 VSUM
PR118 PC73 PR106 VSUM
100/F_4 2200p/50V_6 1K/F_4
12 6/29 Modify
FB2
PC83 PR95
11 *0.068u/25V_6 2.7K/F_4
FB PR132 3.65K/F_6
PC82 PR122 VSUM
0.22u/25V_6 11K/F_4
PR133 10K/F_6
PC71 PR116 PC72 10 PR176
100P/50V_4 97.6K/F_4 220p/50V_4 COMP 10K_6NTC
PR129 1/F_6
18
VO
Panasonic
DROOP
PR128 *0_6
ERT-J1VR103J
ISL6266_VO
VSEN
PC68 PR115 9 ISEN1

RTN
DFB
1000p/50V_6 11.3K/F_4 VW
PC77
0.33u/10V_6 Close to Phase 1 Inductor
15
14
16
17
PR100 PR96
3.9K/F_4 1K/F_4
PC78 VCC_CORE
330p/50V_4 PC81
180p/50V_4
A PC80 PC75 PR101 A

330p/50V_4 0.01u/16V_4 10/F_6
Parallel
VCCSENSE 4
VSSSENSE 4
352-(&7=4
PR105
10/F_6 4XDQWD&RPSXWHU,QF
1A
CPU CORE(ISL6266A)
5 4 3 2 1
5 4 3 2 1
[PWM]
PC57
10u/10V_8
40
PR74 PC49
*0/short_6 0.1u/50V_6
8207A_VBST
+SMDDR_VTERM
VIN
8207A_DH
D D
PC61 PC60
0.3A 10u/10V_8 10u/10V_8 8207A_LX
5
8207A_DL
25
24
23
22
21
20
19
PC50 PC55 PC92
OCP 20A
1
2
3
PQ29 2200p/50V_6 10u/25V_1206 10u/25V_1206
17.2A
GND
VTT
VLDOIN
VBST
DRVH
LL
DRVL
AOL1448 PL5
0.56uH
1 18 +1.5V_SUS
VTTGND PGND
2 17
VTTSNS CS_GND PQ33
AOL1718
5
3 RT8207A 16 PR64
GND PU1 CS 4.7K/F_4
6/29 Modify PR59
+1.5V_SUS 4 15 4 4 *4.7_6 +
MODE V5IN +5V_S5
PQ31
1
2
3
1
2
3
5 14 AOL1718
+SMDDR_VREF VTTREF V5FILT
1
PR61
6 13
VDDQSNS
PC62 +5V_S5 PC44 5.1/F_6 PC46 PC40
VDDQSET
0.0375A 0.033u/50V_6 COMP PGOOD 1u/6.3V_4 1u/6.3V_4 *680p/50V_6 PC123 PC28
2
C REV:B andy 6/11 560u/2.5V 10u/10V_8 C
NC
NC
S3
S5
PR63 +3V_S5
100K/F_4
7
10
11
12
FOR DDR III
HWPG_1.5V 6,35
PR66 (For RT8207A 400KHZ ) close to PC2008

VIN
620K/F_4
S5_1.8V PR71
SUSON 35,42
*0/short_4
S3_1.8V PR76
MAINON 21,35,38,42
*0/short_4
PR79 +5V_S5
*0_4
PC56 PR83
*33p/50V_6 10K/F_4
Vout = (PR150/PR149) X 0.75 + 0.75
AO1718 Rdson=3.8~4.3mOhm
8207A_SET
L(ripple current)
B =(19-1.5)*1.5/(0.56u*400k*19) B
07/06 modify to short-pad. PR88

10K/F_4
S5_1.8V PR73
*0_4
S3_1.8V ~6.168A
Vtrip= (20-(6.168/2))*(4.3mohm/2)=0.03637V
PR219
*0/short_6 +1.5V_SUS RILIM=0.8133/10uA=3.636K
5
6
7
8
PR90
*0/short_6
MAIND 4
37,42 MAIND
PQ12
AO4468
S3 S5 +1.5VSUS REF VTT
3
2
1
+1.5V S0 1 1 ON ON ON
3.6A S3 0 1 ON ON OFF
S4/S5 0 0 OFF OFF OFF

A A
352-(&7=4
4XDQWD&RPSXWHU,QF
1A
DDR 1.5V(TPS51116)
5 4 3 2 1
1 2 3 4 5
+5V_S5 VIN
5/26 Modify Andy TP6 TP5
VIN
41
OCP=15A
+VGPU_CORE 11A
PR6
A +3V *EV@0_4 PC9 A
TP2
PR208 *EV@10u/25V_1206 5/26 Modify Andy
5
EV@200K/F_4 PC156
PC160 EV@1u/10V_6 2 7 8792TON EV@10u/25V_1206
VDD TON PQ57
PR215 5 8792DH 4 EV@AOL1448
EV@100K_4 PC167 EV@1u/10V_6 8792VCC 13 DH
VCC PC155
1
2
3
6 8792BST EV@2200p/50V_4 PC8
BST TP1
14 PR207 EV@10u/25V_1206 5/26 change to DC-10F0M102
43 PG_1V_EN PGOOD EV@1_6 PC4
PR209 *EV@0/short_4 8792EN 1 PU11 EV@0.22u/25V_6
Andy
21,23 +3V_D_EXT EN 4 8792LX
PR211 *EV@0_4 EV@MAX8792ETD+T LX
21,35,43 VGPU_ON PC161 8792SKIP# 12 PL11
SKIP# 3 8792DL EV@1uH
5/4 Modify andy DL
5
PR3 *EV@0_4
8792REFIN 10 PR18
EV@0.1u/10V_4 REFIN 8 *EV@2.2_6
FB 4 + +
PR212 REF-2V
EV@100K_4 8792REF 11 9 8792ILIM PC11
1
2
3
REF ILIM PQ55 *EV@1000p/50V_4
PR220 07/06 modify to short-pad. EV@AOL1718
EP
*0/short_6
B B
R1 PR2
15
EV@39.2K/F_4
PR214 5/26 Modify Andy PC10
EV@41.2K/F_4 PR210 PC13 *EV@330u/2V_7343
*0/short_6 *EV@4700P/25V_4 PC157 PC7
R3 EV@0.1u/50V_6 EV@330u/2V_7343
Place near GND pin15
PR8 PC169 5/26 change to 41.2K/F_4

3
EV@332K/F_4 EV@1000P/50V_4
PR213
Andy
EV@100K_4
2
19 GPU_VID1
Frequency(PR220=200K) 300K
PQ2
PR10 EV@DMN601K-7 VIN +VGPU_CORE
EV@3K_4 PR1
1
R2 EV@49.9K/F_4
PR15 PR13
PC2
AMD Park VID Table EV@1M_6 EV@22_8
EV@0.01u/16V_4
C R4 GPU_VID1 (GPIO15) GPU_VID2 (GPIO20) +VGPU_CORE C
3
0 0 1.12V
3
PR4 1 0 1.05V
3
EV@130K/F_4 2
0 1 0.95V 8792EN 2
PQ4
2 PR12 EV@DMN601K-7
19 GPU_VID2 1 1 0.9V PQ3 EV@1M_6
1
PQ1 EV@DTC144EU
PR5 EV@DMN601K-7
EV@3K_4
1
PC1
EV@0.01u/16V_4
D D
352-(&7=4
4XDQWD&RPSXWHU,QF
1A
GPU CORE(MAX8792)
1 2 3 4 5
5 4 3 2 1
+3V_S5
PC151
42
PC152 EV@0.1u/25V_4
EV@10u/10V_8 2.18A
D PU9 EV@HPA00835RTER D
16 10 +1.8V
VIN PH
1 11 PL10
VIN PH EV@1uH_7X7X3
PR24 2 12
*EV@0/short_4 VIN PH
MAINON 15 13 PR197 *EV@0/short_6
EN BOOT
54418-1.8_VFB 6 14 PC146 R1
VSNS PWRGD EV@0.1u/50V_6 PR25
7 3 EV@100K/F_4
COMP GND
PR22 PC14 8 4
EV@100K/F_4 RT/CLK GND
PAD
PAD
PAD
PAD
PAD
PAD
HWPG_1.8V 35
EV@1000p/50V_4 9 5 PR199
PR200 PR198 SS AGND 54418-1.8_VFB
EV@100K/F_4
EV@15K/F_4 EV@182K/F_4 +3V PC147 PC16 PC15
22
21
20
19
18
17
EV@0.1u/25V_4 EV@10u/10V_8
PC149 EV@10u/10V_8
*EV@100P/50V_4 PC148 R2 PR23
EV@0.01u/25V_4 EV@78.7K/F_4
C C
PC150
EV@1200p/50V_4 V0=0.8*(R1+R2)/R2
+3V_S5
VIN +3VSUS +SMDDR_VTERM +15V
2
+3V_S5
PR166 PR139 PR155 PR130
2.18A PQ47
1M_6 22_8 22_8 1M_6 IV@AOL1448 PC142 PC140
1
+1.8V IV@10u/10V_8IV@0.1u/25V_6
SUS_ON_G SUSD 3 PR189

SUSD 37 2 5 IV@100K_4 5/18 Modify
PU8
3
3
1
3
IV@G9334
PR188 5 4 HWPG_1.8V
35,40 SUSON 2 2 2 2 IV@261/F_4 DRV PGD
4
B PC91 PC143 Rg B
PR165 PQ30 PQ32 PQ27 *2200p/50V_4 1 MAINON
EN
1
PQ36 1M_6 DMN601K-7 DMN601K-7 DMN601K-7 IV@22U/6.3V_8 3

1
PR163 DTC144EU FB +5VPCU
GND
1
1
100K_4 07/06 modify from 1206 to 0805. 6
VCC Modfiy 4/19 andy
PR187
2
2
PR190 Rh IV@47/F_6
IV@100/F_4 PC144
IV@0.1u/25V_6
1
PC141
VIN +3V +5V +1.5V +15V IV@33n/50V_6
Vout1 = (1+Rg/Rh)*0.5
PR68 PR60 PR41 PR62 PR45
1M_6 22_8 22_8 22_8 1M_6
MAINON_ON_G MAIND
MAIND 37,40
3
3
3
PR69
A MAINON 2 1M_6 2 2 2 2 PC33 A
21,35,38,40 MAINON *2200p/50V_4
1
PQ17 PQ18 PQ19 PQ16
352-(&7=4
PR58 PQ20 DMN601K-7 DMN601K-7 DMN601K-7 DMN601K-7
1
100K_4 DTC144EU
1
4XDQWD&RPSXWHU,QF
2

1A
VCCP 1.8V(UP6111A)
5 4 3 2 1
5 4 3 2 1
VIN +1.5V_GPU +15V

+1.5V_SUS
43
PR205 PR202 PR201
5
6
7
8
EV@1M_4 EV@22_8 EV@1M_4
D PR204 D
*EV@0_4 dGPU_D1 4
21,35,41 VGPU_ON 2.97A
3
3
PR203 PQ6
*EV@0/short_4 PR206 EV@AO4468 +1.5V_GPU
PG_1.5V_EN 2 EV@1M_4 2 2
PC153
3
2
1
PQ54 PQ52 *EV@2.2n/50V_4
PQ53 EV@DMN601K-7 EV@DMN601K-7
1
PC154 EV@DTC144EUA
1
EV@1u/10V_4
VIN +1.8V_GPU +15V +1.8V

C C
PR193 PR192 PR191
3
+1.5V_GPU EV@1M_4 EV@22_8 EV@1M_4
dGPU_D 2
PR196
3
EV@1K_4
3
PQ48
PR194 EV@AO3404
0.25A
1
2 EV@1M_4 2 2
PC145
+1.8V_GPU
1
PQ50 PQ49 *EV@2.2n/50V_4

PR195 PQ51 EV@DMN601K-7 EV@DMN601K-7
1
EV@100K_4 EV@PDTC143TT 1
1
2
B
+3V_S5 B
+5VPCU 1 PR216
EV@10K_4
PC159 PU10
2
EV@0.1u/50V_6 EV@RT9018A
4 1 PG_1.5V_EN
VPP PGOOD PG_1.5V_EN 35
2 6 +1V
41 PG_1V_EN VEN VO
3
+1.5V_SUS 8 VIN 1.8A
GND
1
ADJ
9 5
GND NC PR11 PC164
PR9 EV@9.1K/F_4
5/5 Modify
7
EV@100K_4 EV@22U/6.3V_8
2
0.8V 07/06 modify from 1206 to 0805.

PC162 PC163 PC3
EV@10u/10V_8
EV@0.1u/50V_6
EV@0.1u/50V_6
A PR7 A
EV@34K/F_4
352-(&7=4
Vout =0.8(1+R1/R2) 4XDQWD&RPSXWHU,QF
=1V Size Document Number Rev
1A
GPU_POWER
5 4 3 2 1
1 2 3 4 5
VIN
44
PD8
SW1010CPT
A A
PR178
1M_6
Thermal protection
1
S5_ON
35,37 S5_ON
PQ44
AO3409
TH_ON 2
3
S5_ON 2
PQ43
1
VL VL DTC144EU
B B
SYS_SHDN# 3,37
PR184 PR183
1.33K/F_4 200K/F_4 PR180
200K/_6
PC138
0.1u/50V_6
3
8
PR185
10K_6NTC 2.469V 3
+ 1 2
2
- PQ45
PU7A DMN601K-7
4
LM393 PC139
1
0.1u/50V_6
PR186
200K/F_4
+3VPCU
3
C C
VL
S5_ON 2
PR179
PQ46 100K/F_6
DMN601K-7
PR182
1
10K/F_6 PU7B
5 PD9
+ 7 NC_TEMP T96
4.95V 6
-
RB500V-40
LM393
PR181
1M/F_6
For EC control thermal protection (output 3.3V)
D D
352-(&7=4
4XDQWD&RPSXWHU,QF
1A
Thermal Protection
1 2 3 4 5
5 4 3 2 1
MODEL
MODEL: REV ZR6 MB
CHANGE LIST
FROM TO
PAGE
1 1A
A First release 2 1A
1.Page40:change HWPG_1.5V pull up to +3V_S5 for S3 issue 3 1A
2.Page29:Add R570 pull up +1.5V for uma Audio I/O 4 1A
ZQ5 MB 5 1A
3.Page26:Swap HDMI Lane2 for HDMI issue
4.Page31:U34 and R567 no stuff ,R555 stuff it for LAN ID issue 6 1A
D
5.Page02:Q12 and Q13 change Part number from BAM700200F6 to BAM700200H2
7 1A D
6.Page29:R55 and R56 change Part number to CS33303F911(33K) for Audio 8 1A

7.Page29:change R86 and U6 Pin5 pull up to +5V_S5 9 1A
8.Page29:change R84 value to 0 ohm 10 1A
9.Page30:change Q25 and Q27 Part number to BAM70020002 as ZYB 11 1A
10.Page25:L1,L2,L3 change to CX8LL680001 12 1A
11.Page25:C1,C2,C3,C5,C6,C7 change to CH-5006JBD4 13 1A
12.Page25:R11,R14 change to CS01502JB12 14 1A
13.Page28:Add another BT circuit (USB port5),Add Q30,RN37,C792,CN22 15 1A
14.Page07:Change R425,R426 to CS02492FB29 for CRT issue 16 1A
15.Page13:Change BT 2.1 to USB port 7 17 1A
16.Page28:Change BT 2.1 to USB port 7 18 1A
17.Page25:chage 0805 to SHORT Pad R71,R72,R98,R146 19 1A
18.Page29:Stuff R84 U6 and no stuff R86 for Audio bobo noise 20 1A
19.Page10:change R171 and R429 to bead CX8PG181001 21 1A
20.Page30:stuff Q25 and Q27 and no stuff R46 R48 for Audio bobo noise 22 1A
21.Page40:Add PR219 23 1A
C 23.Page41:Add PR220 25 1A C
25.Page36: Change PR16 (0.01/F_7520) to CS+0108GL13 (0.01_3720) 27 1A
C 26.Page41: DEL JP1 and JP4 28 1A
27.Page39: DEL JP2 and JP3 29 1A
28.Page38:change PR171,PR38 to short Pad 30 1A
29.Page36:change PR125,PR14,PR26 to short Pad 31 1A
30.Page37:change PR143,PR145,PR146,PR153,PR157,PR168,PR169,PR170,PR50,PR44,PR56 to short Pad 32 1A
31.Page39:change PR120,PR121,PR104,PR103,PR70,PR75,PR82,PR85 to short Pad 33 1A
32.Page40:change PR71,PR76,PR74 to short Pad 34 1A
33.Page41:change PR209 to short Pad (EV@) 35 1A
34.Page42:change PR24,PR197 to short Pad (EV@) 36 1A
35.Page43:change PR203 to short Pad (EV@) 37 1A
炷P/N烉
36.Page36:Change PQ26 to AO4468炷烉BAM44680003炸炸 38 1A
37.Page37:PD2 and PD5 no stuff 39 1A
38.Page39:PC29 and PC31 no stuff 40 1A
39.Page36:PJ1 change Part number to DFHD08MR140
41 1A
42 1A
01.Page39:PC83 no stuff
43 1A
B
44 1A B
02.Page39:Change PR64 to CS24702FB10 45 1A

03.Page16: Del C539 (*10U/6.3V_6).
04.Page17: Del C538 (*10U/6.3V_6).
D ˣPR217.
05.Page38: Change AGND (0 ohm) to Short Pad(0603): PR154ˣ
ˣPR90.
ˣPR220.
08.Page39:Change AGND (0 ohm) to Short Pad(0805): PR112,PR218.
09.Page43:Change PC164 (22uF/10V_1206) to CH6221M9A07 (22uF/6.3V_0805)
10.Page42:Change PC143 (22uF/10V_1206) to CH6221M9A07 (22uF/6.3V_0805)
11.Page34:Modify HOLE18 to dummy net.
12.Page34:Add HOLE22 for ME.
A A
352-(&7=4
MB Assy' P/N: 31ZQ5MB0000 Project :ZQ5 MB Document No.: 4XDQWD&RPSXWHU,QF
1A
Approved by : Andy_Lin Drawing by :Andy Chen DATE: 2009/03/04 Thermal Protection
5 4 3 2 1

Acer Aspire 4733z Quanta - ZQ5 - RevB

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Acer Aspire 4733z Quanta - ZQ5 - RevB

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5 4 3 2 1

EV@: STUFF FOR EXT VGA THERMAL 3/5V SYS PWR

Penryn 478 Thermal Sensor Fan Driver

USB 2.0 ICH9M

&ORFN*HQHUDWRU &/. +3V

C545 C568 C551 C546 C435

33p/50V_4 CG_XOUT 1 VSS_SRC3 63

5/5 modify R331 *10K_4

4.7K_4 <SECOND>:RTM875N-606-VD-GRT QCI:AL000875000 4.7K_4

A5 C7 PM_THRMTRIP# T108 CPU_TEST1 C23 MISC U26 COMP1 R328 54.9/F_4

Thermal Trip +1.05V CPU Thermal monitor +3V XDP PU/PD

R400 SYS_RST# R391 *1K_4

&38 WINDBOND AL83L771K01 Use 2200p Size

&38 stuff 330U*2, NC330U*2 Size

2K/F_4 *0.1U/10V_4 352-(&7=4

R192 IV@2.21K/F_4 SDVO_CTRLCLK BH5 NC_13

A BC1 NC_23 HDA_SYNC HDA_SYNC_HDMI 12 Differential signal-->NC A

R47 C_PEG_TXP5 C627 EV@.1U/10V_4 PEG_TXP5

AU13 SA_DQ_35 SA_DQS#_7 BH12 SB_DQ_35 SB_DQS#_6 AN5

SA_DQ_48 SA_MA_11 SB_DQ_48 SB_MA_10

VCC_AXG_NCTF_45 AM16 R383 IV@0_8 VCC_NCTF_5 AG32

Y15 1.8V AK25

T14 BA37 VCC_SM_LF2

1. Route VCC_AXG_SENSE and VSS_AXG_SENSE differentially

C322 C328 C312

IV@0.1U/10V_4 SP@0.01U/25V_4 IV@10U/6.3V_8

C614 C613 VCCA_SM_# 1.05V

HD Audio R470 IV@33_4

ICH_TP3 HDA_SDOUT Description

Direct Media Interface

L<0.5",Avoid routing next to clock/high speed signals.

South Bridge Strap Pin (2/3)

PCI Express Port 0 = Default

REQ3# 8 3 FRAME# GNT2# / GPIO53 PWROK

+3V_S5 4/20 Modify '$  $6)LVVXHZKHQL$07LVQRWLPSOHPHQWHG 6$7$>[@*3SLQVLIXQXVHGUHTXLUH

R369 *10K_4 EC_SCI# PM_RSMRST#_R 3 1 +3V +3V +3V +3V

Date: Monday, July 12, 2010 Sheet 14 of 43

AA24 VCC1_05[06] L11 23mA AB29 VSS[007] VSS[113] L13

1U/10V_4 AD11 VCC1_5_A[09] VCCSUS3_3[02] D17 AJ12 VSS[069] VSS[175] U26

B VCC1_5_A[20] VCCSUS3_3[13] V6 E11 VSS[083] VSS[189] Y1 B

0.1U/10V_4 D28 ICH9MREV1.0

A follow ZR6 C372 A

DDR3 (DDR) +3V

DGMK4000004 R307 R306

PC2100 DDR3 SDRAM SO-DIMM

PC2100 DDR3 SDRAM SO-DIMM

M_A_DM2 46 149 M_A_DQ41 198 167

+SMDDR_VREF +3V +SMDDR_VTERM

DDR3 (DDR) STD H=8.0 MM

PC2100 DDR3 SDRAM SO-DIMM

PC2100 DDR3 SDRAM SO-DIMM

M_B_DM2 46 149 M_B_DQ41 198 167

+SMDDR_VREF +3V +SMDDR_VTERM

0518 SWAP PCIE for VGA side

0518 SWAP PCIE for VGA side

RN30 1 2 EV@0_4P2R PEG_TXP1_R Y35 W33 CPEG_RXP1 C199 EV@0.1u/10V_4

PEG_TXP4 U38 T33 CPEG_RXP4 C168 EV@0.1u/10V_4

PCI EXPRESS INTERFACE

PEG_TXP6 R38 P33 CPEG_RXP6 C148 EV@0.1u/10V_4

PEG_TXP7 P35 P30 CPEG_RXP7 C135 EV@0.1u/10V_4

PEG_TXP8 N38 N33 CPEG_RXP8 C123 EV@0.1u/10V_4

PEG_TXP9 M35 N30 CPEG_RXP9 C112 EV@0.1u/10V_4

PEG_TXP10 L38 L33 CPEG_RXP10 C103 EV@0.1u/10V_4

&ORFN*HQHUDWRU&/. +3V

&38 WINDBOND AL83L771K01 Use 2200p Size

&38 stuff 330U2, NC330U2 Size

2K/F_4 *0.1U/10V_4 352-(&7=4

+3V_S5 4/20 Modify '$$6)LVVXHZKHQL$07LVQRWLPSOHPHQWHG 6$7$>[@*3SLQVLIXQXVHGUHTXLUH

Close to NB couple cap & PCIE RESARRAY 4XDQWD&RPSXWHU,QF