Louse ootd — 6/104 EE lob RISC ~ Grobruations of fined lamath Bduaneed RISC Machine High ode vdimaily :- dows fumcliowadiy com he ARMT, ARMA, ARMIO { Y we Joy Hand * Reale in atom ane. 32 bilhota. romefe inibuscion, Q mov wo, td Mov ww, #immdiak date « LDR %, = oxir3ys678 imomow Lecdlion LOR sy fo] rad 14 with value sforrel af Ho LOR My [roy#4). Dz: yard fo Auiste banodseimal no- [Js ptt sat foten nt 4 added te Yo ees eae” Ja. * STR sh. Pa] ; Data un phous to U- STR x0 aca en ee oe aes6 Authmuslic Instiuctions ADD fm, 4,2 5 ho = HIFRD ADC for Mi 2 5 9c0 = dt n24C SUB Ho 94x25 oe M7 CBC der 5 NOX ry -e2.-B een @ ob tt PEND sed: tree 5 HO= Hd & 2 ORR gorre2 5 1= Fl Jao EoR wo, re2 4 Horry “x2 BEQ label ; Bromch if Za10 flog = + BNE abel ; Bronnch if xH0 tava jromnpase the rovlink of No owl 10 iflage well be affect 4 cup so, #10 BEQ Lobel ;va LOR to, #10 5 Y= Io cu %0, #10 5 2feL BEO label = 5 ve pa OL a bits ‘t LDR tor t tow ; LDR sn, # Ox lowo- Ly Henasacimal raped” facture 10° [etFet 2922] Features: = + 32-bit microcontroller + 32-bit ALU + 32-bit data bus 5 Bp titniteans bag, $e emery Ze UGG 7° load-store architecture, (Hodl * 7 processor modes + 37 registers + 3 data formats:8-bit, 16-bit, 32-bit (aus bfe Ledy aunerd Ler. das mat aus & Load lng lula coll wrol thal fo Lumgth of wiiero wonlveller-"ver ve Data transfer instructions: MOV, MVN Operation Description Assembler Cycles, Move Register MOV Rd, % 1 move dato. «— 16-bit immediate MOVWW Rd, # 4 16 beds meve Lobe tb Mbbon 16 hiks MoOvicond)} {s} Rd, Rm, MOV{S} , ,ASR # MOV{S} , ,LSL # (onde 178 MOV{S} , MOV{S} , MVN 10, r1 eons Lt] | 4 — SS Hoe mot Hew movw usd! alow usuh akere * Ereambls of conditions :- Moveg wm} xt 5 Hence Uhvs us move Uf 20 fog ds ack. Ga the merck shod . trae fable for the condilionscos em er i or cent 0000. Equal Equal z=1 con NE Not equal ‘Not equal, or unordered z=0 O10 ch Camy set Greater than, equal, or unordered = C==1 l ou oe Cany clear Less than c=0h 0 ‘Minus, negative Less than, N=1 om PL Plus, positive or er0 Greater than, equal, or unordered = N==0 m0 WS Overflow Unordered Ve ' au No overflow ‘Not unordered v=0 1000 HT Unsigned higher Greater than, or ordered =landZ=( 1001 Ls Unsigned lower orsame Less than o equal C=00Z=1 wo Signed greater than or equal Greater than or equal N=V 0 wu oT Signed less than, Less than, or unordered. Niev 100 Gr Signed greater than Greater than Z=0aN=" uo LE Signed les than orequal Less than, equal, oruordered = Z=LorN!=V 110 None (ald Always (unconditional) Always (unconditional) AnpgUTo VER S500) 22 tei it wl, check condition for EQ ie Zervflog= Od al i ano Baosd on thus Iromsfur: Gs 8 to wwuittin ; £0 {logs sod ae G hop > itheut sb wnlk met aff 1 fag 2 <6p27 Movicond) {s} Rd, Rm, MOV{S} ,,ASR # MOV{S} ,,LSL # one MOV{S} , MOV{S} ,,ROR # MVN 10, r1 ———— Mov #p, #1, ASR #2 5 Bhatt the dota. suet _ side by 2 hon JA use wove t0FP. ASR: Pridlhmelia chip wad no byn no of bits ‘ne unites lo dinate = *Shift instructions: LSL, LSR, ASR, ROR, RRX Description Assembler Cycles Logical shift left LSL Rd, Rn, # 1 Logical shift left LSL Rd, Rn, Rs 1 Logical shift right LSR Rd, Rn, # A, Logical shift right LSR Rd, Rn, Rs ak Arithmetic shift right ASR Rad, Rn, # 1 Arithmetic shift right ASR Rad, Rn, Rs 1 Rotate right ROR Ra, Rn, # Rotate right ROR Rad, Rn, Rs 1 With extension — RRX Rd, Rn ES Rd, Rn, -LSL Rai@n HL Ue shut dota. wn kn by + poorkuon thin thamafn frarn Bn +o Ra L Rd, Ans Rs ae. area’, bid hy data emlanid Rs fonibiowe ond fromafussd to Bd Tn a gol Abiped in Mls te right Mite ane padded, wilh xarn- :ribhmrabic: shift —- (talso cos of Sign) Ms@ bik copia . Relat, Rignt RoR aden Hemme > Reto, Hugh RoR Ra, Rn. As RAX Radi Rn vLielL. lotFeb 2022 ARM instruction format s} Rd, op1, op2 mov — MNEMONICS {condition} MNEMONICS: Short name of the instruction {Condition}: condition is needed to be met in order to execute the instruction {s}: If ‘s’ is specified, condition flags are updated on result of the operation Rd: destination register for storing the result Op1: first operand, it can be a register or an immediate value Op2: second operand (flexible), it can be an immediate value or register with an optional shift Arithmetic instructions: “Arithmetic Instructions 1 | app Basic addition | kg: ADD RO, R1, R2; RO EAI + A 2 | apc Add with Carry Eg: ADC RO, R1, R2; RO € RI + R2 + Carry 3 | sus Basic subtraction | Eg: SUB RO, R1, R2; RO ERI - R2 4 [sec Subtract with borrow (carry) | Eg: SBC RO, R1, R2; RO RI - R2- teary J s |RsB Reverse subtraction | 9: RSB RO, Ri, R2; RO © R2- RI 6 |Rsc Reverse subtraction with carry | Eg: RSC RO, R1, R2; RO €R2 ~ RI - [Carry Note: Normally Arithmetic insiractions donot affect lags. If we want flags to be affected we mast write Sax a postfix | Eg: ADDS Ro, RI, R2. The lag becomes 0 and if becomes 1.Endian support/ Endianness bt i 2aiza i 16it5 i Biz i oi Word at . a Address A Byte at address (A+3) | Byte at address (A: op Byte at address (A: uy Byte at address A — oY Halfword at Address A | Byte at address (A+1) | Byte at address A ¥ Figure A3-1 Little-endian byte format (Oy dofault) 31 24123 i 1615 8i7 ° Byte at address A | Byte at address (A+1) | Byte at address (A+2) | Byte at address (A+3) Byte at address (A+1) Hse Byte at address A Halfword at Address A em Figure A3-2 Big-endian byte format Doe ieotm aaalls LDRB ro.Du) , tomaper 8 bE Framafer, 16 wit Aato Word at Address A Ne LoRH 10, CYLogical instructions: Logic Instructions 1 | AND AND Eg: AND RO, Ri, R2; RO € RI AND R2 2 | ORR OR Eg: ORR RO, Ri, R2; RO ERI OR RI 3 |EOR Ex-OR FOR RO, Ri, R2; RO € RI XOR RZ ; TE RO, RI, R2; RO € AI AND (NOT) RZ 4 [BIC AND with complement ee et eae Eg: CMP RO, R1; s | CMP Ordinary Compare Performs RO ~ RI, Ooes not store the result but (CMN RO, Ri; 6 | CMN Compare with Negated value _| Performs RO + R1, Does not store the result but affects the flags. Eg: TST RO, Ri; 7 |Tst Logical AND, Only affects flags | Sicrrenenagse 1 Dee OO Stare the resuk but Eg: TEQ RO, Ri; 8 | TEQ Logical XOR, Only affects flags | Performs RO XOR Ri, Does not store the result but affects the flags. Note: AND, ORR, EOR and BIC instructions do not affect flags. Uf we want flags to be affected we must write S as a posifix. Eg: ANDS RO, RI, R2. Note: CMP, CMN, TST and TEQ instructions will not store the result. They will only affect the flags. Logical instructions:Examples AND R9, R2, R1 ; RQ = R2 AND R1 AND R9, R2, #0xFFOO ; RO = R2 AND #@xFFOO ANDS R9, R8, #0x19 ORR R9, R2, R1 5 RO = R2 OR R1 ORR R9, R2, #0xFFOO EOR R7, R11, R10 ; R7 = R11 XOR R10 BIC R@, R1, #@xab ; R@ = R1 AND (NOT(#@xab)) ORN R7, R11, R14, ROR #4 ; = R7 = R11 OR (NOT(R14 ROR #4))Load/store instructions: LDR, LDRB, LDRH, LDRSB, LDRSH, STR, STRB, STRH... ao ees * LDR ~ load 32 bits . LDRH_ — load halfword (16 bit unsigned #) / zero-extend to 32 bits * LDRSH __ - load signed halfword / sign-extend to 32 bits * LDRB — load byte (8 bit unsigned #) / zero-extend to 32 bits « LDRSB ~ load signed byte / sign-extend to 32 bits ¢ STR — store 32-bit word “e STRH — store 16-bit halfword (right-most16 bits of register) ¢ STRB : store 8-bit byte (right-most 8 bits of register) Example: Load a Byte LORB ri, [re] @x02000003 [x00 | @x00 | 0x00 | xe: | poems 5 7 @x02000001 nD exe2e00000 Load a Halfword Little Endian LORH r1, [re] [oxo0 [ @x00 | oxe3 | xe | aunt ka Ms 10 = 0x02000000Example: LORH r1, [re] —} r@ = ex2eee8000 od RCS a) Memory Bec) Lr Te) @x20008003 @x89 @x20008002 @xAB @x20008001 @xCD 0x20008000 @xEF r1 before load @x12345678 — r1 after load OxG@@OCDEF | —_ ia 7 i LDSB ri, [re] c 3 r@ = @x2e008000 Ay Corie) a | Memory r1 before load rer ; esha] Brite) @x12345678 — @x20008003 0x89 rl after load @x20008002 @xAB @x20008000 @xEF EF es podded with ms6 bits onainng beeen he Sis nln YS wo wot thee, O will be paclded-Load/store instructions: LDR, LDRB, LDRH, LDRSB, LDRSH, STR, STRB, STRH... Single register load/store ee cue 2 eTRe °" Savvis) LDR r0, [r1] _; rO=memf[r1] “ee Re, [R1] STR ro, [ra] j mem([r1]= nemfrt}="0_~ b ae , preemioy sae register indirect plus offset (limited to 4KB) oe <) as LOR 0, [r1, #4]; O=mem[ri+4] 5 ; bar addaere ® ny Se STR r0, [r1, #12]; mem[r1+12]=r0 poe ivf NE Alternate form: with auto-indexing with write back LDR rO, [r1, #4]! ; rfO=mem[r1+4], r1=r1+4 STR r0, [r1, #12]! ; mem[r1+12]=r0, r1=r1+12 J Hone baat adder x, x0 yo medi Alternate form: with post-indexing LDR r0, [r1], #4 ;r0=mem[r1], ri=r1+4 STR rO, [ri], #12; memf[r1]=r0, ri=r1+i2Example: * Example: STR 10, [rl,#12] ae Npise — ClSt ue 3abt 32 bt ALL 32 bh seyLoad — Stove Avdnt Pe