Computer Organization

CSEN 2202
Module I
Basics of Computer Organization
⚫ Basic organization of the stored program
computer
⚫ operation sequence for execution of a program
⚫ Von Neumann & Harvard Architecture.
⚫ RISC vs. CISC based architecture.
⚫ Fetch, decode and execute cycle,
⚫ Concept of registers and storage,
⚫ Instruction format,
⚫ Instruction sets
⚫ addressing modes.
Introduction
⚫ Today, a personal computer has more
computational power, more main memory, more
disk storage, smaller in size and it is available in
affordable cost.
⚫ This rapid rate of improvement has come both
from advances in the technology used to build
computers and from innovation in computer
design. In this course we will mainly deal with
the innovation in computer design.
⚫ The task that the computer designer handles is
a complex one: Determine what attributes are
important for a new machine, then design a
machine to maximize performance while staying
within cost constraints.
Introduction
⚫ This task has many aspects, including
instruction set design, functional organization,
logic design, and implementation.
⚫ While looking for the task for computer design,
both the terms computer organization and
computer architecture come into picture.
Computer Organization and Architecture

⚫ Architecture is those attributes visible to the

programmer
◼ Instruction set, number of bits used for data
representation, I/O mechanisms, addressing
techniques.
◼ e.g. Is there a multiply instruction?
⚫ Organization is how features are
implemented
◼ Control signals, interfaces, memory technology.
◼ e.g. Is there a hardware multiply unit or is it done
by repeated addition?
Computer Organization and Architecture
⚫ Computer architecture
◼ refers to those parameters of a computer system
that are visible to a programmer or those
parameters that have a direct impact on the logical
execution of a program.
◼ Examples of architectural attributes include
– the instruction set,
– the number of bits used to represent different data types
– I/O mechanisms,
– techniques for addressing memory.
Computer Organization and Architecture
⚫ Computer organization
◼ refers to the operational units and their
interconnections that realize the architectural
specifications.
◼ Examples of organizational attributes include those
hardware details transparent to the programmer
◼ such as
– control signals,
– interfaces between the computer and peripherals,
– the memory technology used.
Structure & Function
⚫ Structure is the way in which components
relate to each other
⚫ Function is the operation of individual
components as part of the structure

⚫ In this course we will touch upon all those

factors and finally come up with the concept
how these attributes contribute to build a
complete computer system.
Function
⚫ All computer functions are:
◼ Data processing
◼ Data storage
◼ Data movement
◼ Control
Operations (1) Data movement
Operations (2) Storage
Operation (3) Processing from/to storage
Operation (4)
Processing from storage to I/O
Basic Unit of a Computer

⚫ The model of a computer can be described by

four basic units in high level abstraction which
is shown in figure
⚫ These basic units are:
◼ Central Processor Unit
◼ Input Unit
◼ Output Unit
◼ Memory Unit
Structure
⚫ The Computer
◼ CPU
– Controls the operation of the
computer and performs its data
processing functions.
◼ Main memory
– Stores data
◼ I/O
– Moves data between the
computer and its external
environment
◼ System interconnection
– Provides for communication
among CPU, main memory, and
I/O
 Structure - Top Level

Peripherals Computer

Central Main
Processing Memory
Unit

Computer
Systems
Interconnection

Input
Output
Communication
lines
Structure - The CPU

CPU

Computer Arithmetic
Registers and
I/O Logic Unit
System CPU
Bus
Internal CPU
Memory Interconnection

Control
Unit
Central Processor Unit (CPU)

⚫ Central processor unit consists of two basic

blocks :
◼ The program control unit has a set of registers and
control circuit to generate control signals.
◼ The execution unit or data processing unit contains a
set of registers for storing data and an Arithmetic
and Logic Unit (ALU) for execution of arithmetic and
logical operations.
⚫ In addition, CPU may have some additional
registers for temporary storage of data.
Structure - The Control Unit

Control Unit

CPU
Sequencing
ALU Logic
Control
Internal
Unit
Bus
Control Unit
Registers Registers and
Decoders

Control
Memory
Input Unit
⚫ With the help of input unit data from outside can
be supplied to the computer. Program or data
is read into main storage from input device or
secondary storage under the control of CPU
input instruction.
⚫ Example of input devices: Keyboard, Mouse,
Hard disk, Floppy disk, CD-ROM drive etc
Output Unit
⚫ With the help of output unit computer results
can be provided to the user or it can be stored
in storage device permanently for future use.
Output data from main storage go to output
device under the control of CPU output
instructions.
⚫ Example of output devices: Printer, Monitor,
Plotter, Hard Disk, Floppy Disk etc.
Memory Unit
⚫ Memory unit is used to store the data and program.
CPU can work with the information stored in
memory unit.
⚫ This memory unit is termed as primary memory or
main memory module.
⚫ These are basically semi conductor memories.
⚫ There ate two types of semiconductor memories -
⚫ Volatile Memory
◼ RAM (Random Access Memory).
⚫ Non-Volatile Memory
◼ ROM (Read only Memory),
◼ PROM (Programmable ROM)
◼ EPROM (Erasable PROM),
◼ EEPROM (Electrically ErasablePROM).
Secondary Memory
⚫ There is another kind of storage device, apart
from primary or main memory, which is known
as secondary memory. Secondary memories
are non volatile memory and it is used for
permanent storage of data and program.
⚫ Example of secondary memories:
⚫ Hard Disk, Floppy Disk, Magnetic Tape: These
are magnetic devices,
⚫ CD-ROM is optical device
⚫ Thumb drive (or pen drive) is semiconductor
memory.
ENIAC - details
⚫ Decimal (not binary)
⚫ 20 accumulators of 10 digits
⚫ Programmed manually by switches
⚫ 18,000 vacuum tubes
⚫ 30 tons
⚫ 15,000 square feet
⚫ 140 kW power consumption
⚫ 5,000 additions per second
von Neumann
⚫ Stored Program concept
⚫ Main memory storing programs and data
⚫ ALU operating on binary data
⚫ Control unit interpreting instructions from
memory and executing
⚫ Input and output equipment operated by
control unit
⚫ Princeton Institute for Advanced Studies
◼ IAS
◼ Completed 1952
von-Neumann Architecture
⚫ Instruction and data stored
in the same memory
module.
⚫ More flexible and easier to
implement.
⚫ Suitable for most of the
general purpose
processors.
⚫ Disadvantage:
⚫ The processor-memory
bus acts as the
bottleneck.
⚫ All instructions and
data are moved back
and forth through the
pipe
Structure of von Neumann machine
von-Neumann Architecture
⚫ How can this be reduced?
⚫ This performance problem is reduced by using
cache memory.(details in memory part)
⚫ Using RISC architecture as it uses less number
of memory reference instruction and uses large
number of registers.
Harvard Architecture

⚫ Separate memory for

program and data.
⚫ Instructions are stored
in program memory
⚫ Data are stored in data
memory.
⚫ Instruction and data
accesses can be done in
parallel.
⚫ Some microcontrollers
and pipelines with
separate instruction and
data caches follow this
concept.
⚫ The processor-memory
bottleneck remains.
IAS - details
⚫ 1000 x 40 bit words
⚫ Binary number
⚫ 2 x 20 bit instructions
⚫ Set of registers (storage in CPU)
⚫ Memory Buffer Register
⚫ Memory Address Register
⚫ Instruction Register
⚫ Instruction Buffer Register
⚫ Program Counter
⚫ Accumulator
⚫ Multiplier Quotient
Structure of IAS –detail
For Interfacing with the Primary Memory
⚫ Two special-purpose registers are used:
⚫ – Memory Address Register (MAR): Holds the
address of the memory location to be accessed.
⚫ – Memory Data Register (MDR): Holds the data
that is being written into memory, or will
receive the data being read out from memory.
⚫ Memory considered as a linear array of
storage locations (bytes or words) each
with unique address.
For Interfacing with the Primary Memory

4095

4096X16
The memory has 4096 words in it
4096 = 212, so it takes 12 bits to select a word in memory
Each word is 16 bits long
Size of MAR=12 bits
Size of MDR=16bits
DATA BUS &ADDRESS BUS.
⚫ The size of the data bus indicate how many bit we
can transfer at a time. Size of data bus is mainly
specified by the data storage capacity of each
location of memory module.
⚫ We have to resolve the issues how to specify a
particular memory location where we want to store
our data or from where we want to retrieve the
data.
⚫ This can be done by the memory address. Each
location can be specified with the help of a binary
address.
⚫ These signal lines use to identify a memory
location is termed as ADDRESS BUS.
ADDRESS BUS
⚫ Size of address bus depends on the memory size.
⚫ For a memory module of capacity of 2n location, we
need n address lines, that is, an address bus of
size n.
⚫ We use a address decoder to decode the address
that are present in address bus
⚫ As for example, consider a memory module of 16
location and each location can store 4 bit of
information.
◼ The size of address bus is 4 bits
◼ size of the data bus is 4 bits
◼ The size of address decoder is 4 X 16.
control signals for read or write
⚫ There is a control signal named R/W.
If R/W = 0, indicates READ operation
⚫ if R/W = 1, indicates WRITE operation

⚫ If the contents of address bus is 0101 and

contents of data bus is 1100 and R/W = 1, then
1100 will be
written in location 5.
⚫ If the contents of address bus is 1011 and
R/W=0, then the contents of location 1011 will
be placed in data bus.
For Interfacing with the Primary Memory
⚫ To read data from memory
◼ a) Load the memory address into MAR.
◼ b) Issue the control signal READ.
◼ c) The data read from the memory is stored into
MDR.
⚫ To write data into memory
◼ a) Load the memory address into MAR.
◼ b) Load the data to be written into MDR.
◼ c) Issue the control signal WRITE.
For Keeping Track of Program /
Instructions
⚫ Two special-purpose registers are used:
⚫ Program Counter (PC): Holds the memory address of
the next instruction to be executed.
⚫ Automatically incremented to point to the next
instruction when an instruction is being executed.
⚫ Instruction Register (IR): Temporarily holds an
instruction that has been fetched from memory.
⚫ Need to be decoded to find out the instruction type.
⚫ Also contains information about the location of the
data.
Generations of Computer
⚫ Vacuum tube - 1946-1957
⚫ Transistor - 1958-1964
⚫ Small scale integration - 1965 on
◼ Up to 100 devices on a chip

⚫ Medium scale integration - to 1971

◼ 100-3,000 devices on a chip

⚫ Large scale integration - 1971-1977

◼ 3,000 - 100,000 devices on a chip

⚫ Very large scale integration - 1978 to date

◼ 100,000 - 100,000,000 devices on a chip

⚫ Ultra large scale integration

◼ Over 100,000,000 devices on a chip
More Complex Execution Logic
⚫ Enable parallel execution of instructions
⚫ Pipeline works like assembly line
◼ Different stages of execution of different instructions
at same time along pipeline
⚫ Superscalar allows multiple pipelines within
single processor
◼ Instructions that do not depend on one another can
be executed in parallel
Performance Assessment
Clock Speed
⚫ Key parameters
◼ Performance, cost, size, security, reliability, power
consumption
⚫ System clock speed
◼ In Hz or multiples of
◼ Clock rate, clock cycle, clock tick, cycle time
⚫ Signals in CPU take time to settle down to 1 or 0
⚫ Signals may change at different speeds
⚫ Operations need to be synchronised
⚫ Instruction execution in discrete steps
◼ Fetch, decode, load and store, arithmetic or logical
◼ Usually require multiple clock cycles per instruction
⚫ Pipelining gives simultaneous execution of instructions
⚫ So, clock speed is not the whole story
System Clock
Instruction Execution Rate
⚫ Millions of instructions per second (MIPS)
⚫ Millions of floating point instructions per
second (MFLOPS)
⚫ Heavily dependent on instruction set, compiler
design, processor implementation, cache &
memory hierarchy
Top Level View of Computer Function
and Interconnection
Program Concept
⚫ Hardwired systems are inflexible
⚫ General purpose hardware can do different
tasks, given correct control signals
⚫ Instead of re-wiring, supply a new set of control
signals
What is a program?
⚫ A sequence of steps
⚫ For each step, an arithmetic or logical
operation is done
⚫ For each operation, a different set of control
signals is needed
Function of Control Unit
⚫ For each operation a unique code is provided
◼ e.g. ADD, MOVE
⚫ A hardware segment accepts the code and
issues the control signals

⚫ We have a computer!
Components
⚫ The Control Unit and the Arithmetic and Logic
Unit constitute the Central Processing Unit
⚫ Data and instructions need to get into the
system and results out
◼ Input/output
⚫ Temporary storage of code and results is
needed
◼ Main memory
Computer Components:
Top Level View
Instruction Cycle
⚫ Two steps:
◼ Fetch
◼ Execute
Fetch Cycle
⚫ Program Counter (PC) holds address of next
instruction to fetch
⚫ Processor fetches instruction from memory
location pointed to by PC
⚫ Increment PC
◼ Unless told otherwise
⚫ Instruction loaded into Instruction Register (IR)
⚫ Processor interprets instruction and performs
required actions
Execute Cycle
⚫ Processor-memory
◼ data transfer between CPU and main memory
⚫ Processor I/O
◼ Data transfer between CPU and I/O module
⚫ Data processing
◼ Some arithmetic or logical operation on data
⚫ Control
◼ Alteration of sequence of operations
◼ e.g. jump
⚫ Combination of above
Example of Program Execution
Instruction Cycle State Diagram
Interrupts
⚫ Mechanism by which other modules (e.g. I/O)
may interrupt normal sequence of processing
⚫ Program
◼ e.g. overflow, division by zero
⚫ Timer
◼ Generated by internal processor timer
◼ Used in pre-emptive multi-tasking
⚫ I/O
◼ from I/O controller
⚫ Hardware failure
◼ e.g. memory parity error
Interrupt Cycle
⚫ Added to instruction cycle
⚫ Processor checks for interrupt
◼ Indicated by an interrupt signal
⚫ If no interrupt, fetch next instruction
⚫ If interrupt pending:
◼ Suspend execution of current program
◼ Save context
◼ Set PC to start address of interrupt handler routine
◼ Process interrupt
◼ Restore context and continue interrupted program
Transfer of Control via Interrupts
Instruction Cycle with Interrupts
Connecting
⚫ All the units must be connected
⚫ Different type of connection for different type of
unit
◼ Memory
◼ Input/Output
◼ CPU
Computer Modules
Memory Connection
⚫ Receives and sends data
⚫ Receives addresses (of locations)
⚫ Receives control signals
◼ Read
◼ Write
◼ Timing
Input/Output Connection(1)
⚫ Similar to memory from computer’s viewpoint
⚫ Output
◼ Receive data from computer
◼ Send data to peripheral
⚫ Input
◼ Receive data from peripheral
◼ Send data to computer
Input/Output Connection(2)
⚫ Receive control signals from computer
⚫ Send control signals to peripherals
◼ e.g. spin disk
⚫ Receive addresses from computer
◼ e.g. port number to identify peripheral
⚫ Send interrupt signals (control)
CPU Connection
⚫ Reads instruction and data
⚫ Writes out data (after processing)
⚫ Sends control signals to other units
⚫ Receives (& acts on) interrupts
Buses
⚫ There are a number of possible interconnection
systems
⚫ Single and multiple BUS structures are most
common
⚫ e.g. Control/Address/Data bus (PC)
⚫ e.g. Unibus (DEC-PDP)
What is a Bus?
⚫ A communication pathway connecting two or
more devices
⚫ Usually broadcast
⚫ Often grouped
◼ A number of channels in one bus
◼ e.g. 32 bit data bus is 32 separate single bit channels
⚫ Power lines may not be shown
Data Bus
⚫ Carries data
◼ Remember that there is no difference between
“data” and “instruction” at this level
⚫ Width is a key determinant of performance
◼ 8, 16, 32, 64 bit
Address bus
⚫ Identify the source or destination of data
⚫ e.g. CPU needs to read an instruction (data)
from a given location in memory
⚫ Bus width determines maximum memory
capacity of system
◼ e.g. 8080 has 16 bit address bus giving 64k address
space
Control Bus
⚫ Control and timing information
◼ Memory read/write signal
◼ Interrupt request
◼ Clock signals
Bus Interconnection Scheme
THE BASIC COMPUTER INSTRUCTIONS

⚫ The Basic Computer has two components, a processor and

memory
⚫ The memory has 4096 words in it
◼ 4096 = 212, so it takes 12 bits to select a word in memory
⚫ Each word is 16 bits long

CPU RAM
0

15 0

4095
INSTRUCTION SET ARCHITECTURE
 Instruction codes

INSTRUCTIONS

⚫ Program
◼ A sequence of (machine) instructions

⚫ (Machine) Instruction
◼ A group of bits that tell the computer to
perform a specific operation (a sequence of
micro-operation)
⚫ The instructions of a program, along with any
needed data are stored in memory
⚫ The CPU reads the next instruction from
memory
⚫ It is placed in an Instruction Register (IR)
⚫ Control circuitry in control unit then translates
the instruction into the sequence of micro
operations necessary to implement it
Instruction Set Architecture (ISA)
⚫ Serves as an interface between software and
hardware.
⚫ Typically consists of information regarding the
programmer’s view of the architecture (i.e. the
registers, address and data buses, etc.).
⚫ Also consists of the instruction set.
⚫ Many ISA’s are not specific to a particular computer
architecture.
⚫ They survive across generations.
⚫ Classic examples: IBM 360 series, Intel x86 series, etc.
Instruction Formats
⚫ Layout of bits in an instruction
⚫ Includes opcode
⚫ Includes (implicit or explicit) operand(s)
⚫ Usually more than one instruction format in an
instruction set
Instruction Length
⚫ Affected by and affects:
◼ Memory size
◼ Memory organization
◼ Bus structure
◼ CPU complexity
◼ CPU speed
Allocation of Bits
⚫ Number of addressing modes
⚫ Number of operands
⚫ Register versus memory
⚫ Number of register sets
⚫ Address range
⚫ Address granularity
 Instruction codes

INSTRUCTION FORMAT
⚫ A computer instruction is often divided into two parts
◼ An opcode (Operation Code) that specifies the operation for that
instruction
◼ An address that specifies the registers and/or locations in memory
to use for that operation
⚫ In the Basic Computer, since the memory contains 4096
(= 212) words, we needs 12 bit to specify which memory
address this instruction will use
⚫ In the Basic Computer, bit 15 of the instruction specifies
the addressing mode (0: direct addressing, 1: indirect
addressing)
⚫ Since the memory words, and hence the instructions, are
16 bits long, that leaves 3 bits for the instruction’s opcode
Instruction Format

1514 1211 0
I Opcode Address
Addressing
mode
 Instruction codes

ADDRESSING MODES
⚫ The address field of an
instruction can represent
either
◼ Direct address: the
address in memory of
the data to use (the
address of the operand),
or
◼ Indirect address: the
address in memory of
the address in memory
of the data to use
⚫ Effective Address (EA)
◼ The address, that can
be directly used without
modification to access
an operand for a
computation-type
instruction, or as the
target address for a
branch-type instruction
BASIC COMPUTER REGISTERS
BASIC COMPUTER INSTRUCTIONS
 Instructions

BASIC COMPUTER INSTRUCTIONS

Hex Code
Symbol I = 0 I=1 Description
AND 0xxx 8xxx AND memory word to AC
ADD 1xxx 9xxx Add memory word to AC
LDA 2xxx Axxx Load AC from memory
STA 3xxx Bxxx Store content of AC into memory
BUN 4xxx Cxxx Branch unconditionally
BSA 5xxx Dxxx Branch and save return address
ISZ 6xxx Exxx Increment and skip if zero

CLA 7800 Clear AC

CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
INC 7020 Increment AC
SPA 7010 Skip next instr. if AC is positive
SNA 7008 Skip next instr. if AC is negative
SZA 7004 Skip next instr. if AC is zero
SZE 7002 Skip next instr. if E is zero
HLT 7001 Halt computer

INP F800 Input character to AC

OUT F400 Output character from AC
SKI F200 Skip on input flag
SKO F100 Skip on output flag
ION F080 Interrupt on
IOF F040 Interrupt off
 Instructions

INSTRUCTION SET COMPLETENESS

A computer should have a set of instructions so that the user can

construct machine language programs to evaluate any function
that is known to be computable.
• Instruction Types
Functional Instructions
- Arithmetic, logic, and shift instructions
- ADD, CMA, INC, CIR, CIL, AND, CLA
Transfer Instructions
- Data transfers between the main memory and the processor registers
- LDA, STA
Control Instructions
- Program sequencing and control
- BUN, BSA, ISZ
Input/Output Instructions
- Input and output
- INP, OUT
Instruction Set Design Issues
⚫ Number of explicit operands:
◼ 0, 1, 2 or 3.
⚫ Location of the operands:
◼ Registers, accumulator, memory, accumulator.
⚫ Specification of operand locations:
◼ Addressing modes: register, immediate, indirect,
relative, etc.
⚫ Sizes of operands supported:
◼ Byte (8-bits), Half-word (16-bits), Word (32-bits),
Double (64-bits), etc.
⚫ Supported operations:
◼ ADD, SUB, MUL, AND, OR, CMP, MOVE, JMP, etc.
Evolution of Instruction Sets
⚫ 1. Accumulator based:
◼ 1960’s (EDSAC, IBM 1130)
⚫ 2. Stack based:
◼ 1960-70 (Burroughs 5000)
⚫ 3. Memory-Memory based:
◼ 1970-80 (IBM 360)
⚫ 4. Register-Memory based:
◼ 1970-present (Intel x86)
⚫ 5. Register-Register based:
◼ 1960-present (MIPS, CDC 6600, SPARC)
 Instruction Format
INSTRUCTION FORMAT

⚫ Instruction Fields
⚫ OP-code field - specifies the operation to be
performed
⚫ Address field - designates memory address(es)
or a processor register(s)
⚫ Mode field - determines how the address field is
to be interpreted (to get effective address or
the operand)
⚫ The number of address fields in the instruction
format depends on the internal organization of
CPU
The three most common CPU
organizations:
⚫ Single accumulator organization:
ADD X /* AC  AC + M[X] */

⚫ General register organization:

ADD R1, R2, R3 /* R1  R2 + R3 */
ADD R1, R2 /* R1  R1 + R2 */
MOV R1, R2 /* R1  R2 */
ADD R1, X /* R1  R1 + M[X] */

⚫ Stack organization:
PUSH X /* TOS  M[X] */
ADD
Zero-Address Instructions
One-Address Instructions
Two/Three-Address Instructions
Two-Address Instructions
 Instruction Format

THREE, AND TWO-ADDRESS INSTRUCTIONS

• Three-Address Instructions

Program to evaluate X = (A + B) * (C + D) :
ADD R1, A, B /* R1  M[A] + M[B] */
ADD R2, C, D /* R2  M[C] + M[D] */
MUL X, R1, R2 /* M[X]  R1 * R2 */

- Results in short programs

- Instruction becomes long (many bits)

• Two-Address Instructions
Program to evaluate X = (A + B) * (C + D) :

MOV R1, A /* R1  M[A] */

ADD R1, B /* R1  R1 + M[A] */
MOV R2, C /* R2  M[C] */
ADD R2, D /* R2  R2 + M[D] */
MUL R1, R2 /* R1  R1 * R2 */
MOV X, R1 /* M[X]  R1 */
 Instruction Format

ONE, AND ZERO-ADDRESS INSTRUCTIONS

• One-Address Instructions
- Use an implied AC register for all data manipulation
- Program to evaluate X = (A + B) * (C + D) :
LOAD A /* AC  M[A] */
ADD B /* AC  AC + M[B] */
STORE T /* M[T]  AC */
LOAD C /* AC  M[C] */
ADD D /* AC  AC + M[D] */
MUL T /* AC  AC * M[T] */
STORE X /* M[X]  AC */
• Zero-Address Instructions
- Can be found in a stack-organized computer
- Program to evaluate X = (A + B) * (C + D) :
PUSH A /* TOS  A */
PUSH B /* TOS  B */
ADD /* TOS  (A + B) */
PUSH C /* TOS  C */
PUSH D /* TOS  D */
ADD /* TOS  (C + D) */
MUL /* TOS (A + B) * (C + D) */
POP X /* M[X]  TOS */
 Addressing Modes

ADDRESSING MODES

⚫ Specifies a rule for interpreting or modifying

the address field of the instruction (before the
operand s actually referenced)
⚫ Variety of addressing modes
◼ to give programming flexibility to the user
◼ to use the bits in the address field of the instruction
efficiently
Addressing Modes
⚫ Implied Mode
⚫ Immediate
⚫ Direct
⚫ Indirect
⚫ Register
⚫ Register Indirect
⚫ Displacement (Indexed)
⚫ Stack
 Addressing Modes

Implied Mode
⚫ Address of the operands are specified
implicitly in the definition of the instruction
⚫ No need to specify address in the
instruction
⚫ EA = AC, or EA = Stack[SP]
⚫ Examples from Basic Computer
⚫ CLA, CMA, INP
Immediate Addressing
⚫ Operand is part of instruction
⚫ Operand = address field
⚫ e.g. ADD 5
◼ Add 5 to contents of accumulator

◼ 5 is operand

⚫ No memory reference to fetch data

⚫ Fast
⚫ Limited range
⚫ Sometimes, require more bits than the address

Opcode Operand
 Addressing Modes

Direct Address Mode

⚫ Instruction specifies the memory address which can be

used directly to access the memory
⚫ Faster than the other memory addressing modes
⚫ Too many bits are needed to specify the address for a
large physical memory space
⚫ EA = IR(addr) (IR(addr): address field of IR)
⚫ e.g. ADD A
Add contents of cell A
to accumulator
Look in memory
at address A for operand
Indirect Addressing Mode

⚫ The address field of an instruction specifies the address of a

memory location that contains the address of the operand
⚫ When the abbreviated address is used large physical memory
can be addressed with a relatively small number of bits
⚫ Slow to acquire an operand because of an additional memory
access
⚫ EA = M[IR(address)]
⚫ e.g. ADD (A)
◼ Add contents of cell pointed to by contents of A to
accumulator
 Addressing Modes

Register Mode

⚫ Address specified in the instruction is the register address

⚫ Designated operand need to be in a register
⚫ Shorter address than the memory address
⚫ Saving address field in the instruction
⚫ Faster to acquire an operand than the memory addressing
⚫ EA = IR(R) (IR(R): Register field of IR)
⚫ Disadvantages
⚫ address space is very limited.
Register Indirect Mode
⚫ Instruction specifies a register which contains the memory
address of the operand
⚫ Saving instruction bits since register address is shorter than the
memory address
⚫ Slower to acquire an operand than both the register addressing
or memory addressing
⚫ EA = [IR(R)] ([x]: Content of x)
Autoincrement or Autodecrement Mode

◼ When the address in the register is used to access

memory, the value in the register is incremented or
decremented by 1 automatically
◼ Generally index register are used for iterative tasks,
◼ There is a need to increment or decrement the index
register after each reference to it.
⚫ Auto-indexing using increment can be depicted
as follows:
EA = (R)
R = (R) + 1
⚫ Auto-indexing using decrement can be
depicted as follows:
⚫ R = (R) - 1
⚫ EA = (R)
Indexed Adressing
⚫ In some machines, both indirect addressing and indexing
are provided, and it is possible to employ both in the same
instruction. There are two possibilities: The indexing is
performed either before or after the indirection.
⚫ If indexing is performed after the indirection, it is termed
postindexing
⚫ EA = (A) + (R)
⚫ First, the contents of the address field are used to access a
memory location containing an address. This address is then
indexed by the register value.
⚫ With preindexing, the indexing is performed before the
indirection:
⚫ EA = ( A + (R) )
⚫ An address is calculated, the calculated address contains
not the operand, but the address of the operand.
Displacement Addressing
⚫ EA = A + (R)
⚫ Address field hold two values
◼ A = base value
◼ R = register that holds displacement
◼ or vice versa
Displacement Addressing Diagram

Instruction

Opcode Register R Address A

Memory

Registers

Pointer to Operand + Operand

Relative Addressing
⚫ A version of displacement addressing
⚫ R = Program counter, PC
⚫ EA = A + (PC)
⚫ i.e. get operand from A cells from current
location pointed to by PC
⚫ c.f locality of reference & cache usage
Base-Register Addressing
⚫ A holds displacement
⚫ R holds pointer to base address
⚫ R may be explicit or implicit
⚫ e.g. segment registers in 80x86
Indexed Addressing
⚫ A = base
⚫ R = displacement
⚫ EA = A + R
⚫ Good for accessing arrays
◼ EA = A + R
◼ R++
Stack Addressing:

⚫ A stack is a linear array or list of locations. It is

sometimes referred to as a pushdown list or last-in-
first-out queue. A stack is a reserved block of
locations. Items are appended to the top of the
stack so that, at any given time, the block is
partially filled. Associated with the stack is a
pointer whose value is the address of the top of the
stack. The stack pointer is maintained in a register.
Thus, references to stack locations in memory are
in fact register indirect addresses.
⚫ The stack mode of addressing is a form of implied
addressing. The machine instructions need not
include a memory reference but implicitly operate
on the top of the stack.
Stack Addressing
⚫ Operand is (implicitly) on top of stack
⚫ e.g.
◼ ADD Pop top two items from stack
and add
ADDRESSING MODES - EXAMPLES -
 Addressing Modes
Name Assem bler syn tax Addressing function
⚫ The different
ways in Immediate #V alue Op erand = Value
which the
location of Register Ri EA = R i
an operand Absolute (Direct) LOC EA = LOC
is specified
in an Indirect (R i ) EA = [R i ]
instruction (LOC) EA = [LOC]
are referred
to as Index X(R i) EA = [R i ] + X
addressing Base with index (R i ,R j ) EA = [R i ] + [R j ]
modes.
Base with index X(R i,R j ) EA = [R i ] + [R j ] + X
and offset

Relative X(PC) EA = [PC] + X

Autoincremen t (R i )+ EA = [R i ] ;
Incremen t R i

Autodecrement − (R i ) Decremen t R i ;
EA = [R i]
questions
⚫ Registers R1 and R2 contain decimal values
1200 and 4600. What is the effective address of
the memory operand and the type of
addressing modes used in each of the following
instructions?
⚫ a) load 20( R1 ), R5
⚫ b) move #3000, R5
⚫ c) store R5, 30(R1,R2)
⚫ d) add –(R2) , R5
⚫ e) sub (R1)+, R5
Questions and answer
⚫ Registers R1 and R2 contain decimal values 1200
and 4600. What is the effective address of the
memory operand and the type of addressing
modes used in each of the following instructions?
⚫ a) load 20( R1 ), R5// index EA=1220
⚫ b) move #3000, R5// immediate R5<-3000
⚫ c) store R5, 30(R1,R2) // base with index and offset
//EA=5830

⚫ d) add –(R2) , R5 //Auto decrement

EA=4599
⚫ e) sub (R1)+, R5 //auto increment
EA=1200
Questions
⚫ A processor has 16 integer registers (R0, R1, .. ,
R15) and 64 floating point registers (F0, F1,… ,
F63). It uses a 2-byte instruction format. There are
four categories of instructions:Type-1, Type-
2, Type-3, and Type-4. Type-1 category consists of
four instructions, each with 3 integer register
operands (3Rs). Type-2 category consists of eight
instructions, each with 2 floating point register
operands (2Fs). Type-3 category consists of
fourteen instructions, each with one integer
register operand and one floating point register
operand (1R+1F). Type-4 category consists of N
instructions, each with a floating point register
operand (1F).
⚫ The maximum value of N is __________.
Answer
⚫ Given, size of instruction format is 2 byte (= 16 bits),
therefore number of instruction encoding = 216
⚫ total number of bits in integer operand = log2(16 integer
registers) = 4
⚫ Total number of bits in floating point operand = log2(64
floating point registers) = 6
⚫ Type-1 category consists of four instructions, each with
3 integer register operands (3Rs).
⚫ number of encoding consumed:
⚫ By type 1 instructions = 4×23×4 = 214
⚫ Type-2 category consists of eight instructions,
each with 2 floating point register operands
(2Fs).
⚫ By type 2 instructions = 8×22×6 = 215

⚫ Type-3 category consists of fourteen

instructions, each with one integer register
operand and one floating point register
operand (1R+1F).
⚫ By type 3 instructions = 14×2(4+6) = 14336
⚫ Type-4 category consists of N instructions,
each with a floating point register operand (1F).
⚫ N*2^6

⚫ Now, number of encoding left for type 4 instructions =

216 − (214 + 215 + 14336) = 2048
Therefore, total number of different instructions of type
4 instructions = 2048 /64 = 32
 Data Transfer and Manipulation

DATA TRANSFER INSTRUCTIONS

• Typical Data Transfer Instructions
Name Mnemonic
Load LD
Store ST
Move MOV
Exchange XCH
Input IN
Output OUT
Push PUSH
Pop POP

• Data Transfer Instructions with Different Addressing Modes

Assembly
Mode Convention Register Transfer
Direct address LD ADR AC  M[ADR]
Indirect address LD @ADR AC  M[M[ADR]]
Relative address LD $ADR AC  M[PC + ADR]
Immediate operand LD #NBR AC  NBR
Index addressing LD ADR(X) AC  M[ADR + XR]
Register LD R1 AC  R1
Register indirect LD (R1) AC  M[R1]
Autoincrement LD (R1)+ AC  M[R1], R1  R1 + 1
Autodecrement LD -(R1) R1  R1 - 1, AC  M[R1]
CISC AND RISC ARCHITECTURE
⚫ Computer architectures have evolved over the
years.
⚫ Features that were developed for mainframes
and supercomputers in the 1960s and 1970s
have started to appear on a regular basis on
later generation microprocessors.
⚫ Two broad classifications of ISA:
⚫ a) Complex Instruction Set Computer (CISC)
⚫ b) Reduced Instruction Set Computer (RISC)
CISC versus RISC Architectures
⚫ Complex Instruction Set Computer (CISC)
◼ More traditional approach.

⚫ Main features:
◼ Complex instruction set

◼ Large number of addressing modes (R-R, R-M, M-M, indexed,

indirect, etc.)
◼ Special-purpose registers and Flags (sign, zero, carry,
overflow, etc.)
◼ Variable-length instructions / Complex instruction encoding

◼ Ease of mapping high-level language statements to machine

instructions
◼ Instruction decoding / control unit design more complex

◼ Pipeline implementation quite complex

Register Set Pentium
Addressing modes inVAX
Reduced Instruction Set Computer
(RISC)
⚫ Very widely used among many manufacturers today.
⚫ Also referred to as Load-Store Architecture.
⚫ Only LOAD and STORE instructions access memory.
⚫ All other instructions operate on processor registers.
⚫ Main features:
◼ Simple architecture for the sake of efficient pipelining.

◼ Simple instruction set with very few addressing modes.

◼ Large number of general-purpose registers; very few special-

purpose.
◼ Instruction length and encoding uniform for easy instruction
decoding.
◼ Compiler assisted scheduling of pipeline for improved
performance.
RISC

Example: Evaluate (A+B)  (C+D)

⚫ RISC
1. LOAD R1, A ; R1 ← M[A]
2. LOAD R2, B ; R2 ← M[B]
3. LOAD R3, C ; R3 ← M[C]
4. LOAD R4, D ; R4 ← M[D]
5. ADD R1, R1, R2 ; R1 ← R1 + R2
6. ADD R3, R3, R4 ; R3 ← R3 + R4
7. MUL R1, R1, R3 ; R1 ← R1  R3
8. STORE X, R1 ; M[X] ← R1
Results of a Comparative Study
⚫ A quantitative comparison of VAX 8700 (a CISC
machine) and MIPS M2000 (a RISC machine) with
comparable organizations was carried out in 1991.
⚫ Some findings:
◼ MIPS required execution of about twice the number of
instructions as compared to VAX.
◼ Cycles Per Instructions (CPI) for VAX was about six times
larger than that of MIPS.
◼ Hence, MIPS had three times the performance of VAX.
◼ Also, much less hardware is required to build MIPS as
compared to VAX.
Conclusion:
⚫ Persisting with CISC architecture is too costly, both in terms of
hardware cost and also performance.
⚫ VAX was replaced by ALPHA (a RISC processor) by Digital
Equipment Corporation (DEC).
⚫ CISC architecture based on x86 is different.
⚫ Because of huge number of installed base, backward compatibility
of machine code is very important from commercial point of view.
⚫ They have adopted a balanced view:
◼ (a) user’s view is a CISC instruction set,

◼ (b) hardware translates every CISC instruction into an

equivalent set of RISC instructions internally,
◼ (c) an instruction pipeline executes the RISC instructions
efficiently.