Analog IC Design LAB MANUAL Subject Code : Laboratory II Regulations : R18-JNTUH Class : IT Year Il Sem. M.Tech (VLSI System Design) Department of Electronics and Communication Engineering BHARAT INSTITUTE OF ENGINEERING AND TECHNOLOGY Ibrahimpatnam - 501 510, HyderabadBharat Institute Of Engineering & Technology Analog IC Design Lab Manual By BHARAT INSTITUTE OF ENGINEERING AND TECHNOLOGY Ibrahimpatnam - 501 510, Hyderabad ELECTRONICS AND COMMUNICATION ENGINEERING VISION AND MISSION OF THE INSTITUTION Vision To achieve autonomous and university status and spread universal education by inculcating discipline, character and knowledge into the young minds and mounds them into enlightened citizens. Mission Our mission is to impart education in a conductive ambience as comprehensive as possible with the support of all the modern technologies and make the students acquire the ability and passion to work wisely, creatively and effectively for the betterment of our society. SION AND MISSION OF ECE DEPARTMEN’ Vision The vision of the Department of Electronics and Communication Engineering is to effectively serve the educational needs of local and rural students within the core area of electronics and communication engineering and develop high quality engineers and responsible citizens. Mission The mission of the Department of Electronics and Communication Engineering is to work closely with industry, research organizations to provide high quality education in both theoretical and practical applications of electronics and communication engineering.Bharat Institute Of Engineering & Technology Analog IC Design Lab Manual | @)| BHARAT INSTITUTE OF ENGINEERING AND TECHNOLOGY Ibrahimpatnam - 501 510, Hyderabad ELECTRONICS AND COMMUNICATION ENGINEERING ational Objectives (PEOs: A graduate of the Electronics & Communication Engineering Program should: Program Educational Objective 1: (PEO1) Graduates will be able to synthesize mathematics, science, engineering fundamentals, laboratory and work-based experiences to formulate and solve engineering problems in Electronics and Communication engineering domains and shall have proficiency in Computer-based engineering and the use of computational tools design of electronics systems. Program Educational Objective 2: (PEO2) Graduates will succeed in entry-level engineering positions within the core Electronics and Communication Engineering, computational or manufacturing firms in regional, national, or international industries and with government agencies. Program Educational Objective 3: (PEO3) Graduates will succeed in the pursuit of advanced degrees in Engineering or other fields where a solid foundation in mathematics, basic science, and engineering fundamentals is required... Program Educational Objective 4: (PEO4) Graduates will be prepared to communicate and work effectively on team based engineering projects and will practice the ethics of their profession consistent with a sense of social responsibility. Program Educational Objective 4: (PEOS) Graduates will be prepared to undertake Research and Development works in the areas of Electronics and Communication fields. Sey POI | Engineering knowledge: Apply the knowledge of mathematics, science, engineering fundamentals, and an engineering specialization to the solution of complex engineering problems related to Electronics and Communication Engineering. PO2 | Problem analysis: Identify, formulate, review research literature, and analyze complex engineering problems related to Electronics and Communication Engineering and reaching substantiated conclusions using first principles of mathematics, natural sciences, and engineering sciences.Bharat Institute Of Engineering & Technology Analog IC Design Lab Manual PO3 Design/development of solutions: Design solutions for complex engineering problems related to Electronics and Communication Engineering and design system components or processes that meet the specified needs with appropriate consideration for the public health and safety, and the cultural, societal, and environmental considerations. PO4 Conduct investigations of complex problems: Use research-based knowledge and research methods including design of experiments, analysis and interpretation of data, and synthesis of the information to provide valid conclusions. POS; Modern tool usage: Create, select, and apply appropriate techniques, resources, and modem engineering and Electronics and Communication Engineering tools including prediction and modeling to complex engineering activities with an understanding of the limitations. PO6 ‘The engineer and society: Apply reasoning informed by the contextual knowledge to assess societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to the Electronics and Communication Engineering professional engineering practice. PO7 Environment and sustainability Understand the impact of the Electronics and Communication Engineering professional engineering solutions in societal and environmental contexts, and demonstrate the knowledge of, and need for sustainable development. POS Ethies: Apply ethical principles and commit to professional ethics and responsibilities and norms of the engineering practice. PO9 Individual and team work: Function effectively as an individual, and as a member or leader in diverse teams, and in multidisciplinary settings. POIO ‘Communication: Communicate effectively on complex engineering activities with the engineering community and with society at large, such as, being able to comprehend and write effective reports and design documentation, make effective presentations, and give and receive clear instructions. POI Project management and finance: Demonstrate knowledge and understanding of the engineering and management principles and apply these to one’s own work, as a member and leader in a team, to manage projects and in multidisciplinary environments. POI2 Life-long learning: Recognize the need for, and have the preparation and ability to engage in independent and life-long leaming in the broadest context of technological change.Bharat Institute Of Engineering & Technology Analog IC Design Lab Manual PSOL PSO1:Professional Skills: An ability to understand the basic concepts in Electronies & Communication Engineering and to apply them to various areas, like Electronics, Communications, Signal processing, VLSI, Embedded systems etc., in the design and implementation of complex systems. PSO2 PSO2:Problem-Solving Skills: An ability to solve complex Electronics and communication Engineering problems, using latest hardware and software tools, along with analytical skills to arrive cost effective and appropriate solutions PSO3 PSO3: Successful Career and Entrepreneurship: An understanding of social- awareness & environmental-wisdom along with ethical responsibility to have a successful career and to sustain passion and zeal for real-world applications using optimal resources as an Entrepreneur.Bharat Institute Of Engineering & Technology Analog IC Design Lab Manual LIST OF EXPERIMENTS Differentiator Lambda Calculation for PMOS and NMOS 17 Design and Simulation of simple current 25 Mirror Design and Simulation of Wilson current 27 Mirror Design and Simulation of Cascade current 29 Mirror Design and Simulation of Cascode current 31 Mirror Design and Simulation of Regulated Cascade 34 Configuration *To Design a High pass, first order 36 Butterworth Filter with a cut-off frequency of f,=1.0 kHz *To Design the Op-Amp as an Integrator and 38 * Topic beyond syllabusBharat Institute Of Engineering & Technology Analog IC Design Lab Manual ANALOG IC DESIGN LAB OBJECTIVES: To understand the basic concept of analog IC design. Furthermore, to develop the necessary framework and tools to analyze and design such systems. HARDWARE REQUIREMENTS: Intel based PC with minimum of 3.60 MHz or faster processor with at least AGB RAM and ITB free disk space Mentor Graphics Software. COURSE OUTCOMES: 1. To understand the SPICE software for circuit design To understand the basics of analog IC design. Lear the behavior of MOSFET and different types of amplifiers To understand the analog circuit implementation using standard cells and Simulation and Design verification. Exposure to analog circuit design techniques in integrated context. To understand the circuit synthesis and Place and Route. To understand Layout, DRC, LVS, Post-layout verifications.Bharat Institute Of Engineering & Technology Analog IC Design Lab Manual Mapping course outcomes leading to the achievement of the program outcomes: Program specific Course Program outcomes outcomes ‘outcomes P02 | Pos | Pos | Pos | Pos | po7| Pos | Pos | Poro | port | por? | psor | pso2 | Pso3 col 3 (3 22 2 I [- [- 22 2 | B OB OB OLB coz 323 2 If 2? ef PB PB iS COs 232i if PB PB OB Coa 2 13 12 | |} | |) |) 12] }) 1343 13 ‘COs 313125811? ier ip Dp ii C06 3 (3 2 2 I I [ 2 2 - FF OB OB #O&B co7 213 13 21- [ [- 22 - -F OB OB OSB dow 2-supportive Shighly relatedBharat Institute Of Engineering & Technology Analog IC Design Lab Manual ATTAINMENT OF PROGRAM OUTCOMES & PROGRAM SPECIFIC OUTCOMES Sr.No. Name of __ the Experiment Program Outcomes (POs) Attained Program Specific outcomes (PSOs) attained Lambda calculation for PMOS and NMOS PO1,PO2,PO3,PO5,PO9, PO10, POI2 PSO1I,PSO2,PSO3 Transconductance plot PO1,PO2,P03,PO5,PO9 PSO1,PSO2,PSO3 Ideal Current source PMOS & NMOS PO1,PO2,PO3,PO5,PO9 PSO1,PSO2,PSO3 NMOS saturated load POI,PO2,PO3,PO5,PO9 PSO1,PSO2,PSO3 ae Single transistor amplifier POI,PO2,PO3,PO5,PO9 PSO1I,PSO2,PSO3 Cascade amplifier PO1,PO2,PO3,PO5,PO9 PSO1,PSO2,PSO3 Wilson current mirror PO1,PO2,PO3,PO5,PO9 PSO1,PSO2,PSO3 Cascade current mirror PO1,PO2,PO3,PO5,PO9 PSO1,PSO2,PSO3 Cascode current mirror PO1,PO2,PO3,PO5,PO9 PSO1I,PSO2,PSO3 Regulated Cascade current mirror PO1,PO2,PO3,PO5,PO9 PSO1I,PSO2,PSO3 *To Design a High pass, first order Butterworth Filter with a cut-off frequency of fL=1.0 kHz PO1,PO2,PO3,PO5,PO9 PSO1,PSO2,PSO3 *To Design the Op- Amp as an Integrator and Differentiator PO1,PO2,P03,PO5,PO9 PSO1,PSO2,PSO3 *Topic beyond syllabusBharat Institute Of Engineering & Technology Analog IC Design Lab Manual VLSI CAD Tool Overview SPICE: SPICE (Simulation Program for Integrated Circuits Emphasis) is an electronic circuit simulator tool developed at University of Berkeley. Many different versions of SPICE are available from many different vendors. Common SPICEs include HSPICE, TANNER and PSPICE ete. It has parts library over 30000 parts and graphical editor also. SPICE takes a circuit net list and performs simulation of the circuit behavior. It also provides log of simulation process, errors, warnings, and statistic at each simulation run, MICROWIND & DSCH Tool: Microwind 3 is a user friendly PC based for Windows tool (95, 98, NT, XP) for desi editing facilities (cut, paste, duplicate, move, stretch), attractive views (MOS characteristics, 2-D sroelectronic circuits. The tool features full ing and simulating cross-section), an also on simulator. DSCH3 is the companion software for logic design. Based on primitives, a hierarchical circuit is built and simulated. Interactive symbols are used for friendly simulation, which includes power consumption. Mentor Graphics Design & simulate with Mentor Graphics tools as follows with five basi steps. 1. Design the schematic in Pyxis. 2 3. Layout the schematic in Pyxis. 4, Perform Physical Verification using Calibre, which includes DRC, LVS and PEX & Net list ulate the schematic and check for parameters. Extraction. 5. Back annotation of parasitic into the schematic.Bharat Institute Of Engineering & Technology Analog IC Design Lab Manual INVOKING MENTOR TOOLS: Right click on the Linux desktop and click on open in terminal. 1. Type csh and press enter. 2. Type source /home/software/eshre/eshre130.eshre 3. Type ed /home/software/FOUNDRY/GDK/Pyxis_SPT_HEP 4, Type /pyxismgr and press enter then pyxis project manager window will be invoked as shown below. ‘Ble at Wew Jerminal Tabs Help [rooteeead-17 ~148 csh [root@€cad-17 ~]# source /none/software/cshre/eshre138.cshre [root@€cad-17 ~]4 cd /nome/software/FOUNDRY/GOK/Pyxis_ SPT MEP [rootaecad-17 Pyxis SPT WEP]® ./pyxisnar{] CREATING A PROJECT: To create a new project click on File » New project, this will invoke the new project window as shown. >Bharat Institute Of Engineering & Technology Analog IC Design Lab Manual Select the project path in the project navigator window. Select the root folder. ‘Next technology libraries have to be added to the project. In order to add the technology files browse on the folder as shown. +Bharat Institute Of Engineering & Technology Analog IC Design Lab Manual Browse the folder to root/software/FOUNDRY/GDK/Pyxis_SPT_HEP/ic_reflibs/tech_libs/generic 13 file and click on OK. ‘Again click on OK then manage external/logie libraries window will pop up as shown, Click on the Add Standard Libraries. The libraries will be added up as shown below and click on OK.Bharat Institute Of Engineering & Technology Analog IC Design Lab Manual Then the pyxis project manager window will be shown where the technology libraries are added to the project and are placed below the project name. CREATING A LIBRARY: To create a library right click on the project name and select new library or click on the icon on the icon bar. CREATING A SCHEMATIC CELL VIEW: To create a schematic cell view, a new cell has to be created in which new Schematic has to be defined, In order to create new cell right click on the manual library below the project name and. select new cell or select the library and click on the icon in the icon bar. Then a new cell window will pop up asking for the cell name in which give the cell name and click OK. To create a schematic in the cell, right click on the cell name and select new schem: Teams peentn eh osi e eineeree eeBharat Institute Of Engineering & Technology Analog IC Design Lab Manual or click on the new cell and select the icon in the icon bar. for the schematic name, A window will pop up askit Schematename: | schematic cainame: {inv Now name the schematic and click on OK which in turn leads to the pyxis schematic editor window as shown. CREATING A SCHEMATI In this section you will become familiar with pla You'll learn how to: + place primitives on the schematic + select and manipulate dev + customizing hotkeys for placing devices + route devices + edit device parameter values ng primitive devices for a inverter + name instances * check and save the schematic + create upper hierarchical symbols * create test bench + simulate using eldo * view results: Select Transient Setup and change the Stop time to 1000N click on ApplyBharat Institute Of Engineering & Technology Analog IC Design Lab Manual Click on Measurement tool in the icon bar which opens up the measurement tool window where |we can measure the different properties of your waveforms.Bharat Institute Of Engineering & Technology Analog IC Design Lab Manual Expe en' Lambda calculation for PMOS and NMOS. TOOLS USED: 1. Operating System-Linux 2, Mentor Graphics Tool. Theory: Mentor graphics to draw the MOS layout and simulate its behavior. The layout window features a grid, scaled in lambda units. The lambda unit is fixed to half of the minimum available lithography of the technology. De or fe Sma Soot Ano dee ia SCR vPro®iQd Deere ase «2 MCE Es ‘stoves . geoe ic £Eu+ ss unwe [vekcome Mevowind 70 04707008 Tr Figure Initialization stage The palette is located in the lower right comer of the screen. A red color indicates the current layer. Initially the selected layer in the palette is polysilicon. By using the following procedure, you can create a manual design of the n-channel MOS.Bharat Institute Of Engineering & Technology Analog IC Design Lab Manual 1. Fix the first comer of the box with the mouse. While keeping the mouse button pressed, move the mouse to the opposite corner of the box. Release the button, This creates a box in polysilicon layer as shown in Figure above. The box width should not be inferior to 2, which is the minimum width of the polysilicon box. 2. Change the current layer into N+ diffusion by a click on the palette of the Diffusion N+ button, Make sure that the red layer is now the N+ Diffusion. Draw a n-diffusion box at the bottom of the drawing as in Figure below. N-diffusion boxes are represented in green. The intersection between diffusion and polysilicon creates the channel of the nMOS device. Figure Creating the N-channel MOS transistorBharat Institute Of Engineering & Technology Analog IC Design Lab Manual Figure Layout of PMOS transistor Figure The cross-section of the nMOS devices >Bharat Institute Of Engineering & Technology Analog IC Design Lab Manual NMOS gate @otysilicon) Thick oxide (si02) Figure 2D view of CMOS inverter. VDD supply NWell PMOS device Output node Poly Gate ‘NMOS device VSS supply Input routing Output routing Figure Complete Layout of CMOS inverter ——————Bharat Institute Of Engineering & Technology Analog IC Design Lab Manual In the example of Figure above, three nodes appear in the cross-section of the n-channel MOS device: the gate (red), the left diffusion called source (green) and the right diffusion called drain (green), over a substrate (gray). A thin oxide called the gate oxide isolates the gate. Various steps of oxidation have lead to stacked oxides on the top of the gate. The physical properties of the source and of the drain are exactly the same. Theoretically, the source is the origin of channel impurities. In the case of this nMOS device, the channel impurities are the electrons. Therefore, the source is the diffusion area with the lowest voltage. The polysilicon gate floats over the channel, and splits the diffusion into 2 zones, the source and the drain. The gate controls the current flow from the drain to the source, both ways. A high voltage on the gate attracts electrons below the gate, creates an electron channel and enables current to flow. Static MOS Characteristics Click on the MOS characteristics icon. The screen shown in Figure below appears. It represents the Id/Vd static characteristics of the nMOS device. - 3] 3| oT : Figure Static Characteristic of MOS >Bharat Institute Of Engineering & Technology Analog IC Design Lab Manual The MOS size (width and length of the channel situated at the intersection of the polysilicon gate and the diffusion) has a strong influence on the value of the current. The MOS width is 3.25jm and the length is 0.25um. A high gate voltage (Vg =2.5V) corresponds to the highest Id/Vd curve. For Vg=0, no current flows. A maximum current around 1.5mA is obtained for Vg=2.5V, Vd=2.5V, with Vs=0.0. The MOS parameters correspond to SPICE Level 3 Simulation Click on Simulate a Start Simulation. The timing diagrams of the NMOS device appear, as shown in Figure below. oo. oo to 30__49 ntag (otapes and eovanl fTage Ne vel Figure. Analog simulation of the MOS device. When the gate is at zero, no channel exists so the node s1 is disconnected from the drain. When the gate is on, the source copies the drain. It can be observed that the nMOS device drives well at zero but poorly at the high voltage. The highest value of sI is around 2.0V, that is VDD minus the threshold voltage. This means that the n-channel MOS device do not drives well logic signal 1, asBharat Institute Of Engineering & Technology Analog IC Design Lab Manual summarized in figure below. Click on More in order to perform more simulations. Click on Close to return to the editor. an! c ~~ Ww a . Wont SW Figure. The nMOS device behavior summary Figure. PMOS device behavior summaryBharat Institute Of Engineering & Technology Analog IC Design Lab Manual MOS Model For the evaluation of the current Ids between the drain and the source as a function of Vd,Vg and Vs. Move ConprTi0n, EXPRESSION FOR THE CURRENT IDS CUT-OFF Vgs<0 Ids =0 LINEAR VdsVes- Ids = KP/2 w (es-v2 ED. vt With: vt=VTO+ GAMMA+ (PHI —vb) — VPHT Conclusion: — Layout of CMOS inverter is done. Simulation is verified successfully. Questions 1. Why NMOS technology is preferred more than PMOS technology? 2. What are the advantages of Twin-tub process? 3. What are the advantages of CMOS process? 4. What is Stick diagram? 5. What are the uses of Stick diagram? 6. Give the various color coding used in stick diagram? 7. What is Body effect? 8. What is Channel-length modulation? 9. What are LVS and DRC tools? 10. What is the difference between simulation and synthesis?Bharat Institute Of Engineering & Technology Analog IC Design Lab Manual Experiment Ni Objective: Design and Simulation of simple Current Mirror TOOLS USED: 1. Operating System-Linux 2. MENTOR GRAPHICS Tool. Theory: A basic current mirror is shown in below figure. It is composed of two transistors, of which one, Mlis diode-connected. M1 receives the reference current Iref and measures it by developing at its gate the voltage VGSI this voltage biases the gate of M2. Figure shows a basic two transistor NMOS current source. The drain and source terminals of the enhanced-mode transistor M1 are connected, which means that Mlalways biased in the saturation region because a MOS transistor behaves as a small signal resistor, when gate and drain are shorted. A transistor in this configuration is referred to as “diode — connected” transistor. The device is always in saturation, Vout>> vss Figure Schematic view of current mirror.Bharat Institute Of Engineering & Technology Analog IC Design Lab Manual Questions 1, Define current mirror output equations 2, Define output resistance of current mirror. 3. Define the ICopy equation from a current mirror using [Mosfet] 4, How does a current mirror produce an amplified current? What is the physical process behind it? 5. How does the voltage difference develop when MOSFET is biased with Current Source? 6. Define Simple MOS current mirror bias circuit 7. What is the impedance of basic mosfet current mirror. 8, Why the extra transistors in this current mirror? 9. Why is the current mirrors output unequal’? 10, How to minimize the effect of threshold voltage mismatch of a current mirror? 11, Why Supply voltage in a current mirror necessary? 12, What is the Input stage of a current mirror circuit?Bharat Institute Of Engineering & Technology Analog IC Design Lab Manual Experiment Ni Objective: Design and Simulation of Wilson current mirror TOOLS USED: 1. Operating System-Linux 2, MENTOR GRAPHICS Tool. Theory: In this current mirror, Shunt-series negative feedback technique is used to improve the output impedance and stabilize the output drain current. In contrast to other existing implementations, it does not require a static current flow and can therefore offer considerable static power savings. Voltapesource_2| igure Schematic view of Wilson current mirror.Bharat Institute Of Engineering & Technology Analog IC Design Lab Manual Simulation Results con is wel (MNMOS 5 » 2 ez £ 5 3° lin (uA) Figure Simulation results Conclusion: The design process is implemented using MENTOR GRAPHICS EDA tool in 130 nm technology. Hence developed the schematic and simulation results is done. Questions 1. Define output Impedance of a Wilson Current Mirror. 2. In Cascode Current Mirror, define Minimum output voltage. 3. Define the output current of Wilson mirror. 4, Designing a MOSFET Wilson current mirror circuitBharat Institute Of Engineering & Technology Analog IC Design Lab Manual Experiment Ni Aim: Design and Simulation of Cascade current mirror TOOLS USED: 1. Operating System-Linux 2. MENTOR GRAPHICS Tool Theory of cascade current mirro: Current mirrors are frequently used in analog and mixed signal circuit design and because they appear so simple, their importance is sometimes overlooked. The design of an improved regulated cascode current mirror that offers very higher resolution and high speed. This can be accomplished by a feedback loop consisting of an amplifier and M2 (i.e. NMOS_1) as source follower, thereby increasing the output resistance (ideally infinite). The performance of the circuit was analyzed using simulations based on a 130nm technology. This circuit has a limitation that the minimum level of output swing is limited, because drain-source voltage of M1 never touches. Figure Schematic view of regulated Cascade current mirrorBharat Institute Of Engineering & Technology Analog IC Design Lab Manual Simulation Results Current (nA) iin (uA) Figure Simulation results of regulated Cascade current mirror Conclusion: The design process is implemented using MENTOR GRAPHICS tool in 130 nm technology. Hence developed the schematic and simulation results is done. QUESTIONS 1. How to calculate the output voltage of the mirror circuit?Bharat Institute Of Engineering & Technology Analog IC Design Lab Manual Experiment 5 Objective: Design and Simulation of Cascode current mirror TOOLS USED: 1. Operating System-Linux 2. MENTOR GRAPHICS Tool Theory: Current mirror circuits are widely used, especially within integrated circuit technology. The mirror circuit generally consists of two transistors, although other devices such as FETs can be used, and some configurations do use more than two devices in the overall circuit to obtain better performance. The current mirror circuit gains its name because it copies or mirrors the current flowing in one active device in another, keeping the output current constant regardless of loading. The current being mirrored can be a constant current, or it can be a varying signal dependent upon the requirement and hence the circuit. Conceptually, an ideal current mirror is simply an ideal inver ing current amplifier that reverses the current direction as well or it is a current-controlled current source (CCS). The current mirror is used to provide bias currents and active loads to circuits, A cascoded current mirror device is disclosed that is capable of producing an output current that is a direct function of an input current received by that device. The cascoded current mirror includes at least two portions connected together in a cascode manner. Provision is also made for feedback connection between those portions. This feedback connection can, for example, be a buffering connection. Voltage signals are generated by this device that can be used to drive and control additional output stages. Each such additional output stage is capable of producing an additional output currentBharat Institute Of Engineering & Technology Analog IC Design Lab Manual Figure Schematic view of cascode current mirror. Simulation Results Current (uA) fim (WA) Figure Simulation results of cascode current mirror >Bharat Institute Of Engineering & Technology Analog IC Design Lab Manual Conclusion: The design process is implemented using MENTOR GRAPHICS tool in 130 nm technology. Hence developed the schematic and simulation results is done. Questions 1. What are the advantages of cascode current mirror? 2. What is the equation of Ro? 3. How does a cascode current mirror maintain equal Vds of the bottom transistors?Bharat Institute Of Engineering & Technology Analog IC Design Lab Manual Experiment Ni Objective: Design and Simulation of regulated cascade configuration. TOOLS USED: 1. Operating System-Linux 2, MENTOR GRAPHICS Tool. Theory: The cascode configuration has a couple of advantages over the traditional common- source amplifier. Consequently, the gain of the overall circuit is increased. Another benefit is achieved from a speed perspective. It was stated above that one of the main benefits of the cascode was to increase the output resistance of the common-source amplifier, thus increasing the gain. This modification was successful because the assumption of very large drain-source of the traditional common-source resistance is no longer valid when dealing with small geometry T™ devices. Figure Schematic of cascode configuration.Bharat Institute Of Engineering & Technology Analog IC Design Lab Manual Simulation Results R.=100K, gain = 24.15 4B K Ri=10K, gain = 22.24 4B Ri=1K, gain = 17.21.68 Figure Schematic of Cascade current mirror QUESTIONS 1. Define Cascode current mirror: current to voltage 2. Why do we use current mirrors? 3. How to bias the MOST current mirror?Bharat Institute Of Engineering & Technology Analog IC Design Lab Manual Experiment No. 7 Objective: To Design a High pass, first order Butterworth Filter with a cut-off frequency of fL=1.0 kHz TOOLS USED: 1. Operating System-Red Hat-16.02 2. MENTOR GRAPHICS Tool Theory The Butterworth filter is a type of signal processing filter designed to have as flat frequency response as possible (no ripples) in the pass-band and zero roll off response in the stop-band. Butterworth filters are one of the most commonly used digital filters in motion analysis and in audio circuits, They are fast and simple to use. However, one main disadvantage of the Butterworth filter is that it achieves this pass band flatness at the expense of a wide transition band as the filter changes from the pass band to the stop band. It also has poor phase characteristics as well. 19 920 98 90° Comer JIst-order Maximally flat ‘@nd-order 03 F (Hz) Normalised FrequencyBharat Institute Of Engineering & Technology Analog IC Design Lab Manual ‘That the higher the Butterworth filter order, the higher the number of cascaded stages there are within the filter design, and the doser the filter becomes to the ideal "brick wall" response. 27KO 16k. 0.33 vo Fig High Pass Butterworth Filter Fig Frequency Response curve Conclusion: Simulation results are verified correctlyBharat Institute Of Engineering & Technology Analog IC Design Lab Manual Experiment Ni Objective: To Design the Op-Amp as an Integrator and Differentiator TOOLS USED: 1. Operating System-Red Hat-16.02 2. MENTOR GRAPHICS Tool Theory In an integrator circuit, the output voltage is integral of the input signal. At low frequencies the gain becomes infinite, so the capacitor is fully charged and behaves like an open circuit, The gain of an integrator at low frequency can be limited by connecting a resistor in shunt with capacitor. In the differentiator circuit, the output voltage is the differentiation of the input voltage. The input impedance of this circuit decreases with increase in frequency, thereby making the circuit sensitive to high frequency noise. At high frequencies, circuit may become unstable Re ct Bf Fig. Operation Amplifier as an Differentiator Conclusion: Simulation results are verified correctly.