Code No: CS301ES Set No.

2A
BHARAT INSTITUTE OF ENGINEERING AND TECHNOLOGY
B .Tech. II Year I Sem., II MID -Term Examinations, 14.02.2022
ANALOG AND DIGITAL ELECTRONICS (Common for CSE, IT)
Objective Exam

Name: ______________________________ Hall Ticket No. A

Answer All Questions. All Questions Carry Equal Marks. Time: 20 Min. Marks: 10.
I. Choose the correct alternative:
1. In a multiplexer, the selection of a particular input line is controlled by_____. [ ]
A) Selection lines B) Data controller C) Logic gates D) Both data controller and selected lines

2. How many select lines would be required for an 8-line-to-1-line multiplexer? [ ]

A) 2 B) 3 C) 4 D) 8

3. 4 to 1 MUX would have _________ inputs. [ ]

A) 2 B) 3 inputs C) 4 inputs D) 5 inputs

4. How many inputs will a decimal-to-BCD encoder have? [ ]

A) 2 B) 4 C) 8 D) 10

5. A code converter is a logic circuit that ____________. [ ]

A)Converts data of one type into another type B) Converts into decimal number C) Inverts the given input D) None

6. On a J-K flip-flop, when is the flip-flop in a hold condition? [ ]

A) J = 1, K = 0 B) J = 0, K = 0 C) J = 0, K = 1 D) J = 1, K = 1

7. The full form of SR in SR latch is __________. [ ]

A) System rated B) Set ready C) Set reset D) None of the Mentioned

8. The characteristic of J-K flip-flop is similar to _________. [ ]

A) T flip-flop B) D flip-flop C) SR and T flip-flop D)T

9. The chip by which both the operation of read and write is performed is ____. [ ]
A) RAM B) ROM C) PROM D) EPROM

10. PAL refers to ______________. [ ]

A) Programmable Array Loaded B) Programmable Array Logic C) Programmable Logic Array D) Programmable Loaded Array

II Fill in the Blanks:

11. The number of NOT gates required for the construction of a 4-to-1 multiplexer is __________

12. The word demultiplex means _________________.

13. A basic S-R flip-flop can be constructed by cross-coupling of ________________ logic gates.
14. In D flip-flop, D stands for ___________.

15. Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as counters. After four input clock pulses,
the binary count is ________

16. In D flip-flop, if clock input is LOW, the Q output is ___________________.

17. Master slave flip flop is also referred to as _____________________________.

18. If one wants to design a binary counter, preferred type of flip-flop is __________.

19. Which of the following flip-flops is free from race around problem? _______________________.

20. A decimal counter has ______ states.

* * *
 Code No: CS301ES Set No. 2B
BHARAT INSTITUTE OF ENGINEERING AND TECHNOLOGY
B .Tech. II Year I Sem., II MID -Term Examinations, 14.02.2022
ANALOG AND DIGITAL ELECTRONICS (Common for CSE, IT)
Objective Exam

Name: ______________________________ Hall Ticket No. A

Answer All Questions. All Questions Carry Equal Marks. Time: 20 Min. Marks: 10.
I. Choose the correct alternative:
1. How many inputs will a decimal-to-BCD encoder have? [ ]
A) 2 B) 4 C) 8 D) 10

2. A code converter is a logic circuit that ____________. [ ]

A)Converts data of one type into another type B) Converts into decimal number C) Inverts the given input D) None

3. On a J-K flip-flop, when is the flip-flop in a hold condition? [ ]

A) J = 1, K = 0 B) J = 0, K = 0 C) J = 0, K = 1 D) J = 1, K = 1

4. The full form of SR in SR latch is __________. [ ]

A) System rated B) Set ready C) Set reset D) None of the Mentioned

5. The characteristic of J-K flip-flop is similar to _________. [ ]

A) T flip-flop B) D flip-flop C) SR and T flip-flop D)T

6. The chip by which both the operation of read and write is performed is ____. [ ]
A) RAM B) ROM C) PROM D) EPROM

7. PAL refers to ______________. [ ]

A) Programmable Array Loaded B) Programmable Array Logic C) Programmable Logic Array D) Programmable Loaded Array

8. In a multiplexer, the selection of a particular input line is controlled by_____. [ ]

A) Selection lines B) Data controller C) Logic gates D) Both data controller and selected lines

9. How many select lines would be required for an 8-line-to-1-line multiplexer? [ ]

A) 2 B) 3 C) 4 D) 8

10. 4 to 1 MUX would have _________ inputs. [ ]

A) 2 B) 3 inputs C) 4 inputs D) 5 inputs

II Fill in the Blanks:

11. In D flip-flop, D stands for ___________.

12. Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as counters. After four input clock pulses,
the binary count is ________

13. In D flip-flop, if clock input is LOW, the Q output is ___________________.

14. Master slave flip flop is also referred to as _____________________________.

15. If one wants to design a binary counter, preferred type of flip-flop is __________.

16. Which of the following flip-flops is free from race around problem? _______________________.

17. A decimal counter has ______ states.

18. The number of NOT gates required for the construction of a 4-to-1 multiplexer is __________

19. The word demultiplex means _________________.

20. A basic S-R flip-flop can be constructed by cross-coupling of ________________ logic gates.
* * *
 Code No: CS301ES Set No. 2C
BHARAT INSTITUTE OF ENGINEERING AND TECHNOLOGY
B .Tech. II Year I Sem., II MID -Term Examinations, 14.02.2022
ANALOG AND DIGITAL ELECTRONICS (Common for CSE, IT)
Objective Exam

Name: ______________________________ Hall Ticket No.

A
Answer All Questions. All Questions Carry Equal Marks. Time: 20 Min. Marks: 10.
I. Choose the correct alternative:
1. The full form of SR in SR latch is __________. [ ]
A) System rated B) Set ready C) Set reset D) None of the Mentioned

2. The characteristic of J-K flip-flop is similar to _________. [ ]

A) T flip-flop B) D flip-flop C) SR and T flip-flop D)T

3. The chip by which both the operation of read and write is performed is ____. [ ]
A) RAM B) ROM C) PROM D) EPROM

4. PAL refers to ______________. [ ]

A) Programmable Array Loaded B) Programmable Array Logic C) Programmable Logic Array D) Programmable Loaded Array

5. In a multiplexer, the selection of a particular input line is controlled by_____. [ ]

A) Selection lines B) Data controller C) Logic gates D) Both data controller and selected lines

6. How many select lines would be required for an 8-line-to-1-line multiplexer? [ ]

A) 2 B) 3 C) 4 D) 8

7. 4 to 1 MUX would have _________ inputs. [ ]

A) 2 B) 3 inputs C) 4 inputs D) 5 inputs

8. How many inputs will a decimal-to-BCD encoder have? [ ]

A) 2 B) 4 C) 8 D) 10

9. A code converter is a logic circuit that ____________. [ ]

A)Converts data of one type into another type B) Converts into decimal number C) Inverts the given input D) None

10. On a J-K flip-flop, when is the flip-flop in a hold condition? [ ]

A) J = 1, K = 0 B) J = 0, K = 0 C) J = 0, K = 1 D) J = 1, K = 1

II Fill in the Blanks:

11. Master slave flip flop is also referred to as _____________________________.
12. If one wants to design a binary counter, preferred type of flip-flop is __________.

13. Which of the following flip-flops is free from race around problem? _______________________.
14. A decimal counter has ______ states.
15. The number of NOT gates required for the construction of a 4-to-1 multiplexer is __________

16. The word demultiplex means _________________.

17. A basic S-R flip-flop can be constructed by cross-coupling of ________________ logic gates.

18. In D flip-flop, D stands for ___________.

19. Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as counters. After four input clock pulses,
the binary count is ________

20. In D flip-flop, if clock input is LOW, the Q output is ___________________.

* * *
 Code No: CS301ES Set No. 2D
BHARAT INSTITUTE OF ENGINEERING AND TECHNOLOGY
B .Tech. II Year I Sem., II MID -Term Examinations, 14.02.2022
ANALOG AND DIGITAL ELECTRONICS (Common for CSE, IT)
Objective Exam

Name: ______________________________ Hall Ticket No. A

Answer All Questions. All Questions Carry Equal Marks. Time: 20 Min. Marks: 10.
I. Choose the correct alternative:
1. How many select lines would be required for an 8-line-to-1-line multiplexer? [ ]
A) 2 B) 3 C) 4 D) 8
2. 4 to 1 MUX would have _________ inputs. [ ]
A) 2 B) 3 inputs C) 4 inputs D) 5 inputs

3. How many inputs will a decimal-to-BCD encoder have? [ ]

A) 2 B) 4 C) 8 D) 10

4. A code converter is a logic circuit that ____________. [ ]

A)Converts data of one type into another type B) Converts into decimal number C) Inverts the given input D) None

5. On a J-K flip-flop, when is the flip-flop in a hold condition? [ ]

A) J = 1, K = 0 B) J = 0, K = 0 C) J = 0, K = 1 D) J = 1, K = 1

6. The full form of SR in SR latch is __________. [ ]

A) System rated B) Set ready C) Set reset D) None of the Mentioned

7. The characteristic of J-K flip-flop is similar to _________. [ ]

A) T flip-flop B) D flip-flop C) SR and T flip-flop D)T

8. The chip by which both the operation of read and write is performed is ____. [ ]
A) RAM B) ROM C) PROM D) EPROM

9. PAL refers to ______________. [ ]

A) Programmable Array Loaded B) Programmable Array Logic C) Programmable Logic Array D) Programmable Loaded Array

10. In a multiplexer, the selection of a particular input line is controlled by_____. [ ]

A) Selection lines B) Data controller C) Logic gates D) Both data controller and selected lines

II Fill in the Blanks:

11. The word demultiplex means _________________.

12. A basic S-R flip-flop can be constructed by cross-coupling of ________________ logic gates.

13. In D flip-flop, D stands for ___________.

14. Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as counters. After four input clock pulses,
the binary count is ________

15. In D flip-flop, if clock input is LOW, the Q output is ___________________.

16. Master slave flip flop is also referred to as _____________________________.

17. If one wants to design a binary counter, preferred type of flip-flop is __________.
18. Which of the following flip-flops is free from race around problem? _______________________.

19. A decimal counter has ______ states.

20. The number of NOT gates required for the construction of a 4-to-1 multiplexer is __________

* * *