QUESTION ONE

a) Draw the memory map of a microprocessor based system where one half of the memory address space is
read write memory, one quarter is non-writeable read only memory, one eighth is erasable but non-
volatile memory and four I/O devices. One I/O device is for supporting an asynchronous serial interface
for communication and the other three for providing a lot of general purpose input and output lines for
monitoring and control. Explain the positioning of the different memory types and input and output
devices. Select actual input and output peripheral components to suit the specification and give the typical
chip select structure for each of the memory and input and output devices. [10]

b) Construct the memory address decoding table and derive from first principles the size of each memory
address space and give the start and end address of each range. [4]

c) What is the purpose of memory address decoding logic? Use discrete random logic only, to implement the
memory address decoding which uses the smallest number of SSI packages. [6]

d) Explain, with reference to the memory map you constructed in a) above what memory mapped I/O is and
why it wastes a lot memory address space. What is the alternative to memory mapped I/O? Draw a
diagram of the memory maps of such a system. [5]

QUESTION TWO

a) Draw to scale accurate character frame timing diagrams on both the TTL side and the RS232 side for the
two ASCII characters: ‘Z’ and ‘#’ whose ASCII codes are $5A and $23 respectively. Assume 8 bits
per character, ODD parity and 1.5 stop bits. [4]

b) What is the function of the MAX232 chip in a serial link? Describe in detail what a local loopback test is
and what a remote loop back test is and how both can be performed around the MAX232 chip in the
testing and troubleshooting of the serial link of a microcomputer. [6]

c) What is a current loop and when is it used in data communications on a serial link and what is its main
advantage when compared to the normal serial system? With the use of diagrams, draw the transistor
level circuit configuration on both the transmitter side and the receiver side of the current loop and
explain its operation. [6]

d) Explain, with detailed drawings, how a bank of DIP switches would be used to enable an operator to set
the operational configuration of a serial link so that it matches that of the device on the other end of that
link. Clearly show the involvement of the PIA in that system. Typically, at what stage in the operation of
the system can the switches be changed so that the changes take effect? [5]

e) On the MC68HC11, the noise flag, NF, is used in place of the parity bit to detect transmission errors.
Explain when this flag bit is set and explain why the use of the noise flag is much more reliable than the
use of simple parity. What should be done on a serial link if there is excessive noise on the link and the
noise flag bit is being set in most of the received characters. [4]

1
 QUESTION THREE

a) Write down the five steps in the continuous sequence of operations while a processor is fetching and
executing instructions. At what stage in this continuous sequence is the presence of interrupts tested
before interrupts are honoured if they are pending? [7]

b) What is a stack and what are the main components central to the operation of a stack? How is a stack
initialized? [4]

c) There are four different possible stack mechanisms. Describe the four different mechanisms and clearly
explain their operation with the use of ISPS (instruction set processor specification) code. [6]

d) With the use of ISPS code, explain in detail the enable cycle bus by bus execution of the immediate
addressing mode instruction ADDA #$75 with machine code: 8B 75 stored starting at address $E793.
Show clearly what is on the address bus and what is on the data bus for each bus cycle. [8]

QUESTION FOUR

a) Manually convert the assembly language subroutine given as listing Q.4 to machine code for the
MC68HC11 microcontroller and write down the Intel hex format and Motorola S format records and
include the end of file (EOF) record in each case. [15]

PORTD EQU $1008

SPI_EXCHANGE EQU $F980
WRITE_ENABLE PSHA
LDAA PORTD
ANDA #$1F
STAA PORTD
LDAA #$06 ; WREN
JSR SPI_EXCHANGE
LDAA PORTD
ORAA #$20
STAA PORTD
PULA
RTS
Listing Q.4

b) What is the branch range of a short branch instruction? Explain how the target address is arrived at after
the execution of a relative branch instruction. What technique can be used to make the short branch
instruction reach the entire 64 kilobyte memory address space. [3]

c) Two values: a and b are being compared. For each of the cases below, determine the state of the critical
arithmetic flags which are used in determining if the comparison conditions are true or false. Note that
these are all 8-bit signed two’s complement comparisons, i.e. both a and b are signed 8-bit two’s
complement numbers. [7]

i) a > b ii) a = b iii) a >= b iv) a <= b v) a < b vi) a > b vii) a <> b
2
 QUESTION FIVE

a) Describe the operation of the following instructions within the instruction set of the MC68HC11
microcontroller: MUL, IDIV and FDIV. State the registers which bring in the input parameters or
operands and those where the results are stored. State clearly the difference between the two divide
instructions. [6]

b) Describe the operation of an input capture channel and an output comparison channel and explain how
both can be related to each other in an automated process control operation. [4]

c) Explain how the speed of a DC motor can be changed by altering its effective DC voltage supply through
pulse width modulation. Explain how an output comparison channel can be used to automatically handle
the control of the speed of a DC motor through pulse width modulation. Draw a complete schematic
diagram from the constant DC voltage source through the several transistors required to be controlled by
the output comparison channel output pin. [15]

QUESTION SIX

a) The I2C interface has two lines or wires: the data line SDA and the clock line SCL together with an
additional ground reference which could be a third line or wire if the connected systems are not on the
same printed circuit board. Draw a diagram which shows two systems connected together through the I 2C
interface. Explain the operation of the data line and the clock line and describe the start condition (S),
the stop condition (P) and the repeated start condition (Sr). Also describe the normal operation of the
two lines during normal data transfer. [8]

b) Describe 7 bit and 10 bit addressing on an I2C interface. [5]

c) Draw a diagram which shows the internal components of two SPI subsystems and clearly label one
subsystem the master and the other one the slave. Explain, with the use of this diagram, an SPI exchange.
[6]

d) With the use of detailed timing diagrams, explain how the MC68HC11 can perform a read operation of
the 25LC640 serial EEPROM. [6]