UC284XA

UC384XA

HIGH PERFORMANCE CURRENT MODE PWM CONTROLLER

NOT FOR NEW DESIGN

1 FEATURES Figure 1. Package

■ TRIMMED OSCILLATOR DISCHARGE
CURRENT
■ CURRENT MODE OPERATION TO 500kHz
AUTOMATIC FEED FORWARD DIP-8 SO-8
COMPENSATION
■ LATCHING PWM FOR CYCLE-BY-CYCLE Table 1. Order Codes
CURRENT LIMITING
■ INTERNALLY TRIMMED REFERENCE WITH Part Number Package
UNDERVOLTAGE LOCKOUT UC2842AD1; UC3842AD1;
■ HIGH CURRENT TOTEM POLE OUTPUT UC2843AD1; UC3843AD1;
SO-8
UNDERVOLTAGE LOCKOUT WITH UC2844AD1; UC3844AD1;
HYSTERESIS UC2845AD1; UC3845AD1
■ LOW START-UP CURRENT (< 0.5mA) UC2842AN; UC3842AN;
DOUBLE PULSE SUPPRESSION UC2843AN; UC3843AN;
DIP-8
UC2844AN; UC3844AN;
2 DESCRIPTION UC2845AN; UC3845AN
The UC384xA family of control ICs provides the
necessary features to implement off-line or DC to
DC fixed frequency current mode control schemes Differences between members of this family are
with a minimal external parts count. Internally im- the under-voltage lockout thresholds and maxi-
plemented circuits include a trimmed oscillator for mum duty cycle ranges. The UC3842A and
precise DUTY CYCLE CONTROL under voltage UC3844A have UVLO thresholds of 16V (on) and
lockout featuring start-up current less than 0.5mA, 10V (off), ideally suited off-line applications The
a precision reference trimmed for accuracy at the corresponding thresholds for the UC3843A and
error amp input, logic to insure latched operation, UC3845A are 8.5 V and 7.9V. The UC3842A and
a PWM comparator which also provides current UC3843A can operate to duty cycles approaching
limit control, and a totem pole output stage de- 100%. A range of the zero to < 50 % is obtained by
signed to source or sink high peak current. The the UC3844A and UC3845A by the addition of an
output stage, suitable for driving N-Channel MOS- internal toggle flip flop which blanks the output off
FETs, is low in the off-state. every other clock cycle.

Figure 2. Block Diagram (toggle flip flop used only in UC3844A and UC3845A)

7
Vi

34V UVLO
5V 8 VREF
5 S/R
GROUND REF 5V 50mA

INTERNAL
2.50V BIAS

VREF GOOD
LOGIC 6
OUTPUT
4
RT/CT OSC T

ERROR AMP.
+ 2R S
2
VFB - R PWM
R 1V LATCH
1
COMP CURRENT
SENSE
3
CURRENT COMPARATOR
SENSE
D95IN331

REV. 5
May 2004 1/16
UC384XA - UC284XA

Table 2. Absolute Maximum Ratings

Symbol Parameter Value Unit
Vi Supply Voltage (low impedance source) 30 V
Vi Supply Voltage (Ii < 30mA) Self Limiting
IO Output Current ±1 A
EO Output Energy (capacitive load) 5 µJ
Analog Inputs (pins 2, 3) – 0.3 to 5.5 V
Error Amplifier Output Sink Current 10 mA
Ptot Power Dissipation at Tamb ≤ 25 °C (DIP-8) 1.25 W
Ptot Power Dissipation at Tamb ≤ 25 °C (SO-8) 800 mW
Tstg Storage Temperature Range – 65 to 150 °C
TJ Junction Operating Temperature – 40 to 150 °C
TL Lead Temperature (soldering 10s) 300 °C
* All voltages are with respect to pin 5, all currents are positive into the specified terminal.

Figure 3. DIP-8/SO-8 Pin Connection (Top view)

COMP 1 8 VREF
VFB 2 7 Vi
ISENSE 3 6 OUTPUT
RT/CT 4 5 GROUND
D95IN332

Table 3. Pin Description

N° Pin Function

1 COMP This pin is the Error Amplifier output and is made available for loop compensation.

2 VFB This is the inverting input of the Error Amplifier. It is normally connected to the switching power
supply output through a resistor divider.

3 ISENSE A voltage proportional to inductor current is connected to this input. The PWM uses this
information to terminate the output switch conduction.

4 RT/CT The oscillator frequency and maximum Output duty cycle are programmed by connecting
resistor RT to Vref and cpacitor CT to ground. Operation to 500kHz is possible.

5 GROUND This pin is the combined control circuitry and power ground.

6 OUTPUT This output directly drives the gate of a power MOSFET. Peak currents up to 1A are sourced
and sunk by this pin.

7 VCC This pin is the positive supply of the control IC.

8 Vref This is the reference output. It provides charging current for capacitor CT through resistor RT.

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 UC384XA - UC284XA

Table 4. Thermal Data

Symbol Parameter DIP-8 SO-8 Unit
Rth j-amb Thermal Resistance Junction-ambient Max. 100 150 °C/W

Table 5. Electrical Characteristcs

( [note 1] Unless otherwise stated, these specifications apply for -25 < Tamb < 85°C for UC284XA;
0 < Tamb < 70°C for UC384XA; Vi = 15V (note 5); RT = 10K; CT = 3.3nF)
UC284XA UC384XA
Symbol Parameter Test Condition Unit
Min. Typ. Max. Min. Typ. Max.
REFERENCE SECTION
VREF Output Voltage Tj = 25°C Io= 1mA 4.95 5.00 5.05 4.90 5.00 5.10 V
∆VREF Line Regulation 12V ≤ Vi ≤ 25V 2 20 2 20 mV
∆VREF Load Regulation 1 ≤ Io ≤ 20mA 3 25 3 25 mV
∆VREF/∆T Temperature Stability (Note 2) 0.2 0.2 mV/°C
Total Output Variation Line, Load, Temperature 4.9 5.1 4.82 5.18 V
eN Output Noise Voltage 10Hz ≤ f ≤ 10KHz 50 50 µV
Tj = 25°C (note 2)
Long Term Stability Tamb = 125°C, 1000Hrs 5 25 5 25 mV
(note 2)
ISC Output Short Circuit -30 -100 -180 -30 -100 -180 mA
OSCILLATOR SECTION
fOSC Frequency Tj = 25°C 47 52 57 47 52 57 KHz
∆fOSC/∆V Frequency Change with Volt. VCC = 12V to 25V – 0.2 1 – 0.2 1 %
∆VREF/∆T Frequency Change with Temp. TA = Tlow to Thigh – 5 – – 5 – %
VOSC Oscillator Voltage Swing (peak to peak) – 1.6 – – 1.6 – V
Idischg Discharge Current (VOSC =2V) TJ = 25°C 7.8 8.3 8.8 7.8 8.3 8.8 mA
ERROR AMP SECTION
V2 Input Voltage VPIN1 = 2.5V 2.45 2.50 2.55 2.42 2.50 2.58 V
Ib Input Bias Current VFB = 5V -0.1 -1 -0.1 -2 µA
AVOL 2V ≤ Vo ≤ 4V 65 90 65 90 dB
BW Unity Gain Bandwidth TJ = 25°C 0.7 1 0.7 1 MHz
PSRR Power Supply Rejec. Ratio 12V ≤ Vi ≤ 25V 60 70 60 70 dB
Io Output Sink Current VPIN2 = 2.7V 2 12 2 12 mA
VPIN1= 1.1V
Io Output Source Current VPIN2 = 2.3V VPIN1 = 5V -0.5 -1 -0.5 -1 mA
VOUT High VPIN2 = 2.3V;RL = 15KΩ to 5 6.2 5 6.2 V
Ground
VOUT Low VPIN2 = 2.7V;RL = 15KΩ to 0.8 1.1 0.8 1.1 V
Pin 8
CURRENT SENSE SECTION
GV Gain (note 3 & 4) 2.85 3 3.15 2.85 3 3.15 V/V
V3 Maximum Input Signal VPIN1 = 5V (note 3) 0.9 1 1.1 0.9 1 1.1 V
SVR Supply Voltage Rejection 12 ≤ Vi ≤ 25V (note 3) 70 70 dB
Ib Input Bias Current -2 -10 -2 -10 µA
Delay to Output 150 300 150 300 ns

3/16
UC384XA - UC284XA

Table 5. Electrical Characteristcs (continued)

( [note 1] Unless otherwise stated, these specifications apply for -25 < Tamb < 85°C for UC284XA;
0 < Tamb < 70°C for UC384XA; Vi = 15V (note 5); RT = 10K; CT = 3.3nF)
UC284XA UC384XA
Symbol Parameter Test Condition Unit
Min. Typ. Max. Min. Typ. Max.
OUTPUT SECTION
VOL Output Low Level ISINK = 20mA 0.1 0.4 0.1 0.4 V
ISINK = 200mA 1.6 2.2 1.6 2.2 V
VOH Output High Level ISOURCE = 20mA 13 13.5 13 13.5 V
ISOURCE = 200mA 12 13.5 12 13.5 V
VOLS UVLO Saturation VCC = 6V; I 0.7 1.2 0.7 1.2 V
SINK = 1mA
tr Rise Time Tj = 25°C 50 150 50 150 ns
CL = 1nF (2)
tf Fall Time Tj = 25°C 50 150 50 150 ns
(2)
CL = 1nF
UNDER-VOLTAGE LOCKOUT SECTION
Start Threshold X842A/4A 15 16 17 14.5 16 17.5 V
X843A/5A 7.8 8.4 9.0 7.8 8.4 9.0 V
Min Operating Voltage X842A/4A 9 10 11 8.5 10 11.5 V
After Turn-on
PWM SECTION
Maximum Duty Cycle X842A/3A 94 96 100 94 96 100 %
X844A/5A 47 48 50 47 48 50 %
Minimum Duty Cycle 0 0 %
TOTAL STANDBY CURRENT
Ist Start-up Current Vi = 6.5V for UCX843A/ 0.3 0.5 0.3 0.5 mA
45A
Vi = 14V for UCX842A/44A 0.3 0.5 0.3 0.5 mA
Ii Operating Supply Current VPIN2 = VPIN3 = 0V 12 17 12 17 mA
Viz Zener Voltage Ii = 25mA 30 36 30 36 V

Notes: 1. Max package power dissipation limits must be respected; low duty cycle pulse techniques are used during test maintain Tj as close
to Tamb as possible.
2. These parameters, although guaranteed, are not 100% tested in production.
3. Parameter measured at trip point of latch with VPIN2 = 0.
4. Gain defined as : A = ∆VPIN1/∆VPIN3; 0 ≤ VPIN3 ≤ 0.8V
5. Adjust Vi above the start threshold before setting at 15 V.

4/16
 UC384XA - UC284XA

Figure 4. Open Loop Test Circuit.

VREF
4.7KΩ RT

2N2222 A Vi
VREF
0.1µF
100KΩ COMP 8
1 7
ERROR AMP. VFB Vi
2 1W
ADJUST 1KΩ 0.1µF
ISENSE 1KΩ
4.7KΩ ISENSE 3 OUTPUT
ADJUST 5KΩ 6 OUTPUT
RT/CT
4 GROUND
5

CT
D95IN343 GROUND

High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and
bypass capacitors should be connected close to pin 5 in a single point ground. The transistor and 5 KΩ
potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to pin 3.

Figure 5. Oscillator Frequency vs Timing Figure 7. Oscillator Discharge Current vs.

Resistance Temperature.
fo Idischg D95IN335
D96IN362
(Hz)
(mA)
Vi=15V
VOSC=2V
1M 8.5
CT
=4
70
pF
1nF

100K 2.2
nF
8.0
4.7
nF

10K 7.5

7.0
1K
300 1K 3K 10K 30K RT(Ω) -55 -25 0 25 50 75 100 TA(˚C)

Figure 6. Maximum Duty Cycle vs Timing Figure 8. Error Amp Open-Loop Gain and
Resistor Phase vs. Frequency.
fo D95IN337
(Hz)
D96IN363 (dB) φ
Vi=15V
VO=2V to 4V
80 30
80 RL=100K
Gain
TA=25˚C
60 60
60
40 90
Phase
40
20 120

20 0 150

-20 180
0
300 1K 3K 10K 30K RT(Ω) 10 100 1K 10K 100K 1M f(Hz)

5/16
UC384XA - UC284XA

Figure 9. Current Sense Input Threshold vs. Figure 12. Output Saturation Voltage vs. Load
Error Amp Output Voltage. Current.
Vth D95IN338 Vsat D95IN341
(V) (V)
Source Saturation
Vi=15V Vi
(Load to Ground)
1.0 -1
TA=25˚C TA=-40˚C
TA=25˚C
-2
0.8 Vi=15V
80µs Pulsed Load 120Hz Rate
TA=125˚C
0.6
3

0.4 TA=-40˚C
2
TA=25˚C
TA=-40˚C
0.2 1
Sink Saturation GND
(Load to Vi)
0.0 0
0 2 4 6 VO(V) 0 200 400 600 IO(mA)

Figure 10. Reference Voltage Change vs. Figure 13. Supply Current vs. Supply Voltage.
Source Current..
D95IN339 Ii D95IN342
60 (mA)
Vi=15V
50
20

40 TA=-40˚C
TA=125˚C 15
30
TA=25˚C

RT=10K
UCX843/45

UCX842/44

10 CT=3.3nF
20 VFB=0V
ISense=0V
5 TA=25˚C
10

0 0
0 20 40 60 80 100 Iref(mA) 0 10 20 30 Vi(V)

Figure 11. Reference Short Circuit Current vs.

Temperature..
D95IN340
ISC
(mA)
Vi=15V
100 RL≤0.1Ω

90

80

70

60

50
-55 -25 0 25 50 75 100 TA(˚C)

6/16
 UC384XA - UC284XA

Figure 14. Output Waveform. Figure 15. Output Cross Conduction

Figure 16. Oscillator and Output Waveforms.

Vi
7 CT
8
5V REG
OUTPUT
PWM
6
RT OUTPUT LARGE RT/SMALL CT
CLOCK
4
OSCILLATOR
CT
ID

CT OUTPUT

5 SMALL RT/LARGE CT
GND

D95IN344

Figure 17. Error Amp Configuration.

2.5V

1mA
+

VFB 2
Zi -
COMP 1
Zf
D95IN345

7/16
UC384XA - UC284XA

Figure 18. Under Voltage Lockout.

7 ON/OFF COMMAND
Vi TO REST OF IC ICC

<17mA
UC3842A UC3843A
UC3844A UC3845A
VON 16V 8.4V <0.5mA
VCC
VOFF 10V 7.6V VOFF VON

D95IN346mod

Figure 19. Current Sense Circuit.

ERROR
AMPL. 2R
IS
1 R 1V
COMP CURRENT
SENSE
R 3 COMPARATOR

CURRENT
RS C SENSE
5
GND
D95IN347
Peak current (is) is determined by the formula
1.0V
I Smax ≈ ------------
RS
A small RC filter may be required to suppress switch transients.

Figure 20. Slope Compensation Techniques.

VREG VREG
8 8
RT RT
RT/CT RT/CT
IS 4 IS 4
RSLOPE CT CT
RSLOPE
R1 ISENSE R1 ISENSE
3 3
5 5
RS RS
GND GND
D95IN348

8/16
 UC384XA - UC284XA

Figure 21. Isolated MOSFET Drive and Current Transformer Sensing.

VCC Vin

+ ISOLATION
5.0Vref BOUNDARY
-

VGS Waveforms

Q1 + +
+ 6 0 0
- - -
50% DC 25% DC
S
Q V(pin 1) -1.4

-
R Ipk =
3RS
( NN )
S

+
COMP/LATCH 3 R

C RS NS NP

D95IN349

Figure 22. Latched Shutdown.

4
OSC

8
R

BIAS

R +

1mA
+ 2R
-
2 EA
R

5
2N
3905

2N
3903

D95IN350

SCR must be selected for a holding current of less than 0.5mA at TA(min).
The simple two transistor circuit can be used in place of the SCR as shown. All resistors are 10K.

9/16
UC384XA - UC284XA

Figure 23. Error Amplifier Compensation

+
From VO 2.5V
1mA
Ri + 2R
-
2 EA
Rd Cf Rf R

1
5
Error Amp compensation circuit for stabilizing any current-mode topology except
for boost and flyback converters operating with continuous inductor current.

+
From VO 2.5V
1mA
RP + 2R
Ri
-
2 EA
CP Rd Cf Rf R

1
5 D95IN351

Error Amp compensation circuit for stabilizing current-mode boost and flyback
topologies operating with continuous inductor current.

Figure 24. External Clock Synchronization.

VREF
8
R

BIAS
RT R

4
OSC
+
CT
EXTERNAL
SYNC INPUT 2R
0.01µF +
-
2 EA
47Ω R
1

5
D95IN352
The diode clamp is required if the Sync amplitude is large enough to cause
the bottom side of CT to go more than 300mV below ground

10/16
 UC384XA - UC284XA

Figure 25. External Duty Cycle Clamp and Multi Unit Synchronization.

VREF 8

RA R

BIAS
8 4
RB 5K R
6
+ 3 4
5 R OSC
- +
5K Q 7

+ + 2R
2 S 2
- -
EA
C 5K R
1 NE555 1
5

TO ADDITIONAL
UCX84XAs
1.44 RB
f= Dmax = D95IN353
(RA + 2RB)C RA + 2RB

Figure 26. Soft-Start Circuit

8 5Vref

R
+
BIAS -
R

4
OSC
+

1mA S
+ 2R Q
2 +
- R
1MΩ EA R 1V -
1

C 5

D95IN354

11/16
UC384XA - UC284XA

Figure 27. Soft-Start and Error Amplifier Output Duty Cycle Clamp.

VCC Vin

+
8 5Vref
-
R
+
BIAS - 7
R

4 6
OSC Q1
+

1mA VClamp S
+ 2R - Q 5
2
- + R
EA R 1V
R2
1 Comp/Latch

5
RS
C R1 BC109
R1 VCLAMP
VCLAMP = · where 0 <VCLAMP <1V Ipk(max) = D95IN355
R1 + R 2 RS

12/16
 UC384XA - UC284XA

Figure 28. SO-8 Mechanical Data & Package Dimensions

mm inch
DIM. OUTLINE AND
MIN. TYP. MAX. MIN. TYP. MAX.
MECHANICAL DATA
A 1.35 1.75 0.053 0.069

A1 0.10 0.25 0.004 0.010

A2 1.10 1.65 0.043 0.065

B 0.33 0.51 0.013 0.020

C 0.19 0.25 0.007 0.010

D (1) 4.80 5.00 0.189 0.197

E 3.80 4.00 0.15 0.157

e 1.27 0.050

H 5.80 6.20 0.228 0.244

h 0.25 0.50 0.010 0.020

L 0.40 1.27 0.016 0.050

k 0˚ (min.), 8˚ (max.)

ddd 0.10 0.004

Note: (1) Dimensions D does not include mold flash, protru-

sions or gate burrs. SO-8
Mold flash, potrusions or gate burrs shall not exceed
0.15mm (.006inch) in total (both side).

0016023 C

13/16
UC384XA - UC284XA

Figure 29. DIP-8 Mechanical Data & Package Dimensions

mm inch
DIM. OUTLINE AND
MIN. TYP. MAX. MIN. TYP. MAX.
MECHANICAL DATA
A 3.32 0.131

a1 0.51 0.020

B 1.15 1.65 0.045 0.065

b 0.356 0.55 0.014 0.022

b1 0.204 0.304 0.008 0.012

D 10.92 0.430

E 7.95 9.75 0.313 0.384

e 2.54 0.100

e3 7.62 0.300

e4 7.62 0.300

F 6.6 0.260

I 5.08 0.200

L 3.18 3.81 0.125 0.150 DIP-8

Z 1.52 0.060

14/16
 UC384XA - UC284XA

Table 6. Revision History

Date Revision Description of Changes

March 1999 4 First Issue in EDOCS

May 2004 5 NOT FOR NEW DESIGN

15/16
UC384XA - UC284XA

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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