The Infineon 32-bit TriCore

A UDO-NG
TM

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Next Generation

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µController Features/Highlights
• very fast interrupt response
(approx. 10-15 cycles or < 0.1 µs @ 150 MHZ)

• Fast context switch

TC1.2 --> 4 cycles -> ½ context
TC1.3 --> 2 cycles -> ½ context
• 16-bit and 32-bit instruction formats
• Bit manipulation unit RISC Processor Feature/Highlights
• Accumulated logical/ compare
• 32-bit load/store Harvard architecture
• Integrated peripheral support
• 16 address & 16 data registers
• Super-scalar execution (4 stage pipeline)
FPU • Single data-memory model
• Memory protection
Tricore • C/ C++ and RTOS support
Powertrain • tightly coupled FPU unit
System Concepts
AUDO
AUDO-NG
DSP Features/Highlights
K. Scheibert
• Sustainable single-cycle dual-MAC
AI MC MA TM
V1.5 • DSP addressing modes
• Zero overhead loop
• Saturation and Q-Math
04/28/2002 • Overflow detection
Page 1 • Rounding
 A UDO-NG
TM

Merging MCU and DSP reduces cost and complexity

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Next Generation

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„ Control and DSP development and

integration/debug can all be done with RTOS + DSP + App
the same development tools
„ Optimized DSP library algorithms can
be used out of the box
TriCore
„ Easy adaptation of DSP functions
integrated in Automatic Code
Generation tool package Memory I/O
„ Devices can quickly be adapted to
Tricore
Powertrain
new market requirements
System Concepts
AUDO „ smaller silicon
AUDO-NG

K. Scheibert One CPU Fast Time to Market

AI MC MA TM
V1.5 TriCore™ One Tool New Features
One RTOS Lower Cost
04/28/2002
Page 2
 TriCore system architecture - AUDO-NG
A UDO-NG
TM

utomotiveUnifieD prOcessor

TriCore Version TC1.3/TC-1M Next Generation

Confidential
• High Performance 32-bit TriCore CPU (TC V1.3/
TC-1M) with 4-stage pipeline and dual issue super-
Program Memory
scalar implementation (fCPU = 150 MHz)
Program Memory Unit 64 • Register sets
- 2x16 address/data 32 bits registers
128 - Switch half context in 2 cycles

LMB Bus - split in PLMB and DLMB

(the other half in 2 cycles)
• Local Memory Bus (LMB)
- 64 bits data, separated busses used for
program and data (PLMB and DLMB)
FPU

• Interrupt System
16 Address 16 Data - Flexible multi-master interrupt system
Tricore 32 bits 32 bits
Powertrain (interrupts serviced by CPU, PCP or DMA)
Registers Registers
System Concepts - Hardware controlled context switch
AUDO - Hardware Interrupt Priority arbitration with
AUDO-NG
128 128 255 priority levels
K. Scheibert - very fast interrupt response time
AI MC MA TM (approx. 10-15 cycles or < 0,1 µs @ 150 MHz)
Data Memory Unit 64
V1.5
• powerful MAC unit supports circular buffer and
Data Memory bit-reverse addressing modes for DSP algorithms
04/28/2002
• single precision Floating Point Unit (FPU) with
Page 3 interrupt capability for exception handling
 A UDO-NG
TM

Four-Stage super-scalar TriCore Pipeline TM utomotiveUnifieD prOcessor

Next Generation

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Instruction 1
Instruction
Instruction 11 MAC MAC
Instruction 2 Write
Execute Execute
Back
Integer
32Bit Decode The
The Issue
Issue Unit
Unit
Instruction
Instruction 11
Fetch The Fetch
forwards Unit
Integer
forwards multiple
Execute
Fetches
multiple
64Bit Integer Pipeline
& multiple Instructions
Issue Instruction
Instruction into into the the
Tricore
Powertrain Load/
in
four
four parallel
pipelines(
pipelines(
Load/
(2-4)
1-3)
1-3)
System Concepts Write Load/Store Pipeline
AUDO 32Bit Store Store Instruction 2
ExecuteInstruction
Instruction21
Back
Instruction 322
AUDO-NG Instruction Decode
K. Scheibert
AI MC MA TM Instruction
Instruction 43
V1.5 Loop Instruction 213 Loop Pipeline
Loop Write
Cache
Execute Back
Buffer
04/28/2002
Page 4
 TriCore system architecture - AUDO-NG
A UDO-NG
TM

FPU - tightly coupled Coprocessor utomotiveUnifieD prOcessor

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Coproc. Pipeline
Coproc. Coproc. Coproc.
Decode Execute Execute

Integer MAC MAC Register

Decode Execute Execute Write
Back
Register Integer
Read Execute
Tricore Integer Pipeline
Powertrain
System Concepts
AUDO
AUDO-NG
Passing Instructions and
K. Scheibert
AI MC MA TM Register Content to Passing result from
V1.5
Coprocessor Coprocessor to Register
04/28/2002
Page 5
 TriCore system architecture - AUDO-NG
A UDO-NG
TM

FPU - tightly coupled to TriCore CPU utomotiveUnifieD prOcessor

Next Generation

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Operand values held in, accessed from and returned to regular data
registers of the TriCore CPU:

Î Direct load/stores of data to/from destination/source registers:

Î Load/Store: No need to load first to integer register file
and then pass-on of arguments to floating point registers
=> same speed for floating-point load/stores as for integer data
=> fast load/store
Tricore
Powertrain
System Concepts Î Preserves real-time capabilities:
AUDO
AUDO-NG Î Context switch works unaltered regardless of type of data
K. Scheibert Î Uncompromised context switch performance
AI MC MA TM
V1.5
„ Tightly coupled coprocessor reduces data Load/store
operations and increase real-time behaviour (context switch)
04/28/2002
Page 6
 A UDO-NG
TM

Efficient Context Saving and Restoring utomotiveUnifieD prOcessor

Next Generation

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„ Fast Interrupt/Function Call:

Task State Regs
„ Automatic Upper
Context Save at
Upper Upper Call/Interrupt/Trap
16 Addr.-REGS 16 Data-REGS „ Branch to target
Lower Lower address
„ Fetch target
64 bits 64 bits instruction
Tricore
Powertrain „ Programmable-size
System Concepts Context Contextn-1
Linked Context-Save-Areas in
AUDO
AUDO-NG Save Contextn
Lists HW-managed linked-lists:
Area Contextn+1 „ Zero Software
K. Scheibert
overhead
AI MC MA TM
V1.5

Single-ported On-chip Data Memory

04/28/2002
Page 7
 AUDO-NG
TM

Super-scalar execution utomotiveUnifieD prOcessor

Next Generation

Confidential

Triple / Dual / Single Issue ~1.3 instr/cycle

Triple Issue Arithmetic Load / Store Loop

Dual Issue Arithmetic Load / Store

Dual Issue Arithmetic Loop

Tricore Dual Issue Load / Store Loop

Powertrain
System Concepts
AUDO Single Issue Arithmetic
AUDO-NG

K. Scheibert Single Issue Load / Store

AI MC MA TM
V1.5
Single Issue Loop

04/28/2002
Page 8
 A UDO-NG
TM
powerful interrupt service system utomotiveUnifieD prOcessor
Next Generation

Confidential
Features Benefits
„ Common approach for interrupt „ Ease of programming
and DMA request processing „ High flexibility
„ Up to 4 x 255 request nodes (SRN), „ Large Number of SRNs
concurrently supported „ Flexible grouping of request into
priority groups
„ Dedicated Arbitration Pipeline (ICU) „ Short arbitration phase: max 4 cycles
„ Zero Software overhead

Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral

Tricore
7 6 5 4 3 2 1 0
Powertrain
SRN SRN SRN SRN SRN SRN
System Concepts
Arbitration SRC SRC SRC SRC SRC SRC
AUDO
AUDO-NG:
AUDO-NG Bus

K. Scheibert
Arbitration 4 cycles
AI MC MA TM FPI Bus
Low context switch 2 cycles
V1.5
Branch to ISR 2 cycles Int. Ack.
Interrupt
Pipeline fill 4 cycles Control
Upper context save 2 cycles Int. Req. Unit (ICU)
04/28/2002
Total
Page 9 14 cycles
 A UDO-NG
TM

TriCore - Supported DSP operations utomotiveUnifieD prOcessor

Next Generation

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Two MACs per cycle: Sensors signal processing:

Matrix calculus FIR, IIR, DFT, FFT,

ld k0,k1
setup ld x0,x1,x2,x3 + + +

1 cycle a1 a2 a3 a4
mac x0 k0
mac x1 k1 loop + z-1 z-1 z-1 z-1
ld k2,k3,k4,k5 ld x4,x5,x6,x7
Tricore
Powertrain b0 b1 b2 b3 b4
System Concepts mac x2,k2
AUDO 1 cycle
mac x3,k3 + + + +
AUDO-NG

K. Scheibert „ Dual 16x16 hardware MAC „ Zero overhead loop

AI MC MA TM
V1.5 „ Packed data „ Bit reverse addressing
„ Parallel load
„ Mac-load-(loop) per cycle
04/28/2002
Page 10
 Peripheral Control Processor (PCP Version 2)
A UDO-NG
TM

Features and Benefits utomotiveUnifieD prOcessor

Next Generation

Confidential
Features Benefits
16 KB PRAM • Smart interrupt driven Processor runs PCP serves as a “first line of defense” for
with fPCP=75 MHz @ fCPU=150 MHz intelligent programmable peripheral
SPB Interface

• Harvard Architecture with separated

Interrupts

PCP2 interrupt service requests

Core Local Code (CRAM) and Parameter
Memory (PRAM) SRAM sections
32 KB PCODE • Single cycle execution for most
implemented instructions
• Interrupt System
– HW controlled register context switch
– HW Interrupt priority arbitration with
Tricore 255 priority levels
Powertrain
System Concepts – very fast interrupt response time
AUDO (approx. 10-15 cycles or < 0.2 µs)
AUDO-NG – channel restart/resume mode
K. Scheibert
– each implemented SRN can be flexible
mapped to TriCore or PCP
AI MC MA TM
V1.5 • Enhanced PCP Version 2 functions:
– self-posted PCP interrupt queue
enlarged to 10 source request nodes
04/28/2002
– deadlock avoidance implemented
Page 11
– 3 nested interrupt levels supported
• PCP handles typical real-time critical tasks
– fast, interrupt-driven routines for peripheral
control (i.e. counterpart of GPTA)
– manipulation/data pre-conditioning of DMA
and peripheral data
• Channel restart/resume mode supports
interrupt-vector-table entry or flexible state-
machines with register context saved
re-entry vector on EXIT instruction
• Clear hierarchical SW partitioning possible
by mapping Low Level Driver Layer to PCP
• One embedded tool chain environment for
TriCore C-Compiler and PCP assembler
• Debugging/Emulation concept supports
TriCore/PCP multiprocessor approach
 A UDO-NG
TM

PCP system architecture

utomotiveUnifieD prOcessor
Next Generation

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„ Small interrupt driven

CRAM PRAM Processor on FPI bus
32KB 16KB
„ Local Code (CRAM) and
64
Parameter Memory (PRAM)
PCP-Core
32 – Accessible by FPI Masters as well
as by the PCP itself
„ PSRN / PICU for Interrupts
5 ... 10
Tricore
PSRN – separate PCP interrupt arbitration
FPI-Interface PICU
Powertrain Configuration bus
System Concepts
Registers PSRN
AUDO
2 ... 7
„ Configuration Registers
AUDO-NG
FPI Bus
32
PCP Interrupt Arbitration Bus

CPU Interrupt Arbitration Bus

accessible via FPI
K. Scheibert
AI MC MA TM „ Services Peripherals &
V1.5
Performs DMA
04/28/2002
Page 12
 A
UDO-NG
TM

PCP channel restart/resume mode on EXIT instruction

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Next Generation

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Up to 255 Channels / SRPNs

Context is the (Register) State of the Channel
Channel invocation: Channel invocation:
(PC is calculated with the priority number) (PC is loaded from the context)

PRAM PCP PCP Code PRAM PCP PCP Code

Tricore
Powertrain PIPN PIPN
System Concepts
AUDO
AUDO-NG

K. Scheibert N N N N N N N N
AI MC MA TM N N N N N N N N
V1.5
Arbitration Vector Table Arbitration

04/28/2002
Page 13
Channel Restart Mode Channel Resume Mode
 AUDO-NG (Next Generation) TC1766
A UDO-NG
TM

utomotiveUnifieD prOcessor
Next Generation

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FPU 128

Tricore Code 128

TriCore TriCore Data
Application (TC1.3/TC1M)
128

LMB 64

LFI

Low Level PCP 32

PCP 64
PCP
DMA
Code (V2) Data
Driver SW
Layer
FPI 32

Tricore
Powertrain Twin ADC FADC
Peripheral
System Concepts
Port Debug SCU STM ASC0 ASC1
CAN
GPTA MSC MLI SSC0 SSC1
32ch 2ch

AUDO
AUDO-NG

K. Scheibert TriCore V1.3 (fCPUmax= 80 MHz) PCP V2 (fPCPmax= 80 MHz)

AI MC MA TM Code: 16 Kbyte Boot ROM
Code: 12 Kbyte RAM
V1.5 4 Kbyte Scratch Pad RAM
Data: 8 Kbyte RAM
4 Kbyte Cache
1,5 Mbyte Flash
4 Kbyte EEPROM emulation
04/28/2002 32 Byte EEPROM
Page 14 Data: 56 Kbyte RAM
 AUDO-NG (Next Generation) TC1796
A UDO-NG
TM

utomotiveUnifieD prOcessor
Next Generation

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FPU 128

Tricore Code TriCore

EBU 128 TriCore Data
Application (TC1.3/TC1M)
128
DPRAM

LMB 64
LFI

Low Level PCP 32

PCP 64
PCP
DMA
Code (V2) Data
Driver SW
Layer
FPI 32 32 32

Tricore Multi
Powertrain CAN GPTA GPTA LTCA MSC1 MSC2
Peripheral
System Concepts
Port Debug SCU STM ASC0 ASC1
4 0 1 2
MLI1 MLI2 SSC0 SSC1 ADC0 ADC1 FADC
nodes
AUDO
AUDO-NG

K. Scheibert TriCore V1.3 (fCPUmax= 150 MHz) PCP V2 (fPCPmax= 75 MHz)

AI MC MA TM Code: 16 Kbyte Boot ROM Code: 32 Kbyte RAM
V1.5 48 Kbyte Scratch Pad RAM Data: 16 Kbyte RAM
16 Kbyte Cache
2 Mbyte Flash
16 Kbyte EEPROM emulation
04/28/2002 Data: 56 Kbyte RAM
Page 15 8 Kbyte Dual Port RAM
 AUDO-NG
A UDO-NG
TM

SW migration path (1): TriCore TC1.2 → TC1.3/TC-1M

utomotiveUnifieD prOcessor
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Program Memory Program Memory

Program Memory Unit 32 Program Memory Unit 64

LMB Bus - split in PLMB and DLMB

64 128

→ TriCore

FPU
TriCore

FPI Bus
TC1.2 16 Address 16 Data 16 Address 16 Data
TC1.3/TC-1M:
32 bits 32 bits 32 bits 32 bits
Registers Registers Registers Registers

64 64 128 128

Data Memory Unit 32 Data Memory Unit 64

Data Memory Data Memory

Tricore
Powertrain
System Concepts
AUDO • written SW modules are fully reusable by recompiling with TC1.3/TC-1M tool
AUDO-NG
chain
K. Scheibert • if the previous code used floating point operation, a recompile with TC1.3/TC-1M
AI MC MA TM
V1.5
provides more performance as it does implement the FPU;
(integrated interrupt capability for FPU exception handling has to be adapted)
• some minor initialization code adaptations for CPU related SFRs have to be
04/28/2002 regarded
Page 16
 AUDO-NG
A
UDO-NG
TM

SW migration path (2): PCP1 → PCP2

utomotiveUnifieD prOcessor
Next Generation

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• Improvements of PCP2: TC1796:
- single cycle execution for most instructions PCP2 runs with bus clock speed:
- up to 3 nested interrupts possible (fPCP = 75 MHz @ fCPU=150 MHz)
- self-posted PCP interrupt queue enlarged
from two to up to 10 possible Source Request
Nodes (SRN2-3/SRN4-8/SRN9-11) and 16 KB PRAM
deadlock avoidance implemented
- additional 5 Source Request Nodes (SRN4-8)

SPB Interface
implemented with programmable assignment

Interrupts
to TriCore CPU or PCP (this SRNs could be PCP2
used as well to enlarge the corresponding Core
interrupt queues)
Tricore
Powertrain - context save optimization; context is only
System Concepts loaded or restored if there is a need
AUDO - additional instruction BCOPY implemented 32 KB PCODE
AUDO-NG
for moving a block of data on the FPI/SPB
K. Scheibert bus by using burst mode with 2/4 or 8 words
AI MC MA TM - additional instructions MCLR/MSET
V1.5 implemented for multiple Bit Set/Clear within
PRAM
04/28/2002 • written PCP1 SW modules are fully reusable on PCP2;
Page 17
adaptation to the introduced improvements requires extra effort
 AUDO: System Architecture
A
AUDO’s triple layer
UDO-NG
TM
architectures perfectly fits to
utomotiveUnifieD prOcessor

Confidential
vertical mapping the demands of automotive
Next Generation

software structures
vertical mapping

Application
Layer
TriCore Code TriCore Data

INT
FPI Bus

Peripheral

Transport
PCP Code Control PCP Data

Layer
Physical Layer
Processor
INT
Tricore
Powertrain
System Concepts

Peripheral
AUDO
System Timer

Management

Layer
AUDO-NG
Real Time

USART 0
USART 1
Watchdog

TwinCAN
Ext.. Bus

PORTS
Module

ADC 0

ADC 1
Debug

Power

GPTU

J1850

SPI 0
SPI 1
GPTA
Interf.

Clock
PLL

K. Scheibert
AI MC MA TM
V1.5

Modular software architecture Cuts software development time

04/28/2002
Page 18 Optimised utilisation of hardware resources Reduced time to market
 example of vertical mapping
A UDO-NG
TM

utomotiveUnifieD prOcessor
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vertical mapping
Crankshaft signal

Application
Layer
1 Application Software

Acquisition and
Treatment 6 Flywheel Status Manager

5 Gap detection & verification

Transport Layer
4 Period prediction, Accel / Decel consistency

1 2
ECU
3 Micro ticks generation, Accel / Decel correction
3 +
- µC Period measurement, Stall detection,
Tricore 4 2
Powertrain Min/Max period consistency
System Concepts 1 Noise digital filtering
AUDO
AUDO-NG

K. Scheibert Physical Layer 4 Harware Shaping and Filtering

AI MC MA TM
V1.5 3 Connection and Wiring

2 Sensor
04/28/2002 1 Physical Flywheel
Page 19
 AUDO-NG architecture
A
UDO-NG
TM

optimized bus structure

utomotiveUnifieD prOcessor
Next Generation

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SRAM
FPU
SPSRAM
Application

DMU
PMU
TriCore
FLASH TC 1.3
DPSRAM

SYNCHRO.
CONTROL
EBU

DATA
LMB
LFI

Remote Peripheral Bus

Periph01
PCP Transfer
System Peripheral Bus

Tricore Periph02
Powertrain

SYNCHRO.
System Concepts

CONTROL
Bridge
AUDO DMA

DATA
Periph11
AUDO-NG

K. Scheibert
Periph12
AI MC MA TM MLI0 MLI1
V1.5
Periph1x
Peripherals
04/28/2002 Other EMU
Page 20 Core Device
 AUDO-NG architecture benefit
A UDO-NG
TM

independent data transfer capability utomotiveUnifieD prOcessor

Next Generation

Confidential

128 Cost for the TriCore/PCP

Remote Peripheral Bus

DPRAM - Usage = 0
128
- Wait = 0

SSC 16 bit 10 Mbit/s

Tricore
Powertrain DMA
System Concepts SSC 16 bit 10 Mbit/s
AUDO
AUDO-NG

K. Scheibert
MLI ADC 300 k.Sample/s
AI MC MA TM
V1.5 30 Mbit/s ADC 300 k.Sample/s
04/28/2002 FADC 2 M.Sample/s
Page 21