module CNT4b (clk,rst,SS,MODE,MIN,MAX,OUT);

input clk;
input rts;
input SS;
input MODE;
input [3:0] MIN;
input [3:0] MAX;
output reg[3:0] OUT;

always @ (posedge clk)

begin
if (rst==1b'1)
OUT= 4b'0;
else if (MODE==1b'1 && SS= 1b'1)
while(OUT < MAX)
OUT=OUT+1b'1;
else if (MODE==1b'0 && SS= 1b'1)
while(OUT > MAX)
OUT=OUT-1b'1;
else
OUT=OUT;
end
endmodule

module DFF(
input wire D,Clk,
output reg Q );

always @(posedge Clk)

Q = D ;
endmodule

module SISO_ShiftRegister(
input wire In, Clk,
output wire Out) ;

wire Q1,Q2,Q3 ;

DFF ff1 (In,Clk,Q1);

DFF ff2 (Q1,Clk,Q2);
DFF ff3 (Q2,Clk,Q3);
DFF ff4 (Q3,Clk,Out);
endmodule