Luan van tot nghiép KE CPUS ng VHDL. 2 1 DAU LOIN M61 thanh phn quan trong cila my tinh 18 b6 xif 1y trung tam (CPU) C6 rat nhiéu céng ste duge ddu wt vao vige chi céc may tinh dap ting yéu cdu ngay cng cao cba xa hdi. B6 cfing chinh 1a vy ma dé Windy dn thyc hién, Dé thigt k& mot CPU véi chife ning cdn m@t céng cu di manh. Trong s@ nhiing cong cu d6, ng6n ngit m6 ta phan eting (VHDL) sé duge sit dung trong dé tai nay Tir ngén ngit VHDL cdc nha thiét k& phan cting 6 thé thiét ké ra nhitng thiét bi phan cting nhut CPU, bé vi diéu khign... mét céch nhanh chéng va ciing cé thé thuc hién m6 phéng va kiém tra khd nang hoat d6ng cia thiét bi truéc Khi dva vao sin xudt, nhé vay c6 thé gidm bét thai gian, chi phf san xual... Do kha nang va tinh higu qua cia ngén ngd VHDL 1a dong cd chinh dé ching em chon dé (i “Thiét ké CPU ding ngén ng VHDL” lam dé (Ai cho lugn vin (St nghi¢p cia minh. Ching em chan thanh biét on toan thé quy thy c6 trong Khoa Céng Nghé Thong Tin Truting Dai Hoc Ky Thuat Cong Nghé TPHCM, xin chan thanh cdm on thay Lé Manh Hai da tn Ginh huéng dan ching em thyc hién Juan van nay. Trong thai gian ngiin, c6 1é chua div dé nghién citu sau mot dé Wai tuong d6i én, nén chée chdn kh6ng thé trénh khdi thi€u s6t, Kinh mong quy thay c6 gép y dé ching em tién bé them. Tp-HCM, ngay 03 thang 05 nim 2003 Huynh Thi Mong Tuyén Duong Huynh Thanh Tang GVHD: Lé Manh Hai Frang |Lugn vin tot nghiép Ké CPUS ding VHDL GIGI THIEU 1. MUC piCH Luan van nay thuc hién m@t sé cOng viée nhu sau. - Thiét ké CPU bling ngén ngit VHDL. - Thyc hién m6 phéng chvong tinh trén chip FLEX10K cia hang Altera. 1. BO CUC - Tim hiéu mét s@ khai niém cia cla ngén ngit VHDL va méi quan he gitta VHDL véi phan cing. - Céng nghé FPGA: tim hiéu mét sé thiét bi FPGAs. ‘Thiét ké CPU: thyc hign mé t4 nhi¢m vu ctia CPU, tip lénh ctia CPU, ché d6 dia chi Iénh cia CPU, hanh vi cia CPU, cde thanh phan cia CPU va viét chuong trinh dé thyc hin mét sé lénh cia CPU. - Thye hién m6 phdng chuong trinh ding phdn mém MAX+Plus II. GVHD: Lé Manh Hai Frang 2Luan van tot nghiép KE CPUS ng VHDL. MUC LUC LOINOI DAU G16] THIEL... I. MUC DCH 1. BO. cyc MUC LU Phin 1 VHDL VA FPGA. 1 GIGI THIEU... 1, Gidi thigu vé VHDL... 2. C&e dac diém cia VADL 1. CAC KHAI NIEM CO BAN 1. Cac khéi.. . 2. Gidi thigu hai don vi thi¢t ké eo ban cia VHDL. 2.1, Khai bao thye thé 2.2. Thc thé kién tric, 3. G6i IIL. MOI QUAN HE GIVA NGON NGU VHDL VA PHAN CCNG 1, Céc thanh phan cia VHDL dé mé ta phan cng. 1.1. Cée kigu cia VADL 1.2. Céc d6i tugng cia ngdn ng VHDL 1.3. Céc todn tit sé hoe 1.3.1, Céc todn tit 1uan ly 1.3.2. Cée todn tit quan he... 1.3.3. Céc todn tit cong 1.3.4, Cée tofin tit dich 1.3.5. Céc todn tit mot ngéi .. 6. Céc toan tit nhan. Céc lénh tudn ty ..... 1. Phép gan bit 2. Phép gén tin hiéu.. 43, Lenh didu kign. 4. Lenh lap.. 2. Su thé hién phan cting bling VHDL 2.1, Cac mach té hgp..... GVHD: Lé Manh Hai Trang 3Lugn vin tot nghiép Ké CPUS 2.1.1. Céc céng luan ly 21,2. Céc toan tit s6 hoe 2.1.3, Céc todn tit dich va quay 2.1.4. BO dén kén! 2.2. Cac mach déng b6 2.2.1, Mach cai 2.2.2. Thanh ghi Iv. CONG NGHE FPG. 1. Cac loai FPGA... 1.1.1. Céng nghé ap trinh ding RAM tinh 1.1.2. Céng nghé lap trinh diing edu chi nghich......rnnsnrnne 1.1.3. Céng nghé lap trinh EPROM va EEPROM. 20 1,2, Cac loai FPGA trén thi truéng, 2. Mat s6 ting dung cla FPGA. 3, Thiét bi Max, Flex ..... Phin2 = THIET KE CPU 1vU n.76 CHUC BO NUG CUA CPU I. TAP LENH CUA CPU IV. CHE DO DIA CHI CUA LENH V. HANH VI CPU....... 1, Dinh thai va ddng bé . 1.1. Gidn 48 dinh thoi dép tng ngdt quang 1.2, Gidn dé chu ky thyc hién lénh 1 byte 1,3. Gidn dé dinh thai chu ky thuc hign ede lénh ré nhanh va lénh jmp & ché “4. Gin 48 dinh thoi chu ky thu hi fa 1.5. Gin dé dinh thai chu ky thyc hién lénh jst Gidin dé dinh thd chu ky thyc hién lénh sta, 1.7. Gin dé dinh thai chu ky thuc hién lénh Ida, and, ade, sbe 1,8, Gidn dé dinh thai chu ky thyc hién lénh sta 2. Khéi phuc vu chufong trinh 3. Mé td hank vi cpu VLCAC THANH PHAN CUA CPU . 7 . 1, Chife nang ciia cdc thanh phan cita CPU. 39 GVHD: Lé Manh Hai Grang 4Luan van t6t nghiép KE CPUS ng VHDL. 2. Thyc hién lénh 3. M6 td cdc thanh phan 3.1, Dan vj ludn ly s6 hoe 41 3.2, Dan vi dich chuyén 3.3. Thanh ghi trang thai 3.4, Thanh ghi tich luy ‘Thanh ghi Iénh. B@ diéu khién cla CPU 9 Phin3 MO PHONG.. 1. MAX+PLUSII 1, Téng Quat. 2. Céch sit dung Max+PlusII 2.1. Thifc hién soan thao va dich mét chung (rink. 2.2. Thyc hién kiém tra két qua sau khi da téng hop mach 2.3, Thoat khdi Max+plusIl. 11. MAN HINH KHI MO PHONG 1. Khéi luan ly sé hoc ALU.. 2. Khéi dich chuyén SHU Khdi didu khién 4, So 46 chan CPU. 5. Man hinh mé phéng Iénh.. Phind KET LUAN KIEN NGHI.. I. NHAN XET CHUNG. a, Nhiing mat dat duge. ‘b. Nhiing van dé tén tai. I, HUONG PHAT TRIEN II. DANH GIA Phan 5 TAI LIEU THAM KHAO. 73 GVHD: Lé Manh Hai Trang 5Lugn van tét nghiép Ké CPUS ing VHDL Phin1 VHDL VA FPGA Phan I gidi thiéu ngén ngit VHDL va mét sé dac diém chinh cia né. Phan Ul trinh bay cdc khdi niém co ban vé khdi, thc thé, kién tric va g6i cia ngén ngit VHDL. Phan Il tinh bay méi quan hé mat thiét gitta ngén ngit VHDL va phan cing. Phan IV gidi thigu vé céng ngh¢ FPGA dé xay dung cdc mach tich hgp. 1. GIGI THIEU 1, Gidi thigu vé VHDL VHDL (VHDL 1a tit viét tt ciia Very Hight Speed Integrated Circuit Hardware Description Language) 12 mot ng6n ngit lap trinh 4% duge thiét ké theo c&ch mé td hnh vi cita hé théng s6.VHDL dude phat trién vao nhitng 1980. VHDL cé nhiéu dic diém thich hgp mé ta hank vi cda céc thanh phan thigt bi dign tit tir nhimng céng lugn I¥ don gidn dén nhitng b6 vi xit ly phife tap. Dac diém ca VHDL 1a cho phép mé t& chinh xéc hanh vi cla nhing mach dién tit. Cang gidng nhv ngén ngi Pascal, C va C++, VHDL bao gdm nhing dic diém hitu fch cho ky thudt thiGt ké nhiing edu tric va trinh bay nhtng dic diém dit ligu. Khong ging nhu nhing ngén ngi lap tink khéc, VHDL cung cp nhiing dic diém cho phép dé mé ta nhiing su kién xdy ra. (xem{1]) 2, Cie dic diém cia VHDL. M6t sé de diém chinh eila ngn ng VHDL (xem/4]) * Dae diém tong qudét: VHDL cé thé dude sit dung dé lap tai liéu thiét ké, thiét k€ mife 46 cao, mé phéng téng hgp va kiém tra phan cing. VHDL cho phép mé ta phan citng tiv mtfc hé théng dén mife céng, hé tr tinh dng thdi nghia 1a tiv céc hgp phan nhé dén Ién hoat d6ng tai mét thoi diém. * H6 rg phan cap thiét ké: Day 1a dac tinh thiét yu cia ngon ngit phan cting da cp. Thiét k€ chifa mét mé ta giao dién ya mét sé phan déc lap dé mé td hoat dong. Hoat dong ciia hé thdng 06 thé dude dic ta dya tren chife nang hodc dya trén edu tréc ctia nhiing phan nhé hon cia ching. Die td cdu tric cdc hop phan 6 thé dutge thuc hién 6 tt cd c&c cp thiét ké * C6 thi vign hi tro: NgOn ngit cung cp co ché aé truy cap dén nhiéu thy vién khéc nhau, Thu vién khéng chi chia dic ta giao di¢n cia GVHD: Lé Manh Hai Frang 6Luan van tot nghiép KE CPUS ng VHDL. thigt ké, mA cdn chita mét s6 dic t& cla hé théng. Cée dic t& va cée mau c6 thé dua vao thu vién sau khi dude dich béi chuong trinh dich. * C6 lenk tudn te: Khi ngudi thiét k& phan chia hé théng thanh nhiing hgp phan déng thai hay phan con, tiép 46 ngudi thiét ké c6 thé mé ta chi tit hoat déng bén trong bing nhiing cu trie ngén ngt Ip tinh tun ut nhu 4c Iénh case, if — then ~ else, loop,..CAc lénh tudn ty cung ep phyong phép don gidn dé tgo ra céc hgp phan phn ciing dya trén chiic ning cila ching, * Thiét ké tuong thich chung: Dé thiét ké tng quét ngén ngit cho phép nguéi thiét ké dat cu hinh m6 t& hgp phan c6 théng sé chung trong thiét ké, Mé ta tudng thich chung cé thé thay déi kich thuéc dic tinh vat ly, dinh thai dc tinh ti, va méi trudng hoat dong cia thiét ké. * Khai béo kiéu va cach ding: Ng6n ng VHDL cho phép mé ta céc ki€u bit, Boolean, integer, floating, kiéu liét ké, kiéu day, ban ghi, Ngoai ra con hé tro cdc kiéu do ngudi sit dung dinh nghia. Ng6n ngit VHDL ciing cho phép dinh nghia lai cdc ton ti cia ngén ngit bai ngudi sit dung * Sit dung cée chuong trinh con: Ng6n ngit VHDL cho phép dinh nghia cdc hm, thi tuc, cdc chudng trinh con cé thé sit dung dé bién déi céc ki€u, dinh nghia don vi ludn 1, dinh nghia lai toan hang, dinh nghia toan tir mi, va cdc ting dung khéc trong ngén ngit 1p tinh. * Diéu khién dinh thdi: Ngbn ng VHDL 1a cho phép dic ta dinh thoi 4 tat cd cde cp nhu 1a: dat gid ti cila tin hiéu, thai gian tré, dinh nghfa tin hiéu déng b6, dit 46 rdng xung ... u1. CAC KHAINIEM CO BAN (xem/1)) ic Khdi VHDL duige m6 ta thanh nhing kh6i, khéi dau ti¢n 1a don vj thigt ke, C6 5 loai don vi thiét ké duge phan thanh hai phan I phdn mé ta kién tric phan citng va phdn mém. +Phin ciing gém c6: Thue thé (entity), cu hinh (configuration), kién tric (architecture) +Phin mém gém c6: g6i (package) va than g6i (package body). 2. Gidi thigu hai don vi thiét ké co ban cilia VHDL Hai don vi thiét ké co ban cia VHDL 1a Entity declaration va Architecture body. GVHD: Lé Manh Hai Frang 7Luan van tot nghiép KE CPUS ng VHDL. M6t Entity 14 m6t mo hinh si dung mét Khai béo thuc thé va ft nhat e6 mét thyc thé kién tric. Khai bao thyc thé 1a mé td téng quat bén ngoai cia mét thye thé, vi du nhu; tén cdc tin hiéu input, output, Than cia kién trie (Architecture body) 1a di vao dic ta bén trong ciia mét thyc thé, vi dy thiét lap suf n6i két lién tue cia cdc thanh phan ma dai cho cfu tric cha mat thyc thé, hode tap hop tat cd cde phat biéu déng thdi hay lién we ma dai dign cho su xit ly eila thu thé. -Mé hinh ciia thye thé _ ——- Su trit nugng phdn ettng ela mOthé thong sé ‘Than kign tric Hinh 1. 2.1. Khai béo thie thé (Entity Delaration) Khai béo thuc thé 18 chi ra tén cia m6 hinh cn thiét ké va danh sach cdc céng giao tiép. Céng 1a nhifng tin hiéu ma thyc thé ding dé giao tiép v6i nhiing mé hinh khéc trong mdi truding (ng quat cba n6. Vidu: Entity mach_cong is Port(a.b : in bit; 1c : out bit ) 3 End mach_cong ; 2.2, Thue thé kién trite (Architecture Body) -Mé t4 chi i€t mOt thy thé duge chi ra bai kiGn trie cba thyte thé nhit sau Vi'dy: mé hinh cho thyc thé mach_cong, & dang céu trac (structural): Architecture arc_mach_cong of mach_cong is ‘Component Xor Port (X, Y: in bit; Z, T: out bit); End component; Component And Port (L, M: input; N, P: out bit); End component; Begin Gi: Xor port map (A, B, Sum); G2: And port map (A, B, C); GVHD: Lé Manh Hai Frang 8Luan van tot nghiép KE CPUS ng VHDL. End arc_mach_ cong; Thyc thé kién tric ¢6 tén J& “are_mach cong”. Ding nhing thanh phan cé s&n cia ngén ngit VHDL nhu céng And, Xor dé néi két ching lai véi nhau tao thanh mét cau tric cho thye thé, 3. G6 ‘Trong méi trudng thiét ké phan cing can phdi nhém cdc hgp phin hay c&c tign ich ding cho vige mé t& cée hgp phan. Nhiing eu tric VHDL dé mé t& céc tiGn ich vA mdi trudng 1A cde dinh nghia kiéu va chuong trinh con, Nhing hop phan va tién ich nhu vay ¢6 thé duge nhém Iai bing céch sit dung khéi, Nhu vi du sau, cach khai bo khdi chita cdc hgp phin va tién ich c6 thé tham kho duoc tif cdc thy thé va cdc kién tric, Ci phép: Package fén cila géi is Khai béo cdc thank phan cia gdi End (én cita géi; Trong phan khéi chifa nhitng dinh nghia chuong trinh con va Gign ich duigc ding bai chuong tinh con Package body ten cita géi is Khai béo cdc thanh phén trong than cita g6i End tén ciia géi ; Ng6n ngit VHDL cho phép sit dung céc thu vién va lién két cdc hop phan phy cila thiét ké véi cdc phan tit cla thy vién khée IIL. M61 QUAN HE GIU'A NGON NGU VHDL VA PHAN CUNG Trong phdn nay trinh bay hai vén dé 1 cde thanh phén cba ngon ng VHDL dé thc hién viéc mé ta phan ciing va su thé hién phan cing bing ng6n ngt VHDL. Phan 1 trinh bay cdc kiéu ciita VHDL, cdc d6i tung ctia VHDL, céc nh tuan oy. Phan 2c: vin dé vé mach (6 hgp va mach dng bé duge tinh bay. 1, Cac thanh phéin cia VHDL dé mé ta phan cing 11. Cae kiéu cita VADL (xem [2, 4]) Trong ng6n ng VHDL cé céc kiéu sau: Kigu ligt k¢ dude dinh nghia bing céch ligt ke danh séch céc gi tri, mi thanh phan ciia danh séch IA mOt tén danh ring hode IA mot ky uf so. GVHD: Lé Manh Hai Frang 9Luan van tot nghiép KE CPUS ng VHDL. Vidy: Type STD_LOGIC is (U'YX'0'7 11); Type STATE_TYPE is (HALT, READY, RUN, ERROR); - Kigu nguyén c6 hai loaiz + Kiéu nguyén duge dinh nghia nhu ving con cia kiéu tng quat da duge c&i sn va cde gidi han phai duge khai bao. Vidy: Type LENGTH is range 0 to 1000; ‘Type BYTE_INT is range -128 to 127; + Kidu nguyén duge dinh nghia bai ngu®i sit dung. Vidy: — Type MY_INTEGET is INTEGER range 0 to 1000; ‘Signal MY_INT: MY_IN’ - Kiéu mang ding dé dinh nghia mét tap chi sé. Vidu: Type WORD is array (10 down to 0) of bit; - Kigu record ding dé dinh nghia tp céc kiéu khée nhau. Vidu: Type CODE_TYPE is (NONE, DATA, STATMT); Type ITEM_TYPE is record cop! End record; 1.2, Cée d6i tuong cita ngén ngit VHDL (xem{1}) ‘Trong ng6n ngit VDHL cé mét so déi tugng nhu hing, bién, tin higu, + Hing: 1a gid tri dude xdc dinh trong suét thdi gian khdi tao, cdc gid tri nay khéng déi trong suét qué trinh thyc thi. Vidu: type TAB is array (BIT, BIT) of BIT; Constant AND_TAB: TAB := ((‘0",'0"),('0",’1’)); - Bin: Gid tri cba bin duige cap nhat tife thi khi duge C6 2 loai bien, bién cyc b6 va bién toan cuc. + Bién cuc bé 6 thé dude khai bao trong cdc chung trinh con hodc trong cdc qué trinh va quan trong 1A trong qué trinh téng hdp noi ma ching cé thé suy ra cdc phan tir nhd. + VHDL déng thai rang bude thu hep su sit dung cde bién toan cuc déi véi su miu ta cp hé thong. -Tin higu: GVHD: Lé Manh Hai Trang 10Luan van tot nghiép KE CPUS ng VHDL. Trén board mach in hodc c4c mach tich hgp théng tin duge lan truyén xuyén qua cée day dan, Trong ngOn ngit VHDL céc day dan nay goi la “tin hiéu”. Ce tin higu hién hitu tir khi bat ddu dén khi két thie ctia qué trinh tai tao. Khéng tao ra tin hiGu méi hodc khéng néi két vat ly voi cée tin higu duge cho phép trong thi gian tai tao, Céc tin higu khéng c6 chia dung nhw céc bién, Céc tin hiéu nhu 1a nhiing déi tugng va 06 cdc két néi duge e6 dinh véi céc tin hiéu khéc. Vidu: Signal Al, A2: BIT_VECTOR(DATA’range) ; Signal A3: BIT; 1.3. Cée todn tit s6 hoe (xem [2]) 1.3.1. Céc todn tit ludn I: or, and, nor, nand, xor, nor nhan céc toan hang kiéu: bit, boolean, vector. Vidu: Signal s, xy: bit_vector(I downto 0); Signal r, a, b: bit; Signal t, d, ¢, f, g : boolean; Begin S<=xandy: R <= (a and b) and ¢; T <= dxorexorfxor g: End; 1.3.2, Cac todn tit quan hé: Todn ti quan hé ludn luén tra vé gié tri boolean duge ma hoé *0" hose “1°, Két qua 1a true néu hai toan hang c6 cling gid tr. > SPE SE [a true fa also true "10" < ‘101'- 1.3.3. Cac todn tit cong: +, +; & ton tit cOng va tri duge dinh nghia cho céc toan hang s@ nguyén Vidu: R<=atbtct/, T<= [(a+b) +6) +1]: S< = (at b) + (+2); 1.3.4, Céc ton ub dich: sil, stl, sla, sra, rol, ror Vidu: Signal S, RI, R2, R3, R4, T1, T2, T3, T4: Bit_Vector (1 To 4); BEGIN RI <= 'SLL'(S, I); GVHD: Lé Manh Hai Frang 11Luan van tot nghiép KE CPUS ng VHDL. T2 <=S(2TO4 & 0; R2 <= ‘ROL(S, 2); » dude ding cho cac kiéu s6 nguyén. 1.3.5, Cac todn tit mot ngdi: ++, + Vidu: SIGNAL R, A:INTEGER ~4 TO 3; BEGIN R<=-A; 1.3.6. Cdc todn tit nhdn: 1, *, mod, rem Phép chia “/”, phép nhan “*”, ly phdn nguyén “mod”, ldy s6 du. “rem” duge xem 1a trong nhém ton tif nhan. Vidu: Signal MEM: NATURAL range 0 to 3; MEM <= (MEM + 1) mod 4; 1.4, Céc lénh tudn tu 1.4.1. Phép gan bién s& Phép gan bién duge thye hién bai todn tit “ xdy ra ngay lap tic khi tinh (oan. Do d6 gid tri ciia bién chi thay déi bai lénh gan tip theo néu gid tri méi khac vi gid tri cd. Vi du: WORD (3 to va thao téc 1.4.2. Phép gdn tin hiéu Phép gan tin higu wong wy nhu phép gan bién nhung higu qua cia enh chi xay ra sau Iénh déng b6. Phép gan tin higu duge thu hién bdi tosn tre Vi du: signal <= A and B; 1.4.3. Lénh diéu kién * Phat biéu if: mét phat biéu if bao gém ca cdc nhdnh elsif va else. Cu phép: IF biéuthitc THEN cau lénh; ELSIF biéu thite THEN cau lénh; ELSE céu lnk; END IF; * Phat biéu case: phat biéu case c6 thé ding dé thay thé cho phat biéu if va nhiéu phét biéu elsif. Ci phép: CASE Bigu thite IS WHEN gid tri hding=> cau lénh; GVHD: Lé Manh Hai Frang 12Luan van tt nghiép KE CPUS ng VHDL. WHEN gid trihdng => — cau lénh; WHEN OTHERS => cau én; END CASE; 1.4.4. Lénh lap * Phat biéu lip: c6 2 kiéu phat bigu lip, d6 1A vong Lip for va w * Vong lip For. Ca phép: For din gid_tri toldownto gid_tri loop End loop; * Vong lap while. Ci phép: __loop_label: WHILE __boolean_expression LOOP: Cau lénh ; END LOOP _ loop label; 2. Su thé hién phn eting bing VHDL (xem [4]) 2.1. Cée mach t6 hop 2.1.1. Cde céng ludn ly : and, nand, or, xor, nor, not ‘Vi du mé ta céng nor c6 2 céng vao nhu sau: Entity nor2 is Port (A, B: in bit; S: out bit); End nor2; Architecture comb of nor2 is Begin S<= A nor B; End comb; le. 2.1.2. Céc todn tit s6’ hoc: Gm 4 ton tit eo ban cong, trit, nhan va chia, Céc todn ti nay thudng thyc hién trén kiéu dit liéu sé nguyén (INTEGER). Trong ng6n ngit VHDL céc toan tit “+", “-*, * *, ‘7° da dutge dinh nghia truéc vi vay cé thé sit dung ma khéng can khai bao. ‘Vi dy: Signal 11, 12 SUM_1: INTEGER range ~16 to 15; Signal N1, N2, SUM_N: INTEGER range 0 to 47; SUM_1<= 11412; SUM_N <= NI+N2; GVHD: Lé Manh Hai Frang 13Lugn vin tot nghiép Ké CPUS ding VHDL 2.1.3. Céc todn tit dich va quay CAc toan tik dich va quay dude thyc hién trén céc d6i tugng duge biéu dién theo kiéu bit_vector. Todn tif dich va quay c6 thé phan biét tinh luan ly va tinh s6 hoc. Tinh luan ly Phép dich phai Iuan ly dich mét mang sang phai ké tiép xoé bit phai nht cita mang va thém vao gié tri 0 4 bit trai nhdt cia mang. Phép dich tri ludn ly thyc hign dich mang sang trai xod bit trai nha cia mang va (hém vao gid tri 0 8 bit phi nhat cia mang. Vidu: Gidtribandiu 10100110 Dich phai luan ly 01010011 Dich trai lun ly 01001100 Tinh sé hoc Phép dich phi nhat cita gid tri ban 86 hoc thyfc hign dich ming sang phai va ly bit tri u im bit rai nha cba gid tri sau khi dich Phép dich tréi sé hoc thyc hién dich mang sang tri va lay bit phai nhat ciia gid tri ban ddu lam bit phai nhit cita gid tri sau khi dich. Vidu: Gié tribanddu 10100101 Dich phai s®hoc 11010010 Dich trai sé hoc 01001011 2.1.4, B6 dén kénh Chie nang cd ban cia bé dén kénh 1a dé chon Iva mét dau ra trong nhiéu ddu vao, trong khi dé mach phan kénh thuc hién thao tée ngude lai, mét dau vao duge truyén dén mét trong nhiing dau ra, cdc gid tri dau ra Khéc gitf gid tri truée cia ching. Vidu: Entity MUX2 is Port (A, B: in bit; Select_A: in bit; Z: out bit) End MUX2; Architecture FIRST of MUX2 is Begin Z<= (A and Select_A) or (B and not Select_A); End FIRS GVHD: Lé Manh Hai Trang 14Luan van tot Ké CPU 8 Bit ding VHDL So 46 phan cing mé ta b dén kénh, LL axa. —T )5 ico Minh 2. + 2.2, Ce mach déng b6(xem[4]) Céc phan ti déng b6 tao thanh m9t ho rat 1én, n6 chtta céc mach cai va cdc thanh ghi Ia cdc phan tir nh. Céc edu trie twong duicng ciia cée mach déng b6. Tai nguyén Tai nguyen Hams hgp hd ing hd nhé” | pénghd Ham 6 hop Hinh 3. 2.2.1, Mach cai Mach cai 1a tai nguyén bé nhé don gidn nhdt, dau yao D dude truyén d€n dau ra Q khi tin hiéu diéu khién G tich cue néu khéng thi gid tri ruse d6 cia D gitt nguyén tren Q. Vi du: ENTITY LATCH IS Port (G: in BIT; D: in BIT; Q: out BIT); END LATCH; Architecture A of LATCH IS Begin P: Process (G, D) GVHD: Lé Manh Hai Frang 15KE CPUS Ludn vin tét nghi¢p ding VHDL 2.2.2. Thanh ghi Thanh ghi ciing tuong ty nhu mach cdi nhung dif liéu duge nhé tai sudn cia Iénh thay vi mie cilia n6, Sy mé th mach cai va thanh ghi gdn gidng nhau. Vidy: Entity FFIS Port (clk: in B End FF; Architecture A of FF IS BEGIN P_FF: process Begin We CLK='I' then Q<=D; Endif; End process P_FF; End A; D: in BIT; Q: out BIT); CONG NGHE EPGA (xem [4, 9) Céng nghé FPGA (FPGA 1A tif viét tit cila Field Programmable Gate Arrays) 18 céng nghé ché tao mach tich hop mat dé cao. FPGA 1a mét thiét bj cfu trie Juan ly c6 thé lap tinh duge béi nguBi sit dung ma khéng cin én mOt cng cu ché tao mach tich hgp. Ngudi thiét k& mudn tao ra FPGAs tot phai sit dung cong cy thiét ké duge trg gitip bai méy tinh goi 1a CAD (computer -Aided - Design). Dau tién thi€t kE mach ludn Iy ban dau ddi héi mot so dé biéu dién mach hay mét mé @ VHDL hode dic tA cée biéu thife luan IY (Boolean). Tir cc ngo vao ban diu mé td mach dude chuyén thinh dang chun nhu céc biéu thie boolean sau 46 dude xit ly bang céng cu (i uu lun ly, ching rat gon cdc bidu thie, sau 46 cée biéu thife Boolean da (6i wu duige truyén tdi cée khéi luan ly cia FPGA thong qua chvong tinh anh xa cOng nghé (technology mapping). B6 anh xa thyc hién t6i thi€u sé khéi duge ding, tiép theo chuong trinh s{p xép (Placement) thuc hién dit mdi khéi vao trong day FPGAs. Buéc cuéi cing trong hé théng CAD dude thyc hién bang phin mém diéu khién luéng (routing) ching n dinh cdc doan FPGA va chon céc chuyén mach c6 thé lap trinh phd hgp véi céc két néi trong khéi luan ly. Sau khi thye hi¢n thanh cOng cée bude sfp xp va tuy€n ngo ra cia he théng CAD dude nap vao don vi lap trinh tao ra chip FPGA. GVHD: Lé Manh Hai Frang 16Ludn van t6t nghi¢p ‘Thiet KE CPU 8 M6 hinh hé héng CAD cia FPGA inh 4. 1, Cac loai FPGA Céc loai FPGA cia nhiéu céng ty khéc nhau c6 céc dic tinh riéng chiing c6 thé duige chia Lam 4 logi chinh: © Cau tric mang déi xting (symmetrical array) * Cu tric hang (row-based ) * Cau tne PLD phan c&ip (PLD [a viet tdt cita Programmable Logic Divice) * Cau tric da céng (sea-of-gates) ; cout we SA) Coo J uses —57][[O[[O GoOoeoooo OQWONO (poe sosic Teepe Block a Két adi = ope Bik A= None ww P]=|=]= oe piece Hinh 5. GVHD: Lé Manh Frang \7Luan van t6t nghiép KE CPUS ng VHDL. LI. Cée cong nghé lap trinh chip C6 nhidu céch hi¢n thye cde phan tit lap tink, cée céng nghé lap tinh dang sit dung hién nay la: RAM tinh, edu chi nghjch (anti-fuse), EPROM transistor va EEPROM transistor. Mac da ‘Ong nghé lap trinh khéc nhau nhung ching c6 chung tinh chat 18 c6 thé cu hinh & m9t trong hai trang thai 14: ON hodc OFF. Céc phan ti 14p tinh ding dé hién thye cdc két ni lap trinh gitta céc kh6i ludn ly ciia FPGA, mot FPGA théng thuding c6 thé c6 hdn 100.000 phan tit lap trinh. Do 46 cdc phan tif lap trinh phai cé cdc (inh chat sau: + Chiém cing {t dign tich eda chip cang t, + Cé khdng tré thép khi d trang thai ON va khdng trd cao khi 6 trang thai OFF, + C6 dién dung kg sinh thap khi két n6i cdc doan day. + C6 thé ché tao mét cach tin cy sO lugng 1én phan ti lap trinh trén mét chip. 1.1.1, Cong nghé lap trinh ding RAM tinh Céng nghé lap tinh SRAM duge sit dung trong céc FPGAs ciia nhiéu céng ty nhu Algotronix concurrent Logic, Plessey semiconductors, Xilinx. Trong céc FPGAs nay, cdc két néi lap trinh duge lam bang transistor truyén (pass-transistor) c4c cng cho phép truyén (pass-gates) hay cdc bO dén kénh (multiplexer), t&t cd diéu dugc diéu khién bing 6 nhé (cell) SRAM. es saa aa za) 1 be =H A wae gate tte T | gah fan Tepe Hinh 6 Céng nghé 1p trinh ram tinh, Trong tru&ng hgp pass-transistor va pass-gates 4 hinh 6 SRAM cell diéu khién céng truyén ON hodc OFF. Khi off gidta hai day ndi véi pass-gates c6 mOt trd khang rt cao. Khi ON né sé tao ra mt tré khang thip két néi gitta hai day néi, Déi v6i bo dén kénh, SRAM cell diéu khién ng nhap ndo cia cdc bé dén kénh sé dude két néi vdi ngé ra cia n6. GVHD: Lé Manh Hai Frang 18Luan van tot nghiép Ké CPU 8 Bit ding VHDL 1.1.2.Cong nghé lap trinh dang cdu chi nghich (anti-fuse) Cong nghé 14p trinh anti-fuse duge sit dung trong céc FPGA cia Actel Corp, QuickLogic va CrossPoint Solution. Tuy anti-fuse duge sit dung trong céc loai FPGA cé cau tao khéc nhau, nhung chife nang 18 nhu nhau. Mat anti-fuse binh thudng sé 4 trang thai tré khang cao, nhung cé thé bi néng chay thanh trang théi trd khdng thap khi dude lap trinh 4 dign thé cao. 4. Céiu tao anti-fuse cia Actel Anti-fuse cia Actel duge goi 14 PLICE. N6 c6 cau tréc hinh chit nhat gém 3 lép: lép duéi cing chia silic mang nhiéu dién tich duong (n+diffusion), lép gitta IA Idp dién méi (Oxy-Nito-Oxy cach dign) va lép trén ching la Poly-Silic, net 2 wite neaitusion RN ant-fuse silicon substrate gt edt ngang cfu wie Hinh 7 céng nghé 14p trinh edu chi nghich PLICE. Anti-fuse PLICE duge lap trinh bing céch dat mdt dign thé cao thich hop (18v) gitfa hai du cita anti-fuse va dong diéu khién khodng SmA qua thiét bj. Dong va 4p ny tao ra mot nhiét igng dil néng ben trong lép dién méi lam né néng chay va tao ra mot lién két gitta poly-silic vA n+diffusion. Hai Iép duéi cing va trén cing cia anti-fuse duge ni véi cée day kim loai dé khi lap trinh anti-fuse sé tao ra mOt ket ndi c6 tr khéng thap (300 dén 500 ohm) giita hai day kim loai. 5. Cétu tao anti-fuse ciia QuickLogic Anti-fuse cila QuickLogic goi IA ViaLink. N6 tuong ty nhu PLICE, cing €6 3 16p kim loai, Tuy nhién Vialink sit dung kim loai mtfe 1 cho 1ép duéi cing, mét hgp kim vé dinh hinh cho lép gitfa va kim loai mifc hai cho lép trén cing. Vialink duge lap trinh bang cach dat dién thé 10v gitta céc dau cia n6. Khi dong dude efp dit trang thai cia silic vo dinh hinh sé thay déi va tgo ra mt lién két din dign gitta hai lép kim loai. GVHD: Lé Manh Hai Frang 19Luan van tét nghiéy KE CPUS Ville Yo inh hinh SVN Hinh 8 Céng nghé lap trinh céiu chi nghich ViaLink. 1.1.3. Cong nghé lap trinh EPROM va EEPROM Céng nghé 1p trinh EPROM dutge sit dung trong céc FPGA ciia Altera Corp va Plus Logic. Céng nghé nay gidng nhw sit dung trong bd nhé EPROM. Khéng giéng MOS Transistor, mét EPROM Transistor gém hai céng, mét cdng treo (floating-gate) va mét céng chon (select-gate). Céng treo duige dat gitfa cng chon va kénh cia transistor. asv ign wt Jen nguén bit tine select gate +————_| | [erxom transistor 7 floating gate word line GND Hinh 9 Céng nghé 14p trinh ROM. O trang thai binh thuding khéng c6 dign tich gitta céng treo va transistor c6 thé chuyén sang trang thai ON mdt cach binh thudng bing céng chon. Khi transistor duge lap trinh bing mgt dong dign Ién chay gitfa nguén va kénh thi mét dién tich duge git lai & cng treo. Dién tich nay lam cho transistor chuyén sang trang thi OFF. Bing céch nay, EPROM transistor c6 thé duge tai lap trinh bling céch hiy bd lép dign tich duge gitt lai 4 céng treo, Trong hinh 9 EPROM transistor duge sit dung trong FPGA theo céch khée véi SRAM va anti-fuse, Thay vi ding cho lap trinh két néi hai day EPROM transistor dude sit dung dé kéo xuéng cdc ngé nhap ciia logic block. Nhu hinh vé trén mét dudng day goi 1A word line dude néi vai céng chon cia EPROM transistor khi transistor chua duge lip tinh trang théi ON, word line cé thé lam cho bit line khdng néi vai mot ng6 nhap cia logic block va bi kéo vé mic logic 0. Nhiéu EPROM transistor «ing vi nhiéu GVHD: Lé Manh Hai Frang 20Luan van tot nghi¢p KE CPUS ding VHDL word line khéc nhau duge néi vai cing mét bit line , khi mot dién wa kéo Jen ngudn néi vdi bit line m6 hinh nay khdng nhiing cho EPROM transistor hiGn thye c4c kt néi ma cdn hign thyc cde chite ning lun ly AND néi day. Nhuge diém cia phutong phép nay 1A céc dién ta tiéu tén nang lugng co dinh. Mét wu diém cia EPROM transistor 14 chting 06 thé t4i lap trinh ma khéng cén bé nhé bén ngoai. Khong giéng nhy SRAM, EPROM transistor khéng thé tai lap trinh ngay trén b6 mach Phuong phép ding EEPROM tuong tw nh EPROM nhuge diém cia né Sn gap ddi dién tich chip so véi EPROM transistor va can nhiéu nguén dién thé ma cdc loai khéc khéng cin at 1.2. Céc loai FPGA trén thi trudng Hign nay trén thi trading 06 mét sé ho FPGA cla céc hang nhu Xilinx, Actel, Altera .v.v. . trong phan nay trinh kién tric cia hang Altera, Kién tric co ban cia Altera FPGA c6 cau tric nhém phan cap ciia cée PLD trong eau trie nay sit dung mang hai chiéu va m@t cfu tric routing lap trinh duge. Kign tric eo ban cla Altera FPGA dia trén céng nghé lap trinh EPROM né gdm mét mang Ién céc khdi lap trinh dude goi 1A nhitng khéi mang luan ly (logic array Blocks) dugc két néi véi nhau bai céc nguén tai nguyén routing goi la mang lap trinh néi lién nhau (Programmable Interconnect Array). C6 hai thé hé Altera FPGA 1a FPMS000 va FPM7000. Kién tréc téng quat cia Altera >| & | PIA rrogrammabte 2 | es © | am Losic array L sok Hinh 10 Kién tric téng quat ctia Altera FPGAs. Altera FPGA c6 edu trie nhém phan cap gém 2 mite mot khéi ludn ly 14 Macrocell mic nay goi lA LAB va mt block goi 1a bd mé rong dutng day GVHD: Lé Manh Hai Frang 21Luan van tot nghiép K€ CPUS ing VHDL lich (expander product terms), s6 Ing macrocell trong mi LAB thay déi tuy theo loai Altera FPGA, méi macrocell gim 3 céng AND néi vao céng OR néi ti€p dén céng XOR va mét filp-flop, céng XOR tzo ra output cia macrocell. Céc ngé nhap cia macrocell xem nhu céc céng AND mét ngé nhap vi ching duge tao ra nhwt cée céng AND néi day cba cdc tin higu, Dung day tich c6 thé 12 mot tin higu trong PIA hay 1a tir bd mé réng dung day tich cia LAB hodc ng6 xudt ciia bat ky Macrocell no, céc tin higu & dang thyc hojc bi nghia 1a phép dio c6 thé lap tinh duge (programmable inversion) véi m6 hinh nay th chife ning cia LAB gidng chic ning cla PLD nhung duéng day tfch ft hon trén mdi thanh ghi. Altera cho ring diéu nay sé 1am cho LAB higu qua hon bai vi hdu hét céc hm logic khong cin c6 s@ dung day tich Ién nhu trong PLD va LAB hé tré mé rong chife ning bing b6 mé rong duding day tich Cau tric ciia Altera LAB fiesta FF “) Cc Expander Hinh 11 Altera LAB. 2. Mét sé ting dung cia FPGA FPGA c6 thé duge sit dung trong hau hét céc ting dung ma hién tai dang ding trong céc chip MPGA, PLD va SSI (Small Scale Integrated). Cac ‘ng dung ciia FPGA cé thé duge liét ké ra nhu sau: Mach 18 hop la ting dung dae bigt (Application-Specific Integrated Circuit): FPGA 14 mét céng cu c6 tinh téng quét, va hoan toan cé thé hién thye duge mach logic sé, N6 dc biét thfch hgp cho vie hién thye ASIC, M6t vai ting dung da duge ghi nhan nhu:1 megabit FIFO controller, kénh giao tip IBM PS/2, DRAM controller, graphic engine, mach nhan biét ky tw qua hinh anh, Ung dung trong céc may tinh dua trén nén cdc FPGA: mot loai may inh méi hoan toan duge ra di nh vo cc FPGA cé thé ti lap trink duge ngay trén mach cia n6, Nhitng méy tinh nay bao gdm céc mach duige thiét ké tit céc FPGA. ¥ tung nay xudt phat tiv viée ding mot chung tinh phdn mém dé “dich” vao phan cing thay vi vao phdn mém theo céch théng GVHD: Lé Manh Hai Frang 22Luan van tot nghiép KE CPUS ng VHDL. thuding. Phan c(ing nay sau d6 duge hién thyc bing céch lap trinh ede board mach FPGA. Phuong phép mi nay c6 2 thuan Igi co ban Ia: Khong yéu cdu qué tinh ly lenh nhu 1a céc bd vi xit ly ruyén thong bai vi chfnh ban than phan ciing [a sy thé hién cita céc 1énh dé, Uu thé nay £6 thé gidp cho We d6 cia mach ting Ién dén hang trim lan, Loai thiét bi méi nay con c6 thé hé trg ede qué tinh xif lf song song & mife d6 rat cao, din dén te ad xit ly tang vot. Ung dung vao vigc tdi cau hinh phan cttng (On-Site Re- Configuration of Hardware): Cong ngh¢ FPGA cdn dude yéu thich 4 chd né cho phép thay déi dutge cu tric cde may dA sin xudt hoan chinh hay da duge sit dung. Ngay ca déi véi cdc may 4 xa cing 6 thé dudc thay déi, bé sung cho thich Ging hoc ngay c& chinh sita lai su sai s6t cla céng vige thiét ké mach d6 Loai FPGA thich hgp nhat cho viéc tai clu hinh nay 1a loai chifa nhiing cong tdc c6 thé tai lap trinh dude. 3. Thiét bi Max, Flex Céng ty Altera 1A m6t nha ché tgo hang dau vé PLD, Altera tao ra PLD trong pham vi tiv cdc thiét bi cé thé dude ding dé thay thé twong duong 300 cdng TTL dén cac thiét bi cé thé thay thé 250000 céng. M6t board mach in Idn vé cée chip c6 thé duge thay thé bling mot PLD don, digu nay sé lam gidm duge kich thuée cla hé théng sO va cing lam gidm duge gid thanh ché tao va chay thit. PLDs ciing phé bién vi chiing c6 thé x6a dude. Cac PLD cé thé x6a duc cho phép nha thiét ké lap trinh mat PLD, va chay thi chting trén mét hé théng thuc, va lam thay déi khi cin thiét. trinh lai cho mét con chip thi nhanh hon nhiéu so vdi viée viét lai mét bread-board hodc lam lai mét board véi nhiéu day dan chin chit. Cudi cing mét thiét k€ duge thyc thi trong m6t PLD e6 thé dé dang duge van chuyén. Thiét ké nay cé thé dude thyc thi trong nhiéu PLD khéc nhau. M6t PLD tiéu bi€u chifa mét day cdc tai nguyén logic nhu 1a cdc céng, céc Mlipflop, céc thanh ghi and/or, véi cdc két néi bén trong gitta cde (i nguyén logic c6 thé lap trinh duge. Cac két néi bén trong nay 6 thé duge bé sung véi cdc dudng fusible (néu chdy dugc), ma trong trudng hop nay thi€t bi chi c6 thé dug M4p tinh mot ln, Ché d6 két néi nay thi phé bién trong cdc PLD ban dau nhu 1a 16L8 va 22L10 PAL's (ching phé bién trong nhiéu nam). Trong céc PLD, gan day cdc két néi bén trong cé thé duge ba sung bing cdc mach chuyén déi CMOS dude diéu khién bing RAM tinh, trong truing hyp nay thi¢t bi c6 thé duge lap tinh lai bing din, ma khong tach ra khéi mach, céc PLD khéc bao gém céc PLD ma ban sé ding trong GVHD: Lé Manh Hai Frang 23Luan van tot nghiép KE CPUS ng VHDL. 6p (class) nay sé c6 cdc két n6i bén trong ma c6 thé duge lap tinh bing dign va x6a bing dén tit ngoai UV (UV Ia viet tdt cia ultraviolet), C6 nhiéu thiét bi ap trinh duge ciia cdc hang khdc nhau é day chi gidi (higu mt vai thiét bi lap tinh théng dung ciia hang Altera 3.1, MAX Altera MAX gém 6 MAX9000, MAX7000, MAX5000 - Ho MAX9000 Ia thé hé thif 3 cita kiGn tric nhiéu ma tran mang (Multiple Array Matrix) bao gém Max9000 va MAX9000A 12 nhiing EEPROM co ban gém nhiing thiét bi cé kha nang lap trinh logic va xod (EPLD) : EPM9320, EPM9320A, EPM9400, EPM9480, EPM9560A. MAX9000 EPLDs phi hgp cho nhiing ké hoach ddi héi kha ning hién (hye gid tr] xudt nhap & mie cao, e6 mat d> tir 320 dén 560 Macrocells khoang 6000 dén 12000 céng, ho MAX9000 c6 thi gian tré tir 10ns dén 20ns va tiéu bigu 18 145MHz, MAX9000 cho phép ngudi thiét ké két hop nhitng thiét bi cé dung lugng nhé vao trong mét thiét bi MAX900, diéu ndy ‘Ukiém khong gian quf gid trén board mach lam gidm gid thanh sn m théi gian cham tré cho viéc hoan thanh san phém. -Ho MAX7000 Ia thé hé thit 2 cila kién tric ma tran mang gém c6 MAX7000, MAX7000A, MAX7000B, MAX7000E, MAX7000S va MAXTO000AE 1a nhiing EEPROM duge ché tao theo céng nghé CMOS, MAX7000 c6 mat 46 tir 32 d€n 512 macrocells, c6 thdi gian delay 3,5ns. ‘Thi€t bi MAX7000 thuding hoat dng véi dién thé Sv, 3.3v, 2.5v 3.2, FLEX Altera FLEX g6m c6 FLEX10K, FLEX8000 va FLEX6000 -FLEX10K c6 kién tric eo ban Flexible Logie Element Matrix. Ho FLEX10K gém cé FLEXIOK, FLEXIOKA, FLEXIOKB, FLEXIOKE 1a mhiing SRAM gém c6 EPFIOK10, EPFI0K20, EPF10K30, EPF10K40, EPFIOK50, EPF10K70, EPFIOK100. Altera FLEXIOK duge nhting yao trong ho lap trinh logic né md ra tinh linh déng, tinh mém déo ctia 16i lap (inh Juan Iy theo kiéu lap trinh truyén thong. N6 Ia hai cu tric logic day di duy nh&t nhting vio mang va mang logic. N6é c6 khodng 10000 dén 250000 céng tiéu biéu, FLEX10K md ra 3 qué trinh, mdi mot thé hé tigp theo cung cp suf thyc thi cao hon, ha gid thanh, 1Am gidm su thiét hai. GVHD: Lé Manh Hai Frang 24Luan van tot nghiép KE CPUS ng VHDL. Phin 2 THIET Ké CPU Céc khdi niém vé ngén ng VHDL, ct phap va ngit nghia cia n6 4% duge tinh bay & phdn 1. Phin nay sit dung cu inie ctia phin 1 dé mo td CPU 8 bit. Phan I néu nhiém vu cia CPU, phan II mé ta té chitc bé nhé ciia CPU, phan III tinh bay tap 1énh CPU, phan IV trinh bay ché dé dia chi cia CPU, phan V mé ta hanh vi cia CPU, phan VI trinh bay cdc thanh phan cia CPU. 1. NHIEM VU Thiét ké mot CPU 8 bit, CPU nay cé mot thanh ghi tich luy, mét bus dit liu 8 bit va m@t bus dia chi 12 bit. N6 thuc hién duige mot sO phép tinh juan ly va sé hoc ed ban. CPU c6 mét sé lénh nhay va ré nhdnh véi cac ch& 9 dia chi tye tiép va gidn tiép. CPU ciing cé mét sé 1énh goi chung trinh con don gidn, c6 mét tin hi¢u déng hé CLK, mot tuy€n ngé ra & bit va hai tuyén ng vao 8 bit c6 dia chi 1a FFEb, FFFh. 11.76 CHUC BO NHG CUA CPU CPU c6 kha nang dinh vi dia chi 4096 byte nhé théng qua bus dia chi 12 bit. B6 nhé nay phan chia thanh 16 trang méi trang 1a 256 byte, trang dau tien nim trong CPU, 4 bit c6 trong s6 cao nhft cia tuy€n dja chi thiét lap dia chi trang (page), 8 bil c6 trong s6 thap nhat cia n6 chi d6 ddi (offset). BO nhé duge phan thanh 16 trang (pageO ->page15), nhung bé nhé cla CPU van duge xif ly nhubé nhé 4K lién tiép nhau, Dé don gidn cho viéc thiét ke ta lay dia chi xuat nhap cia CPU chinh 1a dia chi ciia 6 nhé FFEh ya FFFh Ja 2 céng nhap va xudt cia CPU. Hinh 12 mé td trang va d6 di ciia CPU 0.00 oF 100-1. 200. 247 Ee0- EH PageiT 00. PF| Pagel Hinh 12 Trang va d6 ddi cia dia chi CPU. GVHD: Lé Manh Hai Feang 25Luan van tt nghiép ‘Thiet Ké CPU 8 Bit ding VHDL 1. TAP LENH CUA CPU CPU cf téng cOng 23 lénh, CPU nay c6 mét thanh ghi tich luy dé thyc hign tt cd cdc Iénh, Ngoai ra, CPU cin c6 cdc cd overflow, carry, negative va zero (v, c,n va z). Cac cd nay cé thé dude thay déi béi cdc lénh lién quan dén cd hoc bai céc lénh lm thay di ndi dung cia thanh ghi tich ly. Lénh Ida nap yao thanh ghi tich lay véindi dung ciba bd nhé cé dia chi trong hang lénh, cdn lénh and, ade va sbe truy cp b6 nhé dé lay toan hang a thyc hién cée tinh todn (and, cng va trit) va lu két qua trong thanh ghi (ich ly. Cac 3 z va m duge thiét lap hodc xod dua én két qua cia Ida, and, ade va sbe. Cac \énh ade va sbe cing Anh bung d€n cd v va cd ¢ phu thude vao két qua tong ting. - Bang t6m tit cdc lénh cba CPU Lénh ggi | Mo td chife ning tom tat | Bit | Ch& 49 | Dinh vi | Sitdyng | Thiét nhé dia | dia chi co | epee chi_| | LDA loc _| Nap vio AC titloc 12 | Day di AND loc | And AC véitloc) 12 | Bay ad ADC loc. | Add AC vdi (loc) 12 | day ai SBC loc | Sub AC vai (loc) 12 | Dayal | cs IMP adr_ | Nhiy t6i ade 2 | payai | C6 STA loc | Cat AC vao loc 12 | paydi | co JSR tos | Goichudng tinh contailec | 8 | Trang | Khong IWadr | Re nhinh ti adr nu V 8 | Trang | Khong 3Cadr_— | Re nhdnh ti adr néu C 8 | Trang | Khdng JZadr | RE nhénh ti adr névZ 8 | Trang | Khong JNadr | RE nhdnh ti adr néu 8 | Trang | Khong Nop | Khong im gi - | Khong | Khong CLA | X04 AC - | Khong | Khong CMA Lay bd 1 AC - | Khong | Khéng cmc | Lay ba = | Khéng | Khong ASL | Dich trai s® hoc AC =| Khong | Khong ASR | Dich phi shoc AC - | Khong | Khong Bang 1. Lénh sta cét ndi dung cla thanh ghi tich ly vao vi ti nhé duge ghi trong hang Iénh, Vige thyc hién enh jmp 1a 1am cho lénh ké tiép dude thye hign tiy dia chi duge chi ra trong hang Iénh. Céc lénh Ida, and, adc, sbe, jmp va sta sit dung dia chi 12 bit va c6 thé duge ding véi ché 46 dia chi gin tie. Luge dé dia chi cita lénh jer va cdc lénh ré nhdnh 1a dia chi trang. Cée Iénh nay chi ra rang ma chting thye hién Iénh. Lénh jsr véi dia chi 8 bit chi GVHD: Lé Manh Hai Trang 26Luan van tot nghiép KE CPUS ng VHDL. t6i chung trinh con (tos), nhiing lénh ké tiép thuc hién ty vj tri dO di tos + J ofa trang hién hanh, G cuéi chung trinh con dé quay lai chuong tinh chinh th ding lénh nhay gin tiép d&n dia chi tos. BGn lénh ré nhdnh jy, je, Jz va jn lam cho lénh ké ti€p duge thuc hién tai dia chi ciia trang hién hanh v6i d8 dai do lénh cung c&p n€u cde c¥ twang ting vy, ¢, z hode m duge thiet ap. Céc lénh nop, cla, ema, ast va asr 1a 1énh khéng cin dia chi va thye hign cdc thao tc trén cdc thanh ghi bén trong CPU. Lénh nop khéng thufc hign thao (4c chi ting bé dém chifong trinh 1én 1, ela dé xod thanh ghi ace vé 0, cma lay bi. ndi dung ciia ace, cme bi ndi dung cé ¢, als va asl ding dé dich chuyén s6 hoc trai hay phdi thanh ghi ace. Khi dich tr4i, bit c6 trong sé cao nhat ctia ace dude chuyén vao cd carry, cdc bit c6 trong sé thap hon dich sang tréi 1 bit, Lénh asr gitt nguyén bit dau cia thanh ghi ace va dich chuyén céc bit c6 trong sé thp hon sang bén phai. Ca 2 lénh dich chuyén déu Anh hudng dén céc cd zero va negative. Iv. CHE BO BIA CHI CUA LENH ‘Trong tp lénh c6 3 nhém Jénh, nhém thif nhat c6 dia chi day di cin 2 byte va c6 thé truy cp (di dia chi bat ky cia b6 nhé cia CPU va 6 thé ding dia chi truc tiép hay gidn tiép, nhém thi 2 1a nhém Iénh ding dinh vi trang yéu cdu 2 byte cé thé truy cp ving nhé trang hién hanh ma khéng thé sit dung dia chi gian tiép, nhém thi 3 1a nhém lénh khéng dia chi vi khdng ding bé nhé cho todn hang. * Céc lénh dia chi day di: MA téc vu chi thao téc cia lénh dia chi diy di dude tao ra bai 3 bit c6 trong sO cao nhat ciia byte Iénh du tién, Bil 4 chi ché 4 dia chi rye tiép hodc gidn ti€p (0: truc ti€p, 1: gién ti€p) va 4 bit c6 trong sé thap nhat cha dia chi trang todn hang cia lénh. Byte thif 2 ctia lénh dia chi diy di chi ra dia chi dé d@i va cing vdi dia chi trang dé tao ra dia chi 12 bit cho todn hang. MG téc vu ciia lénh Lenh gginhd | Cac bit ma tae vu Bit 765 |___ 3210 LDA loc ‘000 Dia chi trang AND loc oo Bia chi trang, ADC loc o10 Dis chi trang SBC loc ou Dia chi tang. IMP adr 100 ja chi trang STA loc 101 Dja chi tran GVHD: Lé Manh Hai Frang 27Luan van tt nghiép Thiét Ké CPU 8 Bit dimg VHDL JSR tos Tio : 7 JW ade M1 1 1000 JC adr a1 1 0100 JZadr a1 1 oo10 IN adr a1 1 ool NOP ul ° 0000 CLA 1 o 001 cMA un ° 010 emc a o 100 ASL 1 ° 1000 ASR ul ° 1001 Bang 2. * C&c lgnh dia chi trang Céc lénh nay sit dung dja chi trang nhé ma lénh dang 6 46, Mi téc vu ca jsr 12 110 va 5 bit cdn lai cia byte Iénh dau tién bj bé qua. Vang ma téc vu cila lénh ré nhénh chifa 111, cdn bit 4 ludn 1a 1 va cdc bit c6 trong sé thap hon ciia né chi ra diéu kién dé ré nhanh. Byte thi 2 ciia jsr vA cdc lénh ré nhanh xéc dinh dia chi nhay téi 6 trang hién hanh Dinh vi dia chi trong lénh dia chi trang Dia chi dy 4, Ps lsh jor hay é sinh Ps: test [pe aar Hinh 13, Vi du vé thc hién lénh jsr Pessat JSR sat isk S12 3 52 8 5:13] Leah saw ISR S13] LénbsauJsR a3 (99000000 | sa B 5:34] Ma Jenh chigong tinh coq PC->5°M| Max Ienh chusng th co S56] IMP gidn ip IMP gida tiép Tre ki tne ign Trude ki te hig ea ISR enh JSR Hinh 14, GVHD: Lé Manh Hai Frang 28Luan van tt nghiép KE CPUS ng VHDL. Lénh jsr bat dau thye hién tai vi tf 5:11, & vi tri 5:12 chi ra chuong trinh con bat dau thyc hién tai vi tri 33 cila trang 5:33, day IA vi tri dau tién ciia chifong trinh con ding dé Ivu tif dia chi tré vé khi lap trinh thi khéng duge ding né cho chong trink, khi 4p tinh thi str dung mot lénh nhay gidn Gp tai cudi chiang trinh con dé tra vé chufdng trinh chinh, Nhu trong hinh vé trén thi lénh nhay gidn tiép dit tai vi tri 5:55 va 5:56, sau khi thyc hién enh jor d4t 4 vi tri ddu tien cia chuong trinh con (vi tf $:33), Iénh nhdy gidn ti€p & vi trf 5:55 lam cho chuong trinh chay tré vé vi tri 5:33 sau khi thy hién hoan tat chung trinh con, « Lénh khong dja chi Lénh kh6ng dja chi 1A nhém lénh cuéi cing ciia (ap lénh. Cac lénh nay chiém | byte, trong dé 4 bit c6 trong s6 cao nhdt cla ching 1A 1110, 4 bit con lai dé phan biét céc lénh nop, cla, ema, cme, asl va asr. «+ Dia chi gidn tiép trong CPU Néu bit thi’ 4 ca byte dau tién cia Iénh dia chi ddy da 1a 41” thi dja chi nay IA dia chi gin ti€p cia todn hang. Dia chi gidn tiép sit dung dia chi 12 bit gém c6 12 trang va dO d8i, Dé dé cng véi gid tri trang ca dia chi gidn gp tao dia chi day dit cho tofin hang thye ciia Iénh, V. HANH VI CPU (xem [2, 4]) ‘Trong phan nay mé ta hanh vi cia CPU 8 bit phan mé ta giao dién cia CPU 4 mic phan cing bing viéc siv dung cac bit cho nhiing tin hiéu diéu khién bén ngoai, b6 nhé va truyén dit lies 1. Dinh thdi va déng hd Giao dién mé ta hanh vi gém cé mét tin hiéu déng hd dude ding dé déng bd. Dua trén tin hiéu déng hé, cdc gin dé dinh thdi du¢e trinh bay nh sau 1.1. Gidin dé dinh thoi dap ting ngdt quang ‘Adbas pose cy Hin 15, GVHD: Lé Manh Hai Frang 29Luan van tot nghiép Ké CPU 8 Bit ding VHDL Trong gidn dé dinh thai xit ly tin hiéu ng&t quang véi 2 nhip dng hé SI va S2 thi b6 dém chuong tinh cba CPU duge gén gid tri 066. Chuang trinh bat dau thye hién tir dia chi 066 tré di 1.2. Gin dé chu kj thuc hign lgnh 1 byte: nop, cla, cma, cme, asl, asr. evens S23 clk Adbus read-mem wn Hinh 16. Tai sutn Ién etia xung clock $1, tuyén dia chi xudt hign ndi dung cia PC, tin hiéu doc b6 nhé cing tich eyc. Tai sudin lén cia xung $2, khi dir ligu da sin sing trén tuy€n dif ligu, CPU doe dif liéu dua vao thanh ghi lénh (byte 1) dé thyc hién lénh. 1.3. Gidin dé dinh thoi chu ky thuc hign céc lenh ré nhdnh va lenh jmp eon $e $2 Deen $5-9e $45 atk PLL : ‘s + asbus a databus —< byte'l —< byie 2 Minh 17 Tai sun lén xung SI, tuyén dia chi ly ndi dung ciia PC, tin hiéu read_mem tich cue. Tai sun $2, khi di ligu d& sn sng trén tuyén dif liu, thi dif ligu dude doc vao bytel va tin hiéu read_mem tré vé 0. Sau khi phan ich Iénh, tai ddu chu ky S3 tuyén dia chi phét ndi dung cia PC+1 va tin higu read_mem lai tich cye (én ‘1’). Tai ddu chu ky S4 dif ligu duge doc vao byte2, sau d6 CPU diéu khién tin higu read_mem trd vé 0 va thuc hign Iénh trong chu ky S4. GVHD: Lé Manh Hai Trang 30Luan van tot nghiép Thiét Ké CPU 8 Bit dimg VHDL 1.4. Gién dé dinh thii chu ky thuc hign Ignh Ida, ade, she (ché 46 true ti€p) va lénh jmp (ché 46 gidn tiép). S1--mens $2 pees SI SA ratmm —! LE OLE LL Hinh 18, ‘Ti trang thai S1 dén S4 thyc hién gidng nhu muc 3, dén dau chu ky S5, CPU doc néi dung trén tuyén dif ligu c6 dia chi IA bytel (3-0) & byte2 dé ldy data va thyc hién lénh. 1.5. Gidn dé dinh thai chu ky thu hign lénh jsr sees Slopes S2-pens $3 SH Hens SF SO asus ae seiteeme pL Hinh 19. Gidin dé nay tiy trang thai $1 dén $4 gidng nhu myc 3, d€én chu ky 5 tin higu write_mem tich eye cho phép CPU thy hién thao t4c ghi ndi dung PC (7-0) vao 6 nhé dia chi PC (3-0) & byte2 1.6, Gién dé dinh thi chu ky thc hign lenh sta (ché d6 truc tiép) ee SI-pew S2-pen SP Se lk SUL LU LI LS LT 1 ee re re are com oe i Hinh 20. read-mem GVHD: Lé Manh Hai Frang 3)Luan van tot nghiép Thiét Ké CPU 8 Bit dimg VHDL Gian dé nay tir trang théi $1 d€n S4 gidng nhu mue 3, tai chu ky SS CPU thie hién thao tée ghi ndi dung ac vao 6 nhé dia chi bytel (3-0) & byte2 7. Gién dé dinh thai chu ky thuc hign lgnh Ida, and, ade, she (ché 46 gidn ti€p) fo Sen Sogn $n Shp $n $6 pe Sra E> ae j j rq rf sus ‘el FHRVDY rel HORIy Cnet a> Tir chu ky S1 dén chu ky $4 thyc hién gidng muc 3, du chu ky 5 doc ngi dung 6 nhé 8 dia chi bytel (3-0) & byte2 vao byte 2 Lam dia chi. Dau chu ky S7, phat dia chi trong bytel (3-0) & byte2 ra tuy€n dabus dé doc dit ligu cho CPU xit ly. read-mem databus 1.8. Gién dé dinh théi chu ky thc hign lénh sta (ché dé gidn tiép) eu S1-veu $2 pe $3- eo Sh og $5-9e $6-Deu ST DE $8> clk | l l l l l A= sain a Hinh 22. Tur chu ky S1 dén $6 thyc hién ging véi gidn dé & muc 7, ddu chu ky S7 phat dia chi trong byte1 (3-0) & byte2 dé ghi noi dung ace vao bé nhé. GVHD: Lé Manh Hai Frang 32KE CPUS Luan van tét ngl ing VHDL Tiy 8 gidn 6 trang thai trén vé duge so dé trang thai mé ta hanh victa CPU nh sau: Reset=0 emp (eve ip) enh Idaand,ade, sbe,stactnue tig), mp(zidin up),js. Hinh 23. 2. Khéi phuc vu chuong trinh (xem/ 2, 4]) Khéi utility nay khai béo kiéu con byte d6 dai 8 bit kiéu STD_LOGIC_VECTOR, kiéu con ten 46 dai 10 bit kiéu STD_LOGIC_VECTOR. Ngoai ra khai béo cdc hing s6 c6 gid tri IA cée vector bit ciia cde Iénh. Tén ciia cde lénh dude gin cho cée ma tae vu cita Iénh d6. Kh6i utilities tinh bay hai ham add_cv va sub_ev. Hai ham nay thyc hign cOng va triy hai todn hang kiéu std logic vector c6 do dai 8 bit. Két qua tra vé 1a ki€u bit vector c6 chiéu dai 8 + 2. Trong 46, bit 6 vi tri 841 chi thi cd hd, bit cO vi ti 842 chi thi cd tan. Hai gid wi ADDR_WIDTH va DATA WIDTH 18 chiéu dai bit ciia hai tuyén dja chi va di ligu, PACKAGE UTILITY IS CONSTANT ADDR WIDTH: INTEGER := CONSTANT DATA_ WIDTH: INTEGER :=8; SUBTYPE byte IS std_logic_vector (7 DOWNTO 0); GVHD: Lé Manh Hai Frang 33Luan van tot nghiép KE CPUS ng VHDL. SUBTYPE ten IS std_logic_vector () DOWNTO 0); SUBTYPE nibble IS std_logic_vector (3 DOWNTO 0); FUNCTION add_cv (a, b: byte; cin: std_logic) RETURN ten: FUNCTION sub_ev (a, b: byte; cin: std_logic) RETURN ten; FUNCTION set _if_zero (a: STD_LOGIC_VECTOR) RETURN STD_LOGIC; CONSTANT zero_8: byte := "00000000"; CONSTANT int_66: STD_LOGIC_VECTOR (11 DOWNTO 0):= "000001100110"; CONSTANT zero_12: STD_LOGIC_VECTOR (11 DOWNTO 0):= "000000000000"; CONSTANT cla: std_logic_vector (3 DOWNTO 0):="0001"; CONSTANT cma: std_logic_vector (3 DOWNTO 0) CONSTANT cme: std_logic_vector (3 DOWNTO 0) CONSTANT asl: std_logic_vector (3 DOWNTO 0): CONSTANT asr: std_logic_vector (3 DOWNTO 0) CONSTANT jsr: std_logic_vector (2 DOWNTO 0) CONSTANT bra: std_logic_vector (3 DOWNTO 0):5"1111"; CONSTANT indirect: std_logic:="I'; CONSTANT jmp: std_logic_vector (2 DOWNTO 0):="100"; CONSTANT sta: std_logic_vector (2 DOWNTO "101 CONSTANT Ida: std_logic_vector (2 DOWNTO 0):="000"; CONSTANT ann: std_logic_vector (2 DOWNTO 0):="001"; CONSTANT ade: std_logic_vector (2 DOWNTO 0):="010"; CONSTANT sbe: std_logic_vector (2 DOWNTO 0):="011"; CONSTANT jsr_or_bra:std_logic_vector (1 DOWNTO 0): CONSTANT a_and_b: STD_LOGIC_VECTOR (5 DOWNTO 0) CONSTANT b_compt: STD_LOGIC_VECTOR (5 DOWNTO 0): CONSTANT a_input: STD_LOGIC_VECTOR (5 DOWNTO 0):="000100"; CONSTANT a_add_b: STD_LOGIC_VECTOR (5 DOWNTO 0):="001000"; CONSTANT b_input: STD_LOGIC_VECTOR (5 DOWNTO 0): CONSTANT a_sub_b: STD_LOGIC_VECTOR (5 DOWNTO 0) END UTILITY; ‘Trong than kh6i utility trinh bay hai gidi thugt thye hi¢n hai phép toan cong va tri, Trong ham eng, ket qua phép cng bit va cd nhé ciha né duge tinh nhu sau: Sum = a XOR b XOR carry ((a xor b) and carry) or (a and b) GVHD: Lé Manh Hai Grang 34.Luan van t6t nghiép KE CPUS ng VHDL. ‘Vang for thyc hién 8 phép cOng lién tiép a€ tao ra két qua va cd nhé. Dé xéc dinh bit tran, kiém tra hai ng6 vao cing d&u va két qua khéc dau thi phép tinh da bi tran Néu ddu_a bing dfu_b va ke qua khéc dua thi train ngude lai thi khong tran Di véi phép triv cing twong ty nhu phép c6ng chi Khe 12 truée Khi thy hién thi lay s6 bd ca b va c@ tran, PACKAGE BODY ulility IS FUNCTION add_cv (a, b: byte; cin: std_logic) RETURN ten IS VARIABLE r, c: ten := "0000000000"; VARIABLE a_sign, b_sign: std_logic BEGIN a_sign := a (a LEFT); b_sign := b (b'LEFT); 1(0) := a(0) XOR b(0) XOR cin; ¢(0):=((aO) XOR b(0)) AND cin) OR (a(0) AND b(0)); FOR i IN 1 TO (a'LEFT) LOOP ri) == a(i) XOR bi) XOR eti-1); (i) := (aGi) XOR b(i)) AND e(i-1)) OR (ai) AND b(i)); END LOOP; 1a'LEFT+1) = c(@'LEFT); IF a_sign = b_sign AND r(a’LEFT) /= a_sign ‘THEN r (a'LEFT+2) ELSE r (a'LEFT#2) : END I RETURN r; END add_cv; FUNCTION sub_cy (a, b: byte; cin: std_logic) RETURN ten IS VARIABLE not_b: byte := zero_8; VARIABLE not_c: std_logic; VARIABLE r, c: ten := "0000000000"; VARIABLE a_sign, b_sign: std_logic BEGIN not_b := NOT b; not_¢ := NOT cin; a_sign = a(a'LEFT); b_sign := not_b(b'LEFT); 1(0) := a(0) XOR not_b(0) XOR not_e; (0) == ((a(@) XOR not_b(0)) AND not_c) OR (a(0) AND not_b(0)); GVHD: Lé Manh Hai Feang 35Luan van tot nghiép KE CPUS ng VHDL. FOR i IN 1 TO (a'LEFT) LOOP 1(i) = a(i) XOR not_b(i) XOR c(i-1); c(i) := (a(i) XOR not_b(i)) AND c(i-1)) OR (a(i) AND not_b(i)); END Loop; 1@'LEFT+1) := NOT o(a'LEFT); IF a_sign = b_sign AND r(@'LEFT) =a_sign THEN r(a'LEPT+2) ELSE r(a'LEFT+2) END IF; RETURN r, END sub_cv; END utility; 3. Mé ta hanh vi cpu (xem/4]) M6 td hanh vi cia CPU bang Iénh cpu: PROCESS (clk_cpu) Khai béo cdc bién can thiét cho chung trinh BEGIN Wait UNTIL clk cpu =‘0"; IFreset="0" THEN Dec trang thai ban dau ELSE CASE state IS WHEN S01S10=> at bién vé ban dau IF interrup =I’ THEN Xi ly ngat quing ELSE Phat tin higu doc b6 nhé ND IF; WHEN S1 => IF interrup="I’ THEN Trd vé trang thai S10 ELSE Doc dif ligu trén bus dua vao bytel, ting PC+ 1 IF byte (7 downto 4) = Iénh mot byte THEN Thue hién Iénh 1 byte ELSE Dat trang théi S2; ND IF; END IF; WHEN S: Phat tin higu doc bé nhé dat trang thai $3 WHEN $3 => Doc dif ligu vao byte 2, tang PC +1 IF bytel (7 downto 4) = ré nhanh TE GVHD: Lé Manh Hai Frang 36Luan van tot nghiép KE CPUS ng VHDL. Thue hién lénh ré nhénh, dia chi trong byte 2 ELSIF bytel (4) /= Iénh gién tiép AND bytel(7 downto 5)=jmp THEN ‘Thy hién lénh nhay trve tiép ELSE Bit trang thai s4 END IF; WHEN S4 => Dat trang thai SS IF bytel (7 down to 5)=jsr THEN Phat xung ghi b6 nha ELSE IF byte 1(4) = lénh gién tiép THEN Phat byte2 ra tuyén dia chi Phat xung doc bd nhé ELSIF byte1(7 downto 5)=sta tre tip THEN Phat byte (3-0)&byte2 ra tuyén dia chi Nap ac vao tuyén dif ligu Phat xung ghi b6 nha ELSE Phat bytel(3-0)é&byte2 ra tuyén dia chi Phat xung doc bd nhé END Il WHEN SS => IF lénh jsr THEN Thy hién lénh jor ELSIF lénh sta tryc tiép THEN Kt thtic xung ghi ELSIF lénh gidn tiép THEN Doc byte thif 3 vao byte 2 Dat trang thai s6 IF byte (7 downto 5) jmp THEN Thyc hién lénh jmp gidn tiép END IF; ELSE ‘Thy hién lénh tryc tiép Ida, and, ade, sbe END IF; WHEN S6 => Dal trang thai S7 IF bytel (7 downto 5) = sta THEN Phat byte (3-0)&byte2 ra tuyén dia chi Nap ac vao tuyén data Phat xung ghi b6 nha ELSE Phat bytel(3-0)ébyte2 ra tuyén dia chi GVHD: Lé Manh Hai Fang 37Lu§n van t0t nghigép ‘Thiét Ké CPU 8 Bit dimg VHDL Phat xung doc bd nhé END IF; WHEN s7 =: IF lénh sta gidn ip THEN —_Két thtic xung ghi ELSE ‘Thye hién lénh gién tiép Ida, and, ade, se ENDIF; ‘Tré vé trang thai S10 END IF; END PROCESS; VI. CAC THANH PHAN CUA CPU(Xem/2,4)) So dé mé td téng quét CPU read nen —>[ 008 write nen—>) ceabestoa8N5 patag paUS ‘hon databus? reel | CONTROLLER + Pe_out->} 0 2b = | smar_paye-bos maf offer bus |-nas ino] | Lf, + \/(|CI Lag read. mem ApaUS Nocera on loc, Hinh 24. CPU duge trinh bay & day c6 cae thinh phan chinh la AC, IR , PC, MAR, SR, ALU va SHU. Dong dit ligu chay gidfa cdc thanh phan thdng qua cde tuyén két néi. GVHD: Lé Manh Feang 38Luan van tot nghiép Ké CPU 8 Bit ding VHDL 1, Chife nang ciia c4c thanh phan cua CPU Bay thanh phan cla CPU: AC, IR, PC, MAR va SR 1a céc thanh ghi, ALU va SHU 1a cdc don vi luan ly té hgp. Méi thanh phan c6 mét tap hop yao va ddu ra v6i nhiéu dudng diéu khién. ‘Thanh ghi tich luy AC 1a thanh ghi 8 bit thanh ghi nay c6 nhi¢m vu cung cp ton hang cho don vi ludn lf s@ hoc ALU. Thanh ghi lénh IR n6i vi DBUS thong qua bé Iwan ly sf hoc ALU va cung cap cc bit Jénh dén bé diéu khién va mét dia chi trang dén tuyén dia chi (ADBUS) Thanh ghi bo dém chuong tinh PC 1a mt thanh ghi 12 BIT cing 1a mét bé dém lén theo kiéu nhj phan cung cp cae dia chi Iénh dén tuyén dia chi (ADBUS) théng qua thanh ghi dia chi b6 nhé (MAR). ‘Thanh ghi dia chi mar 1a bd dém dia chi, c4c thanh ghi MAR va PC c6 céc phan trang va 6 dai dude nhan dang béi tin hiéu mar_page, pe_page, mar_offset, pe_offset. S6 trang duige luu tri trong 4 bit c6 trong s6 cao nl Don vi luan ly sO hoc ALU la don vj luan ly t6 hop véi hai Gp hgp déu vAo 8 bit, bén ddu vao cit, ba ddu vao diéu khién, Céc dau ra cba don vi nay duge néi d€n cdc diu vao cia don vi SHU, Shifter (SHU) 1a don vi luan ly 6 hgp va né thye hién nhing thao tae dich chuyén tr4i hay phdi ca todn hang Bit. ‘Thanh ghi trang thai SR c6 4 du vao va 4 dau ra. Cae diu ra cla thanh ghi trang thai truyén qua ALU va SHU réi quay vong tr lai diu vao cia chinh n6, Diéu nay cho phép cde cd duge diéu chinh bai m9t trong nhting don vj lun ly nay. B6 diéu khién (CONTROLLER) phat ra tin hiéu diéu khién cho céc khéi thinh phan va cac bus. Nhiing tin hiéu nay gay ra chuyén d6ng dif liéu théng qua bus hé théng va luu tri di liéu nay vao thanh ghi. B6 diéu khién dua ra tin higu diéu khién dua vao tin higu reset, vao trang thai cla né, vao ngit quang bén ngoai va vao céc bit cila IR va SR. 2. Thue hién Iénh Dya vao Iénh nim trong thanh ghi IR, b6 diéu khién phat sinh céc tin higu diéu khién theo the ty thich hgp dé thyc hién 1énh, Dé minh hoa cho co ché lénh nay c6 thé mé ta chudi su kién dé thuc hién lénh Ida nhu sau. Ban dau bé dém chuong trinh chifa dja chi cla lénh duge phat ra. Vide fim lénh bt dau véi viée chuyén dia chi tiy PC dén MAR va ting PC lén 1 Dé thyc hién dia chi trong PC duge dat trén mar_bus va MAR phai duge cho phép va c6 xung déng hé. Sau 46 b6 diéu khién kich hoat tin hiéu trong GVHD: Lé Manh Hai Frang 39Luan van t6t nghiép KE CPUS ng VHDL. MAR len tuyén dia chi ADBUS cing lic véi viée phat tin hiéu read, Diéu nay 1am cho dif ligu ti b6 nhé xudt hién tren DATABUSI va di qua DBUS, ALU, SHU va OBUS dé téi IR. Dé dat duge myc dich nay CONTROLLER kich hoat tin higu digu khién databus_on_dbus, chi din cho ALU dé dat side_a Ién diu ra cia n6, va diéu khién thanh ghi dich dat dit ligu ddu vao 1én dau ra ma khéng dich chuyén n6, Dit ligu trén dau ra cia SHU duige phép nap vao IR. Tiép theo viée nap 1énh CONTROLLER dua ra tin hiéu thich hgp dua én céc bit cla IR. Céc bit e6 trong s6 cao nhat cia IR 18 0000, chi ti lénh Ida dinh vi truc tiép dé tao ra dia chi ddy di cho lénh Ilda, CONTROLLER cAi ndi dung hién hanh cia PC vao MAR va ké d6 duge dat len ADBUS va phat xung read_mem. Data doc tit b6 nhé sé truyén qua DBUS va MAR BUS dé dén ddu vao cia thanh ghi MAR OFFSET. Lic nay, CONTROLLER kich hoat tin higu dé dat 4 bit c6 trong s6 thép nhat cia PC lén thanh ghi MAR_PAGE. Khi cé dii tin hiéu 6 dau vao xung déng hé mar thyc hign cdi dia chi day di cla ton hang cila Ida vao than ghi nay, Thao téc doc bd nhé tigp theo sé dit todn hang cia lénh Ida len DATABUS, Di ligu 8 bit nay truyén qua DBUS va sn sang trén a_side cla ALU, CONTROLLER diéu khién ALU dat dau vao side_a lén dau ra cha n6, va Lim cho SHU dua dif ligu dau vao dén du ra cia né ma khong dich chuyén, Toén hang cia Ida bay gid xudt hién (én OBUS, CONTROLLER cho phép nap vao AC va tai canh én cita déng hd, toan hang ciba Ida duge cAi vio thanh ghi tich luy Vige thyc hién céc lénh khée duge 1am theo céch tuong ty nhu Gén inh di m6 (4 d6i vdi Iénh Ida, Béi v4i cdc Iénh and, ade, va sbe, khi toan hang ciia lénh c6 mat trén side_a cla ALU, CONTROLLER phat tin higu cho ALU dé thyc hién thao tac and, ade hodc sbe thay vi dua todn hang qua dau ra cia ALU, D6i véi dia chi gidn ti€p, CONTROLLER tgo ra thao tc doc thém tit bd nhé truée khi thyc hién Iénh c tin hiéu diéu khién ngé vao va ngé ra cla CPU Phinti Loai Tén tin higu Chite ning AC Diéu | Load_ac, Napac khign | zero_ae Xoé ac thanh gi IR iéu | Load ir Napir khién thanh ghi PC Bigu___| Increment pe, Tang pe GVHD: Lé Manh Hai Trang 40Luan van tot nghiép ‘Thiet Ké CPU 8 Bit ding VHDL khign | Load_page_pe, Nap phan trang ofa pe thanh ghi | Load_offset_pe Nap phin ddi eda pe Reset_pe Xo’ pe MAR Digu | Load_page_mar Nap phan trang ola mar khign | Load_offset_mar Nap phan di eta mar thant ghi sR Didu | Load_sr Nap st khign | Cm_carry_se Lay bit e@ carry cia st thanh phi MAR_BUS Diéu | Pe_on_mar_page_bus | Dat phn tang oda pe lén phan tang khign bus cia tuyén mar Iron_mar_page_bus | Bat4 bits cia irlén phan trang cia Pe_on_mar_offset_bus | Dit d6 d¥i cia pe én 9 d¥i eta yen dbus_on_mar_offset_bus | Dat dbus lén d6 dati oda tuyén mar BUS Digu | Pe_offset_on_dbus Dat dG d¥i ella pe len dbus khign bus | Obus_on_dbus at obus lén dbus Databus_on_dbus Bat databus bén ngoai lén dbus bén ADBUS Diéu | Mar_on_adbus i mar lén adbus khign bus DATABUS] Digu | Dbus_on_databust Dit databus! bén ngoai lén dbus ben khign bus tong DATABUS2 Digu | Obus_on_databus? Dat obus bén trong 1én databus2 ben khign bus ngodi SHU Bon vi) Arith shift left Dich | bit sang trai logic __|_Arith_shift sight | Djeb 1 bit sang phai ALU Dan vi | Alu_and ‘wit ng6 ra alu ciia phép and 2 ngo vao logic | Alu_not Xuft ng6 ra alu ela phép 6D ng@ vio b lua Xuilt ng ra alu cia chinh ngo vao a ‘Alu_add ‘Alu thu hign eng hai ng6 vao Alu uit ng ra alu cila chinh ng6 vaob Alu_sub ‘Alu thufe hign trit2 ng vao ‘Other vO Read_mem| Khai déng thao téc d6e b6 nho Write_mem Khai dOng thao tée viet bd nhs Incerrup Net quing CPU Bang 3. 3. M6 t cde thanh phin 3.1. Bon vi ludn If s6 hoc (Arithmetic logic unit) ALU cé hai ton hang 8bit, 6 dong ma thao tc (six opcode select lines), 4 cd nhap, 8 duding xudt dif liéu, va 4 cd xudt, Séu dong ma nay chon toan hang ciia ALU theo bang sau. GVHD: Lé Manh Hai Trang 41Luan van tot nghi¢p ‘Thiét Ké CPU 8 Bit dimg VHDL str Dong ma Thaotie | cy (Opeode Hine _| (Operation) 0 | Alu and AND ma 1 | Alu not NoTb m 2 | aAlwa a m 3 | Alu add bPLUSa vean 4 | Alu b ma 5 | Alusub MINUS « ver Bang 4 So d6 mé té phan cing Khoi ALU aly aa alub » to sla sub Hinh 25, Day la doan chvong trinh mé ta hank vi khéi ALU ciia CPU bing ngén ngit VHDL ENTITY alu IS PORT (a side, b_side: IN byte; alu_and, alu_not, alu_a, alu_add, alu_b, alu_sub: IN STD_LOGIC; in_flay z0 uut_flags: OUT nibble); END alu; ARCHITECTURE behavioral OF alu IS BEGIN GVHD: Lé Manh Feang 42KE CPUS Lugn vin tot nghiép ding VHDL coding: PROCESS (a_side, b_side, alu_and, alu_not, alu_a, alu_add, alu_b, alu_sub) VARIABLE t: ten; VARIABLE temp: STD_LOGIC_VECTOR (5 DOWNTO 0); VARIABLE temp]: nibble; VARIABLE v, ¢, 2, n: STD_LOGIC; ALIAS n_flag_in:std_logic IS in_flags (0); ALIAS z_flag_in:std_logic IS in_flags (1); ALIAS c_flag_in:std_logic IS in_flags (2); ALIAS v_flag_in:std_logic IS in_flags (3); BEGIN out_flags <= "0000"; temp (5) := alu_sub; temp (4) := alu_b; temp (3) := alu_add; temp (2) := alu. temp (1) := alu_not; temp (0) = alu_and; CASE temp IS WHEN a_add_b=> T = add_cv (b_side, a_side, c_flag_in); C18); V=t(); WHEN a_sub_b => T := sub_ey (b_side, a_side, ¢_flag_in); CHL) Vist); WHEN a_and_b=> T (7 DOWNTO 0) := a_side AND b_side: C:sc flag in; V:=v_flag_in; WHEN a_input=: T (7 DOWNTO 0) Cc flag _in; WHEN b_inp\ T (7 DOWNTO 0) := b_side ; Cc _flag_in; V:= v_flag_in; WHEN b_compt=> T (7 DOWNTO 0) Css flag in; WHEN OTHERS=>NULL END CASE; N=); Z:= set_if_zero(t(7 DOWNTO 0)); z_out <= (7 DOWNTO 0); temp! (3) temp! (2) :=¢; temp1 (1) = temp! (0) + GVHD: Lé Manh Hai Grang 43Luan van t6t nghiép KE CPUS ng VHDL. out_flags <= temp]; END PROCESS coding: END behavioral; 3.2, Don vi dich chuyén (Shifter unit) Don vi dich chuyén SHU ciia CPU c6 hai cach hoat dng dich tréi hose dich phai, 4 c& nhap vai 8 dudng dif ligu nhap, 4 cd xudt va 8 duding dit ligu xuat. Khi dich trai ton hang né dich chuyén bit 0 vao vi tri cé trong sé thap nhat cia dau ra, di chuyén bit c6 trong sé cao nhat cia du vao dén cd nhd. Khi dich phai bit tin higu 4 ng6 nhap ty bit 7 dén bit 1 dich sang phi mot don vj va n6 néi thém gif tri vao bit c6 trong s6 cao nhat cla ngé ra bing 2i4 tri 0. C4 hai phuong phép dich chuyén, déu c6 nh hudng dén cd zero va cd not. So a6 mé td phan cing cia khéi SHU > + cut put isl I . a oH Hinh 26. oan chvong trinh m6 ta hanh vi cia SHU. ENTITY shifter 1S PORT (alu_side: IN byte; arith_shift_left, arith_shift_right: IN STD_LOGIC; in_flags: IN nibble; obus_side: OUT byte; out_flags: OUT nibble); END shifter: ARCHITECTURE behavior OF shifter IS BEGIN coding: PROCESS (alu_side, arith_shift_left, arith_shift_right ) VARIABLE t, t1: byte; VARIABLE y, ¢, z, n: STD_LOGIC; GVHD: Lé Manh Hai Frang 44Luan van tot nghiép KE CPUS ng VHDL. ALIAS n_flag_in:std_logic IS in_flags (0); ALIAS 7_flag_in:std_logic TS in_flags (1); ALIAS c_flag_in:std_logic IS in_flags (2); ALIAS y_flag_in:std_logic IS in_flags (3); BEG = alu_side; v:= in_flags(3); in_flags(2); 25 in_flags(1); n= in_flags(0); elsif arith_shift_left ="I' then (7); z alu_side(7);—v elsif arith_shift_right ='I' then set_if_ zero(t); }u_side(6) xor alu_side(7); t:= (alu_side(7) & alu_side(7 downto 1)); a:=set_if_zero(\); obus_side <= t; out_flags (3) <= out_flags (2) out_flags (0) <= END PROCESS coding; END behavior, 3.3. Thanh ghi trang thdi (Status register unit) out_flags (1) <=23 Thanh ghi trang thai la thanh ghi déng bé, di liéu nap lén nhiing cd duge diéu khién déng bd bai ngd nh§p cia load va c& cm_carry, Khi cd load duge kich hoat tat cd 4 e3 nhap duge nap vao trong cd cla nhting flip-flops, va khi kich hoat ¢3 cm_carry, c& c duge nap hodn tat So 46 phdncting cita thanh ghi Hinh 27, GVHD: Lé Manh Hai Frang 45Luan van tot nghiép KE CPUS ng VHDL. Dang VHDL mé ta thanh ghi trang thai sit dung qui trinh Iénh xit ly xung clock vao. Bién internal_state trong cu tric hanh vi cia status_register_unit chia gid trj cila thanh ghi. Trén nhiing canh cita xung clock, bién nay chi dinh dén hung xuét cia thanh ghi trang thai. ENTITY sr IS PORT (in_flags: IN nibble; out_status:OUT nibble; load, cm_carry, ck: IN std_logic); END sr; ARCHITECTURE behavioral OF sr IS BEGIN PROCESS(ck) VARIABLE internal_state: nibble:="0000"; ALIAS internal_c: std_logic TS internal_state(2); BEGIN IF(ck="0') THEN IF(oad='1') THEN ELSIF(m_carr} internal_c:=NOT internal_c; END IF out_status<= internal_state; END Il END PRO‘ END behavioral; 3.4, Thanh ghi tich lu§ (Accumulator) So dé phan ciing 1 bit cla Ace Ls— i ) Bb 9-01 12 Gi Hinh 28. ‘Thanh ghi tich lug 18 thanh ghi & bit bling céch nap déng b6 nhap nhitng gid ti ‘0’. Thanh ghi (ich luy nap dif liéu ty bén ngoai vao trong thanh ghi & canh xudng cia xung clock, khi ng6 nh4p nap kich hoat va ngo nh§p ‘0’ bi céim. Déng thai su hoat dng cba ngo nhap zero va load duige dat dng b@ thanh ghi, GVHD: Lé Manh Hai Grang 46Lun vin tot nghiép KE CPUS ding VHDL Doan ma VHDL mé té datafolw cla accumulator trong c&u tric datafolw iia ace ENTITY acc IS PORT (i8: IN byte; 08: OUT byte; load, zero ,ck : IN std_logic); END ace; ARCHITECTURE dataflow OF ace IS BEGIN Process (load, clk) BEGIN IF (ck="0" AND ck’ EVENT) THEN IF load="1" THEN IF zero= ‘1’ THEN 08 <: ELSE 08 <=i8; END I END II END IF; END process; END dataflow; 00000000"; 3.5. Thanh ghi lénh (Instruction register) Thanh ghi Iénh (ir) 1A thanh ghi déng b6 8 bit véi ngd nhap tich eve & mic cao. Ngé nhap cho phép nap clock va nguyén nhan dé thanh ghi nap canh xuéng cia ngé nhap xung clock So 46 1 bit phiin cing cia IR Hinh 29, Doan ma VHDL mé t& thanh ghi lénh trong eu tric dataflow ca ir ENTITY ir IS PORT (i8: IN byte; 08: OUT byte; load, ck: IN std_logic); END ir; ARCHITECTURE dataflow OF ir IS BEGIN PROCESS (load, ck) BEGIN GVHD: Lé Manh Hai Frang 47Luan van tot nghiép K€ CPUS ing VHDL IF (ck="0' AND NOT ck'STABLE) THEN IF load="I' THEN 08 <= i8; END I END IF; END PROCESS; END dataflow; 3. BO diéu khién cia CPU (control section) Bé diéu khién controller gm c6 mét chuéi trang thai, ma méi trang thai git’ m6t tin hiéu diéu khién kich hoat chinh xdc xung clock. Ngo nh§p cia nhiing kh6i ludn ly ti nhiing trang thai cila nhiing flip- flops kh4c nhau va tir nhitng ngo nhap bén ngodi, ma trang théi dé anh hung bén trong bé diéu khién. Ng6 xudt cila khéi ludn 1y (logic block) 1a nhiing tin hiéu diéu khién ma nhifng tin hiéu diéu khién nay tré thanh nhifng ng6 nhap ciia khdi ké tiép. Trang thai ca nhitng flip-flops diva ra nhiing tin higu diéu khién khéc nhau. So dé cu tric bé diéu khién cla CPU oe ee Hinh 30, Nhu mé td trong so dé tt cA nhitng trang thai déng bd véi xung clock va nhiing ng6 xudt g6p phdn dua ra nhitng tin hiéu diéu khién hodc kich hoat nhiing flip-flop. Trong so dé nay trang thai i c6 diéu kién kich hoat béi bdi trang thai k. Trang thai icé diéu kién kich hoat trang thai jva trang thai k ludn ludn dude kfch hoat sau thai gian xung clock ma trang thai j da kich hoat. Tin hiéu diéu khién csx thi luén luén phat ra sau khi trang thai k duge kich hoat hodc khi trang thai i duge kich hoat va diéu kién chéc chdn 1a duge chita dug trén nhiing ngo nhap a, b va c. Tin hiéu diéu khign csy tr thanh kich hoat khi tin higu 6 trong trang thdi j va diéu kién chic chin duge chita trong ngé nhap d va e. Khai béo ENTITY cita bo diéu khién CPU GVHD: Lé Manh Hai Frang 48Luan van tot nghiép KE CPUS ng VHDL. ENTITY control IS PORT (clk: IN std_logic; load_ac, zero_ac, load_ir, load_sr, load_page_mar, Joad_offset_mar, increment_pe, load_page_pc, load_offset_pe, reset_pe, cm_carry_st, pe_on_mar_page_bus, ir_on_mar_page_bus, pe_on_mar_offset_bus, dbus_on_mar_offset_bus, pe_offset_on_dbus, obus_on_dbus, databus_on_dbus, mar_on_adbus, dbus_on_databus, arith_shift_left, arith shift right, alu_and, alu_not, alu_a, alu_add, alu_b, alu_sub: OUT std_logie; ir_lines: IN byte; status: IN nibble; read_mem, write_mem: OUT std_logic; interrupt: IN std_logic); END control; CAc trang thai cia b6 diéu khién Trang thai s1 sl: PROCESS (s(1), clk) BEGIN IF (clk='0" AND clk'EVENT) THEN IF (1) ="I' THEN pc_on_mar_page_bus <='I'; pc_on_mar_offset_bus load_page_mar <='1'; load_offset_mar IF interrupt="1' THEN reset_pe <= "1; s(1) <= ELSE resel_pe <= END I s s(1) END PROCESS; Mé ta phan cting cia khdi S1 GVHD: Lé Manh Hai Trang 49.Luan van t6t nghiéy KE CPUS | pe on mar page bus | pe_on_mar_offset_bus [—> load page mar [load offset mar Je oa reset pe Hinh 31, Trong trang thai 1 bat dau dat dif ligu pe wen mar_bus va tuyén dit ligu nay vao trong mar. Néu ng6 nhap interrupt tfch cye thi ngé nhap pe_reset dude phat ra va tra vé diéu khién dén trang thai 1. Néu CPU khéng ngdt thi trang théi 2 tich ce & canh xudng cia xung clock, Ngoai ra trén canh nay cia xung clock, mar nhan gid tri méi, Trong ma thanh ghi dit li¢u va trang théi diéu khién ching ta c6 ch4c chin ring ching déng bd t4t cd véi canh xuding cila xung clock Trang thai 2 82: ROCESS(s(2), elk) BEGIN IF (clk ='0' AND clk EVENT) THEN IF s(2) ="I' THEN mar_on_adbus read_mem databus_on_dbus <='1'; alu_a<='I'; load_ir <="'I'; increment_pe <: 8G) <=" END IF; END IF; END PROCESS; cing ciia khéi S2 GVHD: Lé Manh Hai Trang 50Luan van tét nghiéy KE CPUS ‘mar_on_adbus | read_mem | datatus_on_dbus | ama | toad ir | inerement_pe 1>po}-e a Hinh 32. Khi 6 trang thai 2, mar di nhan gid tri mdi 4 rong danh séch cho 6 rong trang thai 1. Ndi dung ciia b6 nhd dua ra trong databus phi khdi tao trong ir, Muc dich chi yéu Ia tin higu diéu khién databus_on_dbus phét ra, lin higu alu_a duge tfch cute va c&c ng6 nhap ir duge cho phép. Trén canh ca xung clock trang thai 3 trd nén tich cuc va ir sé c6 gid tri méi cla né Mac di trong trang thai 2 hdm tang cila pe duge chon vi vay gid tri cla né ing én trong canh xuding tiép theo cia xung clock Trang thai 3 s3: PROCESS(s(3), clk) BEGIN IF ll '0" AND clk'EVENT) THEN IF s(3)="I' THEN pe_on_mar_page_bus <='1'; pe_on_mar_offset_bus load_page_mar <='1'; load_offset_mar <="'1' IF ir_lines (7 DOWNTO 4) ELSE s (4) <='0' END IF; END IF; END IF; IF (ir_lines (7 DOWNTO 4) /="1110") THEN, IF ir_lines (1) ="I' THEN "1110" THEN s(4) <="1'; alu_not <= alu_b ELSE alu_not alu_b <='1'; END IF; GVHD: Lé Manh Hai Trang 51Luan van tot nghiép KE CPUS ng VHDL. IF ir_lines (3 DOWNTO 0) arith_shift_left <: "1000" THEN 1 arith_shift_left <='0 END IF; IF ir_lines (3 DOWNTO 0) = "1001" THEN arith_shift_right <: arith_shift_right <= END IF; IF (ir_lines (3) = 'I' OR ir_lines(1) = '1') THEN load_st <='1'; load_ac <= ENDIF; IF ir_lines (2) ="I’ THEN cm_carry_sr <= ELSE em_carry_sr<='0' END IF. IF (ir_lines (3 ELSE zero_ac <= s(2) <="I's ‘0’ AND ir_lines(Q) = '1') THEN zero_ac <="1’; END PROCESS; M6 ta phan citng cia khdi $3 GVHD: Lé Manh Hai Frang 52Luan van t6t nghiéy p> pe on mar page bus | pe on mar_offset_bus | toad page mar load offset. mar »® LO© ))— arith_shift_teft 3 arith shit sight i o my TT) em_earry_sr => rT) load ac ee Hinh 33. Khi trang thai 3 tich cye, trang thai 3 bat dau xii ly doc byte tiép theo tY b6 nhé, trong cing thd gian 46 né kiém tra sé byte trong chi thi lénh hién hanh, Néu né 1a 1énh hai byte thi byte ké iép (rd thanh byte dia chi cita n6 va trang thai 4 dude kich hoat dé tip tue thyc hi¢n 2 byte Iénh. Tren quyén khéc, néu lénh hién hanh 1a 1énh khong dia chi va khéng ddi hdi byte 2, the hign trang thdi 3 va kich hoat trang thai 2 dé thyc hign lénh tiép theo. Nhting lénh khong dia chi (mot byte) thyc hi¢n tinh todn trén thanh ghi va nhiing ci, Tin hiéu alu_b duigc kich hoat vi thé ng ra alu chita noi dung cita ace. GVHD: Lé Manh Hai Frang 53Luan van tot nghiép KE CPUS ng VHDL. - Ham arith shift_right cia alu dude chon né dich chuyén ndi dung cba ace sang ben phai. - Ng nh4p ca thanh ghi trang th4i thi duge cho phép vi thé nhiing gid tri mdi cia nhiing c& dugc phat ra béi thanh ghi dich va nap vao trong thanh ghi trang thai, - Ngé nhap ciia ace duige cho phép vi thé duge nap vao thanh ghi nay véi ng6 ra ciia thanh ghi dich. Trang thai 4 sd: PROCESS(s (4), clk) BEGIN IF (clk ='0' AND clk'EVENT) THEN IF s(4) ='' THEN mar_on_adbus databus_on_dbus dbus_on_mar_offset_bus load_offset_mar <='1 IF (ir_lines (7 DOWNTO 6) /="11") THEN ir_on_mar_page_bus <='I'; load_page_mar <='1'; IF (ir_lines (4) ='1') THEN sS)<="1'; (6) < ELSE s(5)<='0; (6) <= END IF IF (ir_line s(5) ='0') THEN s(@) s(9) END Il increment_pe END IF; --s (4) END IF; --clk END PROCESS; GVHD: Lé Manh Hai Grang 54.Luan van t6t nghi KE CPUS Mé ta phn ciing ciia khoi S4 5 mar_on_adbus | read. mem tp databus_on dbus | dbus on mar offset bus Sp load offset mar increment pe ‘_on_mar_page_bus b@ | = [ ee a TH. | )-@ | LF Hinh 34. Trang théi 4 duide kich hoat khi dia chi diy di hode dia chi trang duge thyc thi, Dé chudn bi doc byte thi hai cia lénh trong tang thai 3, Joad_offset_mar duge kich hoat, byte nay sé phat xung clock trong mar trén canh xuéng tigp theo cila xung clock. Néu lénh dufgc thue thi 1a Iénh dia chi day di thi s@ trang ir chuyén sang trang thai sin sang 6 ngo nhap cia trang ‘mar trong thanh ghi véi xung ké tiép, Néu lénh duge thu thi 18 jsr hoc bra th thanh ghi mar_page giit lai gid tri hién hanh. BGi vi day 1A nhiing 1énh dia chi duy nhat trong trang hién hanh. Trang thai 4 kfch hoat trang théi 5 hodc trang thai 6 cho nhing cach inh bay dia chi rye tiép hoc gidn tiép cia nhiing lénh dia chi day dit va 16 kich hoat trang thai 7 hodc trang thai 9 bai nhiing lenh jsr hoc bra. Trang thai 5 s5: PROCESS(s(5), clk) BEGIN IF (clk="0' AND clk'EVENT) THEN IF s(5) ="I' THEN mat_on_adbus <= read_mem <='1'; databus_on_dbus <="1'; dbus_on_mar_offset_bus <='1'; GVHD: Lé Manh Hai Frang 55Luan van tot nghiép KE CPUS ng VHDL. load_offset_mar <- (6) <="l' END IF; END IF; END PROCESS; M6 ta phin cting cia khdi SS |, mar_on_adbus |, read mem | databus_on_dbus |__5, dbus on_mar_offset hus | toad offset. mar so@® a +H Canh xudng cila xung clock kfch hoat trang thai 5 ngoai ra né cling nap dia chi day di vao mar. Trong trang thai nay vi Uf con tr cia bd nhd chuyén dén mar doc dif li¢u én databus va (go gid tri én ng6 nhap cla thanh ghi mar_offset. Su kich hoat load_offset_mar l& nguyén nhan dé mar nap nhiing byte tit bé nhé trén canh déi cila xung clock. Trang thai 5 kich hoat trang thai 6 ma trang thai ndy thi giéng nhut dude kich hoat béi trang thai 4 néu dia chi true tiép dude sit dung. Trang thai 6 Trang thai 6 dugc kfch hoat khi nhting 1énh thyc thi 1 jmp, sta, Ida, and, add hoge sub. Trong trang thai nay mar chifa nhiing todn hang dia chi day da. 86: PROCESS (s(6), clk) Hinh 35, BEGIN IF (clk = '0' AND clk'EVENT) THEN IF (6) ='I' THEN IF (ir_lines (7 DOWNTO 5) = "100") THEN load_page_pe <='I'; load_offset_pe s(2) <='l'y-goto 2 END IF; GVHD: Lé Manh Hai Trang 56Luan van tot nghiép K€ CPUS ing VHDL IF (ir_lines (7 DOWNTO 5) = "101") THEN mar_on_adbus <='I'; alu_b <='1; ‘obus_on_dbus <: dbus_on_databy write_mem <='1'; IF (ir_lines (7) ='0') THEN mar_on_adbus <='1'; read_mem <='I'; databus_on_dbus IF ir_lines (6 DOWNTO 5) = "00" THEN alu_a ELSE alu_a <= "0; END I IF ir_lines (6 DOWNTO 5) = "01" THEN alu_and <='1'; ELSE alu_and <='0'; END IF; IF ir_lines (6 DOWNTO 5)="10" THEN alu_add <='1'; ELSE alu_add <='0'; END IF; IF ir_lines (6 DOWNTO 5) ="11 alu_sub <='1' ELSE alu_sub <='0; END IF; load_st <= load_ac <= END IF; END IF; END IF; END PROCESS; GVHD: Lé Manh Hai Frang 57Luan van tot Thiét KE CPUS Mé ta phin cting cba khéi S6 s = @) 2) >4e@ CS retartet pe "IO > mar_on_adbus LS atu [ opus ¢ [S abus on O_o > mar_on_adbus |, read_mem [5 statin cus [5 tnt se 13 inde vous =o J stand = sa j-th sh Hinh 36. Trang thai 7 s7: PROCESS(s (7), clk) BEGIN IF (clk = '0' AND clk’ EVENT) THEN IF s (7) ='I' THEN mar_on_adbus <='I'; pe_offset_on_dbus dbus_on_databus <: write_mem <= load_offset_pe <= 8 (8) <='1'; -goto 8 END IF; END IF END PROCE GVHD: Lé Manh Hai Frang 58Luan van tét nghiéy KE CPUS Mé ta phin cting cla khdi S7 ‘mar_on_adbus | —> pe offset_on_dbus |__databus_on_databus | write mem | load_offset_pe —p@ |—© a A Hinh 37. G wang thai 7 tiép tuc thu thi lénh jst. Trong trang théi nay ghi ndi dung cia pe vio thi (ye mar va trong ciing thai gian nay dia chi dau cia thi: tuc chuyén yao thanh ghi pe. Trang thai 8 s8: PROCESS(s(8), clk) BEGIN IF (clk = '0' AND clk’ EVENT) THEN IF s (8) ='I' THEN increment_pe <="I'; s(1) <='1'; END IF; END IF; END PROCESS; M6 ta phiin cing ciia khdi S8 |__ increment_pe jv @ dl d Hinh 38. Sau trang thai 7 trén canh xu@ng cia xung clock thi trang thi 8 tich eve dé thuie thi Iénh jsr. Trong trang thai nay pe chita vj tri dau tién cia thd GVHD: Lé Manh Hai Trang 59Luan van tot nghiép K€ CPUS ing VHDL tue, Trong trang th4i 8 nap tin higu increment_pe va kich hoat trang thai 1 dé nap lénh dau tién cita thi tuc. Trang thai 9 89: PROCESS(s (9), elk) BEGIN IF (clk = '0' AND clk'EVENT) THEN IF (9) ='1' THEN IF (status AND ir_lines (3 DOWNTO 0) /= "0000" THEN load_offset_pe < ELSE load_offset_pe < END PROCESS; M6 ta phan cting cia khéi S9 v0 statas3 saws2 | J > toad_effset pe ia 5 iro 4 status —w@ @ —I Hinh 39. Khi trang thai 4 kfch hoat va mt Iénh ré nhénh bét dau thu thi khi d6 trang thdi 9 duge kich hoat, dia chi Iénh ré nhdnh & trong thanh ghi mar. Trang thai 9 nap mar vao trong pe néu phi hop thi Om giita bit 3 va bit O cia lénh ré nhdnh va nhiing bit thanh ghi trang thai. Néu diéu kién ré nhanh khong thod man thi pe gitt lai gid ti cia n6.Trong mot so trvdng hgp bd digu khign tra vé trang thai 1 dé thyc hign lénh ke tiép GVHD: Lé Manh Hai Trang 60Luan van tot nghiéy ‘Thiét Ké CPU 8 Bit dimg VHDL Két hgp cée hinh ty hinh 28 d€n 36 thanh m6 hinh hoat d6ng cia Khoi diéu khién nhu sau(xem thém [2]) eal b> Hinh 40, ‘Trong hinh céc khéi hinh vudng I, 2, 3, 4, 5, 6, 7, 8, 9 1a nhiing khéi diéu khién trang thai ty 1 dén 9. Nhting khéi hinh tron Igs1, Igs2, 1gs3, Igs4 1a nhiing khdi luan ly Lm nhiém vu chon Iya diéu kign thye hién trang thai tiép theo. GVHD: Lé Manh Frang 61Luan van tot nghiép KE CPUS ng VHDL. Phin3 MO PHONG Phan I gidi thiéu téng quat ich sit dung phan mém MaxPlusII. Phan I trinh bay so dé chan céc khéi ALU, SHU va khéi CONTRONLER bing chip FLEX10K va cdc giao dién mé phéng cba cdc khéi nay. I. MAX+PLUSII 1. Téng Quat Trong qué trinh thiét ké va téng hop mach mét yéu cau dat ra cudi cing 1a kiém tra duge mach da thiGt kE c6 két qua ding theo yeu edu. Trong céc phim mém vé téng hgp va kiém tra mach c6 phan mém Max+plusil 1a mét trong nhitng phin mém rat manh vé téng hgp va kiém tra mach. Sau day 1a phan trinh bay cdch sit dung vé phan mém nay: 2, Cch sit dung Max+PlusII Khéi dng phn mém Max+plusll. Sau khi phn mém Max+plusiI da duge cai dt ta tién hanh khéi dong hu sau: © Bude 1: B&m vao biéu tuong Max+PlusII Sau khi bam vio biéu tugng dé khéi déng man hinh Max+PlusIl hién ra Trinh bay cia man hinh max+plus2 gém cée thanh phan sau: - Dong 1: Thanh toolbar ding hién thj thu myc va tp tin hién hanh, - Dong 2: Gém 5 myc chinh: + Max+plus2 + File + Assign + Option +Help - Dong 3: cdc biéu tugng sit dung truc ti€p cdc ting dung cia Max+plus2 - Dong 4: Khu vife trinh bay céc loai text. © Bude 2: ‘ic thinh phan chinh trong. cae muc dong 2 nhu sau : a Muc Max+plusIl MaxplusIl dita ra nhiéu tro gitip. Hé théng bao gém 11 nhém tng dung tng hop ding dé thiét ké dn thye thi chong trinh. GVHD: Lé Manh Hai Trang 62Luan van tot nghiép K€ CPUS ing VHDL C6 11 phan: > Hierarchy Display: trinh bay céc phan céip sau khi thiét ké' va dich, > Graphic editor: cho ché 46 vé mach thiét ké va kiém tra mach theo dang cu tric Symbol Editor; dua ra mt thye thé (entity) sau khi da dich chudng trinh, Text Editor: yao soan thio chung trinh Waveform Editor: soan théo va kiém tra mach etla chung trinh Floorplan Editor: soan thao va thiét ké theo dang Floorplan Compiler: dich chuéng trinh Simulation: thye hién mé phéng ‘Timing Analyzer: phan tich thi gian cia chip Programmer: xéc dinh eta thiét bi phn cing > Message processor: man hinh thong bao va nh xa d€n céc 16i khi dich. b- Muc file: Muc file gém c6 7 thanh phin c- Muc Assign Muc Assign gdm cé 16 thanh phin v vVVVVVY v d- Muc Options gém cdc thanh phan : e- Muc Help: Ding tro gidp trong phan mém . 2.1. Thue hién soan théo va dich m6t chung trinh thyc hién soan thio va dich 1 chudng trinh ta thuc hién theo trink ty sau * Dé soan thao mét chuong trinh téng hop phan cing Vao File \New\Text editor file Khi nay man hinh soan thao xuat hién, viéc soan thdo trong méi truing nay gidng nhu trinh soan théo winword. Sau khi soan thdo xong ghi tip tin va dit tn tap tin c6 phan mé rng Ia .vhd. « Dé dich mét chuong trinh da duc soan thao ta theo cdc bude sau: ‘Xéc dinh tp tin hién tai cn dich bing céch thuc hién: Chon File\Project\ set project to current file. Sau khi da chon xong theo yéu cfu trén ta tién hanh dich: Chon mye MAX+plus \ COMPILER khi nay cita sé cila COMPILER sé xudthién_ hu hinh sau GVHD: Lé Manh Hai Frang 63‘Luan van tot Ké CPU 8 Bit ding VHDL Man hinh Compiler hién thi nhiéu muc khéc nhau, 46 1 nhiing bd phan cia nhiing qué trinh dich va téng hop mach. Chon nit Start dé bat dau qué trinh dich. Trong quia trinh dich céc muc duyét qua, néu thanh céng thi cée muc sé duge duyét hét va hién thi mot thong béo vé c&c théng tin trong qué trinh dich. Man hinh sau sé thong bdo khi qua trinh dich thanh céng, 2.2, Thue hign kiém tra két qud sau khi da téng hop mach Sau khi dich xong chudng trinh téng hop mach tién hanh kiém tra két qua cia mach duge téng hgp .Viée kiém tra duige tién hanh nh sau: 4a, Sogn théo mét tép tin file waveform editor file. Chon File\Wew \Waveform editor file. Khi nay man hinh soan Waveform editor file xudt hién Smet Ea tor es hal enn 89 2) |v oBBees BDA Ter [Oe coemcon vo FE ie A =| ee | lu al Dé dua cdc thanh phan cin kiém tra ciba mach ta thye hién chon: Chon muc Node \enter Nodes from SNF khi 46 man hinh ciia c4c thanh phan mach sé xuat hién. GVHD: Lé Manh Hai Trang 64Luan van tot nghiép Ké CPU 8 Bit ding VHDL Ta tién hanh chon nit List va dua cde bién cia Node sang man hin Waveform sau d6 chon nit OK, Sau khi da chon xong céc bién trong man hinh Waveform Editor ta lvu (ghi) (én (Ap tin nay vdi phn ma rong .sef. 6. Tin hanh m6 phong két qué trén man hinh Waveform Editor. Khi c6 duge tap tin waveform da duge nhap 6 trén thi c6 thé mé phéng bang thiét ké va xc dinh n6 1am vige ding hay sai, M@ bang mé phéng bing céch chon Max+plus If \ Simulator sé nhin thay cita sé bang mé phang duge mé ra. Chon Start dé bat dau thyc hién mé phéng. Bang md phéng sé hoan thanh, Va dua ra két qui trong bing waveform editor, Két qu ding hay khéng phy thudc vao chung trinh cla ngudii thiét ké tng hgp mach. Tat cd cdc bude trén o6 thé dude thyc hién dude nhiéu lin cho dén khi nao dap ting ding yéu cdu cia ngudi thiét ké va téng hop mach. Trong Max+plusII c6 rat nhiéu eée chifc ning, & day chi trinh bay mot thao tac dé phuc vu cdc céng viéc mé phéng trong luan yan nay. 2.3. Thodt khéi Max+plusIT Chon File \Exit MaxplusIT md (AN HINH KHI MO PHONG 1, Khdi lun If sO hoe ALU Teh SE a) sa) ae | oh Hinh 39 m6 phéng céc tinh hiéu ng6 vao va ngé ra cia khéi ALU. Trong khéi alu thyc hién cdc lénh c6ng, trit, and, not, nap tin hiéu side_a, nap tin hiéu side_b. GVHD: Lé Manh Hai Frang 65