REVA University School of ECE

CONTENTS

Sl. Page
Experiment
No. No.
1. Course Objectives & Syllabus 2
2. Introduction 4
3. Front Panel of Digital IC Trainer Kit 6
Simplification and Realization of given Boolean Expression Using Logic
1. 9
Gates / Universal Gates
2. Half / Full Subtractor Half / Full Adder 16
3. Realization of 4-Bit Parallel Adder / Subtractor using IC 7483 22
Realization of 3 bit Binary to Grey code conversion and vice versa using
4. 28
basic/Universal gates.
5. Realization of 4:1 Multiplexer and 1:4 De-multiplexer 32
6. Arithmetic Circuit realization (Half/Full, Adder / Subtractor) using Mux 37
Construction and verification of JK Master-Slave, T type & D type Flip-
7. 46
Flops using logic gates
Construction and realization of 3 bit ripple up/down counter using IC 7476
8. 51
and other logic gates
Design and verification of mod-n, 3bit synchronous counter using 7476 JK,
9. 55
T & D flip flops
Realize the following shift registers usingIC7474/7495(i) SISO (ii) SIPO
10. 59
(iii)) PISO(iv) )PIPO
11. Challenge Experiments 63
12. Frequently Asked Viva Questions 64
13. Digital IC’s PIN Details 66

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B20EN0302 L T P C
Digital Electronics Lab
Duration :14 Wks 0 0 2 2

Prerequisites:

Number system, Fundamentals of Digital Electronics, Logic gates, Simplification of Boolean

functions

Course Objectives:

Course Objectives are to:

1. Provide basic understanding of logic gates.
2. Demonstrate simplification of Boolean functions using Boolean algebra postulates,
Karnaugh maps.
3. Provide systematic treatment of binary to gray, BCD to Excess-3 code converter and vice
versa using basic gates.
4. Introduce various combinational components like multiplexer, de-multiplexer, encoder,
decoder used in the design of digital circuits.
5. Highlight the applications of multiplexer and de-multiplexer.
6. Introduce various Flip-Flops like JK master slave, T, D flip flops using logic gates.
7. Introduce shift register (SISO, SIPO, PISO, PIPO) and Universal Shift Register,
Sequence generator.
8. Present the design details of 3 bit ripple up/down counter using IC 7476.
9. Present the design intricacies of mod-n, 3bit synchronous counter using 7476 JK, T and D
flip flops.

Course Outcomes:

At the end of the course the learner is expected to be able to:

1. Describe the working of Logic gate circuits. ( b)
2. Explain the operation of parallel adder/ subtractor. ( b, d)
3. Differentiate the concepts of binary to gray code converter, BCD to excess-3code and
vice versa. (e)
4. Design encoders, decoders, MUXs, and D’MUXs ( c, e)
5. Differentiate various types Flip-Flops like, JK master slave, T, D ( e)
6. Explain the operation of shift register (SISO, SIPO, PISO, and PIPO) and Universal Shift
Register,
7. Compare and design various types of counters( b, d, e)

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Syllabus
Digital Electronics Lab - B20EN0302

1. Simplification and Realization of given Boolean Expression Using Logic Gates /

Universal Gates Simplification and realization of Boolean expressions.
2. Half / Full Subtractor Half / Full Adder
3. Realization of 4-Bit Parallel Adder / Subtractor using IC 7483
4. Realization of 3 bit Binary to Grey code conversion and vice versa using
basic/Universal gates.
5. Realization of 4:1 Multiplexer and 1:4 De-multiplexer
6. Arithmetic Circuit realization (Half/Full, Adder / Subtractor) using Mux
7. Construction and verification of JK Master-Slave, T type & D type Flip-Flops using
logic gates
8. Construction and realization of 3 bit ripple up/down counter using IC 7476 and other
logic gates
9. Design and verification of mod-n, 3bit synchronous counter using 7476 JK, T & D
flip flops
10. Realize the following shift registers usingIC7474/7495(i) SISO (ii) SIPO (iii))
PISO(iv) )PIPO

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Introduction
In 1854 George Boole introduced a systematic treatment of logic and developed an algebraic
system now known as Boolean algebra. In 1938, C.E. Shannon introduced a two valued
Boolean algebra called switching algebra, which demonstrated that, the properties of bi-stable
electrical switching circuits could be represented through this algebra. With passage of time
Boolean algebra has emerged as a powerful tool and forms the foundation of many theories
of computer science and engineering.

Boolean algebra like any other mathematical system may be defined with a set of elements, a
set of operators and number of axioms or postulates. A set of element is a collection of
objects having a common property.

A logic gate is an elementary building block of a digital circuit. Most logic gates have two
inputs and one output. At any given moment, every terminal is in one of the two binary
conditions low (0) or high (1), represented by different voltage levels. The logic state of a
terminal can, and generally does, change often, as the circuit processes data. In most logic
gates, the low state is approximately zero volts (0 V), while the high state is approximately
five volts positive (+5 V).

There are three basic logic gates: AND, OR, & NOT, and two Universal logic gates NAND
and NOR other logic gates are emerged from basic gates such as X-OR and X-NOR.
Comparing Boolean algebra with arithmetic and ordinary algebra we note the following
differences:

 Boolean algebra does not have additive or multiplicative inverses; hence there are no
subtraction or division operations.
 Boolean algebra defines an operator called complement which is not available in
normal algebra.
 Normal algebra deals with real number, which constitute an infinite set of elements
where as Boolean algebra deals with a set of only two elements 0 and 1 (defined as
two valued Boolean algebra).
 The distributive law of '+' over '.' i.e., x + (y. z) = (x + y). (x + z) is valid for Boolean
algebra but not for normal algebra.

Using combinations of logic gates, complex operations can be performed. In theory, there is
no limit to the number of gates that can be arrayed together in a single device. But in practice,
there is a limit to the number of gates that can be packed into a given physical space. Arrays
of logic gates are found in digital integrated circuits (lC’s).

As IC technology advances, the required physical volume for each individual logic gate
decreases and digital devices of the same or smaller size become capable of performing ever-
more complicated operations at ever-increasing speeds.

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Why are NAND and NOR Gates called Universal Gates?

They are called universal gates because all of the other gates may be constructed using only
those two gates. That is important because it's a lot cheaper in practice to make lots of similar
things than a bunch of different things (different gates).

All other gates/functions can be implemented by NOR or NAND gates. So they are called
universal gates. In fact, in chips, entire logic maybe built using only NAND or NOR gates.

Eg: Inverter - NAND with inputs shorted,

AND - NAND followed by an inverter (using NAND) OR - giving inverted inputs to
NAND gate.

Implementing with NAND is easier when considering power and area of the chip. They are
called universal gates as they can be used to design all other logic circuit. Elements like X-
OR, NOR etc. Also these gates can be realized through easy combination of diodes thus
making them easy to use base elements in any chip designing project.

NAND, NOR gates are called universal gates because they can be used to create all the
remaining logical gates. Like sending the same input to the inputs of the NAND or NOR will
make it a NOT gate. Because from them you can create any other one! You can make any
other gate using NAND and NOR. Any other gate i.e. AND, OR, XOR etc can be created
using these basic gates i.e. it needs only NAND and NOR gates to create logical circuits.

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Front Panel of Digital IC Trainer Kit

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Identification of Controls on Digital IC Trainer Kit

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Note: Use Patch chords smoothly & test Patch Chord Continuity for every circuit before
connecting.

To Test, connect Patch chord end A to Input Zero (GND) & B to output LED Indicator. If
LED Glows Green (0) then the patch chord is good or else Replace the patch chord.

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Experiment – 1
Simplification and Realization of given Boolean Expression Using Logic
Gates / Universal Gates
Aim: simplification and realization of given Boolean expression using Basic/Universal gates.

Components &Equipment’s required: 74LS-08, 32, 00 & 02, Digital IC Trainer Kit, 4mm.
Patch cards etc.

a) De-Morgan’s theorem using Universal gates:

Truth Table
Input Output
A B
0 0 1 1
0 1 1 1
1 0 1 1
1 1 0 0

Truth Table
Input Output
A B
0 0 1 1
0 1 0 0
1 0 0 0
1 1 0 0

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b) Realisation of SOP expression:

i) Using NAND gates only:

Truth Table
Input Output
A B Y
0 0 1
ii) Using NOR gates only: 0 1 0
1 0 0
1 1 1

c) Realisation of POS expression:

i) Using NAND gates only:

Truth Table
Input Output
A B Y
ii) Using NOR gates only: 0 0 0
0 1 1
1 0 1
1 1 0

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d) Realisation of SOP expression:

i) Using AND-OR gates: Truth Table

A B C D Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
ii) Using only NAND gates: 0 1 1 1 1
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1

e) Realisation of POS expression:

i) Using AND-OR gates: Truth Table

A B C D Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
ii) Using only NOR gates: 1 0 0 0 0
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1

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f) Realise the following expression using only NAND gates:

Truth Table
A B C D
0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 1
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0

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g) Simplification and Realization of given Boolean Expression in SOP form using Logic
Gates/Universal Gates

Using minterm notation Y =  m (5, 6, 7, 13, 14, 15)

Simplification of Boolean expression using K-map

Truth Table
A B C D Y
i) Using basic gates: 0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
ii) Using NAND gates: 0 1 1 0 1
0 1 1 1 1
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
ii) Using NOR gates:
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1

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Simplification & Realisation in POS form:

Simplification using K-map method. From the truth table, using max term notation Boolean
expression can be written as
Y = ∏ M (0, 1, 2, 3, 4, 8, 9, 10, 11, 12)

i) Using Basic gates:

ii) Using NAND gates:

iii) Using NOR gates:

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Procedure:
1. The connections are made as shown in Circuit(by referring IC PIN diagram)
2. The input terminals are connected to the toggle switches & the output is connected to
the Output Connector (LED’s).
3. The power is applied between the VCC & Ground terminals.
4. The Logic levels are applied at the Input for all combinations indicated in Truth Table
& the Output is observed on LED’s.

Faults & Debugging:

1. Check Continuity of given Patch Chords before circuit Connection.
2. Check the working of Toggle Switch & Output LED Indicator {Initially All output
LED Indicators will be in RED (colour- Logic 1)}
3. Check IC Number for the given circuit & connect the circuit by checking pin details.
4. Check operating voltage connected to IC (+Vcc& Gnd.)
5. Apply Exact Combinations of Inputs as in Truth Table & Verify the output.

Note: Students has to Simplify, Realize any given Boolean expression in the examination.
Ex1: f(A,B,C,D) =  m (0,2,5,7,8,10,13,15)

Ans: Simplified expression in SOP form is

Simplified expression in POS form is

Ex2: f(A,B,C,D) =∏ M (0,2,5,7,8,10,13,15)

Ans: Simplified expression in SOP form is
Simplified expression in POS form is

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Experiment – 2
Half/Full Adder
Half/Full Subtractor
Aim:
a. Realization & verify the truth table of Half & Full Adder using Basic Gates/ Universal
Gates
b. Realization & verify the truth table of Half & Full Subtractor using Basic
Gates/Universal Gates

Half Adder:
A combinational circuit that performs the addition of two bits is called a half-adder. From the
verbal explanation of half-adder, we find that this circuit needs two binary inputs and two
binary outputs. The input variables designate the augend and addend bits, the o/p variables
are sum and carry. It is necessary to specify two output variables because the result may
consists’ of two binary digits. Here A, B are inputs, Sum & Carry are outputs.

Note how the same two inputs are directed to two different gates. The inputs to the XOR gate
are also the inputs to the AND gate.

Full Adder:
A combinational circuit that performs the addition of three bits (two significant bits and a
previous carry) is called a full-adder. It consists of three inputs and two outputs. Two of the
input variables are denoted by A and B, represent the two significant bits to be added. The
third input Cin represents the carry from the previous lower significant position. Two outputs
are necessary because the arithmetic sum of three binary digits ranges in the value from 0 to 3
and binary 2 or 3 needs two digits. Here the outputs are Sum and Cout.

The full-adder circuit adds three one-bit binary numbers (Cin, A, B) and outputs two one-bit
binary numbers, a sum (S) and a carry (Cout). The full-adder is usually a component in a
cascade of adders, which add 8, 16, 32, etc. binary numbers.

A full adder is made by combining two half-adders and an additional OR-gate. A full adder
has the carry in capability (denoted as Cin in the diagram) and so allows cascading which
results in the possibility of multi-bit addition. If you look closely, you'll see the full adder is
simply two half adders joined by an OR.

Components &equipments required: 74LS-00, 02, 04, 08, 32, 86. Digital IC Trainer Kit,
4mm. Patch cards etc.

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Circuit Diagram:
Realization of Half Adder using XOR & AND Gate:
Truth Table
Input Output
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Logical Expression: Sum=

Carry=

Realization of Full Adder using Two Half Adders:

Truth Table
Input Output
A B Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

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Half Subtractor:
Cleary this circuit is performing binary subtraction of B from A (A -B, recalling that in
binary 0-1 = 1 borrow 1). Such a circuit is called a half-subtractor, the reason for this is that it
enables a borrow out of the current arithmetic operation but no borrow in from a previous
arithmetic operation. The circuit has two outputs labeled Difference and Borrow

Full Subtractor:
As in the case of the addition using logic gates, a full subtractor is made by combining two
half-subtractors and an additional OR-gate. A full subtractor has the borrow in capability
(denoted as Boin in the diagram below) and so allows cascading which results in the
possibility of multi-bit subtraction.

Full subtractor is a combinational circuit that performs a subtraction of two bits, taking into
account that a 1 may have been borrowed by a lower significant stage. The circuit has 3
inputs and 2 outputs. The three inputs A, B &Boin represents the minuend, subtrahend and
previous burrow respectively. Outputs Bout and Difference represents the Borrow and the
Difference output respectively.

Circuit Diagram:
Realization of Half Subtractor using XOR, NOT & AND Gate:

Truth Table
Input Output
A B D B
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Logical Expression: Difference=

Borrow=

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Realization of Full Subtractor using Two Half Subtractors:

Truth Table
Input Output
A B Boin D Bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Half Adder Using NAND Gates

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Full Adder Using NAND Gates

Half Subtractor Using NAND Gates

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Full Subtractor Using NAND Gates

Procedure:
1. The connections are made as shown in Circuit(by referring IC PIN diagram)
2. The input terminals are connected to the toggle switches & the output is connected to
the Output Connector (LED’s).
3. The power is applied between the VCC & Ground terminals.
4. The Logic levels are applied at the Input for all combinations indicated in Truth Table
& the Output is observed on LED’s.

Faults & Debugging:

1. Check Continuity of given Patch Chords before circuit Connection.
2. Check the working of Toggle Switch & Output LED Indicator {Initially All output
LED Indicators will be in RED (colour- Logic 1)}
3. Check IC Number for the given circuit & connect the circuit by checking pin details.
4. Check operating voltage connected to IC (+Vcc& Gnd.)
5. Apply Exact Combinations of Inputs as in Truth Table & Verify the output.

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Experiment – 3
Realization of 4-Bit Parallel Adder / Subtractor
Aim: Realization of Parallel Adder/ Subtractor using IC 7483.

Parallel adder:
The 7483 IC is a 4-bit parallel adder chip. Note: the chip can also be listed as a 74LS83. The
LS signifies that the chip is a newer, lower-power, faster version. A binary parallel adder is a
digital function that produces the arithmetic sum of two binary numbers in parallel. It consists
of full adders connected in cascades with the output carry from one full adder connected to
input carry of the next full adder.

Components &equipments required: 7483, 7486 & 7404, Digital IC Trainer Kit, 4mm. Patch
cards etc.

PIN Diagram:

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Circuit Diagram:

Note: A1, A2, A3, A4 & B1, B2, B3, B4 &Cin are the Inputs.
S1, S2, S3, S4 and Cout are the Outputs.
Here A1, B1 & S1 are the LSB Bits.
S is considered as selection Input to select for Addition or Subtraction.
For Addition S=0 & For Subtraction S=1.

4 Bit Adder Operation

If control input S = 0, Addition can be performed.

Example 1: When Cin = 0.
If A4 ,A3, A2, A1 = 1 1 0 0
B4, B3, B2, B1 = 0 0 1 1

Then Sum = S4, S3, S2, S1 = 1 1 1 1

In this Case Cout = 0

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Example 2: When Cin = 0.

If A4 ,A3, A2, A1 = 1 1 0 1
B4, B3, B2, B1 = 1 0 1 1

Then Sum = S4, S3, S2, S1 = 1 0 0 0

In this Case Cout = 1

Example 3: When Cin = 1

1
If A4 ,A3, A2, A1 = 1 1 0 1
B4, B3, B2, B1 = 1 0 1 1

Then Sum = S4, S3, S2, S1 = 1 0 0 1

In this Case Cout = 1

Problems:
A := 1111 1111 1100 1100 0111
B := 0000 0000 0011 0011 1110
Cin : = 0 1 0 1 1
Sum =
(Do it yourself)

4 Bit Subtractor +Ve Result

Cout&Cin is shorted & S= 1 (Logic 1)

By normal Subtraction method

Example 1: Subtract
A4 ,A3, A2, A1 = 1 0 0 1
B4, B3, B2, B1 = 0 0 1 1 Give this from Trainer Kit

Then Difference = S4, S3, S2, S1 = 0 1 1 0

By 1’s Compliment method

I Step: B4, B3, B2, B1 = 0 0 1 1 given number

= 1 1 0 0 1’s complement of Subtrahend.

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II Step:
Adding 1’s complement of Subtrahend to the minuend
A4 ,A3, A2, A1 = 1 0 0 1 Given Larger Number
B4, B3, B2, B1 = + 1 1 0 0
= 1 0101

End around carry.

III Step:
Add end around carry to the result.
0 1 0 1 Result except carry
+ 1 Adding carry
0 1 1 0 True Result – Trainer Kit

By 2’s Compliment method

In this case, Cin& S are held at logic 1.

Example 1: Subtract
A4 ,A3, A2, A1 = 1 0 0 1
B4, B3, B2, B1 = 0 0 1 1 Give this from Trainer Kit

Then Difference = S4, S3, S2, S1 = 0 1 1 0

I Step: B4, B3, B2, B1 = 0 0 1 1 given number

=1100 1’s complement of Subtrahend.
+ 1 Adding 1 to get 2’s Complement.
= 1101 2’s omplement of subtrahend.

II Step:
A4 ,A3, A2, A1 = 1 0 0 1 Given Larger Number
B4, B3, B2, B1 = + 1 1 0 1
1 0110

Carry generated

III Step:
Neglect the carry to get true Answer
Therefore Answer = 0 1 1 0 - Trainer Kit

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4 Bit Subtractor – Ve Result

Cout&Cin is shorted & S= 1 (Logic 1)

By normal Subtraction method
Example 1: Subtract
A4 ,A3, A2, A1 = 0 0 1 1 3
B4, B3, B2, B1 = 1 0 0 1 9 Give this from Trainer Kit

Then Difference = S4, S3, S2, S1 = -6

By 1’s Compliment method

I Step: B4, B3, B2, B1 = 1 0 0 1 given number

= 0 1 1 0 1’s complement of Subtrahend.

II Step:
Adding 1’s complement of Subtrahend to the minuend
A4 ,A3, A2, A1 = 0 0 1 1 Given Larger Number
B4, B3, B2, B1 = +0 1 1 0
= 1 0 0 1 Trainer Kit Final Output

Here No End around carry.

III Step:
Here theoretically perform 1’s Compliment operation to get True Answer.
1 0 0 1 (Trainer Kit Output)
1’s Compliment
0 1 1 0 True Answer

By 2’s Compliment method

In this case, Cin & S are held at logic 1.

Example 1: Subtract
A4 ,A3, A2, A1 = 0 0 1 1 3
B4, B3, B2, B1 = 1 0 0 1 9 Give this from Trainer Kit

Then Difference = S4, S3, S2, S1 = -6

I Step: B4, B3, B2, B1 = 1 0 0 1 given number

=0110 1’s complement of Subtrahend.
+ 1 Adding 1 to get 2’s Complement.
= 0111 2’s Complement of subtrahend.

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II Step:
A4, A3, A2, A1 = 0 0 1 1 Given Larger Number
B4, B3, B2, B1 = + 0 1 1 1
1 0 1 0 Trainr Kit Final Output

Carry Not generated

III Step: Here theoretically perform 2’s Compliment operation to get True Answer.
1 0 1 0 (Trainer Kit Output)
2’s Compliment
0 1 1 0 True Answer

Problems:
A := 0110 1100 0100 0111 1111
B := 0100 0111 0110 1100 1111

Diff =
(Do it yourself)

Procedure:
1. The connections are made as shown in Circuit(by referring IC PIN diagram)
2. The input terminals are connected to the toggle switches & the output is connected to
the Output Connector (LED’s).
3. The power is applied between the VCC & Ground terminals.
4. The Logic levels are applied at the Input for all combinations indicated in Truth Table
& the Output is observed on LED’s.
5. Given problems should be worked out & get the outputs.

Faults & Debugging:

1. Check Continuity of given Patch Chords before circuit Connection.
2. Check the working of Toggle Switch & Output LED Indicator {Initially All output
LED Indicators will be in RED (colour- Logic 1)}
3. Check IC Number for the given circuit & connect the circuit by checking pin details.
4. Check operating voltage connected to IC (+Vcc& Gnd.)
5. Apply Exact Combinations of Inputs as in Truth Table & Verify the output.

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Experiment – 4
3 Bit Binary to Gray Code Conversion & Vice Versa

Aim: Realization of 3bit Binary to Gray Code conversion and Vice-Versa using Basic /
Universal gates.

Binary to Gray Code Conversion:

 Invented by Emile Baudot (1845-1903)
 Originally called a "cyclic-permuted" code.
 Telegraph -5 bit codes, Bits stored on a code wheel in the receiver Wheel connected
to the printing disk.
 Matched pattern on wheel and received pattern and then actuated head to print.
 Exhibited at Universal Exposition, Paris (1878).

Binary Codes:
The usual way of expressing a decimal number in terms of a binary number is known as pure
binary coding. A number of other techniques can be used to represent a decimal number.

Gray Code:
Gray coding is an important code and is used for its speed, it is also relatively free from
errors. In pure binary coding or 8421 BCD then counting from 7 (0 1 1 1) to 8 (1000) requires
4 bits to be changed simultaneously. If this does not happen then various numbers could be
momentarily generated during the transition so creating spurious numbers which could be
read.

Gray coding avoids this since only one bit changes between subsequent numbers. To
construct the code there are two simple rules. First start with all 0s and then proceed by
changing the least significant bit (LSB) which will bring about a new state.

Components &equipments required: IC 7486, Digital IC Trainer Kit, 4mm. Patch cards etc.

Steps for converting Binary to Gray Code:

I Step:
The MSB (most significant bit) in the gray code is same as that of corresponding bit
of the binary code.
II Step:
Then going from MSB to LSB (left to right) perform EX-OR operation on two
adjacent binary digits to obtain gray code digit.

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Truth Table for Binary to Gray Code conversion:

INPUT OUTPUT
BCD
BINARY CODE GRAY CODE
Number
B2 B1 B0 G2 G1 G0
0 0 0 0 0 0 0
1 0 0 1 0 0 1
2 0 1 0 0 1 1
3 0 1 1 0 1 0
4 1 0 0 1 1 0
5 1 0 1 1 1 1
6 1 1 0 1 0 1
7 1 1 1 1 0 0

K - Maps:

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Circuit Diagram for Binary to Gray Code Conversion:

To convert a Gray-coded number to binary then follow this method:

 The binary number and the Gray-coded number will have the same number of bits.
 The binary MSB (left-hand bit) and Gray code MSB will always be the same.
 To get the binary next-to-MSB (i.e. next digit to the right) add (EX-OR) the binary MSB and the
gray code next-to-MSB. Record the sum, ignoring any carry.
 Continue in this manner right through to the end.

Gray coding is a non-BCD, Non-weighted reflected binary code.

Truth Table for Gray to Binary Code conversion:

INPUT OUTPUT
GRAY CODE BINARY CODE

G2 G1 G0 B2 B1 B0
0 0 0 0 0 0
0 0 1 0 0 1
0 1 1 0 1 0
0 1 0 0 1 1
1 1 0 1 0 0
1 1 1 1 0 1
1 0 1 1 1 0
1 0 0 1 1 1

K - Maps:

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Circuit Diagram for Gray to Binary Code Conversion:

Procedure:
1. The connections are made as shown in Circuit(by referring IC PIN diagram)
2. The input terminals are connected to the toggle switches & the output is connected to
the Output Connector (LED’s).
3. The power is applied between the VCC & Ground terminals.
4. The Logic levels are applied at the Input for all combinations indicated in Truth Table
& the Output is observed on LED’s.

Faults & Debugging:

1. Check continuity of given patch chords before circuit connection.
2. Check the working of Toggle Switch & Output LED Indicator {Initially All output
LED Indicators will be in RED (colour- Logic 1)}
3. Check IC Number for the given circuit & connect the circuit by checking pin details.
4. Check operating voltage connected to IC (+VCC & GND)
5. Apply Exact Combinations of Inputs as in Truth Table & Verify the output

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Experiment – 5
4:1 Multiplexer / 1:4 De-multiplexer
Using Basic/universal gates

Aim: Realization of 4:1 Multiplexer and 1:4 De-multiplexer.

Multiplexer:
 Multiplexer has many data input lines and one output line.
 Multiplexer (MUX) places the data of one of its input lines on the output line.
 MUX has a set of “n” address lines to select one of 2n input line
 SOP realization is possible using MUX.

A multiplexer is a combinatorial circuit that is given a certain number (usually a power of

two) data inputs, let us say 2n, and n address inputs used as a binary number to select one of
the data inputs. The multiplexer has a single output, which has the same value as the selected
data input.

In other words, the multiplexer works like the input selector. Only one input is selected at a
time, and the selected input is transmitted to the single output.

Demultiplexer:
A demultiplexer (DEMUX) is a device which essentially performs the opposite operation to
the MUX. That is, it functions as an electronic switch (or data distributor) to route an
incoming data signal to one of several outputs.

The demultiplexer is the inverse of the multiplexer, in that it takes a single data input and n
address inputs. It has 2n outputs. Output is inverted in IC 74139 1:4 Demultiplixer.

Components &equipments required: IC 74153, 74139, 7404, 7408, 7432, 7400 & 7420.
Digital IC Trainer Kit, 4mm. Patch cards etc.
Connection Diagram MUX:

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Truth Table:
Address
Enable
Select Data Inputs Output
Inputs Comments
Inputs
S1 S0 I0 I1 I2 I3 Y
0 0
0 0 0 X X X I0 Selected
1 1
0 0
0 0 1 X X X I1 Selected
1 1
0 0
0 1 0 X X X I2 Selected
1 1
0 0
0 1 1 X X X I3 Selected
1 1
1 X X X X X X X MUX Disabled

Circuit Diagram:

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Circuit Diagram:

Connection Diagram DEMUX:

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Truth Table:

Address
Data Input Select Data Outputs
Inputs Comments
S1 S0 Y0 Y1 Y2 Y3
(Da) (Db)
0 0 0 0 0 1 1 1 Y0 Selected

0 1 1 0 1 1 Y1 Selected

1 0 1 1 0 1 Y2 Selected

1 1 1 1 1 0 Y3 Selected

Circuit Diagram:

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Procedure:
1. The connections are made as shown in Circuit(by referring IC PIN diagram)
2. The input terminals are connected to the toggle switches & the output is connected to
the Output Connector (LED’s).
3. The power is applied between the VCC & Ground terminals.
4. The Logic levels are applied at the Input for all combinations indicated in Truth Table
& the Output is observed on LED’s.
5. X in the truth table indicates Don’t care condition since depending on the selection
line the data line will be selected.

Faults & Debugging:

1. Check Continuity of given Patch Chords before circuit Connection.
2. Check the working of Toggle Switch & Output LED Indicator {Initially All output
LED Indicators will be in RED (colour- Logic 1)}
3. Check IC Number for the given circuit & connect the circuit by checking pin details.
4. Check operating voltage connected to IC (+Vcc& Gnd.)
5. Apply Exact Combinations of Inputs as in Truth Table & Verify the output.

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Experiment – 6
Arithmetic Circuit realization
(Half/Full, Adder/Subtractor) using Mux.

Realization of Half Adder Using IC 74153

Truth Table: Implementation Table:

TRUTH TABLE
Input Output
A B S C
0 0 0 0 0
1 0 1 1 0
2 1 0 1 0
3 1 1 0 1

Circuit Diagram:

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OR
Truth Table:
Input Output
A B S C
S1 S0 Ia Ib
0 0 0 0 0
1 0 1 1 0
2 1 0 1 0
3 1 1 0 1

Circuit Diagram:

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Realization of Full Adder Using IC 74153

Truth Table: Implementation Table:

Input Output
A B Cin S Cout
0 0 0 0 0 0
1 0 0 1 1 0
2 0 1 0 1 0
3 0 1 1 0 1
4 1 0 0 1 0
5 1 0 1 0 1
6 1 1 0 0 1
7 1 1 1 1 1

Circuit Diagram:

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OR

Truth Table: Implementation Table:

Input Output
A B S Cout
Cin
S1 S0 Ia Ib
0 0 0 0 0 0
cin Logic
1 0
1
0 0 1 0
2 0 1 0 1 0
cin
3 0 1 1 0 1
4 1 0 0 1 0
cin
5 1 0 1
0 1
6 1 1 0 0 1
cin Logic
7 1 1 1 1 1
1

Circuit Diagram:

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Realization of Half Subtractor Using IC 74153

Truth Table: Implementation Table:
Input Output
A B D B
0 0 0 0 0
1 0 1 1 1
2 1 0 1 0
3 1 1 0 0

Circuit Diagram:

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OR
Truth Table:
Input Output
A B D B
S1 S0 Ia Ib
0 0 0 0 0
1 0 1 1 1
2 1 0 1 0
3 1 1 0 0

Circuit Diagram:

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Realization of Full Subtractor Using IC 74153

Truth Table: Implementation Table:
TRUTH TABLE
Input Output
A B Bin D Bout
0 0 0 0 0 0
1 0 0 1 1 1
2 0 1 0 1 1
3 0 1 1 0 1
4 1 0 0 1 0
5 1 0 1 0 0
6 1 1 0 0 0
7 1 1 1 1 1

Circuit Diagram:

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OR
Truth Table: Implementation Table:
Input Output
A B Bin D Bout
0 0 0 0 0 0
Bin Bin
1 0 0 1
1 1
2 0 1 0 1 1
Logic
3 0 1 1 0 1
1
4 1 0 0 1 0
Logic
5 1 0 1 0 0
0
6 1 1 0 0 0
Bin Bin
7 1 1 1
1 1

Circuit Diagram:

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Procedure:
1. The connections are made as shown in Circuit(by referring IC PIN diagram)
2. The input terminals are connected to the toggle switches & the output is connected to
the Output Connector (LED’s).
3. The power is applied between the VCC & Ground terminals.
4. The Logic levels are applied at the Input for all combinations indicated in Truth Table
& the Output is observed on LED’s.

Faults & Debugging:

1. Check Continuity of given Patch Chords before circuit Connection.
2. Check the working of Toggle Switch & Output LED Indicator {Initially All output
LED Indicators will be in RED (colour- Logic 1)}
3. Check IC Number for the given circuit & connect the circuit by checking pin details.
4. Check operating voltage connected to IC (+Vcc& Gnd.)
5. Apply Exact Combinations of Inputs as in Truth Table & Verify the output.

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Experiment – 7
Master- Slave JK Flip-Flop

Aim: Construction and verification of JK Master-Slave, T type & D type Flip-Flops using
logic gates.

JK Flip-Flop: One way of overcoming the problem with oscillation that occurs with a JK
Flip-Flop when J= K = 1 is to use a so-called master-slave flip- flop which is illustrated in the
circuit diagram.

The master-slave flip-flop is essentially two back-to-back JKFFs, note however, that
feedback from this device is fed back both to the master FF and the slave FF.

Any input to the master-slave flip-flop at J and K is first seen by the master FF part of the
circuit while CLK is High (= 1). This behaviour effectively "locks" the input into the master
FF. An important feature here is that the complement of the CLK pulse is fed to the slave FF.
Therefore the outputs from the master FF are only "seen" by the slave FF when CLK is Low
(=0). Therefore on the High-to-Low CLK transition the outputs of the master are fed through
the slave FF. This means that at most one change of state can occur when J=K = 1 and so
oscillation between the states Q=O and Q= 1 during the same CLK pulse does not occur.

Components &equipments required: IC 7400, & 7410. Digital IC Trainer Kit, 4mm. Patch
cards etc.

Circuit Diagram:

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Truth Table:

Inputs Outputs
CL Comments
J K Qn n
K
0 0 X X X 1 1 Indeterminate State

0 1 X X X 1 0 FF Preset(Set)

1 0 X X X 0 1 FF Cleared(Reset)

1 1 0 0 X Q n-1 n-1 Previous

1 1 0 1 0 1 Reset

1 1 1 0 1 0 Set

1 1 1 1 n-1 Q n-1 Toggle

Note:
Keep = 1 and =1 for verifying the Truth Table of JK Master-
Slave FF & T FF.
Q n is Output level before giving Clock pulse.

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Circuit Diagram:

Truth Table:
Inputs Outputs
Comments
T CLK Qn n
0 0 X X 1 1 Indeterminate State
0 1 X X 1 0 FF Preset(Set)
1 0 X X 0 1 FF Cleared(Reset)
1 1 0 X Q n-1 n-1 Previous
1 1 1 n-1 Q n-1 Toggle

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Circuit Diagram:

Truth Table:

Inputs Outputs
Comments
D CLK Qn n
0 0 X X 1 1 Indeterminate State
0 1 X X 1 0 FF Preset(Set)
1 0 X X 0 1 FF Cleared(Reset)
1 1 0 0 1 Data transferred
1 1 1 1 0 Data transferred

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Circuit Diagram:

Procedure:
1. The connections are made as shown in Circuit(by referring IC PIN diagram)
2. The input terminals (JK, T & D) are connected to the toggle switches & the output is
connected to the Output Connector (LED’s).
3. The power is applied between the VCC & Ground terminals.
4. Connect clock pin to the bounce less pulsar HIGH or LOW
5. The Logic levels are applied at the Inputs as indicated in Truth Table & the Output is
observed on LED’s.
6. X in the truth table indicates Don’t Care condition.

Faults & Debugging:

1. Check Continuity of given Patch Chords before circuit Connection.
2. Check the working of Toggle Switch & Output LED Indicator {Initially All output
LED Indicators will be in RED (colour- Logic 1)}
3. Check IC Number for the given circuit & connect the circuit by checking pin details.
4. Check operating voltage connected to IC (+Vcc& Gnd.)
5. To check outputs apply Clock correctly as specified in Procedure.
6. Apply Exact Combinations of Inputs as in Truth Table & Verify the output.

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Experiment -8
3 Bit ripple up/down Counters
Aim: Construction and realization of 3 bit ripple up/down counter using IC 7476 and other
logic gates.

Counters: The synchronous design of any sequential circuit application for example counter
is a design in which all the flip-flops are connected to a common clock input that is, all the
flip-flops are clocked simultaneously. Therefore to get the next state of application actual
inputs of the flip-flop should be designed according to the requirement.

Hence excitation tables are used to design the actual inputs of the flip-flops to get the next
stage. The excitation table gives the combination of input for the required output condition
before and after the application of clock.

Components &equipments required: IC 7476, 7400, 7404, 7408 & 7410. Digital IC Trainer
Kit, 4mm. Patch cards etc.

Circuit Diagram:

Note:
 J & K inputs of Flip-Flops are connected to logic 1 or Keep it open to operate under
toggle mode.
 When Preset = 1, Clear = 0; Counter is cleared Q0 = Q1 = Q2 = 0
 When Preset = 0, Clear = 1; Counter is preset Q0 = Q1 = Q2 = 1
 Keep Preset = 1, Clear = 1 for count mode.

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Truth Table:
No. of Flip-Flop
Clock Outputs
Pulses Q2 Q1 Q0
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8 0 0 0

Circuit Diagram:

Truth Table:
No. of Flip-Flop
Clock Outputs
Pulses Q2 Q1 Q0
0 1 1 1
1 1 1 0
2 1 0 1
3 1 0 0
4 0 1 1
5 0 1 0
6 0 0 1
7 0 0 0
8 1 1 1

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Circuit Diagram:

Truth Table:
No. of Flip-Flop
Clock Outputs
Pulses Q2 Q1 Q0
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 0 0 0

Circuit Diagram:

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Note:
 When Mode control is at logic 1 counter works as an Up-counter.
 When Mode control is at logic 0 counter works as a Down-counter.

Design and verification of mod-n, 3bit synchronous counter using 7476 JK, T & D flip flops.

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Experiment –9
Design of JK flip-flop 3 Bit Synchronous Counters

Aim: Design and verification of 3-bit Synchronous counter using IC7476.

Synchronous Counters:
In the previous Asynchronous binary counter tutorial, we saw that the output of one counter
stage is connected directly to the clock input of the next counter stage and so on along the
chain.
The result of this is that the Asynchronous counter suffers from what is known as
“Propagation Delay” in which the timing signal is delayed a fraction through each flip-flop.
However, with the Synchronous Counter, the external clock signal is connected to the clock
input of EVERY individual flip-flop within the counter so that all of the flip-flops are
clocked together simultaneously (in parallel) at the same time giving a fixed time
relationship. In other words, changes in the output occur in “synchronisation” with the clock
signal.
The result of this synchronisation is that all the individual output bits changing state at
exactly the same time in response to the common clock signal with no ripple effect and
therefore, no propagation delay.

Synchronous Counter Summary:

Then to summarise some of the main points about Synchronous Counters:
 Synchronous Counters can be made from Toggle or D-type flip-flops.
 Synchronous counters are easier to design than asynchronous counters.
 They are called synchronous counters because the clock input of the flip-flops
are all clocked together at the same time with the same clock signal.
 Due to this common clock pulse all output states switch or change simultaneously.
 With all clock inputs wired together there is no inherent propagation delay.
 Synchronous counters are sometimes called parallel counters as the clock is fed in
parallel to all flip-flops.
 The inherent memory circuit keeps track of the counters present state.
 The count sequence is controlled using logic gates.
 Overall faster operation may be achieved compared to Asynchronous counters.

Components &equipments required: IC 7476, 7400, 7404, & 7408. Digital IC Trainer Kit,
4mm. Patch cards etc.

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Excitation Tables:

Q (n) Q (n+1) J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

PS NS Flip-Flop Inputs
Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0
0 0 0 0 0 0 1 0 X 0 X 1 X
1 0 0 1 0 1 0 0 X 1 X X 1
2 0 1 0 0 1 1 0 X X 0 1 X
3 0 1 1 1 0 0 1 X X 1 X 1
4 1 0 0 1 0 1 X 0 0 X 1 X
5 1 0 1 1 1 0 X 0 1 X X 1
6 1 1 0 1 1 1 X 0 X 0 1 X
7 1 1 1 0 0 0 X 1 X 1 X 1

Circuit Diagram:

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Truth Table:

No. of Flip-Flop
Clock Outputs
Pulses Q2 Q1 Q0
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8 0 0 0

K-Maps:

Circuit Diagram:

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Note:
 Carryout the design similarly

Assignment:
 Design of T flip-flop 3 Bit Synchronous Counters
 Design of D flip-flop 3 Bit Synchronous Counters

Procedure:
 The connections are made as shown in Circuit(by referring IC PIN diagram)
 The input terminals are connected to the toggle switches & the output is connected to
the Output Connector (LED’s).
 The power is applied between the VCC & Ground terminals.
 Connect clock pin to the bounce less pulsar LOW.
 The clock input is applied as indicated in Truth Table & the Output is observed on
LED’s.
 X in the truth table indicates irrelevant care condition.

Faults & Debugging:

 Check Continuity of given Patch Chords before circuit Connection.
 Check the working of Toggle Switch & Output LED Indicator {Initially All output
LED Indicators will be in RED (colour- Logic 1)}
 Check IC Number for the given circuit & connect the circuit by checking pin details.
 Check operating voltage connected to IC (+Vcc& Gnd.)
 To check outputs apply Clock correctly as specified in Procedure.
 Apply Exact Combinations of Inputs as in Truth Table & Verify the output.

Assignment:
Design and verification of random sequence counter, 3bit synchronous counter using
7476 JK, T & D flip flops.

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Experiment – 10
SHIFT REGISTERS
Aim: Realization of shift register and Sequence Generator.
 Shift Right Operation (SIPO, SISO, PIPO, PISO).
 Shift Left Operation.

Shift Registers: The 7495 is a 4-Bit Shift Register with serial and parallel synchronous
operating modes. It has a Serial (DS) and four Parallel (D0-D3) Data inputs and four Parallel
Data outputs (Q0 –Q3). The serial or parallel mode of operation is controlled by a Mode
Control input and two Clock Inputs (CLK1) and (CLK2). The serial (right-shift) or parallel
data transfers occur synchronous with the HIGH to LOW transition of the selected clock
input.

When the Mode Control input is HIGH, CLK2 is enabled. A HIGH to LOW transition on
enabled CLK2 transfers parallel data from D0-D3 the inputs to the Q0 –Q3 outputs. When the
Mode Control input is LOW, CLK1 is enabled. A HIGH to LOW transition on enabled CLK1
transfers the data from Serial input (DS) shifts the data to Q3 to Q2 to Q1 to Q0 output
respectively (right-shift). A left -shift is accomplished by externally connecting Qo to D1, Q1
to D2, and Q2 to D3, and operating the 7495 in the parallel mode (Mode Control input =
HIGH).

Components &equipments required: IC 7495, Digital IC Trainer Kit, 4mm. Patch cards
etc.

Circuit Diagram:

Note:
Ds: Serial input data (to be right shifted)

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D3 D2 D1 &Do : Parallel data inputs.

M: Mode Control
Keep M = 1 for loading parallel data and enable clock 2.
M = 0 for enabling clock 1.
Clock 1: For the operation of shift right of data,
Clock 2: For loading Parallel input data.
Q3 Q2 Q1 & Q0: Parallel outputs of the shift register.

Shift Right Operation

i) Serial Input Parallel Output Operation (SIPO)

To perform SIPO operation consider a 4 Bit data Say 0 1 0 1.

Following steps are used here:
 Mode control is made 0.
 Clock 1 (PIN No. 9) of IC 7495 is connected to the Clock Pulse.
 A serial input to be converted to Parallel Output is given to serial input Ds (PIN No.
1) of IC 7495.
 After 4 Clock pulses, the serial input data appears in parallel form as: Q3 Q2 Q1 &
Q0.

ii) Serial Input Serial Output Operation (SISO)

To perform SISO operation consider a 4 Bit data Say 0 1 0 1.

Following steps are used here:
Mode control is made 0.
 Clock 1 (PIN No. 9) of IC 7495 is connected to the Clock Pulse.
 A serial input to be converted to Parallel Output is given to serial input Ds (PIN No.
1) of IC 7495.
 After 4 Clock pulses, the serial input data appears in parallel form as: Q3 Q2 Q1 &
Q0.
 The next 3 Clock Pulses move the data out of the shift register serially at Q0 output as
shown in Truth Table.

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Truth Table:
SIPO & SISO

iii) Parallel Input Parallel Output Operation (PIPO)

To perform PIPO operation consider a 4 Bit data Say 0 1 0 1.

Following steps are used here:
 Mode control is made 1.
 Clock 2 (PIN No. 8) of IC 7495 is connected to the Clock Pulse.
 The Parallel Input to be loaded into shift register are given to D3 D2 D1 & D0 inputs
of IC 7495.
 Now D3 D2 D1 & D0 Parallel inputs appear on Q3 Q2 Q1 & Q0 as shown in Truth
table.

iv) Parallel Input Serial Output Operation (PISO)

To perform PISO operation consider a 4 Bit data Say 0 1 0 1.

Following steps are used here:
 Mode control is made 1.
 Clock 2 (PIN No. 8) of IC 7495 is connected & the Clock Pulse is applied.
 The Parallel Input to be loaded into shift register are given to D3 D2 D1 & D0 inputs
of IC 7495.
 Now D3 D2 D1 & D0 Parallel inputs appears on Q3 Q2 Q1 & Q0 as shown in Truth
table.
 Mode control is made 0
 Then Clock 1 (PIN No. 9) of IC 7495 is connected to the Clock Pulse
 The next 3 Clock Pulses move the data out of the shift register serially at Q0 output as
shown in Truth Table.

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Truth Table:

Shift Left Operation

To perform Shift Left operation consider a 4 Bit data Say 0 1 0 1.

Following steps are used here:
 Short output Q0 & D1, Output Q1 & D2, And Output Q2 & D3
Note: After shorting above mentioned terminals, Don’t give any input for D1, D2 & D3.
 Mode control is made 1.
 Serial Input data is entered at D0 (IC PIN No. 5) input.
 Clock 2 (PIN No. 8): Apply 4 Clock pulse & observe the output according to Truth
table.

Truth Table:

Outputs Shift Left

Mode
Clock Data Input Pulse
Control Q3 Q2 Q1 Q0 (D0)
1 Clock-2 1 1 (LSB) 1
1 0 0 2
1 0 1 1 3
1 0 1 0 0 4

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Challenge experiments:

1. Design a digital circuit to turn on and turn off the bulb with respect to ambient light
availability.

2. Design a digital circuit to generate 10 clock pulses upon receiving the control signal.

3. Design a digital circuit for 4 bit barrel shifter.

4. Design a digital circuit to perform 2bit* 2bit multiplier.

5. Design a digital circuit to perform 2bit comparator.

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Frequently Asked Viva Questions

1. Why NAND & NOR gates are called universal gates?
2. Realize the EX – OR gates using minimum number of NAND gates.
3. Give the truth table for EX-NOR and realize using NAND gates?
4. What are the logic low and High levels of TTL IC’s and CMOS IC’s?
5. Compare TTL logic family with CMOS family?
6. Which logic family is fastest and which has low power dissipation?
7. What are the different methods to obtain minimal expression?
8. What is a Min term and Max term
9. State the difference between SOP and POS.
10. What is meant by canonical representation?
11. What is K-map? Why is it used?
12. What are universal gates?
13. What is a half adder?
14. What is a full adder?
15. What are the applications of adders?
16. What is a half subtractor?
17. What is a full subtractor?
18. What are the applications of subtractors?
19. Realize a full adder using two half adders
20. Realize a full subtractors using two half subtractors
21. What is the internal structure of 7483 IC?
22. What do you mean by code conversion?
23. What are the applications of code conversion?
24. How do you realize a subtractor using full adder?
25. What is a ripple Adder? What are its disadvantages?
26. What are code converters?
27. What is the necessity of code conversions?
28. What is gray code?
29. What is a multiplexer?
30. What is a de-multiplexer?
31. What are the applications of multiplexer and de-multiplexer?
32. What is the difference between multiplexer &demultiplexer?
33. In 2n to 1 multiplexer how many selection lines are there?
34. What is a comparator?
35. What are the applications of comparator?
36. How do you realize a higher magnitude comparator using lower bit comparator
37. Design a 2 bit comparator using a single Logic gates?
38. Design an 8 bit comparator using a two numbers of IC 7485?
39. What are the applications of decoder?
40. What is the difference between decoder & encoder?
41. For n- 2n decoder how many i/p lines & how many o/p lines are there?
42. What are the different codes & their applications?

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43. What are code converters?

44. What is the difference between decoder and de-mux?
45. What is a priority encoder?
46. What is the role of an encoder in communication?
47. What is the advantage of using an encoder?
48. What is the difference between Flip-Flop & latch?
49. What is the advantage of Edge triggering over level triggering?
50. What is the relation between propagation delay & clock frequency of flip-flop?
51. What is race around in flip-flop & how to overcome it?
52. Convert the J K Flip-Flop into D flip-flop and T flip-flop?
53. What is the necessity for sequence generation?
54. What are PISO, SIPO, and SISO with respect to shift register?
55. Differentiate between serial data & parallel data
56. What is the significance of Mode control bit?
57. What is a ring counter?
58. What is a Johnson counter?
59. How many Flip-flops are present in IC 7495?
60. What is an asynchronous counter?
61. How is it different from a synchronous counter?
62. Realize asynchronous counter using T flip-flop
63. What are synchronous counters?
64. What are the advantages of synchronous counters?
65. What is an excitation table?
66. Write the excitation table for D & T FF
67. Design mod-5 synchronous counter using T FF
68. What is a presettable counter?
69. What are the applications of presettable counters?
70. Explain the working of IC 74193
71. What is a decade counter?
72. What do you mean by a ripple counter?
73. Explain the design of Modulo-N counter (N _ 9) using IC 7490

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DIGITAL IC’s PIN DETAILS

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Sec / Batch : …………….. Date :………………….. Sec / Batch : …………….. Date :…………………..
Name USN Name USN

Experiment: Table No. …………… Experiment: Table No. ……………

Sl. Component Range Qty Sl. Component Range Qty
No. No.
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
10 10
Signature of Faculty Signature of Faculty

Sec / Batch : …………….. Date :………………….. Sec / Batch : …………….. Date :…………………..
Name USN Name USN

Experiment: Table No. …………… Experiment: Table No. ……………

Sl. Component Range Qty Sl. Component Range Qty
No. No.
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
10 10
Signature of Faculty Signature of Faculty

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Sec / Batch : …………….. Date :………………….. Sec / Batch : …………….. Date :…………………..
Name USN Name USN

Experiment: Table No. …………… Experiment: Table No. ……………

Sl. Component Range Qty Sl. Component Range Qty
No. No.
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
10 10
Signature of Faculty Signature of Faculty

Sec / Batch : …………….. Date :………………….. Sec / Batch : …………….. Date :…………………..
Name USN Name USN

Experiment: Table No. …………… Experiment: Table No. ……………

Sl. Component Range Qty Sl. Component Range Qty
No. No.
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
10 10
Signature of Faculty Signature of Faculty

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Sec / Batch : …………….. Date :………………….. Sec / Batch : …………….. Date :…………………..
Name USN Name USN

Experiment: Table No. …………… Experiment: Table No. ……………

Sl. Component Range Qty Sl. Component Range Qty
No. No.
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
10 10
Signature of Faculty Signature of Faculty

Sec / Batch : …………….. Date :………………….. Sec / Batch : …………….. Date :…………………..
Name USN Name USN

Experiment: Table No. …………… Experiment: Table No. ……………

Sl. Component Range Qty Sl. Component Range Qty
No. No.
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
10 10
Signature of Faculty Signature of Faculty

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