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OPA462
SBOS803A – DECEMBER 2018 – REVISED DECEMBER 2019
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
OPA462 HSOIC (8) 4.89 mm × 3.90 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
125
±IN
100
75
Differential Voltage High Current
Output Stage
OUT 50
Amplifier Amplifier
25
Biasing 0
+IN 1 10 100 1k 10k 100k 1M 10M
Current Limiting
Enable/Disable Frequency (Hz)
Status
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA462
SBOS803A – DECEMBER 2018 – REVISED DECEMBER 2019 www.ti.com
Table of Contents
1 Features .................................................................. 1 7.4 Device Functional Modes........................................ 20
2 Applications ........................................................... 1 8 Application and Implementation ........................ 21
3 Description ............................................................. 1 8.1 Application Information............................................ 21
4 Revision History..................................................... 2 8.2 Typical Applications ................................................ 21
5 Pin Configuration and Functions ......................... 3 9 Power Supply Recommendations...................... 27
6 Specifications......................................................... 4 10 Layout................................................................... 27
6.1 Absolute Maximum Ratings ...................................... 4 10.1 Layout Guidelines ................................................. 27
6.2 ESD Ratings ............................................................ 4 10.2 Layout Example .................................................... 30
6.3 Recommended Operating Conditions....................... 4 11 Device and Documentation Support ................. 31
6.4 Thermal Information .................................................. 4 11.1 Device Support .................................................... 31
6.5 Electrical Characteristics........................................... 5 11.2 Documentation Support ....................................... 31
6.6 Typical Characteristics: Table of Graphs .................. 7 11.3 Support Resources ............................................... 32
6.7 Typical Characteristics .............................................. 9 11.4 Trademarks ........................................................... 32
7 Detailed Description ............................................ 19 11.5 Electrostatic Discharge Caution ............................ 32
7.1 Overview ................................................................. 19 11.6 Glossary ................................................................ 32
7.2 Functional Block Diagram ....................................... 19 12 Mechanical, Packaging, and Orderable
7.3 Feature Description................................................. 19 Information ........................................................... 32
4 Revision History
Changes from Original (December 2018) to Revision A Page
• Changed OPA462 from advanced information (preview) to production data (active) ............................................................ 1
DDA PACKAGE
8-Pin SO PowerPAD™
Top View
±IN 2 7 V+
PowerPAD
+IN 3 6 OUT
V± 4 5 Status Flag
Not to scale
Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
E/D 8 I Enable or disable
E/D Com 1 I Enable and disable common
–IN 2 I Inverting input
+IN 3 I Noninverting input
OUT 6 O Output
Status Flag is an open-drain active-low output referenced to E/D Com. This pin
Status Flag 5 O
goes active for either an overcurrent or overtemperature condition.
V– 4 — Negative (lowest) power supply
V+ 7 — Positive (highest) power supply
The PowerPAD is internally connected to V–. The PowerPAD must be soldered
PowerPAD PowerPAD — to a printed-circuit board (PCB) connected to V–, even with applications that
have low power dissipation.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VS Supply voltage 190 V
+IN, –IN Signal input pins (2) (V–) – 0.3 (V+) + 0.3 V
E/D to E/D Com 7 V
All input pins (2) ±10 mA
Output short circuit (3) Continuous Continuous
TA Operating –55 125 °C
TJ Junction 150 °C
TSTG Storage –55 125 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input terminals, Status Flag, E/D, and E/D Com, and Output are diode-clamped to the power-supply rails. Input signals that can swing
more than 0.3 V beyond the supply rails must be current-limited to 10 mA or less.
(3) Short-circuit to ground.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
20 20
16 16
Amplifiers (%)
Amplifiers (%)
12 12
8 8
4 4
0 0
-4 -3.2 -2.4 -1.6 -0.8 0 0.8 1.6 2.4 3.2 4 -5 -4 -3 -2 -1 0 1 2 3 4 5
Offset Voltage (mV) Offset Voltage (mV)
Figure 1. Offset Voltage Production Distribution at 25°C Figure 2. Offset Voltage Distribution at 85°C
20 30
25
16
20
Amplifiers (%)
Amplifiers (%)
12
15
8
10
4
5
0 0
-5 -4 -3 -2 -1 0 1 2 3 4 5 -20 -16 -12 -8 -4 0 4 8 12 16 20
Offset Voltage (mV) Offset Voltage Drift (PV/qC)
Figure 3. Offset Voltage Distribution at –40°C Figure 4. Offset Voltage Drift Distribution from –40°C to
+85°C
4 500
3 400
300
2
Offset Voltage (mV)
200
Offset Voltage (PV)
1 100
0 0
-100
-1
-200
-2
-300
-3 -400
-4 -500
-50 -25 0 25 50 75 100 100s/div
Temperature (qC)
1 1
0 0
-1 -1
-2 -2
TA = -40
-3 -3 TA = 25
TA = 85
-4 -4
-90 -89.5 -89 -88.5 -88 -87.5 -87 -86.5 -86 -85.5 -85 85 86 87 88 89 90
Common-mode Voltage (V) Common-mode Voltage (V)
Figure 7. Offset Voltage vs Common-Mode Voltage Figure 8. Offset Voltage vs Common-Mode Voltage
(Low VCM) (High VCM)
4 4
3 3
2 2
Offset Voltage (mV)
1 1
0 0
-1 -1
-2 -2
-3 -3
-4 -4
3 5 7 9 11 13 15 6 18 30 42 54 66 78 90
Power Supply Voltage (V) Power Supply Voltage (V)
Figure 9. Offset Voltage vs Power Supply (Low Supply) Figure 10. Offset Voltage vs Power Supply (High Supply)
4 5
TA = -40, RL = 5k:
3 4 TA = -40, RL = 10k:
TA = 25, RL = 5k:
2 3 TA = 25, RL = 10k:
Offset Voltage (mV)
Offset Voltage (mV)
TA = 85, RL = 5k:
1 2 TA = 85, RL = 10k:
0 1
-1 0
-2 TA = -40, RL = 5k: -1
TA = -40, RL = 10k:
-3 TA = 25, RL = 5k: -2
TA = 25, RL = 10k:
-4 TA = 85, RL = 5k: -3
TA = 85, RL = 10k:
-5 -4
-90 -88 -86 -84 -82 -80 80 82 84 86 88 90
Output Voltage (V) Output Voltage (V)
Figure 11. Offset Voltage vs Output Voltage (Low Output) Figure 12. Offset Voltage vs Output Voltage (High Output)
130 80
60
120 1
40
110
20
100 10 0
-50 -25 0 25 50 75 100 1 10 100 1k 10k 100k 1M 10M
Temperature (qC) Frequency (Hz)
150 120
100
140 0.1 Rejection Ratio (dB)
80
130
60
120 1
40
110 20
100 10 0
-50 -25 0 25 50 75 100 10m 100m 1 10 100 1k 10k 100k 1M 10M
Temperature (qC) Frequency (Hz)
100
Voltage (25V/div)
EMIRR IN+ (dB)
90
80
70
60
50
10M 100M 1G 10G Time (100 Ps/div)
Frequency (Hz)
50 400
300
40
200
30 100
20 0
-100
10
-200
0 -300
-100 -80 -60 -40 -20 0 20 40 60 80 100 -50 -25 0 25 50 75 100
Input Bias Current (pA) Temperature (qC)
Figure 19. Input Bias Current Production Distribution at Figure 20. IB vs Temperature
℃
25℃
30
IB-
IB+
20 Ios
Input Bias Current (pA)
Voltage (2 V/div)
10
-10
Enable
Output
-20 Status
-90 -60 -30 0 30 60 90
Common-mode Voltage (V) Time (2 Ps/div)
4 20
Status Flag (V)
130
3 0 120 1
110
2 -20
100 10
1 -40
90 RL = 10k:
RL = 5k:
0 -60 80 100
Time (200 Ps/div) -50 -25 0 25 50 75 100
Temperature (qC)
Figure 23. Current Limit Response Figure 24. Open-Loop Gain vs Temperature
80 125
Gain (dB)
Phase (q)
120 1 60 100
TA = -40qC, RL = 10k: 40 75
TA = -40qC, RL = 5k:
100 TA = 25qC, RL = 10k: 10 20 50
TA = 25qC, RL = 5k:
TA = 85qC, RL = 10k: 0 25
TA = 85qC, RL = 5k:
80 100 -20 0
0 1 2 3 4 5 6 7 8 9 10 10m 100m 1 10 100 1k 10k 100k 1M 10M
Swing from Rail (V) Frequency (Hz)
Figure 25. Open-Loop Gain vs Output Voltage Figure 26. Open-Loop Gain and Phase vs Frequency
10000 30
G= 1
G= 1
20 G= 10
1000
10
Gain (dB)
Zo (:
0
100
-10
10 -20
1 10 100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M
Frequency (Hz) Frequency (Hz)
Figure 27. Open-Loop Output Impedance vs Frequency Figure 28. Closed-Loop Gain vs Frequency
200 100
Vs=r90 V
175 Vs=r50 V
Vs=r6 V 80
150
Output Voltage (VPP)
125 60
100
75 40
50
20 TA = -40qC
25 TA = 25qC
TA = 85qC
0 0
1 10 100 1k 10k 100k 1M 10M 0 10 20 30 40 50
Frequency (Hz) Output Current (mA)
Figure 29. Maximum Output Voltage vs Frequency Figure 30. Positive Output Voltage vs Output Current
50
-40
-60
40
-80
Sinking
Sourcing
-100 30
0 10 20 30 40 50 -50 -25 0 25 50 75 100
Output Current (mA) Temperature (qC)
Figure 31. Negative Output Voltage vs Output Current Figure 32. Short-Circuit Current vs Temperature
VIN
VOUT
Voltage (20 V/div)
VIN
VOUT
Figure 33. Negative Overload Recovery Figure 34. Positive Overload Recovery
60
Rising
Output Delta to Final Value (12 m/div)
Falling
50
Phase Margin (q)
40
30
20
10
Time (2 Ps/div) 10 100 1000
Cload (pF)
Figure 35. Settling Time Figure 36. Phase Margin vs Capacitive Load
Overshoot ( )
40 40
20 20
0 0
10 100 1000 10 100 1000
Capactiance (pF) Capactiance (pF)
G = –1 G = +1
Figure 37. Small-Signal Overshoot vs Capacitive Load Figure 38. Small-Signal Overshoot vs Capacitive Load
VIN VIN
VOUT VOUT
Voltage (5 mV/div)
Voltage (5 mV/div)
Figure 39. Small-Signal Step Response Figure 40. Small-Signal Step Response
Figure 41. Large-Signal Step Response Figure 42. Large-Signal Step Response
Figure 43. Slew Rate vs Output Step Size Figure 44. Slew Rate vs Supply Voltage (Inverting)
40 0.1 -60
Noise (dB)
VOUT = 1V G= 1. 10k: Load
Noise ( )
VOUT = 5V G= 1. 5k: Load
VOUT = 10V G= 1. 10k: Load
30 VOUT = 20V G= 1. 5k: Load
VOUT ! 40V
Slew Rate (V/Ps)
0.01 -80
20
0.001 -100
10
0 0.0001 -120
40 60 80 100 120 140 160 180 20 200 2k 20k
Supplpy Voltage (V) Frequency (Hz)
G = 10
Figure 45. Slew Rate vs Supply Voltage (Noninverting) Figure 46. THD+N Ratio vs Frequency
0.1 -60 1 -40
Noise (dB)
0.01 -80
0.001 -100
0.001 -100
Figure 47. THD+N Ratio vs Frequency Figure 48. THD+N Ratio vs Output Amplitude
G= 1, 5k: Load
G= 1, 10k: Load
0.1 G= 1, 5k: Load -60
Total Harmonic Distortion
0.01 -80
0.001 -100
0.0001 -120
100m 1 10 100 Time (1 s/div)
Output Amplitude (VPP)
G = 20
Figure 49. THD+N Ratio vs Output Amplitude Figure 50. 0.1-Hz to 10-Hz Noise
1000 10
Voltage Noise Spectral Density (nV —Hz)
100
0.1
10 0.01
1 10 100 1k 10k 100k 1 10 100 1k 10k 100k 1M 10M
Frequency (Hz) Frequency (Hz)
Figure 51. Input Voltage Noise Spectral Density Figure 52. Current Noise Density
60 4
Quiescient Current (mA)
45 3
Amplifiers (%)
30 2
15 1
0 0
2 2.25 2.5 2.75 3 3.25 3.5 3.75 4 0 20 40 60 80 90
Quiescent Current (mA) Supply Voltage (V)
Figure 53. Quiescent Current Production Distribution at Figure 54. Quiescent Current vs Supply Voltage
℃
25℃
0.8
Quiescent Current (mA)
3.5
VFLAG to V- (V)
0.6
3
0.4
2.5
0.2
Vs = 6V E/D Com = -90V
Vs = 90V E/D Com = 0V
2 0
-50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100
Temperature (qC) Temperature (qC)
Figure 55. Quiescent Current vs Temperature Figure 56. Status Flag Voltage vs Temperature
4 100
E/D Com Current
80 E/D Current
3.5
60
Quiescent Current (mA)
TA = -40qC -60
1.5
TA = 25qC -80
TA = 85qC
1 -100
0 1 2 3 4 5 0 1 2 3 4 5
Enable Voltage (V) Enable Voltage (V)
Figure 57. Quiescent Current vs Enable Voltage Figure 58. Enable Current vs Enable Voltage
15
Status Flag Current (mA)
10
TA=-40qC
TA=25qC
TA=85qC
0
0 1 2 3 4 5
Status Flag Voltage - ED COM (V)
7 Detailed Description
7.1 Overview
The OPA462 is an operational amplifier (op amp) with high voltage of 180 V, and a high current drive of 30 mA.
This device is unity-gain stable and features a gain-bandwidth product of 6.5 MHz. The high-voltage OPA462
offers excellent accuracy and wide output swing, and has no phase inversion problems that are typically found in
similar op amps. The device can be applied in many common op amp configurations requiring a supply voltage
range from ±6-V to ±90-V.
The OPA462 features an enable-disable function that provides the ability to turn off the output stage and reduce
power consumption when not being used. The device also features a Status Flag pin that indicates an
overtemperature or overcurrent fault conditions.
V+
±IN
Biasing
+IN
Current Limiting
Enable/Disable
Status
IP
RP
DVDD
(Digital Supply)
V+
-IN E/D 5V Logic
VOUT
+IN E/D Com
V-
V-
(Negative Op Amp Supply)
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
90 V
100 nF
Z1 Status
Flag 90 V
3 V to 5 V
+
±
D1
± E/D VO
85 VPK
+ E/D Com RL
VI D2 10 k
5 VPK R3 100 nF 1W
10 k Z2
±90 V
D1, D2 = 1N5271B zener, PSMA100A TVS, etc.
Z1, Z2 = 1N4935, ES3A, etc. Fast rectifier.
±90 V
where
• SR = 6.5 × 106 V/s
• VPK = 85 V (3)
The best practice for a typical parameter such as slew rate to allow for variance. In this example, keeping the
large signal fMAX to 10 kHz is sufficient to make sure the output avoids slew rate limiting.
Figure 62. OPA462 Large-Signal Output With a 10-kHz Sine Input From a TINA-TI Simulation
8.2.2 Improved Howland Current Pump for Bioimpedance Measurements in Multiparameter Patient
Monitors
R14 R15
100 k 100 k
0V
90 V
100 nF Vo1
R13
R11 ± 125
100 k Vout
+
VP 100 nF AM1
2.5 Vpk
±90 V RL
500
R12
99.88 k
Figure 64. Output Voltage Compliance for an Improved Howland Current Pump
90 V
100 nF Vo1
R13
R11 ± 125
100 k Vout
VP +
100 nF AM1
400 Hz
2.5 Vpk RL
±90 V
1k
R12
99.88 k
A 2.5-Vpk sine-wave source applied to the input point at R11 results in a 20-mA peak current through the load, as
shown in Figure 66. The load has been set to 1 kΩ, but any resistance that supports the output compliance
range can be used.
Figure 66. Improved Howland Current Pump Applied as a Peak AC-Current Generator
10 Layout
NOTE
The SO-8 PowerPAD is pin-compatible with standard SO-8 packages, and as such, the
OPA462 is a drop-in replacement for operational amplifiers in existing sockets. Always
solder the PowerPAD to the PCB V– plane, even with applications that have low power
dissipation. Solder the device to the PCB to provide the necessary thermal, mechanical,
and electrical connections between the leadframe die pad and the PCB.
40
30
20
10
0
0 0.5 1.0 1.5 2.0 2.5 3.0
2
Copper Area (inches ), 2 oz
E/D COM
Typically V± or GND E/D GND
±IN ±IN V+ V+
3RZHU3$'Œ
(must connect to
V± or GND)
V± V± Status Flag
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
11.4 Trademarks
PowerPAD, TINA-TI, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 10-Dec-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
OPA462IDDA ACTIVE SO PowerPAD DDA 8 75 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 85 OPA462
OPA462IDDAR ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 85 OPA462
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
TUBE
Pack Materials-Page 3
GENERIC PACKAGE VIEW
DDA 8 PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4202561/G
PACKAGE OUTLINE
DDA0008J SCALE 2.400
PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
C
6.2
TYP SEATING PLANE
5.8
A PIN 1 ID
AREA 0.1 C
6X 1.27
8
1
5.0 2X
4.8 3.81
NOTE 3
4
5
0.51
8X
4.0 0.31
B 1.7 MAX
3.8 0.1 C A B
NOTE 4
0.25
TYP
0.10
SEE DETAIL A
4 5
EXPOSED
THERMAL PAD
3.1 0.25
2.5 GAGE PLANE
0.15
0 -8 1.27 0.00
1 8
0.40
DETAIL A
2.6 TYPICAL
2.0
4221637/B 03/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012, variation BA.
www.ti.com
EXAMPLE BOARD LAYOUT
DDA0008J PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.95)
NOTE 9
SOLDER MASK
(2.6) DEFINED PAD
SOLDER MASK
OPENING
8X (1.55) SEE DETAILS
1
8
8X (0.6)
(3.1)
SYMM SOLDER MASK
(1.3) OPENING
TYP (4.9)
NOTE 9
6X (1.27)
5
4
( 0.2) TYP
VIA SYMM METAL COVERED
BY SOLDER MASK
(1.3) TYP
(5.4)
4221637/B 03/2016
NOTES: (continued)
www.ti.com
EXAMPLE STENCIL DESIGN
DDA0008J PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.6)
BASED ON
0.125 THICK
STENCIL
8X (1.55)
1
8
8X (0.6)
(3.1)
SYMM
BASED ON
0.127 THICK
STENCIL
6X (1.27)
5
4
4221637/B 03/2016
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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