Date: 25 Feb 2022

VLSI Design Lab EC-16203

Experiment 7

Objective: To design and simulate Ring Counter and Johnson Counter using Verilog.
Tools & Apparatus Used: Xilinx ISE
Theory: These are sequential circuits that are used for counting the pulses.
Ring Counter: A ring counter is also known as SISO (serial in serial out) shift register counter,
where the output of the flip flop is connected to the input of the flip flop which acts as a ring
counter. The designing of the ring counter can be done by using four D-Flip Flops with a
common clock signal.

Figure 7.1 Ring Counter

Johnson Counter: It is also known as a modified ring counter. It is designed with a group of
flip-flops, where the inverted output from the last flip-flop is connected to the input of the first
flip-flop. Generally, it is implemented by using D flip-flops or JK flip-flops. It is also known
as an inverse feedback counter or twisted ring counter.

Figure 7.2 Ring Counter

Verilog Codes:

Ring Counter Verilog Code:

module ring_counter(Clock, Reset, Count_out);
input Clock;
input Reset;
output [3:0] Count_out;
reg [3:0] Count_temp;

always @(posedge(Clock),Reset)
begin
if(Reset == 1'b1) begin //when Reset is high
Count_temp = 4'b0001; end //The Count value is reset to "0001".
else if(Clock == 1'b1) begin //When the Clock is high
//Left shift the Count value.
Count_temp = {Count_temp[2:0],Count_temp[3]}; end
end
assign Count_out = Count_temp;
endmodule

Johnson Counter Verilog Code:

module johnson_counter(Clock, Reset, Count_out );
input Clock;
input Reset;
output [3:0] Count_out;
reg [3:0] Count_temp;

always @(posedge(Clock) or Reset)

begin
if(Reset == 1'b1) begin //when Reset is high
Count_temp = 4'b0000; end //The Count value is reset to "0000".
else if(Clock == 1'b1) begin //When the Clock is high
//Left shift the Count value and at the same time
//negate the least significant bit.
Count_temp = {Count_temp[2:0],~Count_temp[3]}; end
end
assign Count_out = Count_temp;

endmodule

RTL Schematics:
RTL Schematic: Ring Counter

Figure 7.3 RTL Schematic: Ring Counter

RTL Schematic: Johnson Counter
 Figure 7.4 RTL Schematic: Johnson Counter

Output Waveforms:
Ring Counter:

Figure 7.5 Output Waveform: Ring Counter

Johnson Counter:

Figure 7.6 Output Waveform: Johnson Counter

Result: We have successfully designed and simulated ring counter and Johnson counter
through Verilog in Xilinx software. We have verified the results using the test bench.