8086

PIN OUT – INPUTS

 A0 Add
Bus
A19

D0 Data
Bus
8086 D15

Control
signals
 Address bus

BIU RD Discs
I/o
WR ROM RAM
Ports Video

Data Bus

ALU

CLK
Control
& Timing

EU
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 37 A19/S6
AD9 7 35 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
AD6 10 8086 31 HOLD RQ/GT0
AD5 11 30 HLDA RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
Minimum & Maximum Modes of Operations
8088/8086 can be configured to work in any of the two modes
Minimum Mode
MN/MX’ –logic 1
Single processor in system
Smaller systems/ Cheaper

Maximum Mode
MN/MX’ – logic 0
Larger systems – more than one processor
e.g. – Numeric Data processor (8087) –co-processor
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 37 A19/S6
AD9 7 35 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
AD6 10 8086 31 HOLD RQ/GT0
AD5 11 30 HLDA RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
Instruction Cycle

Machine Cycle

T states

MOV BX,[0114H]
8B1E 1401
CLK is crystal controlled clock sent to 8086 from
an external clock generator device such as 8284
One cycle of this clock is called a state
A state is measured as falling edge of one clock
pulse to falling edge of next clock pulse
Different versions of 8086 have maximum clock
frequencies of between 5MHz and 10MHz
The minimum time of one state will be between
100nS to 200nS
Basic operation such as
reading a byte from memory /port
writing a byte to a memory/port
called a machine cycle
 FC 5 MHZ
CLK
CSYNC
2.5MHz
PCLK
X1
15 MHz
X2

+5V 8284

10K

e RESET
p RES
10µ
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 37 A19/S6
AD9 7 35 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
AD6 10 8086 31 HOLD RQ/GT0
AD5 11 30 HLDA RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
8086
INSTRUCTION CYCLE,
MACHINE CYCLE
Machine Cycle
MEMR
◦ Opcode
◦ Data

MEMW
◦ Data

IOR
IOW
MOV AX,BX
8B C3
Fetch Instruction - 1 MEMR
1 Machine Cycle
ADD BX,[0110]
03 1E 10 01
Instruction Fetch
2 MEMR – 2 Machine Cycle
Instruction Execute
Read Data from DS:0110 – 1 MEMR
3 Machine Cycles
ADD [0110],BX
01 1E 10 01
Instruction Fetch
2 MEMR – 2 Machine Cycle
Instruction Execute
Read Data from DS:0110 – 1 MEMR
Store Result in DS:0110
4 Machine Cycles
CBW
98
1 MEMR
1 Machine Cycle
ADD AX,[BX]
03 07
1 MEMR Instruction Fetch
1 MEMR data from DS:[BX]
2 Machine cycles
8086
PIN OUT – ADDRESS BUS
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 37 A19/S6
AD9 7 35 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
AD6 10 8086 31 HOLD RQ/GT0
AD5 11 30 HLDA RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
next
Minimum & Maximum Modes of Operations
8088/8086 can be configured to work in any of the two modes
Minimum Mode
MN/MX’ –logic 1
Single processor in system
Smaller systems/ Cheaper

Maximum Mode
MN/MX’ – logic 0
Larger systems – more than one processor
e.g. – Numeric Data processor (8087) –co-processor
ADDRESS & DATA being MULTIPLEXED on the

ADDRESS BUS

A0 – A15 + D0 – D15 AD0 – AD15

De-multiplexed externally using latch

 LS273

Octal Latch
G OE

ALE

back
Signal Address Status
AD16 /S3 AD16 Segment Acccess
AD17/S4 AD15
AD18/S5 AD14 Int Flag Sttaus
AD19/S6 AD13 0
BHE/S7 AD12 1
 A16-A19
S6-S3 A16-A19
LS373
BHE’/S7 BHE’
G OE’

ALE

8086
AD8-AD15 LS373 A8-A15
G OE’

AD0-AD7 LS373 A0-A7

G OE’

MN/MX’ 5V

System Bus of 8086 (Address)

8086
PIN OUT – CONTROL BUS
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 37 A19/S6
AD9 7 35 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
AD6 10 8086 31 HOLD RQ/GT0
AD5 11 30 HLDA RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
M/IO’ RD’ WR’ Bus cycle
1 0 1 MEMR’
1 1 0 MEMW’
0 0 1 IOR’
0 1 0 IOW’
M/IO’ IOR’
RD’

M/IO’ IOW’
WR’
M/IO’ MEMR’
RD’

M/IO’ MEMW’
WR’
8086
PIN OUT – DATA BUS
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 37 A19/S6
AD9 7 35 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
AD6 10 8086 31 HOLD RQ/GT0
AD5 11 30 HLDA RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
Buffered Systems
Buffering of control/data/addr busses 
signals sufficiently strong to drive various IC
chips
Pulse leaves IC chip - drop in strength
Based on distance between the IC generating
the signal & the IC receiving the signal
More Pins a signal is connected (Fanout)
stronger the signal must be
Bus buffering  Boosting the signals
traveling on the bus
Unidirectional Buffer - 74LS244
Bidirectional Buffer - 74LS245
 A Bus B Bus
Outputs Outputs

0
A Bus B Bus

E DIR

0 0
1
 A Bus B Bus
Inputs/Outputs Inputs/Outputs

E DIR

DEN DT/R
During write cycle 8086 asserts DT/R’ signal high to put
the buffers in the transmit mode

When 8086 asserts DEN low to enable the buffers- data

o/p from 8086 will pass through the buffers to the
addressed port or memory loc

back
 System Bus of 8086(Data)

8086
AD8-AD15 LS245 D8-D15
DT/R’ DIR OE’
DEN’

AD0-AD7 LS245 D0-D7

DIR OE’

MN/MX’ 5V
8086
SYSTEM BUS
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 37 A19/S6
AD9 7 35 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
AD6 10 8086 31 HOLD RQ/GT0
AD5 11 30 HLDA RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
Signals of 8086 used during a bus transfer
AD15 – AD0 – Multiplexed Address & Data
A19/S6 – A16/S3 – Higher order Address / Status
M/IO’ – Indicates whether access is to
memory or I/O Device
RD’ - Read Operation from Memory/IO
WR’ - Write Operation to Memory/IO
ALE - When set – Multiplexed AD0 – AD15
has address
DT/R’ - 8086 is transmitting/receiving data
DEN’ - Enable data buffers connected to
8086
 A16-A19
S6-S3 A16-A19
LS373
BHE’/S7 BHE’
G OE’

ALE

8086
AD8-AD15 LS373 A8-A15
G OE’

AD0-AD7 LS373 A0-A7

G OE’

MN/MX’ 5V

System Bus of 8086 (Address)

 RD
MEMR

LS244 LOGIC MEMW

WR
CIRCUIT IOR
IO/M OE’
IOW

8086
AD8-AD15 LS245 D8-D15
DT/R’ DIR OE’
DEN’

AD0-AD7 D0-D7
LS245
DIR OE’

MN/MX’ 5V
System Bus of 8086(Data + Control)
8086
BUS OPERATIONS
Signals of 8086 used during a bus transfer
AD15 – AD0 – Multiplexed Address & Data
A19/S6 – A16/S3 – Higher order Address / Status
M/IO’ – Indicates whether access is to
memory or I/O Device
RD’ - Read Operation from Memory/IO
WR’ - Write Operation to Memory/IO
ALE - When set – Multiplexed AD0 –
AD15 has address
DT/R’ - 8086 is transmitting/receiving
data
DEN’ - Enable data buffers connected to
8086
 A16-A19
S6-S3 A16-A19
LS373
BHE’/S7 BHE’
G OE’

ALE

8086
AD8-AD15 LS373 A8-A15
G OE’

AD0-AD7 LS373 A0-A7

G OE’

MN/MX’ 5V

System Bus of 8086 (Address)

 RD
MEMR

LS244 LOGIC MEMW

WR
CIRCUIT IOR
IO/M OE’
IOW

8086
AD8-AD15 LS245 D8-D15
DT/R’ DIR OE’
DEN’

AD0-AD7 LS245 D0-D7

DIR OE’

MN/MX’ 5V

System Bus of 8086(Data + Control)

 Tw
T1 T2 T3 T4
CLK

A19-A16/S6–S3 A19 – A16 S7 – S3

AD19- AD16 A15-A0 DataData

Data
Address Setup Data Setup
M/IO’

ALE
DT/R’

RD’

DEN’

200 ns
800 ns

Bus Timings for a Read Operation

READY Signal & WAIT States
 T1 T2 Tw T3 T4
CLK

A19-A16/S6–S3 A19 – A16 S7 – S3

AD0- AD15 A15-A0 Data

Address Setup Data Setup
M/IO’

ALE
DT/R’

RD’

DEN’

200 ns
1000 ns

Bus Timings for a Read Operation

 T1 T2 T3 T4
CLK

A19-A16/S6–S3 A19 – A16 S7 – S3

AD0- AD15 A15-A0 Data

Address Setup
M/IO’

ALE
DT/R’

WR’

DEN’

200 ns
800 ns

Bus Timings for a Write Operation

8086
OTHER PINS
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 37 A19/S6
AD9 7 35 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
AD6 10 8086 31 HOLD RQ/GT0
AD5 11 30 HLDA RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
Interrupts
Maskable –
◦ INTR input
◦ Ack INTA’ output

Non-Maskable
◦ NMI Input
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 37 A19/S6
AD9 7 35 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
AD6 10 8086 31 HOLD RQ/GT0
AD5 11 30 HLDA RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
DMA
HOLD
◦ Input

HLDA
◦ Output
8086
MAXIMUM MODE
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 37 A19/S6
AD9 7 35 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
AD6 10 8086 31 HOLD RQ/GT0
AD5 11 30 HLDA RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
next
8086 8087
S2’ S1’ S0’ Function
0 0 0 INTA
0 0 1 IOR
0 1 0 IOW
0 1 1 Halt
1 0 0 Opcode fetch
1 0 1 MEMR
1 1 0 MEMW
1 1 1 Passive

QS0 QS1 Function

0 0 Queue Idle
0 1 First byte in opcode
1 0 Queue is empty
1 1 Subsequent byte of opcode
S2 MRDC’
S1 MWTC’
S0 AMWTC’
IOR’
IOW’
AIOW’
DT/R’
DEN
8288
ALE

CLK
AEN’
CEN
IOB