Polytechnic University of Puerto Rico

Department of Electrical & Computer Engineering and Computer Science

COE3301 – Logic Circuits Lab
final Tests

I. Design the following functions using logic Gates (5 PT)

A B C Y1 Y2
0 0 0 1 1
0 0 1 1 0
0 1 0 1 0
0 1 1 0 0
1 0 0 1 1
1 0 1 0 1
1 1 0 0 1
1 1 1 0 0

Implement Y1 using NAND-NAND Implement Y2 using NOR-NOR

II. Design the following functions using decoder 3:8 (5 PT)

A. Implement the function of the prevue step Y1 with decoder active Low.

B. Implement the function of the prevue step Y2 with decoder active High
.
III. Design the following functions using multiplexer only (5 PT)

A. Implement the function of the prevue step Y1 with only multiplexer 4:1 or 2:1

B. Implement the function of the prevue step Y2 with only multiplexer 8:1.
IV. Design the following functions using only one multiplexer (10 PT)
Show circuit implementation.

A. m(0,1,3,5,9,12,15)+d(4,7,8,10,13)
A B C D Y 4:1

0 0 0 0 1

0 0 0 1 1
C’+D
0 0 1 0 0

0 0 1 1 1
C’
0 1 0 0 -

0 1 0 1 1

0 1 1 0 0

0 1 1 1 -

1 0 0 0 -

1 0 0 1 1 C’

1 0 1 0 -

1 0 1 1 0
C’+D
1 1 0 0 1

1 1 0 1 -

1 1 1 0 0

1 1 1 1 1
 V. Design a SYNCHRONOUS SEQUENTIAL Machine (Mealy/Moore)
to detect the following Sequential 1011101 reusing bits.

Complete all step for this problem:

A. DIAGRAMA:(10pt)
 B. Table for the Flip Flop (10pt)

QA QB QC X SA RA SB RB SC RC QA’ QB’ QC’ Z

0 0 0 0 0 X 0 x 0 X 0 0 0 0

0 0 0 1 0 X 0 x 1 0 0 0 1 0

0 0 1 0 0 X 1 0 0 1 0 1 0 0

0 0 1 1 0 X 0 x x 0 0 0 1 0

0 1 0 0 0 X 0 1 0 X 0 0 0 0

0 1 0 1 0 X x 0 1 0 0 1 1 0

0 1 1 0 0 X x 0 0 1 0 1 0 0

0 1 1 1 1 0 0 1 0 1 1 0 0 0

1 0 0 0 0 1 1 0 0 X 0 1 0 0

1 0 0 1 x 0 0 x 1 0 1 0 1 0

1 0 1 0 x 0 1 0 0 1 1 1 0 0

1 0 1 1 0 1 0 x x 0 0 0 1 0

1 1 0 0 0 1 x 0 0 x 0 1 0 0

1 1 0 1 x 0 x 0 1 0 1 1 1 1

1 1 1 0 0 1 x 0 0 1 0 1 0 0

1 1 1 1 0 1 0 1 x 0 0 0 1 0
C. KARNAUGH Maps (5pt)
D. Show the SEQUENTIAL Machine CIRCUITO (10pt)
1. Show the parte number of IC to implement

Part number for implementation:

 7411
 7432
 7404
 7410
V. Bono (10pt) Design a SYNCHRONOUS SEQUENTIAL Machine (mealy)
to detect the following Sequential 101 OR 110 use overlapping.
Diagram: and table state Only