° a @ ey % Department of Electrical, Electronic and Communication Engineering Course Code: EECE 3261 Course Title: VLSI Design [Assignment Name [ Rise time, fall time expression in CMOS inverter, ~ | Power consumption of CMOS inverter. Submitted by: Submitted to: Name: Sayed Shifat Ahmed Dr. Sheikh Rashel Al Ahmed Roll No: 170501 Associate Professor Year: 34 Semester:2" Dept. of EECE, PUST. Session: 2016-17 Dept. of EECE, PUST. Date of assignment: 02.04.22 Date of submission: 09.04.22 Scanned with CamScannerAn expression of ise time & Gall time in a CMos inverter . Every cineuit has some parasilie capacilanee components | associahed aith CMOS. There capacitance results in addlaying jhe volage change in the circuit. So we will get limitations our speed of operation ckpending on how Past we jean charge or discharge thee capacitors. To illustrate tu vise time , fall Hime of capacitors in o CMDS iwerter 16 discussed here i | Rise time The vise lime of te oulput cignal ave defined as te Kime cequived for the voltage to change from its 10% level to 90% level of the maxtmum | value |fall time s The Fall Hime of the output slgnal are afintd as | the time required for the voltage to change from its 90% level tb 10% level of the maximum value. Scanned with CamScannerTn Ws eiveuth demonetnalion , r— Yoo when, A Vin= 0, Vo =Vpp Vin o— ———e V, T= ON Cinpst) 45 output) T, = OFF re : Vin=4, 0 Vy = ae T, = OFF 1, = ON Rise lime estimation = Wie condition ¢o te find out the vise time we need to Consider when the ‘put falls from 4% © Land pMos CT) is conducting and nMOS becom open. Thre is a large eapacilor Ce) connected with outpul that ave continuously, charging and discharging . Whan, Vin =O Aken, pMDS =ON nMos = OFF iv makes a path te changing 8 (Catutakion)) the capacilor C, . —— “oo [-—7— «vr who, Vin = 4 twn, MOS =OFF nMOS =ON WV make, o path lo discharge => > \w capocilor Cy Scanned with CamScannerSo. Vinal let a > ww devive we for vise Hime, input = © PHOS —>eonducling — mode it, eNOS ie in saluralion ken, Where, To = Be Cves eel) Bp = ransislor a > a rans conduclan & =Be a Se, this current charges C., = VnCon “T Vou = ase our = ASP ge e es we Peal Tagp = current through - drain Ye souree > Vor = Bp (Vas ~\Verl) -t im phos. ze Se eect = Be (Nas Weel) >t, - _2Xoo Oe [pssumt, E=ty >for vise wm Pp (Yoo Weel when, Veut = +Vop .¢@ yp amaleoacy [ul . Be (Yep - 02¥px)” tonsiler, Weel = 0°2 pp | a Zon nC. Bp x O'GAVon Sty = 3G Pp -Yop Scanned with CamScannerFall Hime estimation * TWS condition so to find oul tu fall Kine we netd to Consider win the npub yisey from O to Land consider nMOS (1) 16 conducting and pM0S become open, ‘This Leads to discharging the capacitor C, and make a path to Sround. When, Vin = 4 thn, aMoszon eos =orF ei make a path fp discharge. Ye capacitor ¢,. So, derive ean for Gall hime, 4 ° > npuk = 4 nM0S > conducting mode if, Mos iy in saturation then, Tyga = Pn (Was Went) 7 zi So, this capacitor je discharging, : oe ~Voop = et Bn (Vos - (Wenl) = Nv = SO > Vout 2-¢, 2 Nour» at= or Pn CVqs- [Venl) —— “oo lure, @n =tunseonduela Nee of Mos =pl w = og: ML Scanned with CamScannerat, = BY [em tah, = for tril 8 Co - Wn When, Vout = Vpn Sty = _2¥oo 8 a . oa | cost, \Ynl = 0 | Qlop= 0°2pp > be = Se, Pn Von So, Rise lim, | = Ce a Fall Vine, ty 2 eu IIs By Vop Relation belween Rise time , Fall Kime. Fromm eqn ay, ad 3, b 7 Teo \os ‘ 24/6, Yoo i> ce eS Bn ty ee Here, Bn, Bp are directly proportional. to the mobility of eleelrons , holes respectively ie cn i) ty Ba Ya y Pe Ye Scanned with CamScannerNenet, we know the mobilily of clechon (Yn) of wivansislor is 25 Vines greater than the mobility of holes Cre) of — p-transislor, ie, Y= 25 \p Nena, rt Bn 2:5 ty Be a Rise lime Cty) = 2:5 x Fall Ke (te) > ty = 25h, Pn = 2-5 Bp te, nM0S transistor is 25 Yims faster than pros | Tran s\otor. So, From rise time Ctr), fall Fim Cty) eqn we have, Q) te te oe AL Yoo ® tite ag Scanned with CamScanner{8 Show that, Power Consumplion of CMOS depends upon operating Frequency, SS Oe Tn an inverter the capacilor C, ig charged through Ye phos Wansistor and ener some amount of energy to taken from the Power supply. The some part of te energy is dissipated in ePMOS and some 16 stored on the capacilor Fuvther in high to low transition the eapacilor is discharge and tht stored ecntrgy is dissipated in nMOS deviee. During low to high transition the load capacikanee Cy is charged. Hene te energy taken from ‘the power Supply to charge this Capacitor. 9 Yoo & ve [7 dL R Fig.2 Cirewit used for power eonsumption analysis Scanned with CamScanner/ The current through ‘the capacitor and tt village across i} are = be ® be. Garve)” eins he ° _. Rey \. Scanned with CamScannerRet - Goon (oo~ Ys) [ né 7 sey ° NI- a (wey Ke on let ~2 Vp, 7 \ aS bare, ie -5): afe-\] | = (vee Van) @, [4 2 2 | 7& = $e ¢ Mypm Vas)” Similarly, the discharging energy consumption is equal bo the charging Power consumption Ee = S eu(ype-¥ss) A single cycle requires the capacitor to both change | | jens discharge . So, te telal energy consumption v - ioe ce aie, (%p2Vss) + La lp- Veo eee co Opp - Yes) [This shows ‘that, the half enengy is supplied by ty power supply and stored in G and other halt is dissipated in pMos Thus in switching each suitching cycle which consist of — ow-to-high to high- to-low Transition a Fixed amount of energy ig equal b v. Cu Cp" Yes) is taken, Scanned with CamScanner| So, power consumption per cyele 15, | [oe crue veya per cyl, | The vate at which somlhing occurs over parlieular period of the Hime 15 called Frequiney, The inverter alternately changer ond discharges its output capaci tan ed. ene, if a gate is switched on & off “E” Vimes then the power consumption is given by, e | | P= (Mpp- Vos) x i Power is energy per unit Hime Hene, Ye power apngumption in CM0S eireult depends upon, W te power supply vollage. Ci) the ecapacitenet of — load capacitor, Cu) the switching Frequeney, of the input. Scanned with CamScanner