module Prob_5_13 (GTE, LTE, A, B, C, D); output [3:0] GTE, LTE;

Input [31: 0] A, B, C, D;
reg [3:0] GTE, LTE;
always @ (A, B, C, D)
begin
GTE = 0;
LTE = 0;
if ((A>=B) && (A>=C) && (A>=D)) GTE = GTE | 4'b1000;
if ((B>=A) && (B>=C) && (B>=D)) GTE = GTE | 4'b0100;
if ((C>=A) && (C>=B) && (C>=D)) GTE = GTE | 4'b0010;
if ((D>=A) && (D>=B) && (D>=C)) GTE = GTE | 4'b0001;
if ((A<=B) && (A<=C) && (A<=D)) LTE = LTE | 4'b1000;
if ((B<=A) && (B<=C) && (B<=D)) LTE = LTE | 4'b0100;
if ((C<=A) && (C<=B) && (C<=D)) LTE = LTE | 4'b0010;
if ((D<=A) && (D<=B) && (D<=C)) LTE = LTE | 4'b0001;
end endmodule

module t_Prob_5_13 ();

wire [3:0] GTE, LTE;
reg [31: 0] A, B, C, D;
Prob_5_13 M0 (GTE, LTE, A, B, C, D); initial
begin
A = 2; B = 2; C = 2; D = 2;
#10 A = 2; B = 2; C = 2; D = 1;
#10 A = 2; B = 2; C = 1; D = 1;
#10 A = 2; B = 1; C = 1; D = 1;
#10 A = 525; B = 1; C = 2; D = 1;
#10 $finish;
end
endmodule