4 bit universal shift register

S0 S1——> Operation

0 0 ——-> Previous State

0 1 ——->Shift Right

1 0 ——-> Shift Left

1 1 ——-> Parallel Load

module universal_shift(a,s,clk,p);

input [3:0]a;

input [1:0]s;

input clk;

output reg [3:0]p;

initial

p<=4'b0110;

always@(posedge clk)

begin

case (s)

2'b00:

begin

p[3]<=p[3];

p[2]<=p[2];

p[1]<=p[1];

p[0]<=p[0];

end

2'b01:

begin

p[3]<=p[0];
p[2]<=p[3];

p[1]<=p[2];

p[0]<=p[1];

end

2'b10:

begin

p[0]<=p[3];

p[1]<=p[0];

p[2]<=p[1];

p[3]<=p[2];

end

2'b11:

begin

p[0]<=a[0];

p[1]<=a[1];

p[2]<=a[2];

p[3]<=a[3];

end

endcase

end

endmodule

Module shift_reg(y,clk,rst,cntrl,in);

Output reg [3:0] y;

Input clk,rst;

Input [3:0] in;

Input [1:0] cntrl;

always@(posedge clk)

Begin

If (rst)

y<=0;

Else

begin

Case(cntrl)

00: y<=in; // data load;

01: y<=y<<1;

10:y<=y>>1;

Default: y<=x;

end case

End

End

Endmodule