SLIC SRI LANKA TECHNOLOGICAL CAMPUS BACHELOR OF SCIENCE HONOURS IN ENGINEERT YEAR 2-— SEMESTER 4 - January 2018 End-Semester Examination EE 2201 - Analog Electronics 11 Three Hours Answer all Questions No. of Questions : 04 No. of Pages : 07 (including the cover page) Important Instructions to the candidates ‘+ If @ page or a part of this question paper is not printed, please inform the Supervisor immediately. * Candidate's registration number should be written clearly and legibly on all answer sheets. + IFESSAY TYPE: Write the answers to all questions on the writing paper that is provided. ‘+ Blectronic devices capable of storing and retrieving text, including electronic dictionaries and ‘mobile phones are not allowed. * Candidates must not seek, give or receive assistance of any kind during the exam. Any cheating, any attempt to cheat, assisting others to cheat, or participating therein, or engaging in such improper conduct is a serious violation and will generally result in disqualification of the candidate’s paper, and any other disciplinary action as may be deemed appropriate. O74L There are two basic types of voltage regulators. Basic voltage regulators are classified as either SERIES or SHUNT, depending on the location or position of the regulating element(s) in relation to the circuit load resistance. Each type of cirenit can provide an output de voltage that is regulated or ‘maintained at a set value even if the input voltage varies or if the load connected to the output changes. Figure 1.1 shows a circuit of a series voltage regulator which is designed to maintain a fixed voltage Vor = 20 V; 0 — 0.5 A when the full wave rectified sinusoidal is applied as an input Vin. The average input de voltage on no-load condition is 30 V. The input voltage may vary between 30 — 25.5 V at no-load and full-load conditions, respectively. Following transistor and Zener diode are chosen for the above design. Zenor diode: Vz = 20V, Ry = 400. Transistor: Py = 40W, Iemax = 3A, Veumax = 40 V, hfe = 50 and Vez = 0.6 V. Voltage regulation is defined as VR = (Vw. — Ye fy where Vyz and Vp, are the no-load and full Joad voltages, respi ly. es YY Lt Vout 7 as i 20v Fig 1.1 a. Calculate R, at no load condition. (5 marks) b. Calculate R, at full load condition. (5 marks) c. Select suitable resistor for Ry (5 marks) 4. Calculate output voltage regulation (%).. (5 marks) e. Verify whether the transistor ratings are suitable or not. (5 marks) (Total 25 marks)2. Oscillator is an electronic circuit that generates a periodic waveform on its output without an external signal source. If the output signal varies sinusoidally, the circuit is referred to as a sinusoidal oscillator. If the output voltage rises quickly to one voltage level and later drops quickly to another voltage level, the circuit is generally referred to as a pulse or square-wave oscillator. a, Figure 2.1 shows a square wave oscillator. Explain the operation of the oscillator considering the charging/ discharging of the capacitor, C. You may provide necessary waveforms. Rj, Reand Ry are fixed known resitors and V-, Vand ¥,, ate node voltages of interting, non- interting and output terminals respectively. (10 marks) Ry Re Rs Fig 2.1 b. Derive an expression for the frequency of oscillation fy for the following circuit. Refer Fig 2.2. Here Z, and Z, are the impedances of the corresponding RC circuits. Vj, Vs Vy and V, represent the node voltages. (Hint: For an sinusoidal oscillator, at a given oscillator Srequency fo, the loop gain is always maintained as unity , AGewPGjo) = 1 ) (15 marks) (Total 25 marks)Fig 2.2 3, a, Prove that when a capacitor Cj. is connected between the input and output terminals B and C of a network which provides a voltage gain Ay as shown in Fig 3.1, can be decomposed in to a capacitance C,,—C,,(I+4,) connecting across the input terminals and another capacitance Cy, = {ut connecting across the output terminals which ultimately gives the same effect (Hint: Use Miller's theorem to simplify the circuit) (5 marks) 8 fT c « tt > Coc Ri =F Che Blo. Sn Fig 3.1b. Fig 3.2 shows a wide-band amplifier. Draw an AC equivalent circuit by assuming the hi frequency effect of the given transistor. R, and Ry are the source and load resistance of the circuit. Rests of the resistors are used to bias the transistor. Cyc and Cpe are junction capacitors and are relatively small compared to coupling and bypass capacitors C,, C; and Ce. (5 marks) Fig 3.2 c. Input network of the above AC equivalent circuit can be simplified to a form depicted in Fig 3.3. Derive an expression for Ry; and C; (Hint: use Thevenin theorem to simplify the circuit). ( marks) Roni Wy Em Fig 3.3 . Hence, prove that the 3-dB cut-off frequency fn Draw the frequency response of the circuit and mark necessary information. (5 marks), Follow the same procedure and find the equation for cut-off value fi for the output network as well. (5 marks) (Total 25 marks) 4 ‘The power spectral density of a signal shows the distribution of the average signal power across frequency. You are given a random signal f(t) which is described by 1 $s 2808 7 a. Derive the Fourier transform of signal fit). (5 marks) b. Draw the two sided power spectrum ofthe signal (5 marks) ¢. Above signal f(t) is filtered through a low-pass filter whose frequency response is given in Fig 4.1. What would be the spectrum of the output signal. (5 marks) IGGw9! 10 = t = Fig 4.1 4. The given Operational Amplifier circuit in Fig 4.2 has a frequency response similar to an inductor and considered as a simulated inductor. Derive an expression for the input impedance Zig of the circuit of Fig. 4.2 and hence show that the circuit behaves as a frequency-dependent inductor for Ry < Rp. Find the inductance of the simulated inductor. (Hint: Write the input impedance as 2,, = R+ jat.) (5 marks)¢. IfRi = 1 kQ and C; = 100nF, calculate the value of Ro required to provide an inductance of 250mH at 500Hz. (S marks) (Total 25 marks) R: Fig 4.2 End of Question Paper