Assignment-13

1. 4kx16 bit RAM to infer BRAM 

Code:
module bram_4Kx16bit(

input clk,wen,rst,

input [11:0] address,

input [15:0] datain,

output reg [15:0] data_out

);

reg[15:0] mem[0:4095];

integer i;

always@(posedge clk)

if(rst)

for(i=0;i<4096;i=i+1)

mem[i]<=16'd0;

else if(wen)

mem[address]<=datain;

else

data_out<=mem[address];

endmodule

Testbench:
module bram_4Kx16bit_tb(

);
reg clk=1'b0;
reg wen,rst;
reg[15:0] datain;
reg[11:0] address;
 wire [15:0] data_out;
bram_4Kx16bit uut(.clk(clk),.rst(rst),.address(address),.datain(datain),.data_out(data_out));

always #5 clk=~clk;
initial begin
wen=1'b1; rst=1'b1;
#30 rst=1'b0;
//#300 wen=1'b0;
#1000 $stop;
end
integer i;
initial begin
for(i=0;i<100;i=i+1)
begin
datain=$urandom;
address=$urandom;
#10;
end
end
endmodule
Simulation:
2. 128x4 bit RAM to infer DRAM 

Code:

module dram_128x4bit(

input clk,wen,rst,

input [6:0] address,

input [3:0] datain,

output wire [3:0] data_out

);

reg[3:0] mem[0:127];

integer i;

assign data_out = wen?data_out:mem[address];

always@(posedge clk)

begin

if(rst)

begin

for(i=0;i<128;i=i+1)

mem[i]<=4'd0;

end

else

begin

if(wen)

mem[address]<=datain;

end

end

endmodule

Testbench:

module dram_128x4bit_tb(
 );

reg clk = 1'b0;

reg wen,rst;

reg [3:0] datain;

reg [6:0] address;

wire [3:0] data_out;

dram_128x4bit uut
(.clk(clk),.wen(wen),.datain(datain),.rst(rst),.address(address),.data_out(data_out));

always #5 clk=~clk;

integer i;

initial begin

wen=1'b1; rst=1'b1;address=1'b0;

#30 rst=1'b0;

for(i=0; i<100; i=i+1)

begin

datain=$urandom;

address=i;

#10;

end

wen=1'b0;

for(i=0; i<100; i=i+1)

begin

address=i;

#10;

end

#100 $stop;

end

endmodule
Simulation: