Ec237 Digital System and Combinational Circuits Unit 4

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
PUDUCHERRY TECHNOLOGICAL UNIVERSITY, PUDUCHERRY – 605 014
Course Name : Analog and Digital Electronics

Course Code : EC237
Topic : Digital system and Combinational circuits
Presented by
Vidya Sagar . P
Research Scholar
Department of ECE,PTU.
Department of Electronics and Communication Engineering, PTU.

Syllabus
UNIT-I Diode Characteristics Periods: 9
Diode applications: PN junction diode, VI-characteristics – Junction diode models – Junction diode as switch – Diode CO1
specifications – Circuit applications of diodes – Smoothing circuits – Zener diode as Voltage Regulator.
UNIT-II Linear applications of Operational Amplifiers Periods: 9
Linear applications of OP-AMP: Block diagram of OP-AMP – Differential amplifier – OP-AMP ideal parameters – Inverting, Non- CO2
inverting amplifier – Voltage follower – Summing, Average scaling and Instrumentation amplifier.
UNIT-III Non-linear applications of Operational Amplifiers Periods: 9
Non-linear applications of OP-AMP: Comparator – Schmitt trigger – Square wave generator – Triangular wave generator – DAC and CO3
ADC characteristics. Active filters and multivibrators: Low Pass Filter – High Pass Filter – Band Pass Filter – Band elimination Filter
– Astable, Monostable and Bistable multivibrator.
UNIT-IV Digital system and Combinational circuits Periods: 9
Digital system and Combinational circuits: Boolean algebra – Standard representation for logic functions – K map representation CO4
of logic functions – K map minimization – Don’t care conditions – Adders – Encoders – Decoders – Multiplexer – Demultiplexer –
ALU.
UNIT-V Sequential circuits Periods: 9
Sequential circuits: SR flip flop – JK flip flop – D and T flip flop – Shift registers – Binary ripple counter – Synchronous up/down CO5
counter – BCD counter – Ring counter – Johnson counter – Serial adder.
Lecture Periods: 45 Tutorial Periods: 0 Practical Periods: 0 Total Periods: 45
Text Books:
1. Morris Mano, Digital design, PHI learning, Sixth Edition,2018.
2. Sedra and Smith, Microelectronic circuits, Oxford University press, seventh edition, 2017.
3. Y.N. Bapat, Electronic circuits and systems – analog and digital, Tata Mc. Graw Hill, 2005.
Reference Books:
1. Millman J and Halkias C, Integrated Electronics, Tata Mc. Graw Hill, Second Edition, 2017.
2. Boylestad RL & Nashelsky L, Electronic Devices & Circuit theory, Pearson Education, Eleventh edition, 2015.
2 Department of Electronics and Communication Engineering, PTU. VIDYA SAGAR P
Introduction Definitions:
Literal: A literal is a complemented or uncomplemented Boolean variable.

Examples: a and ā are distinct literals. ā+cd is not
Product Term :A product term is a single literal or a logical product (AND) of two or
more literals.
Examples: a, ā, ac, ācd, aaāb are product terms ; ā+cd is not a product term.
Sum Term :A sum term is a single literal or a logical sum (OR) of two or more literals.
Examples: a, ā, a+c, ā+c+d are sum terms; ā+cd is not a sum term.
Minterm of n variables: A product of n literals in which every variable appears exactly
once.
f(a,b,c,d): ab’cd’, a’bc’d’
Maxterm of n variables: A sum of n literals in which every variable appears exactly once.
f(a,b,c,d): (a’+b+c+d), (a’+b’+c+d)

What are Karnaugh1 maps?
Karnaugh maps provide an alternative way of simplifying logic circuits.

Instead of using Boolean algebra simplification techniques, you can transfer
logic values from a Boolean statement or a truth table into a Karnaugh map.
The arrangement of 0's and 1's within the map helps you to visualize the
logic relationships between the variables and leads directly to a simplified
Boolean statement.
1Named for the American electrical engineer Maurice Karnaugh.

Description of Kmaps and Terminology
For example, the minterms for a function having the inputs x and y are:
Consider the Boolean function,
Its minterms are:

Similarly, a function having three inputs, has the minterms that are shown in
this diagram.

A Kmap has a cell for each minterm.

This means that it has a cell for each line for the truth table of a function.
The truth table for the function F(x,y) = xy is shown at the right along with
its corresponding Kmap.

As another example, we give the truth table and KMap for the function,
F(x,y) = x + y at the right.
This function is equivalent to the OR of all of the minterms that have a value
of 1. Thus:

Kmap Simplification for Two Variables
Of course, the minterm function that we derived from our Kmap was not in
simplest terms.
That’s what we started with in this example.
We can, however, reduce our complicated expression to its simplest terms by
finding adjacent 1s in the Kmap that can be collected into groups that are
powers of two.
• In our example, we have two such groups.

– Can you find them?

The best way of selecting two groups of 1s form our simple Kmap is shown
below.
We see that both groups are powers of two and that the groups overlap.
The next slide gives guidance for selecting Kmap groups.

The rules of Kmap simplification are:

Groupings can contain only 1s; no 0s.
Groups can be formed only at right angles; diagonal groups are not allowed.
The number of 1s in a group must be a power of 2 – even if it contains a
single 1.
The groups must be made as large as possible.
Groups can overlap and wrap around the sides of the Kmap.

K-Map
A=0 A=1
AB’
0 2
B=0 0 1
1 3
B=1 1 1
A’B AB
f(A,B) = A + B

Another Example f(A,B)=B
ID A B f(A,B) minter
m
0 0 0 0
1 0 1 1 A’B
2 1 0 0
3 1 1 1 AB
f(A,B)=A’B+AB=(A’+A)B=B

K-map
• Find rectangles to cover 1’s in adjacent entries.

• Rectangles can overlap but should not include 0’s.
A B C Y
• Use the rectangle that corresponds to a product term. 0 0 0 1
0 0 1 1
Y
AB
0 1 0 0
00 01 11 10 0 1 1 0
C
1 0 0 0
0 1 0 0 0
1 0 1 0
1 1 0 0
1 1 0 0 0 1 1 1 0
y(A,B)=A’B’C’+A’B’C= A’B’(C’+C)=A’B’

Kmap Simplification for Three Variables
A Kmap for three variables is constructed as shown in the diagram below.

We have placed each minterm in the cell that will hold its value.
Notice that the values for the yz combination at the top of the matrix form a
pattern that is not a normal binary sequence.
Thus, the first row of the Kmap contains all minterms where x has a value of
zero.
The first column contains all minterms where y and z both have a value of
zero.

This grouping tells us that changes in the variables x and y have no influence
upon the value of the function: They are irrelevant.
This means that the function,
 reduces to F(x) = z.
You could verify

this reduction
with identities or
a truth table.

Now for a more complicated Kmap. Consider the function:
Its Kmap is shown below. There are (only) two groupings of 1s.
Can you find them?

In this Kmap, we see an example of a group that wraps around the sides of a
Kmap.
This group tells us that the values of x and y are not relevant to the term of
the function that is encompassed by the group.
What does this tell us about this term of the function?
What about the

green group in
the top row?

The green group in the top row tells us that only the value of x is significant
in that group.
We see that it is complemented in that row, so the other term of the reduced
function is .
Our reduced function is:
Recall that we had

six minterms in our
original function!

Kmap Simplification for Four Variables
Our model can be extended to accommodate the 16 minterms that are

produced by a four-input function.
This is the format for a 16-minterm Kmap.

We have populated the Kmap shown below with the nonzero minterms from
the function:
Can you identify (only) three groups in this Kmap?
Recall that
groups can
overlap.

Our three groups consist of:

A purple group entirely within the Kmap at the right.
A pink group that wraps the top and bottom.
A green group that spans the corners.
Thus we have three terms in our final function:

It is possible to have a choice as to how to pick groups within a Kmap, while
keeping the groups as large as possible.
The (different) functions that result from the groupings below are logically
equivalent.

4-input K-map
Y
A B C D Y
AB 0 0 0 0 1
CD 00 01 11 10 0 0 0 1 0
00 0 0 1 0 1
0 0 1 1 1
0 1 0 0 0
01 0 1 0 1 1
0 1 1 0 1
11 0 1 1 1 1
1 0 0 0 1
10
1 0 0 1 1
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0

4-input K-map
A B C D Y
Y 0 0 0 0 1
AB 0
CD 00 01 11 10 0 0 1 0
0 0 1 0 1
00 1 0 0 1 0 0 1 1 1
0 1 0 0 0
01 0 1 0 1 0 1 0 1 1
0 1 1 0 1
11 1 1 0 0 0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
10 1 1 0 1
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0

4-input K-map
A B C D Y
0 0 0 0 1
Y 0 0 0 1 0
CD
AB
00 01 11 10 0 0 1 0 1
0 0 1 1 1
00 1 0 0 1
0 1 0 0 0
0 1 0 1 1
01 0 1 0 1
0 1 1 0 1
0 1 1 1 1
11 1 1 0 0
1 0 0 0 1
1 0 0 1 1
10 1 1 0 1 1 0 1 0 1
1 0 1 1 0
Y = AC + ABD + ABC + BD 1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0

Don’t Care Conditions
Real circuits don’t always need to have an output defined for every possible
input.
If a circuit is designed so that a particular set of inputs can never happen, we
call this set of inputs a don’t care condition.
Don’t Care Entry: “-” means the entry is not relevant either at input or
output.
In other words, we are free to assign either 0 or 1 to reduce the Boolean
expression.
They are very helpful to us in Kmap circuit simplification.

In a Kmap, a don’t care condition is identified by an X in the cell of the

minterm(s) for the don’t care inputs, as shown below.
In performing the simplification, we are free to include or ignore the X’s
when creating our groups.

In one grouping in the Kmap below, we have the function:

Another 3-Input example
Id a b c f (a,b,c)
0 0 0 0 0
1 0 0 1 0
2 0 1 0 1
3 0 1 1 0
4 1 0 0 1
5 1 0 1 1
6 1 1 0 -
7 1 1 1 1

Corresponding K-map
b=1
(0,0) (0,1) (1,1) (1,0)
0 2 6 4
c=0 0 1 - 1
1 3 7 5
c=1 0 0 1 1
a=1
f(a,b,c) = a + bc’

Yet another example
Id a b c f (a,b,c,d)
0 0 0 0 1
1 0 0 1 1
2 0 1 0 -
3 0 1 1 0
4 1 0 0 1
5 1 0 1 1
6 1 1 0 0
7 1 1 1 0

Corresponding K-map
b=1
(0,0) (0,1) (1,1) (1,0)
0 2 6 4
c=0 1 - 0 1
1 3 7 5
c=1 1 0 0 1
a=1
f(a,b,c) = b’

A different grouping gives us the function:

The truth table of:
 differs from the truth table of:
However, the values for which they differ, are the inputs for which we have
don’t care conditions.

K-maps with Don’t Cares
A B C D Y
Y
0 0 0 0 1
AB
CD 00 01 11 10 0 0 0 1 0
0 0 1 0 1
00 0 0 1 1 1
0 1 0 0 0
0 1 0 1 X
01 0 1 1 0 1
0 1 1 1 1
1 0 0 0 1
11 1 0 0 1 1
1 0 1 0 X
1 0 1 1 X
10
1 1 0 0 X
1 1 0 1 X
1 1 1 0 X
1 1 1 1 X

Y
A B C D Y
AB 0 0 0 0 1
CD 00 01 11 10
0 0 0 1 0
0 0 1 0 1
00 1 0 X 1
0 0 1 1 1
0 1 0 0 0
0 1 0 1 X
01 0 X X 1 0 1 1 0 1
0 1 1 1 1
1 0 0 0 1
11 1 1 X X 1 0 0 1 1
1 0 1 0 X
1 0 1 1 X
10 1 1 X X 1 1 0 0 X
1 1 0 1 X
1 1 1 0 X
1 1 1 1 X

A B C D Y
0 0 0 0 1 Y
0 0 0 1 0 AB
0 0 1 0 1 CD 00 01 11 10
0 0 1 1 1
0 1 0 0 0 00 1 0 X 1
0 1 0 1 X
0 1 1 0 1
0 1 1 1 1 01 0 X X 1
1 0 0 0 1
1 0 0 1 1
1 0 1 0 X 11 1 1 X X
1 0 1 1 X
1 1 0 0 X
10 1 1 X X
1 1 0 1 X
1 1 1 0 X
1 1 1 1 X
Y = A + BD + C

Prime Implicants
A group of 1’s which are adjacent and can be combined on a Karnaugh Map is
called an implicant.
The biggest group of 1’s which can be circled to cover a 1 is called a prime
implicant.
they are the only implicants we care about.

Prime Implicants
AB
CD 00 01 11 10 Prime Implicants Non-prime Implicants
00 0 0 0 1
01 0 0 1 1
11 0 1 1 1
10 0 1 1 1

All The Prime Implicants
AB
CD 00 01 11 10 Prime Implicants
00 0 0 0 1
01 0 0 1 1
11 0 1 1 1
10 0 1 1 1
When looking for a minimal solution –only circle prime implicants…
A minimal solution will never contain non-prime implicants

Essential Prime Implicants
AB
CD 00 01 11 10
00 0 0 0 1 Not all prime implicants are required…

01 0 0 1 1
11 0 1 1 1 A prime implicant which is the only
cover of some 1’s is essential – a
10 0 1 1 1
minimal solution requires it.
Essential Prime Implicants Non-essential Prime Implicants

A Minimal Solution Example
AB
CD 00 01 11 10
00 0 0 0 1
01 0 0 1 1
11 0 1 1 1
10 0 1 1 1
Not required…
F = AB’ + BC + AD
Minimum

Another Example
AB
CD 00 01 11 10
00 1 0 0 1
01 1 1 0 0
11 1 1 1 0
10 1 0 0 1 A’B’ is not required…
Every one one of its

locations is covered by
F = A’D + BCD + B’D’ multiple implicants
Minimum After choosing essentials,
everything is covered…

Finding the Minimum Sum of Products
1. Find each essential prime implicant and include it in the solution.

2. Determine if any minterms are not yet covered.
3. Find the minimal # of remaining prime implicants which finish the cover.

Yet Another Example
(Use of non-essential primes)
AB
CD 00 01 11 10
00 1 1 0 0 AD
01 0 0 1 1
CD
A’C
11 1 1 1 1
10 1 1 0 0
Essentials: A’D’ and AD

Non-essentials: A’C and CD A’D’
Solution: A’D’ + AD + A’C
or
A’D’ + AD+ CD

Combinational functional blocks
Combinational: The outputs depend only

on the current input values It uses only Combinatorial
logic gates. Logic Circuit
m Boolean Inputs n Boolean Outputs
Sequential
The outputs depend on the
current and past input
values It uses logic gates and
storage elements

Classifications of Combinational Circuits

BINARY ADDITION
• Conceptually similar to
decimal addition
• Example: Add the binary Add the Binary numbers 11010 and 1100
numbers 1010 and 11
(carry)(carry)
(carry)
1 1
1
1 1 0 1 0
1 0 1 0
+ 1 1 0 0
+ 1 1
1 0 0 1 1 0
1 1 0 1

Multiple-bit Addition
° Consider single-bit adder for each bit position.
A3 A2 A1 A0 B3 B2 B1 B0
A 0 1 0 1 B 0 1 1 1
Ci+1 Ci
1 1 1
A 0 1 0 1 Ai
B 0 1 1 1 +Bi
1 1 0 0 Si
Each bit position creates a sum and carry

ADDER
In electronics, an adder is a digital circuit that performs addition of
numbers.
In modern computers and other kinds of processors, adders are used in the
arithmetic logic unit (ALU), but also in other parts of the processor, where
they are used to calculate addresses, table indices, and similar operations.
Although adders can be constructed for many numerical representations,
such as binary-coded decimal or excess-3, the most common adders operate on
binary numbers.
Adders are the basic building blocks of all arithmetic circuits; adders add two
binary numbers and give out sum and carry as output. Basically we have two
types of adders.
Half Adder.
Full Adder.
Half-Adder
Basic rules of binary addition are performed by a half Inputs Outputs
adder, which has two binary inputs (A and B) and two A B Cout S
binary outputs (Carry out and Sum). 0 0 0 0
The half adder adds two binary digits called as augend and 0 1 0 1
addend. 1 0 0 1
1 1 1 0
XOR is applied to both inputs to produce sum.
OR gate is applied to both inputs to produce carry.
The inputs and outputs can be
The logic symbol and equivalent circuit are: summarized on a truth table.
S Dec Binary
A S
1 1
S A +1 +1
Cout
B Cout B 2 10
Carry <= X AND Y; Sum<= X XOR Y;
Full Adder
 The full adder adds 3 one bit numbers.

 Where two can be referred to as operands.
 One can be referred to as bit carried in.
 It produces 2-bit output, and these can be referred to as output carry and sum.
A
Cin A B S Cout
B SUM
0 0 0 0 0 Cin
Si = A xor B xor Cin
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1 Cout = A.B + A.Cin + B.Cin Cout
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Full Adder
C A B SUM Cout
0 0 0 0 0 AB
0 0 1 1 0 C 00 01 11 10
SUM = A’B’C+A’BC’+AB’C’+ABC
0 1 0 1 0 0 1 1
0 1 1 0 1
1 0 0 1 0 1 1 1
1 0 1 0 1 SUM
1 1 0 0 1 = C(A B + A B) + CIN (A B + A B)
1 1 1 1 1 =CIN (A Ex-NOR B) + CIN (A Ex-OR B)
AB = CIN (A ⊕ B) + CIN (A ⊕ B)
C 00 01 11 10
Therefore, S = CIN ⊕ (A ⊕ B)
0 1
1 1 1 1
Cout Cout = A&B+C&B+C&A

Full-Adder
A full-adder can be constructed from two half adders as shown:
By contrast, a full adder has three binary inputs (A, B, and Inputs Outputs
Carry in) and two binary outputs (Carry out and Sum). The A B Cin Cout S
truth table summarizes the operation. 0 0 0 0 0
0 0 1 0 1
A A S A S
Symbol 0 1 0 0 1
A S S S
S 0 1 1 1 0
B B Cout B Cout 1 0 0 0 1
Cout B
Sum Cin 1 0 1 1 0
Cin 1 1 0 1 0
1 1 1 1 1
Cout
Half Adder Half Adder
Cin
Cin
Cin + xy
Cin

Full Adder
° Putting it all together

• Single-bit full adder
• Common piece of computer hardware
Ai Bi
C i+1 Full Adder Ci
Si
Block Diagram

4-Bit Adder
° Chain single-bit adders together.

° What does this do to delay?
A3 B3 A2 B2 A1 B1 A0 B0
Full Adder Full Adder Full Adder Full Adder 0

C3 C2 C1
C4 S3 S2 S1 S0
C 1 1 1 0
A 0 1 0 1
B 0 1 1 1
S 1 1 0 0
Parallel Adders
Full adders are combined into parallel adders that can add binary numbers with multiple
bits. A 4-bit adder is shown.
A4 B4 A3 B3 A2 B2 A1 B1
C0
A B Cin A B Cin A B Cin A B Cin
Cout S Cout S Cout S Cout S
C4
C3 C2 C1
S4 S3 S2 S1
The output carry (C4) is not ready until it propagates through all of the full adders. This is
called ripple carry, delaying the addition process.

Parallel Adders
The logic symbol for a 4-bit parallel adder is shown. This 4-bit adder includes a carry in (labeled
(C0) and a Carry out (labeled C4).
S
1 1
Binary 2 2 4-bit
number A 3 3 sum
4 4
1
Binary 2
number B 3
4
Input Output
C0 C4
carry carry
The 74LS283 is an example. It features look-ahead carry, which adds logic to minimize the
output carry delay. For the 74LS283, the maximum delay to the output carry is 17 ns.

Comparators
The function of a comparator is to compare the magnitudes of two binary numbers to

determine the relationship between them. In the simplest form, a comparator can test for
equality using XNOR gates.
How could you test two 4-bit numbers for equality?
AND the outputs of four XNOR gates.
A1
B1
A2
B2 Output
A3
B3
A4
B4

Comparators
IC comparators provide outputs to indicate which of the numbers is larger or if they are
equal. The bits are numbered starting at 0, rather than 1 as in the case of adders. Cascading
inputs are provided to expand the comparator to larger numbers.
COMP
A0 0
A1 A
A2
A3 3
Cascading A>B A>B
A=B A=B Outputs
inputs
A<B A<B
B0 0
B1 A
The IC shown is the 4-bit 74LS85.
B2
B3 3

Comparators
IC comparators can be expanded using the cascading inputs as shown. The lowest order
comparator has a HIGH on the A = B input.
LSBs MSBs
A0 COMP A4 COMP
A1 0 A5 0
A2 A A6 A
A3 A7
3 3
A>B A>B A>B A>B
+5.0 V A=B A=B A=B A=B Outputs
A<B A<B A<B A<B
B0 0 B4 0
B1 A B5 A
B2 B6
B3 3 B7 3

ENCODERS
An encoder is a device that is used to convert a signal or certain data into code.
This kind of conversion is done for a variety of reasons, the most common being
data compression.
Other reasons for using encoders include:
 data encryption for making the data secure
 translating data from one code to another new or existing code.
Encoders may be analog or digital devices.

In analog devices, the encoding is done using analog circuitry
While
 in digital encoders the encoding is done using program algorithms

Example of an ENCODER
Inputs Output

Further example of Encoders
If in an encoder the following input was given, the output/address would
be as indicated:
ABCDEFGH S0 S1 S2
1 0 0 0 000 0 0 0 0
ABCDEFGH S0 S1 S2
0
1 0 0 0 0 010 0 1 0 1
0
0
0
1

Encoders
 Octal-to-Binary Encoder (8-to-3) I7
I6
I7 I6 I5 I4 I3 I2 I1 I0 Y2 Y1 Y0
Encoder
I5
Y2
Binary
0 0 0 0 0 0 0 1 0 0 0 I4
I3 Y1
0 0 0 0 0 0 1 0 0 0 1
I2 Y0
0 0 0 0 0 1 0 0 0 1 0 I1
0 0 0 0 1 0 0 0 0 1 1 I0
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1 I7
0 1 0 0 0 0 0 0 1 1 0 I6 Y2
1 0 0 0 0 0 0 0 1 1 1 I5
I4
Y2  I 7  I 6  I 5  I 4 I3 Y1
Y1  I 7  I 6  I 3  I 2 I2
I1
Y0  I 7  I 5  I 3  I1 I0 Y0

Priority encoder
 If two inputs are active simultaneously, the output produces an undefined combination. We
can establish an input priority to ensure that only one input is encoded.
 Another ambiguity in the octal-to-binary encoder is that an output with all 0’s is generated
when all the inputs are 0; the output is the same as when D0 is equal to 1.
V=0no valid inputs

V=1valid inputs
X’s in output columns represent

don’t-care conditions X’s in the
input columns are useful for
representing a truth table in
condensed form. Instead of listing
all 16 minterms of four variables.

Priority Encoders
 4-Input Priority Encoder ( V is a valid bit indicator)
D3
Encoder
V
Priority
D2 y
D1 x
D0

1

DECODERS
A decoder, on the other hand, functions the reverse of an encoder.
It is a device that is used to decode an encoded signal or data.
It does this to help retrieve the data that was encoded in the first place.
Both encoders and decoders usually function in cycle, i.e., an application that
uses an encoder would ideally also require a decoder.
A decoder chooses one of the wires and make it output 1.
The output whose index is given by the binary value on S (select input) is set
to 1. All others are set to 0.
Only one wire can be ‘ON’ at a time.
 Whichever one is ‘ON’ is based on the input (ie @ the selector).

Example of a DECODER
Output
NB: Only ONE of the line
will have the value 1; others
will have 0.

Further example of Decoders
If in a decoder the following selects were made, the output would be as indicated:
S0 S1 S2 ABCDEFGH
1 0 1 00000100
0 1 0 00100000

Decoders
 2-to-4 Line Decoder Y3
Y0 Y2
Decoder
I1
Binary
Y1
Y2 Y1
I0 Y3
Y0
I1 I0 Y0 Y1 Y2 Y3
0 0 1 0 0 0
I1
0 1 0 1 0 0
I0
1 0 0 0 1 0
1 1 0 0 0 1 Y3  I1 I 0 Y2  I1 I 0
Y1  I1 I 0 Y0  I1 I 0
Decoders
 3-to-8 Line Decoder (Binary to Octal conversion) Y7  I 2 I1 I 0
Y6  I 2 I1 I 0
Y0 Y5  I 2 I1 I 0
Y1 Y4  I 2 I1 I 0
Y2
Decoder
I2 Binary Y3 Y3  I 2 I1 I 0
I1 Y4 Y2  I 2 I1 I 0
I0 Y5
Y1  I 2 I1 I 0
Y6
Y7 Y0  I 2 I1 I 0
I2
I1
I0

Multiplexers
An n-input and b-bit multiplexer has n sources of data, each of which b bits
wide, and there are b output bits.
A multiplexer is a unidirectional device.
Multiplexers are used in any application in which data must be switched
from multiple sources to a destination.
e.g., processor’s registers to ALU

What is a Multiplexer (MUX)?
 A MUX is a digital switch that has

multiple inputs (sources) and a
Multiplexer
single output (destination). Block Diagram
 The select lines determine which
input is connected to the output.
2N 1
MUX
Output
 MUX Types Inputs
(sources) (destination)
  2-to-1 (1 select line)

  4-to-1 (2 select lines) N
  8-to-1 (3 select lines) Select

Lines
  16-to-1 (4 select lines)

Typical Application of a MUX
Multiple Sources Selector Single Destination
MP3 Player
Docking Station
D0
Laptop
MUX
D1
Sound Card Y
D2
D3
Surround Sound System
Digital B A Selected Source

Satellite
0 0 MP3
0 1 Laptop
1 0 Satellite
Digital
1 1 Cable TV
Cable TV

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4-to-1 Multiplexer (MUX)
D0
MUX
D1
Y
D2
D3
B A
B A Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3

What is a Demultiplexer (DEMUX)?
 A DEMUX is a digital switch with

a single input (source) and a Demultiplexer
multiple outputs (destinations). Block Diagram
 The select lines determine which

output the input is connected to.
DEMUX
1 2N
Input Outputs
 DEMUX Types (source) (destinations)
  1-to-2 (1 select line)

N
  1-to-4 (2 select lines)
Select
  1-to-8 (3 select lines) Lines
  1-to-16 (24)(4 select lines)

Typical Application of a DEMUX
Single Source Selector Multiple Destinations
B/W Laser
Printer
Fax
Machine
D0
DEMUX
X D1
D2 Color Inkjet
Printer
D3
Selected
B A
Destination
Pen
0 0 B/W Laser Printer Plotter
0 1 Fax Machine
1 0 Color Inkjet Printer
1 1 Pen Plotter

1-to-4 De-Multiplexer (DEMUX)
D0
DEMUX
D1
X
D2
D3
B A
B A D0 D1 D2 D3
0 0 X 0 0 0
0 1 0 X 0 0
1 0 0 0 X 0
1 1 0 0 0 X

A basic ALU
1-bit logic unit

One AND, one OR and one multiplexer
Operation (0/1) controls the output.
1-bit adder
Inputs a and b are two bits to be added.
CarryIn: a carry bit from another adder
CarryOut: a carry bit generated from this adder

Let’s Build a 1-Bit ALU
 This is an one-bit ALU which can do Logical

AND and Logical OR operation.
 Result = a AND b when operation = 0
 Result = a OR b when operation = 1
 The operation line is the input of a MUX.

Building a 1-Bit ALU (cont’d)
 Adding a full adder to our ALU

Thank you………………

Ec237 Digital System and Combinational Circuits Unit 4

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DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

PUDUCHERRY TECHNOLOGICAL UNIVERSITY, PUDUCHERRY – 605 014

Course Name : Analog and Digital Electronics

Topic : Digital system and Combinational circuits

Department of Electronics and Communication Engineering, PTU.

Literal: A literal is a complemented or uncomplemented Boolean variable.

3 Department of Electronics and Communication Engineering, PTU. VIDYA SAGAR P

Karnaugh maps provide an alternative way of simplifying logic circuits.

1Named for the American electrical engineer Maurice Karnaugh.

4 Department of Electronics and Communication Engineering, PTU. VIDYA SAGAR P

5 Department of Electronics and Communication Engineering, PTU. VIDYA SAGAR P

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A Kmap has a cell for each minterm.

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• In our example, we have two such groups.

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The rules of Kmap simplification are:

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• Find rectangles to cover 1’s in adjacent entries.

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A Kmap for three variables is constructed as shown in the diagram below.

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You could verify

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Now for a more complicated Kmap. Consider the function:

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What about the

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Recall that we had

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Our model can be extended to accommodate the 16 minterms that are

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Can you identify (only) three groups in this Kmap?

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Our three groups consist of:

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They are very helpful to us in Kmap circuit simplification.

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In a Kmap, a don’t care condition is identified by an X in the cell of the

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In one grouping in the Kmap below, we have the function:

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A different grouping gives us the function:

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The truth table of:

 differs from the truth table of:

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