‘Seay Educatinal Tt) GM INSTITUTE OF TECHNOLOGY ‘Approved by AICTE. | Afilted to VTUBalgaum | Recognized by Govt of Karnataka EMBEDDED SYSTEMS Semester: VI Subject Code: 18EC62 Prepared by: Mr. HARISHA G C Assistant Professor Department of E&CE GMIT, Davanagere aaoe202 Prof Hanh Gc, GMI, OMGModule 1 ARM-32 bit Microcontroller: Thumb-2 technology and applications of ARM, Architecture of ARM Cortex M3, Various Units in the architecture, Debugging support, General Purpose Registers, Special Registers, exceptions, interrupts, stack operation, reset sequence (Text 1: Ch-1, 2, 3) L1,L2Introduction to ARM CORTEX — M3 The Cortex - M3 addresses the following requirements for 32-bit embedded processor market. * Greater performance efficiency: allowing more work to be done without increasing the frequency or power requirements + Low power consumption: enabling longer battery life, especially critical in portable products including wireless networking applications + Enhanced determinism: guaranteeing that critical tasks and interrupts are serviced as quickly as possible and in a known number of cycles + Improved code density: ensuring that code fits in even the smallest memory footprints + Ease of use: providing easier programmability and debugging for the growing number of 8- bit and 16-bit users migrating to 32 bits * Lower cost solutions: reducing 32-bit-based system costs close to those of legacy 8-bit and 16-bit devices and enabling low-end, 32-bit microcontrollers to be priced at less than US$1 for the first time * Wide choice of development tools: from low-cost or free compilers to full-featured development suites from many development tool vendorsBrief History of ARM ARM is acronym for Advanced RISC Machines Ltd. Founded 1990, a joint venture of Acorn Computer groups, Apple Computer and VLSI Technology In 1991, Texas Instruments, NEC, Sharp, and ST Microelectronics, licensed the ARM processor designs ARM does not manufacture processors or sell the chips directly. Applications of ARM processors includes mobile phones, computer hard disks, personal digital assistants (PDAs), home entertainment systems, and many other consumer productsWhy ARM? + ARM is one of the most licensed and thus widespread processor cores in the world * Used especially in portable devices due to low power consumption and reasonable performance + ARM enables their partners to build their products in an efficient, affordable and secure wayARM Processor v/s ARM MCU Developed by ARM “se ip Davos by manioturers houses, chip manufacturers Figure: The Cortex ~ M3 Processor v/s Cortex M3 based MCUARCHITECTURE VERSION =a "apse 946, 1 ees fe | eee exam oar, eS ol SrOnQARM Cortex-MO, CCortex-Mt (FPGA) ‘Architecture | Architecture | Architectureve | Architecture v7 ! ! 7A apticaton) | on eas | ARMI136, 1176, | \v7-M (microcontroller) 1 ore | 29. Cortex ' : FIGURE 1.2 The Evolution of ARM Processor Architecture,APOIOEGE-S ARDIOESE-S ARBIOBEHS: APDTO20E ARDATO2ZE ARDITO26E-S ARM IS8IFFS. APMIITBLZS /ARDATT MPCore ARDATISST2YS. Cortex:Mo ConeeMt Contexts Processor Naming ‘Memory Management Architecture Version Features ARMNAT ARMNAT ARMNSE ARNT wu ARMS MMU, ARSE Muu ARMWSE MPU ARMWSE DsP ARMWSE ARMWSE MPU (optional) ARMWSE, MMU ARMWSE MMU ARMWSE MMU o MPU ARMS Mu. ARMS MMU + TrustZone ARMS [MMU + multiprocessor cache support ARNE MPU ARMNE-M, ARNNE-M, FPGA TOM interface ARMV7-M Po Harsha 6G RRBUeitional) Other Features DSP, Jazote DSP, Jazate psp DMA DSP DsP psp DSP, Jazote DSP, Jazete DSP, Jazele DSP, Jazote psp Nuc NuicTable 1.1 ARM Processor Names Continued Processor cones Conan Rae conan AB coneraS ARM Thun [Memory Management Name Architecture Version Features ‘otner Features ABONT A weu ose ARNT Neu DSP + Feating| pone ARNT MMU + rstZare Ds, Jara, NEON + foaing pore ANA MM + TrstZone + De, Jat, rrtiprocessor NEON fing bone “ wr | we | we ry w = SIMO, v6 sananced | memory —] ose suppor instucions | “Sioa ‘38603 Thumb-2 Itechnoiogy| TR ‘nociced| netsInstruction Set Development Thom 2 technology "22h and tet "Thumb inetion set + ARM instruction set ~ 32 bits + Thumb instruction set ~ 16 bits Cones Cate) GE) > Subset of ARM instruction set and provides higher code density > — Useful for product with tight memory requirements > Ex: ARM7TDMI + Thumb-2 instruction set (Ex: ARM Cortex - M3 > superset of thumb instructions that contains both 16-bit and 32-bit instructions > Reduces switching between ARM and Thumb stateCortex — M3 Processor Applications Low-cost microcontrollers Automotive Data communications Industrial control Consumer productsOverview of the Cortex-M3 Cortex-M3_ : Processor core system ee Sel 5 el 2 + 32-bit register bank 35 2 Interrupts g6 3 : Debug [[) Trace * 32-bit memory interfaces = av |si|) “" + The processor has a Harvard architecture Memory interface : 7 + However, the instruction and data ™ os , Instruction bus |_| protection buses share the same memory unit space Debug « Bus interconnect, L| pores + MPU + Little endian and Big endian a =e ‘memory systems are supported Code Memory system Private memory ‘and peripherals peripherals | OPtional + Debugging featuresRegisters The RO through R7 can be accessed by all 16-bit Thumb instructions and all 32-bit Thumb-2 instructions. The reset value is unpredictable. ‘The R8 through R12 can be accessible by all Thumb- 2 instructions but not by all 16-bit Thumb instructions RIB is the stack pointer (SP). In the Cortex-M3 processor, there are two SPs, > Main Stack Pointer (MSP): This is the default SP; it is used by the operating system (OS) kernel, exception handlers, and all application codes that require privileged access, > Process Stack Pointer (PSP): This is used by the base-level application code (when not running an exception handler). > The lowest 2 bits of the stack pointers are always 0, which means they are always word aligned. Name Functions (and benked registers) General purpose register cm — (iremes] General purpose register Gora use et | a egies General purpose register General purpose register General purpose register General purpose register General purpose register General purpose register General purpose register High registers: General purpose register a Cereal pupese reste Main Stack Pointer (MSP), Process Stack Pointer (PSP) Link Register (LR) Progam Cote PO) rogram status registers vemos a ” [REONTAOL 0} Coral register aSTACK PUSH AND POP Stack is a memory usage model. It is simply part ofthe system memory, and a pointer register (inside the processor) is used to make it work as afirst-in/last-out butter. The common use of a stack isto save register Contents before some data processing and then restore those contents from the stack after the processing task is done. ‘Stack PUSH operation to back up register contents contents Memory FIGURE 3.2 Stack POP operation to restore register contents Register contents Data processing (cxiginal register contents destroyed) Basic Concept of Stack Memory. When doing PUSH and POP operations, the pointer register, commonly called stack pointer, is adjusted automatically to prevent next stack operations from corupting previous stacked data. More details on stack ‘operations are provided on later part of this chaptet 7, 0VGIn the Cortex-M3, the instructions for accessing stack memory are PUSH and POP. PUSH (RO) ; R13=R13-4, then Memory[R13] = RO POP {RO} ; RO = Memory[R13], then R13 = R13 + 4 + The Cortex-M3 uses a full-deseending stack arrangement. + The SP decrements when new data is stored in the stack, PUSH and POP are usually used to save register contents to stack memory at the start of a subroutine and then restore the registers from stack at the end of the subroutine. + You can PUSH or POP multiple registers in one instruction: subroutine_l PUSH (RO-R7, R12, R14} ; Save registers : Do your processing POP —-{RO-R7, R12, R14} : Restore registers Bx R14 : Return to calling function + Inside program code, both the MSP and the PSP can be called R/3/SP. + However, you can access a particular one using special register access instructions (MRS/MSR).Link register R14 or LR: LR is used to store the return program counter (PC) when a subroutine or function is called —for example, when you're using the branch and link (BL) instruction: main ; Main program BL function! ; Call functioni using Branch with Link instruction : PC = function and : LR = the next instruction in main function : : Program code for function 1 BX LR Return ‘The LR bit 0 is readable and writable. Program Counter R15: Because of the pipelined nature of the Cortex-M3 processor, when you read this register, you will find that the value is different than the location of the executing instruction, normally by 4. For example: 0x1000 : MOV RO, PC ; RO = 0x1004Stack Operations Stack (>, faceprepSpecial Registers: *+ Program Status registers (PSRs) *+ Interrupt Mask registers (PRIMASK, FAULTMASK, and BASEPRD) + Control register (CONTROL) » Special registers can only be accessed via MSR and MRS instructions > They do not have memory addresses > They cannot be used for normal data processing MRS , ; Read special register MSR , ; write to special register Register Function xPSR Provide arithmetic and logic processing flags (zero flag and carry flag), execution status, and current executing interrupt number PRIMASK Disable all interrupts except the nonmaskable interrupt (NMI) and hard fault FAULTMASK Disable all interrupts except the NMI BASEPRI Disable all interrupts of specific priority level or lower priority level CONTROL, Define privileged status and stack pointer selectionOPERATION MODE: + Thread Mode — can be operated in privileged or user level + Handler Mode ~ operated in only privileged level CONTROL(0] = 0 Privileged Handler mode. Exception When not running an exception hander | Thread mode (eg, main program) (coNTROLo}=0) (CONTROL 1} can be either 0 ort Program of ‘CONTROL register CONTROL{O] = 1 Ifa program running at the user access level tries to access SCS (System Control Space) or special registers, a fault exception will occur.Program Status Registers: *+ Application Program Status register (APSR) + Interrupt Program Status register (IPSR) + Execution Program Status register (EPSR) v When they are accessed as a collective item, the name xPSR is used. > You can read the PSRs using the MRS instruction. v ‘You can also change the APSR using the MSR instruction, but IPSR and EPSR are read-only. For example: MRS: MRS MRS: MSR 10, APSR; Read Flag state into RO 10, IPSR__ ; Read Exception/Interrupt state 10,EPSR__ ; Read Execution state APSR, 10__ ; Write Flag state ‘The three PSRs can be accessed together or separately using the special register access instructions MSR and MRS.psa [w]|zlolvlo 1PSR Excoption number PSR veut | 7 cur \GURE 3.3 Program Status Registers (PSRs) in the Corto MB. a7 | 90 | 29 | 20 | 27 | 2625] 24 [20:20] 19:16 15:0[ 9 | #[ 7] 6] o| +0 wen [Nu] z ° v [@ [reur |r ur Exception number FIGURE 3.4 ‘Combined Program Status Registers (XPSA) in the Cortex M3. ‘Table 3.1 Bit Fields in Cortex:M3 Program Status Registers Bit Description N Negative Zz Ze ce Carryfoorow v Overton Q Sticky saturation lag low Interupt-Continuable Instruction (C) bts, IF-THEN instruction status bit T ‘Thumb state, always 1; trying to clear ths bit will cause a fauit exception Exception number Indicates which exception the processor is handing sha GC, GMI, OVSPRIMASK, FAULTMASK, and BASEPRI registe! + The PRIMASK, FAULTMASK, and BASEPRI registers are used to disable exceptions + The PRIMASK and BASEPRI registers — Used to disable interrupts in timing — critical tasks + An OS could use FAULTMASK to temporarily disable fault handling when a task has crashed. Table 3.2 Cortex-M3 Interrupt Mask Registers Register Name Description PRIMASK ‘A 1-bit register, when this is set, it allows nonmaskable interrupt (NMI) and the hard fault exception; all other interrupts and exceptions are masked. The default value is 0, which means that no masking is set. FAULTMASK ‘A 1-bit register, when this is set, it allows only the NMI, and all interrupts and fault handling exceptions are disabled. The default value is 0, which means that no masking is set BASEPRI A register of up to 8 bits (depending on the bit width implemented for priority leve). It defines the masking priority level. When this is set, it disables all interrupts of the same or lower level (arger priority value). Higher priority interrupts can stil be allowed. If this is set to 0, the masking function is disabled (this is the default)Example Functions / Assembly Code to access PRIMASK, FAULTMASK, and BASEPRI registers x= __get_BASEPRI(); // Read BASEPRI register x=__get_PRIMARK(); // Read PRIMASK register x= __get_FAULTMASK(); // Read FAULTMASK register __Set_BASEPRI(x); // Set new value for BASEPRI _set_PRIMASK(x); // Set new value for PRIMASK _Set_FAULTMASK(x); // Set new value for FAULTMASK _disable_irq(); // Clear PRIMASK, enable IRQ. _enable_irq(); // Set PRIMASK, disable IRQ. MRS. MRS. MRS. MSR MSR MSR 10, BASEPRI ; Read BASEPRI register into RO 10, PRIMASK ; Read PRIMASK register into RO 10, FAULTMASK ; Read FAULTMASK register into RO BASEPRI, 10 ; Wri RO into BASEPRI register PRIMASK, 10 ; Write RO into PRIMASK register FAULTMASK, 10 ; Wri e RO into FAULTMASK register The PRIMASK, FAULTMASK, and BASEPRI registers eannot be set in the user access level.+ Tread Mode — can be operated in privileged of user level + Handler Mode — operated in only privileged level ‘The control register is used to define the privilege level and the SP selection. This register has 2 bits. Bit Function CONTROL{t]} Stack status: 1 = Atemate stack is used 0 = Default stack (MSP) is used It itis in the thread or base level, the alternate stack is the PSP. There is no alternate stack for handler mode, 30 tis bit must be O when the processor isin handler mode. CONTROLO} 0 = Privieged in thread mode 1 = User state in thread mode tin handler mode (not thread mode), the processor operates in privileged mode CONTROLI): This bit is related to the SP selection + Inthe Cortex-M3, the CONTROLI] bit is always 0 in handler mode, However, in the thread or base level, it can be either 0 or 1. + This bit is writable only when the core is in thread mode and privileged. In the user state or handler mode, writing to this,bitis not allowed. 5s, Harsha GC, OMIT, OVSCONTROL{OJ: This bit is related to selection of privileged state/level - ‘The CONTROL(0] bit is writable only in a privileged state, Once it enters the user state, the only way to switch back to privileged is to trigger an interrupt and change this in the exception handler. Example statements to access the control register in C — x=__get CONTROL(); // Read CONTROL eee ee | OMRo __set_CONTROL(x); // Set the CONTROL value to x When not runing an exception hander | Thread mode Thread mode (eg, main program) (CONTROL]=0) | (CONTROLO|= 1) CONTROL 1] canbe eter 0 ort To access the control register in assembly, the MRS and MSR instructions are used: MRS | 10, CONTROL ; Read CONTROL register into RO MSR | CONTROL, 10 ; Write RO into CONTROL registerOPERATION MODE: + Thread Mode — can be operated in privileged or user level + Handler Mode ~ operated in only privileged level CONTROL(0] = 0 Privileged Handler mode. Exception When not running an exception hander | Thread mode (eg, main program) (coNTROLo}=0) (CONTROL 1} can be either 0 ort Program of ‘CONTROL register CONTROL{O] = 1 Ifa program running at the user access level tries to access SCS (System Control Space) or special registers, a fault exception will occur.Reprogram CONTROL ‘Switch to user Privileged mode by writing handler to CONTROL register User thread FIGURE 3.7 Switching of Operation Mode by Programming the Control Register or by Exceptions. ‘The support of privileged and user access levels provides a more secure and robust architecture. When a user program goes wrong, it will not be able to corrupt control registers in the Nested Vectored Interrupt Controller (NVIC). In addition, if the Memory Protection Unit (MPU) is present, itis possible to block user programs from accessing memory regions used by privileged processes.Privileged hander Privileged ( Starting read User thread FIGURE 3.8 ‘Simple Applications Do Not Require User Access Level in Thread Mode. Intornpt oat | Interrupt serve Interupt senice i Fie) routine (IS) routine (SR) Interrupt i * Main . program ' program : H | Tine T : “Thread mode | Hanger mode ‘Tread mode Teas mode | Mandermose | Thread made (orveged) ! (oriveged) (Grieg) (use : (Grvioged) ' (use Fount 3.10, ha oMI, VG Sting Prosesior Mode and Prviege Level ternInterrupts vs Exceptions + Varying terminology but for intel — Interrupt (synchronous, device generated) + Maskable: device-generated, associated with IRQs (interrupt request lines); may be temporarily disabled (still pending) + Nonmaskable: some critical hardware failures ~ Exceptions (asynchronous) + Processor-detected — Faults — correctable (restartable); e.g. page fault — Traps — no reexecutionneeded; e.g. breakpoint — Aborts — severe error; process usually terminated (by signal) + Programmed exceptions (software interrupts) t (system call), int3 (breakpoint) to (overflow), bounds (address check) In most cases, the NMI could be connected to a watchdog timer or a voltage-monitoring block that wars the processor when the voltage drops below a certain level. The NMI exception can be activated any time, even right after the core exits reset.Table 3.4 Exception Types in Cortex-M3. Exception Number Exception Type _—Priority 1 Reset 3 (Highest) 2 NMI 2 3 Hard fault a 4 MemManage | Settable 5 Bus fault Settable 6 Usage fault Settable 7-10 - - 4 sve Settable 12 Debug monitor Settable 13, - - 14 PendSV Settable 15 SYSTICK Settable 240} 962055 RQ Function Reset Nonmaskable interrupt Al classes of fault, when the corresponding fault handler cannot be activated because itis currently disabled or masked by exception masking Memory management fault; caused by MPU Violation or invalid accesses (such as an instruction fetch from a nonexecutable region) Enror response received from the bus system; caused by an instruction prefetch abort or data access error Usage fault; typical causes are invalid instructions or invalid state transition attempts (such as trying to switch to ARM state in the Cortex-M3) Reserved ‘Supervisor call via SVC instruction Debug monitor Reserved Pendable request for system service System tick timer Settable sho 6 cIRE@inpsut #0-289 “THE BUILT-IN NESTED VECTORED INTERRUPT CONTROLLER + Nested interrupt support + Vectored interrupt support + Dynamic priority changes support + Reduction of interrupt latency + Interrupt maskingVECTOR TABLES ‘The vector tabl an array of word data inside the system memory, each representing the starting address of one exception type. The veetor table is relocatable, and the relocation is controlled by a relocation register in the NVIC Because the Cortex-M3_ can support only ‘Thumb instructions, the LSB of all the exception vectors should be set to 1. Table 3.5 Vector Table Definition after Reset Exception Type 18-255 7 16 5 4 3 2 "1 7-10 ‘Address Offset ols 0GFF os oo ac 08s oat 00 ac oxtc-0128 ons ons onto oot Exception Vector FQ 42-299 Fon FOO ‘sysTiOK Pendsv Reserved Debug menitor sve Reserved Usage faut Bus fut MemManage faut Hard faut Nu Reset ‘Stating vale ofthe MSPTHE MEMORY MAP + 4GB memory space + The Cortex-M3 design has an intemal bus infrastructure optimized for this memory usage. + The system-level memory region contains the interrupt controller and the debug components. These devices have fixed addresses OxFFFFFFFF (0x€0000000 OXDFFFFFFF (0xA0000000 OxOFFFFFFF (0x60000000 OxSFFFFFFF ‘6x40000000 OxSFFFFFFF (0x20000000 Ox1FFFFFFF ‘6x00000000 ‘System level Extemal device External RAM Peripherals SRAM CODE Private peripherals including build-in interrupt controller (NVIC), MPU control registers, and debug components Mainly used as external peripherals Mainly used as external memory Mainly used as peripherals Mainly used as static RAM Mainly used for program code. Also provides exception vector table after power upTHE BUS INTERFACE Code memory buses System bus Private peripheral bus THE MPU (Optional, This unit allows access rules to be set up for privileged access and user program access. When an access rule is violated, a fault exception is generated, and the fault exception handler will be able to analyze the problem and correct it, if possible The OS can set up the MPU to protect data use by the OS kernel and other privileged processes to be protected from untrusted user programs. The MPU can also be used to make memory regions read-only, to prevent accidental erasing of data or to isolate ‘memory regions between different tasks in a multitasking system. Overall, it can help make embedded systems more robust and reliable.THE INSTRUCTION SET +The Cortex-M3 supports the Thumb-2 instruction set, Its flexible and powerful yet easy to use. + In previous ARM processors, the central processing unit (CPU) had two operation states: a 32-bit ARM state and a 16-bit ‘Thumb state. + Inthe ARM state, the instructions are 32 bits and can execute all supported instructions with very high performance. + In the Thumb state, the instructions are 16 bits, so there is a much higher instruction code density, but the Thumb state does not have all the functionality of ARM instructions and may require more instructions to complete certain types of operations (Goon Insbucsons) eat in Thumb ate Inston) FicuRe 2.7 ‘Swchng between ARM Coxe and Thumb Cade in Tadional ARM Processors Such asthe ARMT,The Cortex-M3 processor has a number of advantages over traditional ARM processors, such as *+ No state switching overhead, saving both execution time and instruction space + No need to separate ARM code and Thumb code source files, making software development and maintenance easier + It’s easier to get the best efficiency and performance, in turn making it easier to write software, because there is no need to worry about switching code between ARM and Thumb to try to get the best density/performance + The Cortex-M3 processor has a number of interest EX: FUBX, BFI, BFC, UDIV, SDIV, WFE, WFI, MSR.MRS ete. 1g and powerful instructions, *+ Note that not all the instructions in the Thumb-2 instruction set are implemented on the Cortex-MB. coprocessor instructions Single Instruction-Multiple Data BLX with immediate - used to switch processor state from Thumb to ARM Change process state (CPS) instructions SETEND (Set Endian)DEBUGGING SUPPORT Program execution controls, including halting and stepping, instruction breakpoints, data watchpoints, registers and ‘memory accesses, profiling, and traces. Unlike traditional ARM processors, the CPU core itself does not have a Joint Test Action Group (TAG) interface. Instead, a debug interface module is decoupled from the core, and a bus interface called the Debug Access Port (DAP) is provided at the core level. Through this bus interface, external debuggers can access control registers to hardware as well as system memory, even when the processor id runningSTACK MEMORY OPERATIONS In the Cortex-M3, besides normal software-controlled stack PUSH and POP, the stack PUSH and POP operations are also carried out automatically when entering or exiting an exception/interrupt handler, Operations of the stack + Stack operations are memory write or read operations, with the address specified by an SP + Data in registers is saved into stack memory by a PUSH operation and can be restored to registers later by a POP operation. + The SP is adjusted automatically in PUSH and POP so that multiple data PUSH will not cause old stacked data to be erased. + The Cortex-M3 uses a full-descending stack operation model. The SP points to the last data pushed to the stack memory, and the SP decrements before a new PUSH operation.Stack Operation Basics: One Register in Each Stack Operation. Main program z X, RL oY, R20 Z BL function1 ‘Subroutine OO function] PUSH {RO} PUSH {RL} PUSH {R2} could be POP. (R2} POP (R21) POP (20) LR _*® + Back to main program ROX, RLY, R20 2 i next instructions aaoe202 ha oMI, VG ; Executing task RO to stack R1 to stack R2 to stack (RO, RL and store store store changed) restore R2 and SP restore Rl and SP restore RO and SP Return & adjust SP & adjust SP & adjust SP R2 re adjusted xe adjusted re adjustedMain program RO x, RL oy, R22 Subroutine BL function 1.——__ function 1 PUSH (RO R2) ; Store RO, Rl, R2 to stack ves? Executing task (RO, Rl and R2 } could be changes) Pop (RO R2) ; restore RO, Rl, R2 ee } Back to main progran 2RO x, Rl OY, R22 Main program ROX, RLY, R22 ‘Subroutine BL function 1 ——__ function 2 PUSH (RO R2, LR} + Save registers # including Link register # Executing task (RO, Rl and R2 7 could be changed) ae PRO x, RLY, RZ Z 2 of Hareha 6 GMI, OVS Stack Operation Basics: Multiple Register Stack Operation Stack Operation Basics: Combining Stack POP and RETURN.Memory aress Memory address ro [oaimaasare PUSH (RO) ‘Ceaiped 4 ‘Occupied ‘Occupied ‘Occupied 012385676 }+— sP 2 Occupied Taat pushed data —*— SP POP {RO} Coa Oeaiied Cortex-M3 Stack PUSH Implementation Ossiied ariansTs—}— se sick ew Cpe Oveupied 7 Cortex-M3 Stack POP Implementation eco’ Desisere js Ro [__o2aa5676 Because each PUSH/POP operation transfers 4 bytes of data (each register contains | word, or 4 bytes), the SP decrements/increments by 4 at a time. In the Cortex-M3, R13 is defined as the SP. When an interrupt takes place, a number of registers will be pushed automatically, and R13 will be used as the SP for this stacking process. Similarly, the pushed registers will be restored/popped automatically when exiting an interrupt handler, and the SP. will also be adjusted. aSwapping content of A and B C Statements 1. C=B; 2. B=A; 3.A=C; Note: C is a temporary memory Using Assembly PUSH and POP 1. PUSH A 2. PUSH _B 3. POP A 4. POP BThe Two-stack Model in the Cortex-M3 Intorrpt ext CONTROL{1}-0: Both Thread Level ‘and Handler Use Main Stack ‘Thread mode Interrupt service |! routine (ISR) H nore CONTROL{1]=1: Thread Level Uses Process Stack and Handler Uses Main ! Stack. a ‘Two separate stack memory space are Thread mode | andormode | Taread made used (use PSP) ! (Use MSP) | (se PSP)x = _get_MsP( —set_MSP(x); // Set the value of MSP x = get_PSP(); // Read the value of PSP —set_PsP(x); // Set the value of PSP MRS RO, MSP MSR MSP, RO MRS RO. PSP MSR PSP, RO 3 (1 Read the value of MSP : Read Main Stack Pointer to RO Write RO to Main Stack Pointer Read Process Stack Pointer to RO Write RO to Process Stack Pointer Prof Hanh Gc, GMI, OMG “After the processor exits reset, it will read two words from memory Address 0x00000000: Starting value of R13 (the SP) Address 0x00000004: Reset vector (the starting address of program execution; LSB should be set to I to indicate Thumb state) Fetch initial ‘Fetch reset Instruction SP value vector fetch ‘Address = a (0x00000004 reset vector 4 Time Reset SequenceInitial Stack Pointer Value and Initial Program Counter Value Example oe ee oo. intial SP valve <— ee J" ox20008000 20007 FFC [tat stacked Rem 020007 FF8 |[—2nd stacked term = = an ack grows ‘After the reset vector is fetched, the Cortex-M3 can tat asa then start to execute the program from the reset : gL vector address and begin normal operations. Cee Hy Other memory It is necessary to have the SP initialized, because some of the exceptions (such as NMI) can happen right after reset, and the stack memory could be a as required for the handler of those exceptions. 0x00000100 Boot code Other exception Reset vectors vector ‘ox00000004 || —oxc0000707 x00000000 || — «20008000Q.No. QUESTIONS Explain the simplified view of ARM Cortex — M3 with a neat diagram Explain the register organization of ARM Cortex M3 Explain the operation modes and privilege levels of ARM Cortex — M3 with a neat transition diagram Explain the instructions used to access special registers with suitable examples Explain the Special registers of ARM Cortex — M3 in detail What is stack? Explain basic concept of stack memory of ARM Cortex — M3 Explain the stack operation using PUSH and POP instructions in ARM Cortex M3 Explain two stack model and reset sequence in ARM cortex M3 Explain the applications of Cortex M3 Describe the functions of exceptions with a vector table and priorities Describe the memory map of Cortex M3 with a neat diagramaaoe202 END OF MODULE THANK YOU Prot Harsha 6 G GMT, OVG